2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/mutex.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/timer.h>
42 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
48 #define NVME_Q_DEPTH 1024
49 #define NVME_AQ_DEPTH 256
50 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
57 #define NVME_NR_AEN_COMMANDS 1
58 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
60 static int use_threaded_interrupts;
61 module_param(use_threaded_interrupts, int, 0);
63 static bool use_cmb_sqes = true;
64 module_param(use_cmb_sqes, bool, 0644);
65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
67 static struct workqueue_struct *nvme_workq;
72 static int nvme_reset(struct nvme_dev *dev);
73 static void nvme_process_cq(struct nvme_queue *nvmeq);
74 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
75 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
78 * Represents an NVM Express device. Each nvme_dev is a PCI function.
81 struct nvme_queue **queues;
82 struct blk_mq_tag_set tagset;
83 struct blk_mq_tag_set admin_tagset;
86 struct dma_pool *prp_page_pool;
87 struct dma_pool *prp_small_pool;
89 unsigned online_queues;
93 struct msix_entry *entry;
95 struct work_struct reset_work;
96 struct work_struct scan_work;
97 struct work_struct remove_work;
98 struct work_struct async_work;
99 struct timer_list watchdog_timer;
100 struct mutex shutdown_lock;
103 dma_addr_t cmb_dma_addr;
108 #define NVME_CTRL_RESETTING 0
110 struct nvme_ctrl ctrl;
111 struct completion ioq_wait;
114 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
116 return container_of(ctrl, struct nvme_dev, ctrl);
120 * An NVM Express queue. Each device has at least two (one for admin
121 * commands and one for I/O commands).
124 struct device *q_dmadev;
125 struct nvme_dev *dev;
126 char irqname[24]; /* nvme4294967295-65535\0 */
128 struct nvme_command *sq_cmds;
129 struct nvme_command __iomem *sq_cmds_io;
130 volatile struct nvme_completion *cqes;
131 struct blk_mq_tags **tags;
132 dma_addr_t sq_dma_addr;
133 dma_addr_t cq_dma_addr;
145 * The nvme_iod describes the data in an I/O, including the list of PRP
146 * entries. You can't see it in this data structure because C doesn't let
147 * me express that. Use nvme_init_iod to ensure there's enough space
148 * allocated to store the PRP list.
151 struct nvme_queue *nvmeq;
153 int npages; /* In the PRP list. 0 means small pool in use */
154 int nents; /* Used in scatterlist */
155 int length; /* Of data, in bytes */
156 dma_addr_t first_dma;
157 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
158 struct scatterlist *sg;
159 struct scatterlist inline_sg[0];
163 * Check we didin't inadvertently grow the command struct
165 static inline void _nvme_check_size(void)
167 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
168 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
169 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
170 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
171 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
172 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
173 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
174 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
175 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
176 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
177 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
178 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
182 * Max size of iod being embedded in the request payload
184 #define NVME_INT_PAGES 2
185 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
188 * Will slightly overestimate the number of pages needed. This is OK
189 * as it only leads to a small amount of wasted memory for the lifetime of
192 static int nvme_npages(unsigned size, struct nvme_dev *dev)
194 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
195 dev->ctrl.page_size);
196 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
199 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
200 unsigned int size, unsigned int nseg)
202 return sizeof(__le64 *) * nvme_npages(size, dev) +
203 sizeof(struct scatterlist) * nseg;
206 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
208 return sizeof(struct nvme_iod) +
209 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
212 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
213 unsigned int hctx_idx)
215 struct nvme_dev *dev = data;
216 struct nvme_queue *nvmeq = dev->queues[0];
218 WARN_ON(hctx_idx != 0);
219 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
220 WARN_ON(nvmeq->tags);
222 hctx->driver_data = nvmeq;
223 nvmeq->tags = &dev->admin_tagset.tags[0];
227 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
229 struct nvme_queue *nvmeq = hctx->driver_data;
234 static int nvme_admin_init_request(void *data, struct request *req,
235 unsigned int hctx_idx, unsigned int rq_idx,
236 unsigned int numa_node)
238 struct nvme_dev *dev = data;
239 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
240 struct nvme_queue *nvmeq = dev->queues[0];
247 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
248 unsigned int hctx_idx)
250 struct nvme_dev *dev = data;
251 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
254 nvmeq->tags = &dev->tagset.tags[hctx_idx];
256 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
257 hctx->driver_data = nvmeq;
261 static int nvme_init_request(void *data, struct request *req,
262 unsigned int hctx_idx, unsigned int rq_idx,
263 unsigned int numa_node)
265 struct nvme_dev *dev = data;
266 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
267 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
274 static void nvme_complete_async_event(struct nvme_dev *dev,
275 struct nvme_completion *cqe)
277 u16 status = le16_to_cpu(cqe->status) >> 1;
278 u32 result = le32_to_cpu(cqe->result);
280 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) {
281 ++dev->ctrl.event_limit;
282 queue_work(nvme_workq, &dev->async_work);
285 if (status != NVME_SC_SUCCESS)
288 switch (result & 0xff07) {
289 case NVME_AER_NOTICE_NS_CHANGED:
290 dev_info(dev->ctrl.device, "rescanning\n");
291 queue_work(nvme_workq, &dev->scan_work);
293 dev_warn(dev->ctrl.device, "async event result %08x\n", result);
298 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
299 * @nvmeq: The queue to use
300 * @cmd: The command to send
302 * Safe to use from interrupt context
304 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
305 struct nvme_command *cmd)
307 u16 tail = nvmeq->sq_tail;
309 if (nvmeq->sq_cmds_io)
310 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
312 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
314 if (++tail == nvmeq->q_depth)
316 writel(tail, nvmeq->q_db);
317 nvmeq->sq_tail = tail;
320 static __le64 **iod_list(struct request *req)
322 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
323 return (__le64 **)(iod->sg + req->nr_phys_segments);
326 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
328 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
329 int nseg = rq->nr_phys_segments;
332 if (rq->cmd_flags & REQ_DISCARD)
333 size = sizeof(struct nvme_dsm_range);
335 size = blk_rq_bytes(rq);
337 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
338 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
340 return BLK_MQ_RQ_QUEUE_BUSY;
342 iod->sg = iod->inline_sg;
352 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
354 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
355 const int last_prp = dev->ctrl.page_size / 8 - 1;
357 __le64 **list = iod_list(req);
358 dma_addr_t prp_dma = iod->first_dma;
360 if (iod->npages == 0)
361 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
362 for (i = 0; i < iod->npages; i++) {
363 __le64 *prp_list = list[i];
364 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
365 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
366 prp_dma = next_prp_dma;
369 if (iod->sg != iod->inline_sg)
373 #ifdef CONFIG_BLK_DEV_INTEGRITY
374 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
376 if (be32_to_cpu(pi->ref_tag) == v)
377 pi->ref_tag = cpu_to_be32(p);
380 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
382 if (be32_to_cpu(pi->ref_tag) == p)
383 pi->ref_tag = cpu_to_be32(v);
387 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
389 * The virtual start sector is the one that was originally submitted by the
390 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
391 * start sector may be different. Remap protection information to match the
392 * physical LBA on writes, and back to the original seed on reads.
394 * Type 0 and 3 do not have a ref tag, so no remapping required.
396 static void nvme_dif_remap(struct request *req,
397 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
399 struct nvme_ns *ns = req->rq_disk->private_data;
400 struct bio_integrity_payload *bip;
401 struct t10_pi_tuple *pi;
403 u32 i, nlb, ts, phys, virt;
405 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
408 bip = bio_integrity(req->bio);
412 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
415 virt = bip_get_seed(bip);
416 phys = nvme_block_nr(ns, blk_rq_pos(req));
417 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
418 ts = ns->disk->queue->integrity.tuple_size;
420 for (i = 0; i < nlb; i++, virt++, phys++) {
421 pi = (struct t10_pi_tuple *)p;
422 dif_swap(phys, virt, pi);
427 #else /* CONFIG_BLK_DEV_INTEGRITY */
428 static void nvme_dif_remap(struct request *req,
429 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
432 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
435 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
440 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
443 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
444 struct dma_pool *pool;
445 int length = total_len;
446 struct scatterlist *sg = iod->sg;
447 int dma_len = sg_dma_len(sg);
448 u64 dma_addr = sg_dma_address(sg);
449 u32 page_size = dev->ctrl.page_size;
450 int offset = dma_addr & (page_size - 1);
452 __le64 **list = iod_list(req);
456 length -= (page_size - offset);
460 dma_len -= (page_size - offset);
462 dma_addr += (page_size - offset);
465 dma_addr = sg_dma_address(sg);
466 dma_len = sg_dma_len(sg);
469 if (length <= page_size) {
470 iod->first_dma = dma_addr;
474 nprps = DIV_ROUND_UP(length, page_size);
475 if (nprps <= (256 / 8)) {
476 pool = dev->prp_small_pool;
479 pool = dev->prp_page_pool;
483 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
485 iod->first_dma = dma_addr;
490 iod->first_dma = prp_dma;
493 if (i == page_size >> 3) {
494 __le64 *old_prp_list = prp_list;
495 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
498 list[iod->npages++] = prp_list;
499 prp_list[0] = old_prp_list[i - 1];
500 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
503 prp_list[i++] = cpu_to_le64(dma_addr);
504 dma_len -= page_size;
505 dma_addr += page_size;
513 dma_addr = sg_dma_address(sg);
514 dma_len = sg_dma_len(sg);
520 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
521 struct nvme_command *cmnd)
523 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
524 struct request_queue *q = req->q;
525 enum dma_data_direction dma_dir = rq_data_dir(req) ?
526 DMA_TO_DEVICE : DMA_FROM_DEVICE;
527 int ret = BLK_MQ_RQ_QUEUE_ERROR;
529 sg_init_table(iod->sg, req->nr_phys_segments);
530 iod->nents = blk_rq_map_sg(q, req, iod->sg);
534 ret = BLK_MQ_RQ_QUEUE_BUSY;
535 if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
538 if (!nvme_setup_prps(dev, req, blk_rq_bytes(req)))
541 ret = BLK_MQ_RQ_QUEUE_ERROR;
542 if (blk_integrity_rq(req)) {
543 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
546 sg_init_table(&iod->meta_sg, 1);
547 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
550 if (rq_data_dir(req))
551 nvme_dif_remap(req, nvme_dif_prep);
553 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
557 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
558 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
559 if (blk_integrity_rq(req))
560 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
561 return BLK_MQ_RQ_QUEUE_OK;
564 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
569 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
571 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
572 enum dma_data_direction dma_dir = rq_data_dir(req) ?
573 DMA_TO_DEVICE : DMA_FROM_DEVICE;
576 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
577 if (blk_integrity_rq(req)) {
578 if (!rq_data_dir(req))
579 nvme_dif_remap(req, nvme_dif_complete);
580 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
584 nvme_free_iod(dev, req);
588 * We reuse the small pool to allocate the 16-byte range here as it is not
589 * worth having a special pool for these or additional cases to handle freeing
592 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
593 struct request *req, struct nvme_command *cmnd)
595 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
596 struct nvme_dsm_range *range;
598 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
601 return BLK_MQ_RQ_QUEUE_BUSY;
602 iod_list(req)[0] = (__le64 *)range;
605 range->cattr = cpu_to_le32(0);
606 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
607 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
609 memset(cmnd, 0, sizeof(*cmnd));
610 cmnd->dsm.opcode = nvme_cmd_dsm;
611 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
612 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
614 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
615 return BLK_MQ_RQ_QUEUE_OK;
619 * NOTE: ns is NULL when called on the admin queue.
621 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
622 const struct blk_mq_queue_data *bd)
624 struct nvme_ns *ns = hctx->queue->queuedata;
625 struct nvme_queue *nvmeq = hctx->driver_data;
626 struct nvme_dev *dev = nvmeq->dev;
627 struct request *req = bd->rq;
628 struct nvme_command cmnd;
629 int ret = BLK_MQ_RQ_QUEUE_OK;
632 * If formated with metadata, require the block layer provide a buffer
633 * unless this namespace is formated such that the metadata can be
634 * stripped/generated by the controller with PRACT=1.
636 if (ns && ns->ms && !blk_integrity_rq(req)) {
637 if (!(ns->pi_type && ns->ms == 8) &&
638 req->cmd_type != REQ_TYPE_DRV_PRIV) {
639 blk_mq_end_request(req, -EFAULT);
640 return BLK_MQ_RQ_QUEUE_OK;
644 ret = nvme_init_iod(req, dev);
648 if (req->cmd_flags & REQ_DISCARD) {
649 ret = nvme_setup_discard(nvmeq, ns, req, &cmnd);
651 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
652 memcpy(&cmnd, req->cmd, sizeof(cmnd));
653 else if (req->cmd_flags & REQ_FLUSH)
654 nvme_setup_flush(ns, &cmnd);
656 nvme_setup_rw(ns, req, &cmnd);
658 if (req->nr_phys_segments)
659 ret = nvme_map_data(dev, req, &cmnd);
665 cmnd.common.command_id = req->tag;
666 blk_mq_start_request(req);
668 spin_lock_irq(&nvmeq->q_lock);
669 __nvme_submit_cmd(nvmeq, &cmnd);
670 nvme_process_cq(nvmeq);
671 spin_unlock_irq(&nvmeq->q_lock);
672 return BLK_MQ_RQ_QUEUE_OK;
674 nvme_free_iod(dev, req);
678 static void nvme_complete_rq(struct request *req)
680 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
681 struct nvme_dev *dev = iod->nvmeq->dev;
684 nvme_unmap_data(dev, req);
686 if (unlikely(req->errors)) {
687 if (nvme_req_needs_retry(req, req->errors)) {
688 nvme_requeue_req(req);
692 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
695 error = nvme_error_status(req->errors);
698 if (unlikely(iod->aborted)) {
699 dev_warn(dev->ctrl.device,
700 "completing aborted command with status: %04x\n",
704 blk_mq_end_request(req, error);
707 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
711 head = nvmeq->cq_head;
712 phase = nvmeq->cq_phase;
715 struct nvme_completion cqe = nvmeq->cqes[head];
716 u16 status = le16_to_cpu(cqe.status);
719 if ((status & 1) != phase)
721 if (++head == nvmeq->q_depth) {
726 if (tag && *tag == cqe.command_id)
729 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
730 dev_warn(nvmeq->dev->ctrl.device,
731 "invalid id %d completed on queue %d\n",
732 cqe.command_id, le16_to_cpu(cqe.sq_id));
737 * AEN requests are special as they don't time out and can
738 * survive any kind of queue freeze and often don't respond to
739 * aborts. We don't even bother to allocate a struct request
740 * for them but rather special case them here.
742 if (unlikely(nvmeq->qid == 0 &&
743 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
744 nvme_complete_async_event(nvmeq->dev, &cqe);
748 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
749 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
750 memcpy(req->special, &cqe, sizeof(cqe));
751 blk_mq_complete_request(req, status >> 1);
755 /* If the controller ignores the cq head doorbell and continuously
756 * writes to the queue, it is theoretically possible to wrap around
757 * the queue twice and mistakenly return IRQ_NONE. Linux only
758 * requires that 0.1% of your interrupts are handled, so this isn't
761 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
764 if (likely(nvmeq->cq_vector >= 0))
765 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
766 nvmeq->cq_head = head;
767 nvmeq->cq_phase = phase;
772 static void nvme_process_cq(struct nvme_queue *nvmeq)
774 __nvme_process_cq(nvmeq, NULL);
777 static irqreturn_t nvme_irq(int irq, void *data)
780 struct nvme_queue *nvmeq = data;
781 spin_lock(&nvmeq->q_lock);
782 nvme_process_cq(nvmeq);
783 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
785 spin_unlock(&nvmeq->q_lock);
789 static irqreturn_t nvme_irq_check(int irq, void *data)
791 struct nvme_queue *nvmeq = data;
792 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
793 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
795 return IRQ_WAKE_THREAD;
798 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
800 struct nvme_queue *nvmeq = hctx->driver_data;
802 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
804 spin_lock_irq(&nvmeq->q_lock);
805 __nvme_process_cq(nvmeq, &tag);
806 spin_unlock_irq(&nvmeq->q_lock);
815 static void nvme_async_event_work(struct work_struct *work)
817 struct nvme_dev *dev = container_of(work, struct nvme_dev, async_work);
818 struct nvme_queue *nvmeq = dev->queues[0];
819 struct nvme_command c;
821 memset(&c, 0, sizeof(c));
822 c.common.opcode = nvme_admin_async_event;
824 spin_lock_irq(&nvmeq->q_lock);
825 while (dev->ctrl.event_limit > 0) {
826 c.common.command_id = NVME_AQ_BLKMQ_DEPTH +
827 --dev->ctrl.event_limit;
828 __nvme_submit_cmd(nvmeq, &c);
830 spin_unlock_irq(&nvmeq->q_lock);
833 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
835 struct nvme_command c;
837 memset(&c, 0, sizeof(c));
838 c.delete_queue.opcode = opcode;
839 c.delete_queue.qid = cpu_to_le16(id);
841 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
844 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
845 struct nvme_queue *nvmeq)
847 struct nvme_command c;
848 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
851 * Note: we (ab)use the fact the the prp fields survive if no data
852 * is attached to the request.
854 memset(&c, 0, sizeof(c));
855 c.create_cq.opcode = nvme_admin_create_cq;
856 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
857 c.create_cq.cqid = cpu_to_le16(qid);
858 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
859 c.create_cq.cq_flags = cpu_to_le16(flags);
860 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
862 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
865 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
866 struct nvme_queue *nvmeq)
868 struct nvme_command c;
869 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
872 * Note: we (ab)use the fact the the prp fields survive if no data
873 * is attached to the request.
875 memset(&c, 0, sizeof(c));
876 c.create_sq.opcode = nvme_admin_create_sq;
877 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
878 c.create_sq.sqid = cpu_to_le16(qid);
879 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
880 c.create_sq.sq_flags = cpu_to_le16(flags);
881 c.create_sq.cqid = cpu_to_le16(qid);
883 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
886 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
888 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
891 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
893 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
896 static void abort_endio(struct request *req, int error)
898 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
899 struct nvme_queue *nvmeq = iod->nvmeq;
900 u16 status = req->errors;
902 dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
903 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
904 blk_mq_free_request(req);
907 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
909 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
910 struct nvme_queue *nvmeq = iod->nvmeq;
911 struct nvme_dev *dev = nvmeq->dev;
912 struct request *abort_req;
913 struct nvme_command cmd;
916 * Shutdown immediately if controller times out while starting. The
917 * reset work will see the pci device disabled when it gets the forced
918 * cancellation error. All outstanding requests are completed on
919 * shutdown, so we return BLK_EH_HANDLED.
921 if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
922 dev_warn(dev->ctrl.device,
923 "I/O %d QID %d timeout, disable controller\n",
924 req->tag, nvmeq->qid);
925 nvme_dev_disable(dev, false);
926 req->errors = NVME_SC_CANCELLED;
927 return BLK_EH_HANDLED;
931 * Shutdown the controller immediately and schedule a reset if the
932 * command was already aborted once before and still hasn't been
933 * returned to the driver, or if this is the admin queue.
935 if (!nvmeq->qid || iod->aborted) {
936 dev_warn(dev->ctrl.device,
937 "I/O %d QID %d timeout, reset controller\n",
938 req->tag, nvmeq->qid);
939 nvme_dev_disable(dev, false);
940 queue_work(nvme_workq, &dev->reset_work);
943 * Mark the request as handled, since the inline shutdown
944 * forces all outstanding requests to complete.
946 req->errors = NVME_SC_CANCELLED;
947 return BLK_EH_HANDLED;
952 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
953 atomic_inc(&dev->ctrl.abort_limit);
954 return BLK_EH_RESET_TIMER;
957 memset(&cmd, 0, sizeof(cmd));
958 cmd.abort.opcode = nvme_admin_abort_cmd;
959 cmd.abort.cid = req->tag;
960 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
962 dev_warn(nvmeq->dev->ctrl.device,
963 "I/O %d QID %d timeout, aborting\n",
964 req->tag, nvmeq->qid);
966 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
968 if (IS_ERR(abort_req)) {
969 atomic_inc(&dev->ctrl.abort_limit);
970 return BLK_EH_RESET_TIMER;
973 abort_req->timeout = ADMIN_TIMEOUT;
974 abort_req->end_io_data = NULL;
975 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
978 * The aborted req will be completed on receiving the abort req.
979 * We enable the timer again. If hit twice, it'll cause a device reset,
980 * as the device then is in a faulty state.
982 return BLK_EH_RESET_TIMER;
985 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
987 struct nvme_queue *nvmeq = data;
990 if (!blk_mq_request_started(req))
993 dev_warn(nvmeq->dev->ctrl.device,
994 "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid);
996 status = NVME_SC_ABORT_REQ;
997 if (blk_queue_dying(req->q))
998 status |= NVME_SC_DNR;
999 blk_mq_complete_request(req, status);
1002 static void nvme_free_queue(struct nvme_queue *nvmeq)
1004 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1005 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1007 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1008 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1012 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1016 for (i = dev->queue_count - 1; i >= lowest; i--) {
1017 struct nvme_queue *nvmeq = dev->queues[i];
1019 dev->queues[i] = NULL;
1020 nvme_free_queue(nvmeq);
1025 * nvme_suspend_queue - put queue into suspended state
1026 * @nvmeq - queue to suspend
1028 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1032 spin_lock_irq(&nvmeq->q_lock);
1033 if (nvmeq->cq_vector == -1) {
1034 spin_unlock_irq(&nvmeq->q_lock);
1037 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1038 nvmeq->dev->online_queues--;
1039 nvmeq->cq_vector = -1;
1040 spin_unlock_irq(&nvmeq->q_lock);
1042 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1043 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1045 irq_set_affinity_hint(vector, NULL);
1046 free_irq(vector, nvmeq);
1051 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1053 spin_lock_irq(&nvmeq->q_lock);
1054 if (nvmeq->tags && *nvmeq->tags)
1055 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1056 spin_unlock_irq(&nvmeq->q_lock);
1059 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1061 struct nvme_queue *nvmeq = dev->queues[0];
1065 if (nvme_suspend_queue(nvmeq))
1069 nvme_shutdown_ctrl(&dev->ctrl);
1071 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1072 dev->bar + NVME_REG_CAP));
1074 spin_lock_irq(&nvmeq->q_lock);
1075 nvme_process_cq(nvmeq);
1076 spin_unlock_irq(&nvmeq->q_lock);
1079 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1082 int q_depth = dev->q_depth;
1083 unsigned q_size_aligned = roundup(q_depth * entry_size,
1084 dev->ctrl.page_size);
1086 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1087 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1088 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1089 q_depth = div_u64(mem_per_q, entry_size);
1092 * Ensure the reduced q_depth is above some threshold where it
1093 * would be better to map queues in system memory with the
1103 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1106 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1107 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1108 dev->ctrl.page_size);
1109 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1110 nvmeq->sq_cmds_io = dev->cmb + offset;
1112 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1113 &nvmeq->sq_dma_addr, GFP_KERNEL);
1114 if (!nvmeq->sq_cmds)
1121 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1124 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1128 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1129 &nvmeq->cq_dma_addr, GFP_KERNEL);
1133 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1136 nvmeq->q_dmadev = dev->dev;
1138 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1139 dev->ctrl.instance, qid);
1140 spin_lock_init(&nvmeq->q_lock);
1142 nvmeq->cq_phase = 1;
1143 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1144 nvmeq->q_depth = depth;
1146 nvmeq->cq_vector = -1;
1147 dev->queues[qid] = nvmeq;
1153 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1154 nvmeq->cq_dma_addr);
1160 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1163 if (use_threaded_interrupts)
1164 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1165 nvme_irq_check, nvme_irq, IRQF_SHARED,
1167 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1168 IRQF_SHARED, name, nvmeq);
1171 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1173 struct nvme_dev *dev = nvmeq->dev;
1175 spin_lock_irq(&nvmeq->q_lock);
1178 nvmeq->cq_phase = 1;
1179 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1180 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1181 dev->online_queues++;
1182 spin_unlock_irq(&nvmeq->q_lock);
1185 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1187 struct nvme_dev *dev = nvmeq->dev;
1190 nvmeq->cq_vector = qid - 1;
1191 result = adapter_alloc_cq(dev, qid, nvmeq);
1195 result = adapter_alloc_sq(dev, qid, nvmeq);
1199 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1203 nvme_init_queue(nvmeq, qid);
1207 adapter_delete_sq(dev, qid);
1209 adapter_delete_cq(dev, qid);
1213 static struct blk_mq_ops nvme_mq_admin_ops = {
1214 .queue_rq = nvme_queue_rq,
1215 .complete = nvme_complete_rq,
1216 .map_queue = blk_mq_map_queue,
1217 .init_hctx = nvme_admin_init_hctx,
1218 .exit_hctx = nvme_admin_exit_hctx,
1219 .init_request = nvme_admin_init_request,
1220 .timeout = nvme_timeout,
1223 static struct blk_mq_ops nvme_mq_ops = {
1224 .queue_rq = nvme_queue_rq,
1225 .complete = nvme_complete_rq,
1226 .map_queue = blk_mq_map_queue,
1227 .init_hctx = nvme_init_hctx,
1228 .init_request = nvme_init_request,
1229 .timeout = nvme_timeout,
1233 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1235 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1236 blk_cleanup_queue(dev->ctrl.admin_q);
1237 blk_mq_free_tag_set(&dev->admin_tagset);
1241 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1243 if (!dev->ctrl.admin_q) {
1244 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1245 dev->admin_tagset.nr_hw_queues = 1;
1248 * Subtract one to leave an empty queue entry for 'Full Queue'
1249 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1251 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1252 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1253 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1254 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1255 dev->admin_tagset.driver_data = dev;
1257 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1260 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1261 if (IS_ERR(dev->ctrl.admin_q)) {
1262 blk_mq_free_tag_set(&dev->admin_tagset);
1265 if (!blk_get_queue(dev->ctrl.admin_q)) {
1266 nvme_dev_remove_admin(dev);
1267 dev->ctrl.admin_q = NULL;
1271 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1276 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1280 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1281 struct nvme_queue *nvmeq;
1283 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1284 NVME_CAP_NSSRC(cap) : 0;
1286 if (dev->subsystem &&
1287 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1288 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1290 result = nvme_disable_ctrl(&dev->ctrl, cap);
1294 nvmeq = dev->queues[0];
1296 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1301 aqa = nvmeq->q_depth - 1;
1304 writel(aqa, dev->bar + NVME_REG_AQA);
1305 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1306 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1308 result = nvme_enable_ctrl(&dev->ctrl, cap);
1312 nvmeq->cq_vector = 0;
1313 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1315 nvmeq->cq_vector = -1;
1322 nvme_free_queues(dev, 0);
1326 static void nvme_watchdog_timer(unsigned long data)
1328 struct nvme_dev *dev = (struct nvme_dev *)data;
1329 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1332 * Skip controllers currently under reset.
1334 if (!work_pending(&dev->reset_work) && !work_busy(&dev->reset_work) &&
1335 ((csts & NVME_CSTS_CFS) ||
1336 (dev->subsystem && (csts & NVME_CSTS_NSSRO)))) {
1337 if (queue_work(nvme_workq, &dev->reset_work)) {
1339 "Failed status: 0x%x, reset controller.\n",
1345 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1348 static int nvme_create_io_queues(struct nvme_dev *dev)
1353 for (i = dev->queue_count; i <= dev->max_qid; i++) {
1354 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1360 max = min(dev->max_qid, dev->queue_count - 1);
1361 for (i = dev->online_queues; i <= max; i++) {
1362 ret = nvme_create_queue(dev->queues[i], i);
1364 nvme_free_queues(dev, i);
1370 * Ignore failing Create SQ/CQ commands, we can continue with less
1371 * than the desired aount of queues, and even a controller without
1372 * I/O queues an still be used to issue admin commands. This might
1373 * be useful to upgrade a buggy firmware for example.
1375 return ret >= 0 ? 0 : ret;
1378 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1380 u64 szu, size, offset;
1382 resource_size_t bar_size;
1383 struct pci_dev *pdev = to_pci_dev(dev->dev);
1385 dma_addr_t dma_addr;
1390 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1391 if (!(NVME_CMB_SZ(dev->cmbsz)))
1394 cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1396 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1397 size = szu * NVME_CMB_SZ(dev->cmbsz);
1398 offset = szu * NVME_CMB_OFST(cmbloc);
1399 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1401 if (offset > bar_size)
1405 * Controllers may support a CMB size larger than their BAR,
1406 * for example, due to being behind a bridge. Reduce the CMB to
1407 * the reported size of the BAR
1409 if (size > bar_size - offset)
1410 size = bar_size - offset;
1412 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1413 cmb = ioremap_wc(dma_addr, size);
1417 dev->cmb_dma_addr = dma_addr;
1418 dev->cmb_size = size;
1422 static inline void nvme_release_cmb(struct nvme_dev *dev)
1430 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1432 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1435 static int nvme_setup_io_queues(struct nvme_dev *dev)
1437 struct nvme_queue *adminq = dev->queues[0];
1438 struct pci_dev *pdev = to_pci_dev(dev->dev);
1439 int result, i, vecs, nr_io_queues, size;
1441 nr_io_queues = num_possible_cpus();
1442 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1447 * Degraded controllers might return an error when setting the queue
1448 * count. We still want to be able to bring them online and offer
1449 * access to the admin queue, as that might be only way to fix them up.
1452 dev_err(dev->ctrl.device,
1453 "Could not set queue count (%d)\n", result);
1458 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1459 result = nvme_cmb_qdepth(dev, nr_io_queues,
1460 sizeof(struct nvme_command));
1462 dev->q_depth = result;
1464 nvme_release_cmb(dev);
1467 size = db_bar_size(dev, nr_io_queues);
1471 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1474 if (!--nr_io_queues)
1476 size = db_bar_size(dev, nr_io_queues);
1478 dev->dbs = dev->bar + 4096;
1479 adminq->q_db = dev->dbs;
1482 /* Deregister the admin queue's interrupt */
1483 free_irq(dev->entry[0].vector, adminq);
1486 * If we enable msix early due to not intx, disable it again before
1487 * setting up the full range we need.
1490 pci_disable_msix(pdev);
1492 for (i = 0; i < nr_io_queues; i++)
1493 dev->entry[i].entry = i;
1494 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1496 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1500 for (i = 0; i < vecs; i++)
1501 dev->entry[i].vector = i + pdev->irq;
1506 * Should investigate if there's a performance win from allocating
1507 * more queues than interrupt vectors; it might allow the submission
1508 * path to scale better, even if the receive path is limited by the
1509 * number of interrupts.
1511 nr_io_queues = vecs;
1512 dev->max_qid = nr_io_queues;
1514 result = queue_request_irq(dev, adminq, adminq->irqname);
1516 adminq->cq_vector = -1;
1519 return nvme_create_io_queues(dev);
1522 nvme_free_queues(dev, 1);
1526 static void nvme_set_irq_hints(struct nvme_dev *dev)
1528 struct nvme_queue *nvmeq;
1531 for (i = 0; i < dev->online_queues; i++) {
1532 nvmeq = dev->queues[i];
1534 if (!nvmeq->tags || !(*nvmeq->tags))
1537 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1538 blk_mq_tags_cpumask(*nvmeq->tags));
1542 static void nvme_dev_scan(struct work_struct *work)
1544 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1546 if (!dev->tagset.tags)
1548 nvme_scan_namespaces(&dev->ctrl);
1549 nvme_set_irq_hints(dev);
1552 static void nvme_del_queue_end(struct request *req, int error)
1554 struct nvme_queue *nvmeq = req->end_io_data;
1556 blk_mq_free_request(req);
1557 complete(&nvmeq->dev->ioq_wait);
1560 static void nvme_del_cq_end(struct request *req, int error)
1562 struct nvme_queue *nvmeq = req->end_io_data;
1565 unsigned long flags;
1567 spin_lock_irqsave(&nvmeq->q_lock, flags);
1568 nvme_process_cq(nvmeq);
1569 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1572 nvme_del_queue_end(req, error);
1575 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1577 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1578 struct request *req;
1579 struct nvme_command cmd;
1581 memset(&cmd, 0, sizeof(cmd));
1582 cmd.delete_queue.opcode = opcode;
1583 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1585 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1587 return PTR_ERR(req);
1589 req->timeout = ADMIN_TIMEOUT;
1590 req->end_io_data = nvmeq;
1592 blk_execute_rq_nowait(q, NULL, req, false,
1593 opcode == nvme_admin_delete_cq ?
1594 nvme_del_cq_end : nvme_del_queue_end);
1598 static void nvme_disable_io_queues(struct nvme_dev *dev)
1601 unsigned long timeout;
1602 u8 opcode = nvme_admin_delete_sq;
1604 for (pass = 0; pass < 2; pass++) {
1605 int sent = 0, i = dev->queue_count - 1;
1607 reinit_completion(&dev->ioq_wait);
1609 timeout = ADMIN_TIMEOUT;
1610 for (; i > 0; i--) {
1611 struct nvme_queue *nvmeq = dev->queues[i];
1614 nvme_suspend_queue(nvmeq);
1615 if (nvme_delete_queue(nvmeq, opcode))
1620 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1626 opcode = nvme_admin_delete_cq;
1631 * Return: error value if an error occurred setting up the queues or calling
1632 * Identify Device. 0 if these succeeded, even if adding some of the
1633 * namespaces failed. At the moment, these failures are silent. TBD which
1634 * failures should be reported.
1636 static int nvme_dev_add(struct nvme_dev *dev)
1638 if (!dev->ctrl.tagset) {
1639 dev->tagset.ops = &nvme_mq_ops;
1640 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1641 dev->tagset.timeout = NVME_IO_TIMEOUT;
1642 dev->tagset.numa_node = dev_to_node(dev->dev);
1643 dev->tagset.queue_depth =
1644 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1645 dev->tagset.cmd_size = nvme_cmd_size(dev);
1646 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1647 dev->tagset.driver_data = dev;
1649 if (blk_mq_alloc_tag_set(&dev->tagset))
1651 dev->ctrl.tagset = &dev->tagset;
1653 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1655 /* Free previously allocated queues that are no longer usable */
1656 nvme_free_queues(dev, dev->online_queues);
1659 queue_work(nvme_workq, &dev->scan_work);
1663 static int nvme_dev_map(struct nvme_dev *dev)
1666 int bars, result = -ENOMEM;
1667 struct pci_dev *pdev = to_pci_dev(dev->dev);
1669 if (pci_enable_device_mem(pdev))
1672 dev->entry[0].vector = pdev->irq;
1673 pci_set_master(pdev);
1674 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1678 if (pci_request_selected_regions(pdev, bars, "nvme"))
1681 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1682 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1685 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1689 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1695 * Some devices don't advertse INTx interrupts, pre-enable a single
1696 * MSIX vec for setup. We'll adjust this later.
1699 result = pci_enable_msix(pdev, dev->entry, 1);
1704 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1706 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1707 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1708 dev->dbs = dev->bar + 4096;
1711 * Temporary fix for the Apple controller found in the MacBook8,1 and
1712 * some MacBook7,1 to avoid controller resets and data loss.
1714 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1716 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1717 "queue depth=%u to work around controller resets\n",
1721 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1722 dev->cmb = nvme_map_cmb(dev);
1724 pci_enable_pcie_error_reporting(pdev);
1725 pci_save_state(pdev);
1732 pci_release_regions(pdev);
1734 pci_disable_device(pdev);
1738 static void nvme_dev_unmap(struct nvme_dev *dev)
1740 struct pci_dev *pdev = to_pci_dev(dev->dev);
1742 if (pdev->msi_enabled)
1743 pci_disable_msi(pdev);
1744 else if (pdev->msix_enabled)
1745 pci_disable_msix(pdev);
1750 pci_release_regions(pdev);
1753 if (pci_is_enabled(pdev)) {
1754 pci_disable_pcie_error_reporting(pdev);
1755 pci_disable_device(pdev);
1759 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1764 del_timer_sync(&dev->watchdog_timer);
1766 mutex_lock(&dev->shutdown_lock);
1768 nvme_stop_queues(&dev->ctrl);
1769 csts = readl(dev->bar + NVME_REG_CSTS);
1771 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1772 for (i = dev->queue_count - 1; i >= 0; i--) {
1773 struct nvme_queue *nvmeq = dev->queues[i];
1774 nvme_suspend_queue(nvmeq);
1777 nvme_disable_io_queues(dev);
1778 nvme_disable_admin_queue(dev, shutdown);
1780 nvme_dev_unmap(dev);
1782 for (i = dev->queue_count - 1; i >= 0; i--)
1783 nvme_clear_queue(dev->queues[i]);
1784 mutex_unlock(&dev->shutdown_lock);
1787 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1789 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1790 PAGE_SIZE, PAGE_SIZE, 0);
1791 if (!dev->prp_page_pool)
1794 /* Optimisation for I/Os between 4k and 128k */
1795 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1797 if (!dev->prp_small_pool) {
1798 dma_pool_destroy(dev->prp_page_pool);
1804 static void nvme_release_prp_pools(struct nvme_dev *dev)
1806 dma_pool_destroy(dev->prp_page_pool);
1807 dma_pool_destroy(dev->prp_small_pool);
1810 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1812 struct nvme_dev *dev = to_nvme_dev(ctrl);
1814 put_device(dev->dev);
1815 if (dev->tagset.tags)
1816 blk_mq_free_tag_set(&dev->tagset);
1817 if (dev->ctrl.admin_q)
1818 blk_put_queue(dev->ctrl.admin_q);
1824 static void nvme_reset_work(struct work_struct *work)
1826 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1829 if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
1833 * If we're called to reset a live controller first shut it down before
1837 nvme_dev_disable(dev, false);
1839 set_bit(NVME_CTRL_RESETTING, &dev->flags);
1841 result = nvme_dev_map(dev);
1845 result = nvme_configure_admin_queue(dev);
1849 nvme_init_queue(dev->queues[0], 0);
1850 result = nvme_alloc_admin_tags(dev);
1854 result = nvme_init_identify(&dev->ctrl);
1858 result = nvme_setup_io_queues(dev);
1862 dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1863 queue_work(nvme_workq, &dev->async_work);
1865 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1868 * Keep the controller around but remove all namespaces if we don't have
1869 * any working I/O queue.
1871 if (dev->online_queues < 2) {
1872 dev_warn(dev->ctrl.device, "IO queues not created\n");
1873 nvme_remove_namespaces(&dev->ctrl);
1875 nvme_start_queues(&dev->ctrl);
1879 clear_bit(NVME_CTRL_RESETTING, &dev->flags);
1883 nvme_dev_remove_admin(dev);
1884 blk_put_queue(dev->ctrl.admin_q);
1885 dev->ctrl.admin_q = NULL;
1886 dev->queues[0]->tags = NULL;
1888 nvme_disable_admin_queue(dev, false);
1890 nvme_dev_unmap(dev);
1892 nvme_remove_dead_ctrl(dev);
1895 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1897 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1898 struct pci_dev *pdev = to_pci_dev(dev->dev);
1900 if (pci_get_drvdata(pdev))
1901 pci_stop_and_remove_bus_device_locked(pdev);
1902 nvme_put_ctrl(&dev->ctrl);
1905 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
1907 dev_warn(dev->ctrl.device, "Removing after probe failure\n");
1908 kref_get(&dev->ctrl.kref);
1909 if (!schedule_work(&dev->remove_work))
1910 nvme_put_ctrl(&dev->ctrl);
1913 static int nvme_reset(struct nvme_dev *dev)
1915 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1918 if (!queue_work(nvme_workq, &dev->reset_work))
1921 flush_work(&dev->reset_work);
1925 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1927 *val = readl(to_nvme_dev(ctrl)->bar + off);
1931 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1933 writel(val, to_nvme_dev(ctrl)->bar + off);
1937 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1939 *val = readq(to_nvme_dev(ctrl)->bar + off);
1943 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
1945 struct nvme_dev *dev = to_nvme_dev(ctrl);
1947 return !dev->bar || dev->online_queues < 2;
1950 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1952 return nvme_reset(to_nvme_dev(ctrl));
1955 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1956 .module = THIS_MODULE,
1957 .reg_read32 = nvme_pci_reg_read32,
1958 .reg_write32 = nvme_pci_reg_write32,
1959 .reg_read64 = nvme_pci_reg_read64,
1960 .io_incapable = nvme_pci_io_incapable,
1961 .reset_ctrl = nvme_pci_reset_ctrl,
1962 .free_ctrl = nvme_pci_free_ctrl,
1965 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1967 int node, result = -ENOMEM;
1968 struct nvme_dev *dev;
1970 node = dev_to_node(&pdev->dev);
1971 if (node == NUMA_NO_NODE)
1972 set_dev_node(&pdev->dev, 0);
1974 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1977 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
1981 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1986 dev->dev = get_device(&pdev->dev);
1987 pci_set_drvdata(pdev, dev);
1989 INIT_WORK(&dev->scan_work, nvme_dev_scan);
1990 INIT_WORK(&dev->reset_work, nvme_reset_work);
1991 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1992 INIT_WORK(&dev->async_work, nvme_async_event_work);
1993 setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1994 (unsigned long)dev);
1995 mutex_init(&dev->shutdown_lock);
1996 init_completion(&dev->ioq_wait);
1998 result = nvme_setup_prp_pools(dev);
2002 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2007 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2009 queue_work(nvme_workq, &dev->reset_work);
2013 nvme_release_prp_pools(dev);
2015 put_device(dev->dev);
2023 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2025 struct nvme_dev *dev = pci_get_drvdata(pdev);
2028 nvme_dev_disable(dev, false);
2030 queue_work(nvme_workq, &dev->reset_work);
2033 static void nvme_shutdown(struct pci_dev *pdev)
2035 struct nvme_dev *dev = pci_get_drvdata(pdev);
2036 nvme_dev_disable(dev, true);
2039 static void nvme_remove(struct pci_dev *pdev)
2041 struct nvme_dev *dev = pci_get_drvdata(pdev);
2043 del_timer_sync(&dev->watchdog_timer);
2045 pci_set_drvdata(pdev, NULL);
2046 flush_work(&dev->async_work);
2047 flush_work(&dev->reset_work);
2048 flush_work(&dev->scan_work);
2049 nvme_remove_namespaces(&dev->ctrl);
2050 nvme_uninit_ctrl(&dev->ctrl);
2051 nvme_dev_disable(dev, true);
2052 nvme_dev_remove_admin(dev);
2053 nvme_free_queues(dev, 0);
2054 nvme_release_cmb(dev);
2055 nvme_release_prp_pools(dev);
2056 nvme_put_ctrl(&dev->ctrl);
2059 #ifdef CONFIG_PM_SLEEP
2060 static int nvme_suspend(struct device *dev)
2062 struct pci_dev *pdev = to_pci_dev(dev);
2063 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2065 nvme_dev_disable(ndev, true);
2069 static int nvme_resume(struct device *dev)
2071 struct pci_dev *pdev = to_pci_dev(dev);
2072 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2074 queue_work(nvme_workq, &ndev->reset_work);
2079 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2081 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2082 pci_channel_state_t state)
2084 struct nvme_dev *dev = pci_get_drvdata(pdev);
2087 * A frozen channel requires a reset. When detected, this method will
2088 * shutdown the controller to quiesce. The controller will be restarted
2089 * after the slot reset through driver's slot_reset callback.
2091 dev_warn(dev->ctrl.device, "error detected: state:%d\n", state);
2093 case pci_channel_io_normal:
2094 return PCI_ERS_RESULT_CAN_RECOVER;
2095 case pci_channel_io_frozen:
2096 nvme_dev_disable(dev, false);
2097 return PCI_ERS_RESULT_NEED_RESET;
2098 case pci_channel_io_perm_failure:
2099 return PCI_ERS_RESULT_DISCONNECT;
2101 return PCI_ERS_RESULT_NEED_RESET;
2104 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2106 struct nvme_dev *dev = pci_get_drvdata(pdev);
2108 dev_info(dev->ctrl.device, "restart after slot reset\n");
2109 pci_restore_state(pdev);
2110 queue_work(nvme_workq, &dev->reset_work);
2111 return PCI_ERS_RESULT_RECOVERED;
2114 static void nvme_error_resume(struct pci_dev *pdev)
2116 pci_cleanup_aer_uncorrect_error_status(pdev);
2119 static const struct pci_error_handlers nvme_err_handler = {
2120 .error_detected = nvme_error_detected,
2121 .slot_reset = nvme_slot_reset,
2122 .resume = nvme_error_resume,
2123 .reset_notify = nvme_reset_notify,
2126 /* Move to pci_ids.h later */
2127 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2129 static const struct pci_device_id nvme_id_table[] = {
2130 { PCI_VDEVICE(INTEL, 0x0953),
2131 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2132 NVME_QUIRK_DISCARD_ZEROES, },
2133 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2134 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2135 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2136 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2139 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2141 static struct pci_driver nvme_driver = {
2143 .id_table = nvme_id_table,
2144 .probe = nvme_probe,
2145 .remove = nvme_remove,
2146 .shutdown = nvme_shutdown,
2148 .pm = &nvme_dev_pm_ops,
2150 .err_handler = &nvme_err_handler,
2153 static int __init nvme_init(void)
2157 nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2161 result = pci_register_driver(&nvme_driver);
2163 destroy_workqueue(nvme_workq);
2167 static void __exit nvme_exit(void)
2169 pci_unregister_driver(&nvme_driver);
2170 destroy_workqueue(nvme_workq);
2174 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2175 MODULE_LICENSE("GPL");
2176 MODULE_VERSION("1.0");
2177 module_init(nvme_init);
2178 module_exit(nvme_exit);