2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/async.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
33 #include <linux/pci-p2pdma.h>
38 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
39 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
41 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
44 * These can be higher, but we need to ensure that any command doesn't
45 * require an sg allocation that needs more than a page of data.
47 #define NVME_MAX_KB_SZ 4096
48 #define NVME_MAX_SEGS 127
50 static int use_threaded_interrupts;
51 module_param(use_threaded_interrupts, int, 0);
53 static bool use_cmb_sqes = true;
54 module_param(use_cmb_sqes, bool, 0444);
55 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
57 static unsigned int max_host_mem_size_mb = 128;
58 module_param(max_host_mem_size_mb, uint, 0444);
59 MODULE_PARM_DESC(max_host_mem_size_mb,
60 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
62 static unsigned int sgl_threshold = SZ_32K;
63 module_param(sgl_threshold, uint, 0644);
64 MODULE_PARM_DESC(sgl_threshold,
65 "Use SGLs when average request segment size is larger or equal to "
66 "this size. Use 0 to disable SGLs.");
68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
74 static int io_queue_depth = 1024;
75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
78 static int queue_count_set(const char *val, const struct kernel_param *kp);
79 static const struct kernel_param_ops queue_count_ops = {
80 .set = queue_count_set,
84 static int write_queues;
85 module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
86 MODULE_PARM_DESC(write_queues,
87 "Number of queues to use for writes. If not set, reads and writes "
88 "will share a queue set.");
90 static int poll_queues = 0;
91 module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
92 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
97 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
98 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
101 * Represents an NVM Express device. Each nvme_dev is a PCI function.
104 struct nvme_queue *queues;
105 struct blk_mq_tag_set tagset;
106 struct blk_mq_tag_set admin_tagset;
109 struct dma_pool *prp_page_pool;
110 struct dma_pool *prp_small_pool;
111 unsigned online_queues;
113 unsigned io_queues[HCTX_MAX_TYPES];
114 unsigned int num_vecs;
118 unsigned long bar_mapped_size;
119 struct work_struct remove_work;
120 struct mutex shutdown_lock;
126 struct nvme_ctrl ctrl;
128 mempool_t *iod_mempool;
130 /* shadow doorbell buffer support: */
132 dma_addr_t dbbuf_dbs_dma_addr;
134 dma_addr_t dbbuf_eis_dma_addr;
136 /* host memory buffer support: */
138 u32 nr_host_mem_descs;
139 dma_addr_t host_mem_descs_dma;
140 struct nvme_host_mem_buf_desc *host_mem_descs;
141 void **host_mem_desc_bufs;
144 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
148 ret = kstrtoint(val, 10, &n);
149 if (ret != 0 || n < 2)
152 return param_set_int(val, kp);
155 static int queue_count_set(const char *val, const struct kernel_param *kp)
159 ret = kstrtoint(val, 10, &n);
160 if (n > num_possible_cpus())
161 n = num_possible_cpus();
163 return param_set_int(val, kp);
166 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
168 return qid * 2 * stride;
171 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
173 return (qid * 2 + 1) * stride;
176 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
178 return container_of(ctrl, struct nvme_dev, ctrl);
182 * An NVM Express queue. Each device has at least two (one for admin
183 * commands and one for I/O commands).
186 struct device *q_dmadev;
187 struct nvme_dev *dev;
189 struct nvme_command *sq_cmds;
190 /* only used for poll queues: */
191 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
192 volatile struct nvme_completion *cqes;
193 struct blk_mq_tags **tags;
194 dma_addr_t sq_dma_addr;
195 dma_addr_t cq_dma_addr;
206 #define NVMEQ_ENABLED 0
207 #define NVMEQ_SQ_CMB 1
208 #define NVMEQ_DELETE_ERROR 2
213 struct completion delete_done;
217 * The nvme_iod describes the data in an I/O, including the list of PRP
218 * entries. You can't see it in this data structure because C doesn't let
219 * me express that. Use nvme_init_iod to ensure there's enough space
220 * allocated to store the PRP list.
223 struct nvme_request req;
224 struct nvme_queue *nvmeq;
227 int npages; /* In the PRP list. 0 means small pool in use */
228 int nents; /* Used in scatterlist */
229 int length; /* Of data, in bytes */
230 dma_addr_t first_dma;
231 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
232 struct scatterlist *sg;
233 struct scatterlist inline_sg[0];
237 * Check we didin't inadvertently grow the command struct
239 static inline void _nvme_check_size(void)
241 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
242 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
243 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
244 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
245 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
246 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
247 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
248 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
249 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
250 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
251 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
252 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
253 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
256 static unsigned int max_io_queues(void)
258 return num_possible_cpus() + write_queues + poll_queues;
261 static unsigned int max_queue_count(void)
263 /* IO queues + admin queue */
264 return 1 + max_io_queues();
267 static inline unsigned int nvme_dbbuf_size(u32 stride)
269 return (max_queue_count() * 8 * stride);
272 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
274 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
279 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
280 &dev->dbbuf_dbs_dma_addr,
284 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
285 &dev->dbbuf_eis_dma_addr,
287 if (!dev->dbbuf_eis) {
288 dma_free_coherent(dev->dev, mem_size,
289 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
290 dev->dbbuf_dbs = NULL;
297 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
299 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
301 if (dev->dbbuf_dbs) {
302 dma_free_coherent(dev->dev, mem_size,
303 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
304 dev->dbbuf_dbs = NULL;
306 if (dev->dbbuf_eis) {
307 dma_free_coherent(dev->dev, mem_size,
308 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
309 dev->dbbuf_eis = NULL;
313 static void nvme_dbbuf_init(struct nvme_dev *dev,
314 struct nvme_queue *nvmeq, int qid)
316 if (!dev->dbbuf_dbs || !qid)
319 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
320 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
321 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
322 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
325 static void nvme_dbbuf_set(struct nvme_dev *dev)
327 struct nvme_command c;
332 memset(&c, 0, sizeof(c));
333 c.dbbuf.opcode = nvme_admin_dbbuf;
334 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
335 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
337 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
338 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
339 /* Free memory and continue on */
340 nvme_dbbuf_dma_free(dev);
344 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
346 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349 /* Update dbbuf and return true if an MMIO is required */
350 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
351 volatile u32 *dbbuf_ei)
357 * Ensure that the queue is written before updating
358 * the doorbell in memory
362 old_value = *dbbuf_db;
366 * Ensure that the doorbell is updated before reading the event
367 * index from memory. The controller needs to provide similar
368 * ordering to ensure the envent index is updated before reading
373 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
381 * Max size of iod being embedded in the request payload
383 #define NVME_INT_PAGES 2
384 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
387 * Will slightly overestimate the number of pages needed. This is OK
388 * as it only leads to a small amount of wasted memory for the lifetime of
391 static int nvme_npages(unsigned size, struct nvme_dev *dev)
393 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
394 dev->ctrl.page_size);
395 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
399 * Calculates the number of pages needed for the SGL segments. For example a 4k
400 * page can accommodate 256 SGL descriptors.
402 static int nvme_pci_npages_sgl(unsigned int num_seg)
404 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
407 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
408 unsigned int size, unsigned int nseg, bool use_sgl)
413 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
415 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
417 return alloc_size + sizeof(struct scatterlist) * nseg;
420 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
422 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
423 NVME_INT_BYTES(dev), NVME_INT_PAGES,
426 return sizeof(struct nvme_iod) + alloc_size;
429 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
430 unsigned int hctx_idx)
432 struct nvme_dev *dev = data;
433 struct nvme_queue *nvmeq = &dev->queues[0];
435 WARN_ON(hctx_idx != 0);
436 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
437 WARN_ON(nvmeq->tags);
439 hctx->driver_data = nvmeq;
440 nvmeq->tags = &dev->admin_tagset.tags[0];
444 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
446 struct nvme_queue *nvmeq = hctx->driver_data;
451 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
452 unsigned int hctx_idx)
454 struct nvme_dev *dev = data;
455 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
458 nvmeq->tags = &dev->tagset.tags[hctx_idx];
460 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
461 hctx->driver_data = nvmeq;
465 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
466 unsigned int hctx_idx, unsigned int numa_node)
468 struct nvme_dev *dev = set->driver_data;
469 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
470 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
471 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
476 nvme_req(req)->ctrl = &dev->ctrl;
480 static int queue_irq_offset(struct nvme_dev *dev)
482 /* if we have more than 1 vec, admin queue offsets us by 1 */
483 if (dev->num_vecs > 1)
489 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
491 struct nvme_dev *dev = set->driver_data;
494 offset = queue_irq_offset(dev);
495 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
496 struct blk_mq_queue_map *map = &set->map[i];
498 map->nr_queues = dev->io_queues[i];
499 if (!map->nr_queues) {
500 BUG_ON(i == HCTX_TYPE_DEFAULT);
505 * The poll queue(s) doesn't have an IRQ (and hence IRQ
506 * affinity), so use the regular blk-mq cpu mapping
508 map->queue_offset = qoff;
509 if (i != HCTX_TYPE_POLL)
510 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
512 blk_mq_map_queues(map);
513 qoff += map->nr_queues;
514 offset += map->nr_queues;
521 * Write sq tail if we are asked to, or if the next command would wrap.
523 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
526 u16 next_tail = nvmeq->sq_tail + 1;
528 if (next_tail == nvmeq->q_depth)
530 if (next_tail != nvmeq->last_sq_tail)
534 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
535 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
536 writel(nvmeq->sq_tail, nvmeq->q_db);
537 nvmeq->last_sq_tail = nvmeq->sq_tail;
541 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
542 * @nvmeq: The queue to use
543 * @cmd: The command to send
544 * @write_sq: whether to write to the SQ doorbell
546 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
549 spin_lock(&nvmeq->sq_lock);
550 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
551 if (++nvmeq->sq_tail == nvmeq->q_depth)
553 nvme_write_sq_db(nvmeq, write_sq);
554 spin_unlock(&nvmeq->sq_lock);
557 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
559 struct nvme_queue *nvmeq = hctx->driver_data;
561 spin_lock(&nvmeq->sq_lock);
562 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
563 nvme_write_sq_db(nvmeq, true);
564 spin_unlock(&nvmeq->sq_lock);
567 static void **nvme_pci_iod_list(struct request *req)
569 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
570 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
573 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
575 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
576 int nseg = blk_rq_nr_phys_segments(req);
577 unsigned int avg_seg_size;
582 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
584 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
586 if (!iod->nvmeq->qid)
588 if (!sgl_threshold || avg_seg_size < sgl_threshold)
593 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
595 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
596 int nseg = blk_rq_nr_phys_segments(rq);
597 unsigned int size = blk_rq_payload_bytes(rq);
599 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
601 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
602 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
604 return BLK_STS_RESOURCE;
606 iod->sg = iod->inline_sg;
617 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
619 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
620 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
621 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
625 if (iod->npages == 0)
626 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
629 for (i = 0; i < iod->npages; i++) {
630 void *addr = nvme_pci_iod_list(req)[i];
633 struct nvme_sgl_desc *sg_list = addr;
636 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
638 __le64 *prp_list = addr;
640 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
643 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
644 dma_addr = next_dma_addr;
647 if (iod->sg != iod->inline_sg)
648 mempool_free(iod->sg, dev->iod_mempool);
651 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
654 struct scatterlist *sg;
656 for_each_sg(sgl, sg, nents, i) {
657 dma_addr_t phys = sg_phys(sg);
658 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
659 "dma_address:%pad dma_length:%d\n",
660 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
665 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
666 struct request *req, struct nvme_rw_command *cmnd)
668 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
669 struct dma_pool *pool;
670 int length = blk_rq_payload_bytes(req);
671 struct scatterlist *sg = iod->sg;
672 int dma_len = sg_dma_len(sg);
673 u64 dma_addr = sg_dma_address(sg);
674 u32 page_size = dev->ctrl.page_size;
675 int offset = dma_addr & (page_size - 1);
677 void **list = nvme_pci_iod_list(req);
681 length -= (page_size - offset);
687 dma_len -= (page_size - offset);
689 dma_addr += (page_size - offset);
692 dma_addr = sg_dma_address(sg);
693 dma_len = sg_dma_len(sg);
696 if (length <= page_size) {
697 iod->first_dma = dma_addr;
701 nprps = DIV_ROUND_UP(length, page_size);
702 if (nprps <= (256 / 8)) {
703 pool = dev->prp_small_pool;
706 pool = dev->prp_page_pool;
710 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
712 iod->first_dma = dma_addr;
714 return BLK_STS_RESOURCE;
717 iod->first_dma = prp_dma;
720 if (i == page_size >> 3) {
721 __le64 *old_prp_list = prp_list;
722 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
724 return BLK_STS_RESOURCE;
725 list[iod->npages++] = prp_list;
726 prp_list[0] = old_prp_list[i - 1];
727 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
730 prp_list[i++] = cpu_to_le64(dma_addr);
731 dma_len -= page_size;
732 dma_addr += page_size;
738 if (unlikely(dma_len < 0))
741 dma_addr = sg_dma_address(sg);
742 dma_len = sg_dma_len(sg);
746 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
747 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
752 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
753 "Invalid SGL for payload:%d nents:%d\n",
754 blk_rq_payload_bytes(req), iod->nents);
755 return BLK_STS_IOERR;
758 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
759 struct scatterlist *sg)
761 sge->addr = cpu_to_le64(sg_dma_address(sg));
762 sge->length = cpu_to_le32(sg_dma_len(sg));
763 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
766 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
767 dma_addr_t dma_addr, int entries)
769 sge->addr = cpu_to_le64(dma_addr);
770 if (entries < SGES_PER_PAGE) {
771 sge->length = cpu_to_le32(entries * sizeof(*sge));
772 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
774 sge->length = cpu_to_le32(PAGE_SIZE);
775 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
779 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
780 struct request *req, struct nvme_rw_command *cmd, int entries)
782 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
783 struct dma_pool *pool;
784 struct nvme_sgl_desc *sg_list;
785 struct scatterlist *sg = iod->sg;
789 /* setting the transfer type as SGL */
790 cmd->flags = NVME_CMD_SGL_METABUF;
793 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
797 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
798 pool = dev->prp_small_pool;
801 pool = dev->prp_page_pool;
805 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
808 return BLK_STS_RESOURCE;
811 nvme_pci_iod_list(req)[0] = sg_list;
812 iod->first_dma = sgl_dma;
814 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
817 if (i == SGES_PER_PAGE) {
818 struct nvme_sgl_desc *old_sg_desc = sg_list;
819 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
821 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
823 return BLK_STS_RESOURCE;
826 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
827 sg_list[i++] = *link;
828 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
831 nvme_pci_sgl_set_data(&sg_list[i++], sg);
833 } while (--entries > 0);
838 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
839 struct nvme_command *cmnd)
841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
842 struct request_queue *q = req->q;
843 enum dma_data_direction dma_dir = rq_data_dir(req) ?
844 DMA_TO_DEVICE : DMA_FROM_DEVICE;
845 blk_status_t ret = BLK_STS_IOERR;
848 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
849 iod->nents = blk_rq_map_sg(q, req, iod->sg);
853 ret = BLK_STS_RESOURCE;
855 if (is_pci_p2pdma_page(sg_page(iod->sg)))
856 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
859 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
860 dma_dir, DMA_ATTR_NO_WARN);
865 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
867 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
869 if (ret != BLK_STS_OK)
873 if (blk_integrity_rq(req)) {
874 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
877 sg_init_table(&iod->meta_sg, 1);
878 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
881 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
884 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
890 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
895 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
897 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
898 enum dma_data_direction dma_dir = rq_data_dir(req) ?
899 DMA_TO_DEVICE : DMA_FROM_DEVICE;
902 /* P2PDMA requests do not need to be unmapped */
903 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
904 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
906 if (blk_integrity_rq(req))
907 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
910 nvme_cleanup_cmd(req);
911 nvme_free_iod(dev, req);
915 * NOTE: ns is NULL when called on the admin queue.
917 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
918 const struct blk_mq_queue_data *bd)
920 struct nvme_ns *ns = hctx->queue->queuedata;
921 struct nvme_queue *nvmeq = hctx->driver_data;
922 struct nvme_dev *dev = nvmeq->dev;
923 struct request *req = bd->rq;
924 struct nvme_command cmnd;
928 * We should not need to do this, but we're still using this to
929 * ensure we can drain requests on a dying queue.
931 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
932 return BLK_STS_IOERR;
934 ret = nvme_setup_cmd(ns, req, &cmnd);
938 ret = nvme_init_iod(req, dev);
942 if (blk_rq_nr_phys_segments(req)) {
943 ret = nvme_map_data(dev, req, &cmnd);
945 goto out_cleanup_iod;
948 blk_mq_start_request(req);
949 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
952 nvme_free_iod(dev, req);
954 nvme_cleanup_cmd(req);
958 static void nvme_pci_complete_rq(struct request *req)
960 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
962 nvme_unmap_data(iod->nvmeq->dev, req);
963 nvme_complete_rq(req);
966 /* We read the CQE phase first to check if the rest of the entry is valid */
967 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
969 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
973 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
975 u16 head = nvmeq->cq_head;
977 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
979 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
982 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
984 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
987 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
988 dev_warn(nvmeq->dev->ctrl.device,
989 "invalid id %d completed on queue %d\n",
990 cqe->command_id, le16_to_cpu(cqe->sq_id));
995 * AEN requests are special as they don't time out and can
996 * survive any kind of queue freeze and often don't respond to
997 * aborts. We don't even bother to allocate a struct request
998 * for them but rather special case them here.
1000 if (unlikely(nvmeq->qid == 0 &&
1001 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
1002 nvme_complete_async_event(&nvmeq->dev->ctrl,
1003 cqe->status, &cqe->result);
1007 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
1008 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1009 nvme_end_request(req, cqe->status, cqe->result);
1012 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
1014 while (start != end) {
1015 nvme_handle_cqe(nvmeq, start);
1016 if (++start == nvmeq->q_depth)
1021 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1023 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
1025 nvmeq->cq_phase = !nvmeq->cq_phase;
1031 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1032 u16 *end, unsigned int tag)
1036 *start = nvmeq->cq_head;
1037 while (nvme_cqe_pending(nvmeq)) {
1038 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1040 nvme_update_cq_head(nvmeq);
1042 *end = nvmeq->cq_head;
1045 nvme_ring_cq_doorbell(nvmeq);
1049 static irqreturn_t nvme_irq(int irq, void *data)
1051 struct nvme_queue *nvmeq = data;
1052 irqreturn_t ret = IRQ_NONE;
1056 * The rmb/wmb pair ensures we see all updates from a previous run of
1057 * the irq handler, even if that was on another CPU.
1060 if (nvmeq->cq_head != nvmeq->last_cq_head)
1062 nvme_process_cq(nvmeq, &start, &end, -1);
1063 nvmeq->last_cq_head = nvmeq->cq_head;
1067 nvme_complete_cqes(nvmeq, start, end);
1074 static irqreturn_t nvme_irq_check(int irq, void *data)
1076 struct nvme_queue *nvmeq = data;
1077 if (nvme_cqe_pending(nvmeq))
1078 return IRQ_WAKE_THREAD;
1083 * Poll for completions any queue, including those not dedicated to polling.
1084 * Can be called from any context.
1086 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
1088 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1093 * For a poll queue we need to protect against the polling thread
1094 * using the CQ lock. For normal interrupt driven threads we have
1095 * to disable the interrupt to avoid racing with it.
1097 if (nvmeq->cq_vector == -1) {
1098 spin_lock(&nvmeq->cq_poll_lock);
1099 found = nvme_process_cq(nvmeq, &start, &end, tag);
1100 spin_unlock(&nvmeq->cq_poll_lock);
1102 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1103 found = nvme_process_cq(nvmeq, &start, &end, tag);
1104 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1107 nvme_complete_cqes(nvmeq, start, end);
1111 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1113 struct nvme_queue *nvmeq = hctx->driver_data;
1117 if (!nvme_cqe_pending(nvmeq))
1120 spin_lock(&nvmeq->cq_poll_lock);
1121 found = nvme_process_cq(nvmeq, &start, &end, -1);
1122 spin_unlock(&nvmeq->cq_poll_lock);
1124 nvme_complete_cqes(nvmeq, start, end);
1128 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1130 struct nvme_dev *dev = to_nvme_dev(ctrl);
1131 struct nvme_queue *nvmeq = &dev->queues[0];
1132 struct nvme_command c;
1134 memset(&c, 0, sizeof(c));
1135 c.common.opcode = nvme_admin_async_event;
1136 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1137 nvme_submit_cmd(nvmeq, &c, true);
1140 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1142 struct nvme_command c;
1144 memset(&c, 0, sizeof(c));
1145 c.delete_queue.opcode = opcode;
1146 c.delete_queue.qid = cpu_to_le16(id);
1148 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1151 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1152 struct nvme_queue *nvmeq, s16 vector)
1154 struct nvme_command c;
1155 int flags = NVME_QUEUE_PHYS_CONTIG;
1158 flags |= NVME_CQ_IRQ_ENABLED;
1161 * Note: we (ab)use the fact that the prp fields survive if no data
1162 * is attached to the request.
1164 memset(&c, 0, sizeof(c));
1165 c.create_cq.opcode = nvme_admin_create_cq;
1166 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1167 c.create_cq.cqid = cpu_to_le16(qid);
1168 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1169 c.create_cq.cq_flags = cpu_to_le16(flags);
1171 c.create_cq.irq_vector = cpu_to_le16(vector);
1173 c.create_cq.irq_vector = 0;
1175 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1178 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1179 struct nvme_queue *nvmeq)
1181 struct nvme_ctrl *ctrl = &dev->ctrl;
1182 struct nvme_command c;
1183 int flags = NVME_QUEUE_PHYS_CONTIG;
1186 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1187 * set. Since URGENT priority is zeroes, it makes all queues
1190 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1191 flags |= NVME_SQ_PRIO_MEDIUM;
1194 * Note: we (ab)use the fact that the prp fields survive if no data
1195 * is attached to the request.
1197 memset(&c, 0, sizeof(c));
1198 c.create_sq.opcode = nvme_admin_create_sq;
1199 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1200 c.create_sq.sqid = cpu_to_le16(qid);
1201 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1202 c.create_sq.sq_flags = cpu_to_le16(flags);
1203 c.create_sq.cqid = cpu_to_le16(qid);
1205 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1208 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1210 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1213 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1215 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1218 static void abort_endio(struct request *req, blk_status_t error)
1220 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1221 struct nvme_queue *nvmeq = iod->nvmeq;
1223 dev_warn(nvmeq->dev->ctrl.device,
1224 "Abort status: 0x%x", nvme_req(req)->status);
1225 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1226 blk_mq_free_request(req);
1229 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1232 /* If true, indicates loss of adapter communication, possibly by a
1233 * NVMe Subsystem reset.
1235 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1237 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1238 switch (dev->ctrl.state) {
1239 case NVME_CTRL_RESETTING:
1240 case NVME_CTRL_CONNECTING:
1246 /* We shouldn't reset unless the controller is on fatal error state
1247 * _or_ if we lost the communication with it.
1249 if (!(csts & NVME_CSTS_CFS) && !nssro)
1255 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1257 /* Read a config register to help see what died. */
1261 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1263 if (result == PCIBIOS_SUCCESSFUL)
1264 dev_warn(dev->ctrl.device,
1265 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1268 dev_warn(dev->ctrl.device,
1269 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1273 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1275 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1276 struct nvme_queue *nvmeq = iod->nvmeq;
1277 struct nvme_dev *dev = nvmeq->dev;
1278 struct request *abort_req;
1279 struct nvme_command cmd;
1280 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1282 /* If PCI error recovery process is happening, we cannot reset or
1283 * the recovery mechanism will surely fail.
1286 if (pci_channel_offline(to_pci_dev(dev->dev)))
1287 return BLK_EH_RESET_TIMER;
1290 * Reset immediately if the controller is failed
1292 if (nvme_should_reset(dev, csts)) {
1293 nvme_warn_reset(dev, csts);
1294 nvme_dev_disable(dev, false);
1295 nvme_reset_ctrl(&dev->ctrl);
1300 * Did we miss an interrupt?
1302 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
1303 dev_warn(dev->ctrl.device,
1304 "I/O %d QID %d timeout, completion polled\n",
1305 req->tag, nvmeq->qid);
1310 * Shutdown immediately if controller times out while starting. The
1311 * reset work will see the pci device disabled when it gets the forced
1312 * cancellation error. All outstanding requests are completed on
1313 * shutdown, so we return BLK_EH_DONE.
1315 switch (dev->ctrl.state) {
1316 case NVME_CTRL_CONNECTING:
1317 case NVME_CTRL_RESETTING:
1318 dev_warn_ratelimited(dev->ctrl.device,
1319 "I/O %d QID %d timeout, disable controller\n",
1320 req->tag, nvmeq->qid);
1321 nvme_dev_disable(dev, false);
1322 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1329 * Shutdown the controller immediately and schedule a reset if the
1330 * command was already aborted once before and still hasn't been
1331 * returned to the driver, or if this is the admin queue.
1333 if (!nvmeq->qid || iod->aborted) {
1334 dev_warn(dev->ctrl.device,
1335 "I/O %d QID %d timeout, reset controller\n",
1336 req->tag, nvmeq->qid);
1337 nvme_dev_disable(dev, false);
1338 nvme_reset_ctrl(&dev->ctrl);
1340 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1344 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1345 atomic_inc(&dev->ctrl.abort_limit);
1346 return BLK_EH_RESET_TIMER;
1350 memset(&cmd, 0, sizeof(cmd));
1351 cmd.abort.opcode = nvme_admin_abort_cmd;
1352 cmd.abort.cid = req->tag;
1353 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1355 dev_warn(nvmeq->dev->ctrl.device,
1356 "I/O %d QID %d timeout, aborting\n",
1357 req->tag, nvmeq->qid);
1359 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1360 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1361 if (IS_ERR(abort_req)) {
1362 atomic_inc(&dev->ctrl.abort_limit);
1363 return BLK_EH_RESET_TIMER;
1366 abort_req->timeout = ADMIN_TIMEOUT;
1367 abort_req->end_io_data = NULL;
1368 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1371 * The aborted req will be completed on receiving the abort req.
1372 * We enable the timer again. If hit twice, it'll cause a device reset,
1373 * as the device then is in a faulty state.
1375 return BLK_EH_RESET_TIMER;
1378 static void nvme_free_queue(struct nvme_queue *nvmeq)
1380 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1381 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1382 if (!nvmeq->sq_cmds)
1385 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1386 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1387 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1389 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1390 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1394 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1398 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1399 dev->ctrl.queue_count--;
1400 nvme_free_queue(&dev->queues[i]);
1405 * nvme_suspend_queue - put queue into suspended state
1406 * @nvmeq: queue to suspend
1408 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1410 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1413 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1416 nvmeq->dev->online_queues--;
1417 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1418 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1419 if (nvmeq->cq_vector == -1)
1421 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1422 nvmeq->cq_vector = -1;
1426 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1430 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1431 nvme_suspend_queue(&dev->queues[i]);
1434 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1436 struct nvme_queue *nvmeq = &dev->queues[0];
1439 nvme_shutdown_ctrl(&dev->ctrl);
1441 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1443 nvme_poll_irqdisable(nvmeq, -1);
1446 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1449 int q_depth = dev->q_depth;
1450 unsigned q_size_aligned = roundup(q_depth * entry_size,
1451 dev->ctrl.page_size);
1453 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1454 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1455 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1456 q_depth = div_u64(mem_per_q, entry_size);
1459 * Ensure the reduced q_depth is above some threshold where it
1460 * would be better to map queues in system memory with the
1470 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1473 struct pci_dev *pdev = to_pci_dev(dev->dev);
1475 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1476 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1477 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1479 if (nvmeq->sq_dma_addr) {
1480 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1485 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1486 &nvmeq->sq_dma_addr, GFP_KERNEL);
1487 if (!nvmeq->sq_cmds)
1492 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1494 struct nvme_queue *nvmeq = &dev->queues[qid];
1496 if (dev->ctrl.queue_count > qid)
1499 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1500 &nvmeq->cq_dma_addr, GFP_KERNEL);
1504 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1507 nvmeq->q_dmadev = dev->dev;
1509 spin_lock_init(&nvmeq->sq_lock);
1510 spin_lock_init(&nvmeq->cq_poll_lock);
1512 nvmeq->cq_phase = 1;
1513 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1514 nvmeq->q_depth = depth;
1516 nvmeq->cq_vector = -1;
1517 dev->ctrl.queue_count++;
1522 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1523 nvmeq->cq_dma_addr);
1528 static int queue_request_irq(struct nvme_queue *nvmeq)
1530 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1531 int nr = nvmeq->dev->ctrl.instance;
1533 if (use_threaded_interrupts) {
1534 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1535 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1537 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1538 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1542 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1544 struct nvme_dev *dev = nvmeq->dev;
1547 nvmeq->last_sq_tail = 0;
1549 nvmeq->cq_phase = 1;
1550 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1551 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1552 nvme_dbbuf_init(dev, nvmeq, qid);
1553 dev->online_queues++;
1554 wmb(); /* ensure the first interrupt sees the initialization */
1557 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1559 struct nvme_dev *dev = nvmeq->dev;
1563 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1566 * A queue's vector matches the queue identifier unless the controller
1567 * has only one vector available.
1570 vector = dev->num_vecs == 1 ? 0 : qid;
1574 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1578 result = adapter_alloc_sq(dev, qid, nvmeq);
1584 nvmeq->cq_vector = vector;
1585 nvme_init_queue(nvmeq, qid);
1588 result = queue_request_irq(nvmeq);
1593 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1597 nvmeq->cq_vector = -1;
1598 dev->online_queues--;
1599 adapter_delete_sq(dev, qid);
1601 adapter_delete_cq(dev, qid);
1605 static const struct blk_mq_ops nvme_mq_admin_ops = {
1606 .queue_rq = nvme_queue_rq,
1607 .complete = nvme_pci_complete_rq,
1608 .init_hctx = nvme_admin_init_hctx,
1609 .exit_hctx = nvme_admin_exit_hctx,
1610 .init_request = nvme_init_request,
1611 .timeout = nvme_timeout,
1614 static const struct blk_mq_ops nvme_mq_ops = {
1615 .queue_rq = nvme_queue_rq,
1616 .complete = nvme_pci_complete_rq,
1617 .commit_rqs = nvme_commit_rqs,
1618 .init_hctx = nvme_init_hctx,
1619 .init_request = nvme_init_request,
1620 .map_queues = nvme_pci_map_queues,
1621 .timeout = nvme_timeout,
1625 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1627 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1629 * If the controller was reset during removal, it's possible
1630 * user requests may be waiting on a stopped queue. Start the
1631 * queue to flush these to completion.
1633 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1634 blk_cleanup_queue(dev->ctrl.admin_q);
1635 blk_mq_free_tag_set(&dev->admin_tagset);
1639 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1641 if (!dev->ctrl.admin_q) {
1642 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1643 dev->admin_tagset.nr_hw_queues = 1;
1645 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1646 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1647 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1648 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1649 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1650 dev->admin_tagset.driver_data = dev;
1652 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1654 dev->ctrl.admin_tagset = &dev->admin_tagset;
1656 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1657 if (IS_ERR(dev->ctrl.admin_q)) {
1658 blk_mq_free_tag_set(&dev->admin_tagset);
1661 if (!blk_get_queue(dev->ctrl.admin_q)) {
1662 nvme_dev_remove_admin(dev);
1663 dev->ctrl.admin_q = NULL;
1667 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1672 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1674 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1677 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1679 struct pci_dev *pdev = to_pci_dev(dev->dev);
1681 if (size <= dev->bar_mapped_size)
1683 if (size > pci_resource_len(pdev, 0))
1687 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1689 dev->bar_mapped_size = 0;
1692 dev->bar_mapped_size = size;
1693 dev->dbs = dev->bar + NVME_REG_DBS;
1698 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1702 struct nvme_queue *nvmeq;
1704 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1708 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1709 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1711 if (dev->subsystem &&
1712 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1713 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1715 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1719 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1723 nvmeq = &dev->queues[0];
1724 aqa = nvmeq->q_depth - 1;
1727 writel(aqa, dev->bar + NVME_REG_AQA);
1728 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1729 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1731 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1735 nvmeq->cq_vector = 0;
1736 nvme_init_queue(nvmeq, 0);
1737 result = queue_request_irq(nvmeq);
1739 nvmeq->cq_vector = -1;
1743 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1747 static int nvme_create_io_queues(struct nvme_dev *dev)
1749 unsigned i, max, rw_queues;
1752 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1753 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1759 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1760 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1761 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1762 dev->io_queues[HCTX_TYPE_READ];
1767 for (i = dev->online_queues; i <= max; i++) {
1768 bool polled = i > rw_queues;
1770 ret = nvme_create_queue(&dev->queues[i], i, polled);
1776 * Ignore failing Create SQ/CQ commands, we can continue with less
1777 * than the desired amount of queues, and even a controller without
1778 * I/O queues can still be used to issue admin commands. This might
1779 * be useful to upgrade a buggy firmware for example.
1781 return ret >= 0 ? 0 : ret;
1784 static ssize_t nvme_cmb_show(struct device *dev,
1785 struct device_attribute *attr,
1788 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1790 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1791 ndev->cmbloc, ndev->cmbsz);
1793 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1795 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1797 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1799 return 1ULL << (12 + 4 * szu);
1802 static u32 nvme_cmb_size(struct nvme_dev *dev)
1804 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1807 static void nvme_map_cmb(struct nvme_dev *dev)
1810 resource_size_t bar_size;
1811 struct pci_dev *pdev = to_pci_dev(dev->dev);
1817 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1820 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1822 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1823 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1824 bar = NVME_CMB_BIR(dev->cmbloc);
1825 bar_size = pci_resource_len(pdev, bar);
1827 if (offset > bar_size)
1831 * Controllers may support a CMB size larger than their BAR,
1832 * for example, due to being behind a bridge. Reduce the CMB to
1833 * the reported size of the BAR
1835 if (size > bar_size - offset)
1836 size = bar_size - offset;
1838 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1839 dev_warn(dev->ctrl.device,
1840 "failed to register the CMB\n");
1844 dev->cmb_size = size;
1845 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1847 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1848 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1849 pci_p2pmem_publish(pdev, true);
1851 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1852 &dev_attr_cmb.attr, NULL))
1853 dev_warn(dev->ctrl.device,
1854 "failed to add sysfs attribute for CMB\n");
1857 static inline void nvme_release_cmb(struct nvme_dev *dev)
1859 if (dev->cmb_size) {
1860 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1861 &dev_attr_cmb.attr, NULL);
1866 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1868 u64 dma_addr = dev->host_mem_descs_dma;
1869 struct nvme_command c;
1872 memset(&c, 0, sizeof(c));
1873 c.features.opcode = nvme_admin_set_features;
1874 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1875 c.features.dword11 = cpu_to_le32(bits);
1876 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1877 ilog2(dev->ctrl.page_size));
1878 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1879 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1880 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1882 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1884 dev_warn(dev->ctrl.device,
1885 "failed to set host mem (err %d, flags %#x).\n",
1891 static void nvme_free_host_mem(struct nvme_dev *dev)
1895 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1896 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1897 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1899 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1900 le64_to_cpu(desc->addr),
1901 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1904 kfree(dev->host_mem_desc_bufs);
1905 dev->host_mem_desc_bufs = NULL;
1906 dma_free_coherent(dev->dev,
1907 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1908 dev->host_mem_descs, dev->host_mem_descs_dma);
1909 dev->host_mem_descs = NULL;
1910 dev->nr_host_mem_descs = 0;
1913 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1916 struct nvme_host_mem_buf_desc *descs;
1917 u32 max_entries, len;
1918 dma_addr_t descs_dma;
1923 tmp = (preferred + chunk_size - 1);
1924 do_div(tmp, chunk_size);
1927 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1928 max_entries = dev->ctrl.hmmaxd;
1930 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1931 &descs_dma, GFP_KERNEL);
1935 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1937 goto out_free_descs;
1939 for (size = 0; size < preferred && i < max_entries; size += len) {
1940 dma_addr_t dma_addr;
1942 len = min_t(u64, chunk_size, preferred - size);
1943 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1944 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1948 descs[i].addr = cpu_to_le64(dma_addr);
1949 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1956 dev->nr_host_mem_descs = i;
1957 dev->host_mem_size = size;
1958 dev->host_mem_descs = descs;
1959 dev->host_mem_descs_dma = descs_dma;
1960 dev->host_mem_desc_bufs = bufs;
1965 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1967 dma_free_attrs(dev->dev, size, bufs[i],
1968 le64_to_cpu(descs[i].addr),
1969 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1974 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1977 dev->host_mem_descs = NULL;
1981 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1985 /* start big and work our way down */
1986 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1987 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1989 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1990 if (!min || dev->host_mem_size >= min)
1992 nvme_free_host_mem(dev);
1999 static int nvme_setup_host_mem(struct nvme_dev *dev)
2001 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2002 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2003 u64 min = (u64)dev->ctrl.hmmin * 4096;
2004 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2007 preferred = min(preferred, max);
2009 dev_warn(dev->ctrl.device,
2010 "min host memory (%lld MiB) above limit (%d MiB).\n",
2011 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2012 nvme_free_host_mem(dev);
2017 * If we already have a buffer allocated check if we can reuse it.
2019 if (dev->host_mem_descs) {
2020 if (dev->host_mem_size >= min)
2021 enable_bits |= NVME_HOST_MEM_RETURN;
2023 nvme_free_host_mem(dev);
2026 if (!dev->host_mem_descs) {
2027 if (nvme_alloc_host_mem(dev, min, preferred)) {
2028 dev_warn(dev->ctrl.device,
2029 "failed to allocate host memory buffer.\n");
2030 return 0; /* controller must work without HMB */
2033 dev_info(dev->ctrl.device,
2034 "allocated %lld MiB host memory buffer.\n",
2035 dev->host_mem_size >> ilog2(SZ_1M));
2038 ret = nvme_set_host_mem(dev, enable_bits);
2040 nvme_free_host_mem(dev);
2044 static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int irq_queues)
2046 unsigned int this_w_queues = write_queues;
2049 * Setup read/write queue split
2051 if (irq_queues == 1) {
2052 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2053 dev->io_queues[HCTX_TYPE_READ] = 0;
2058 * If 'write_queues' is set, ensure it leaves room for at least
2061 if (this_w_queues >= irq_queues)
2062 this_w_queues = irq_queues - 1;
2065 * If 'write_queues' is set to zero, reads and writes will share
2068 if (!this_w_queues) {
2069 dev->io_queues[HCTX_TYPE_DEFAULT] = irq_queues;
2070 dev->io_queues[HCTX_TYPE_READ] = 0;
2072 dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues;
2073 dev->io_queues[HCTX_TYPE_READ] = irq_queues - this_w_queues;
2077 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2079 struct pci_dev *pdev = to_pci_dev(dev->dev);
2081 struct irq_affinity affd = {
2083 .nr_sets = ARRAY_SIZE(irq_sets),
2087 unsigned int irq_queues, this_p_queues;
2090 * Poll queues don't need interrupts, but we need at least one IO
2091 * queue left over for non-polled IO.
2093 this_p_queues = poll_queues;
2094 if (this_p_queues >= nr_io_queues) {
2095 this_p_queues = nr_io_queues - 1;
2098 irq_queues = nr_io_queues - this_p_queues;
2100 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2103 * For irq sets, we have to ask for minvec == maxvec. This passes
2104 * any reduction back to us, so we can adjust our queue counts and
2108 nvme_calc_io_queues(dev, irq_queues);
2109 irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT];
2110 irq_sets[1] = dev->io_queues[HCTX_TYPE_READ];
2115 * If we got a failure and we're down to asking for just
2116 * 1 + 1 queues, just ask for a single vector. We'll share
2117 * that between the single IO queue and the admin queue.
2119 if (result >= 0 && irq_queues > 1)
2120 irq_queues = irq_sets[0] + irq_sets[1] + 1;
2122 result = pci_alloc_irq_vectors_affinity(pdev, irq_queues,
2124 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2127 * Need to reduce our vec counts. If we get ENOSPC, the
2128 * platform should support mulitple vecs, we just need
2129 * to decrease our ask. If we get EINVAL, the platform
2130 * likely does not. Back down to ask for just one vector.
2132 if (result == -ENOSPC) {
2137 } else if (result == -EINVAL) {
2140 } else if (result <= 0)
2148 static void nvme_disable_io_queues(struct nvme_dev *dev)
2150 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2151 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2154 static int nvme_setup_io_queues(struct nvme_dev *dev)
2156 struct nvme_queue *adminq = &dev->queues[0];
2157 struct pci_dev *pdev = to_pci_dev(dev->dev);
2158 int result, nr_io_queues;
2161 nr_io_queues = max_io_queues();
2162 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2166 if (nr_io_queues == 0)
2169 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2171 if (dev->cmb_use_sqes) {
2172 result = nvme_cmb_qdepth(dev, nr_io_queues,
2173 sizeof(struct nvme_command));
2175 dev->q_depth = result;
2177 dev->cmb_use_sqes = false;
2181 size = db_bar_size(dev, nr_io_queues);
2182 result = nvme_remap_bar(dev, size);
2185 if (!--nr_io_queues)
2188 adminq->q_db = dev->dbs;
2191 /* Deregister the admin queue's interrupt */
2192 pci_free_irq(pdev, 0, adminq);
2195 * If we enable msix early due to not intx, disable it again before
2196 * setting up the full range we need.
2198 pci_free_irq_vectors(pdev);
2200 result = nvme_setup_irqs(dev, nr_io_queues);
2204 dev->num_vecs = result;
2205 result = max(result - 1, 1);
2206 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2209 * Should investigate if there's a performance win from allocating
2210 * more queues than interrupt vectors; it might allow the submission
2211 * path to scale better, even if the receive path is limited by the
2212 * number of interrupts.
2214 result = queue_request_irq(adminq);
2216 adminq->cq_vector = -1;
2219 set_bit(NVMEQ_ENABLED, &adminq->flags);
2221 result = nvme_create_io_queues(dev);
2222 if (result || dev->online_queues < 2)
2225 if (dev->online_queues - 1 < dev->max_qid) {
2226 nr_io_queues = dev->online_queues - 1;
2227 nvme_disable_io_queues(dev);
2228 nvme_suspend_io_queues(dev);
2231 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2232 dev->io_queues[HCTX_TYPE_DEFAULT],
2233 dev->io_queues[HCTX_TYPE_READ],
2234 dev->io_queues[HCTX_TYPE_POLL]);
2238 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2240 struct nvme_queue *nvmeq = req->end_io_data;
2242 blk_mq_free_request(req);
2243 complete(&nvmeq->delete_done);
2246 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2248 struct nvme_queue *nvmeq = req->end_io_data;
2251 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2253 nvme_del_queue_end(req, error);
2256 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2258 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2259 struct request *req;
2260 struct nvme_command cmd;
2262 memset(&cmd, 0, sizeof(cmd));
2263 cmd.delete_queue.opcode = opcode;
2264 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2266 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2268 return PTR_ERR(req);
2270 req->timeout = ADMIN_TIMEOUT;
2271 req->end_io_data = nvmeq;
2273 init_completion(&nvmeq->delete_done);
2274 blk_execute_rq_nowait(q, NULL, req, false,
2275 opcode == nvme_admin_delete_cq ?
2276 nvme_del_cq_end : nvme_del_queue_end);
2280 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2282 int nr_queues = dev->online_queues - 1, sent = 0;
2283 unsigned long timeout;
2286 timeout = ADMIN_TIMEOUT;
2287 while (nr_queues > 0) {
2288 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2294 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2296 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2301 /* handle any remaining CQEs */
2302 if (opcode == nvme_admin_delete_cq &&
2303 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2304 nvme_poll_irqdisable(nvmeq, -1);
2314 * return error value only when tagset allocation failed
2316 static int nvme_dev_add(struct nvme_dev *dev)
2320 if (!dev->ctrl.tagset) {
2321 dev->tagset.ops = &nvme_mq_ops;
2322 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2323 dev->tagset.nr_maps = 2; /* default + read */
2324 if (dev->io_queues[HCTX_TYPE_POLL])
2325 dev->tagset.nr_maps++;
2326 dev->tagset.timeout = NVME_IO_TIMEOUT;
2327 dev->tagset.numa_node = dev_to_node(dev->dev);
2328 dev->tagset.queue_depth =
2329 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2330 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2331 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2332 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2333 nvme_pci_cmd_size(dev, true));
2335 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2336 dev->tagset.driver_data = dev;
2338 ret = blk_mq_alloc_tag_set(&dev->tagset);
2340 dev_warn(dev->ctrl.device,
2341 "IO queues tagset allocation failed %d\n", ret);
2344 dev->ctrl.tagset = &dev->tagset;
2346 nvme_dbbuf_set(dev);
2348 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2350 /* Free previously allocated queues that are no longer usable */
2351 nvme_free_queues(dev, dev->online_queues);
2357 static int nvme_pci_enable(struct nvme_dev *dev)
2359 int result = -ENOMEM;
2360 struct pci_dev *pdev = to_pci_dev(dev->dev);
2362 if (pci_enable_device_mem(pdev))
2365 pci_set_master(pdev);
2367 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2368 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2371 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2377 * Some devices and/or platforms don't advertise or work with INTx
2378 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2379 * adjust this later.
2381 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2385 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2387 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2389 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2390 dev->dbs = dev->bar + 4096;
2393 * Temporary fix for the Apple controller found in the MacBook8,1 and
2394 * some MacBook7,1 to avoid controller resets and data loss.
2396 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2398 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2399 "set queue depth=%u to work around controller resets\n",
2401 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2402 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2403 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2405 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2406 "set queue depth=%u\n", dev->q_depth);
2411 pci_enable_pcie_error_reporting(pdev);
2412 pci_save_state(pdev);
2416 pci_disable_device(pdev);
2420 static void nvme_dev_unmap(struct nvme_dev *dev)
2424 pci_release_mem_regions(to_pci_dev(dev->dev));
2427 static void nvme_pci_disable(struct nvme_dev *dev)
2429 struct pci_dev *pdev = to_pci_dev(dev->dev);
2431 pci_free_irq_vectors(pdev);
2433 if (pci_is_enabled(pdev)) {
2434 pci_disable_pcie_error_reporting(pdev);
2435 pci_disable_device(pdev);
2439 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2442 struct pci_dev *pdev = to_pci_dev(dev->dev);
2444 mutex_lock(&dev->shutdown_lock);
2445 if (pci_is_enabled(pdev)) {
2446 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2448 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2449 dev->ctrl.state == NVME_CTRL_RESETTING)
2450 nvme_start_freeze(&dev->ctrl);
2451 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2452 pdev->error_state != pci_channel_io_normal);
2456 * Give the controller a chance to complete all entered requests if
2457 * doing a safe shutdown.
2461 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2464 nvme_stop_queues(&dev->ctrl);
2466 if (!dead && dev->ctrl.queue_count > 0) {
2467 nvme_disable_io_queues(dev);
2468 nvme_disable_admin_queue(dev, shutdown);
2470 nvme_suspend_io_queues(dev);
2471 nvme_suspend_queue(&dev->queues[0]);
2472 nvme_pci_disable(dev);
2474 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2475 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2478 * The driver will not be starting up queues again if shutting down so
2479 * must flush all entered requests to their failed completion to avoid
2480 * deadlocking blk-mq hot-cpu notifier.
2483 nvme_start_queues(&dev->ctrl);
2484 mutex_unlock(&dev->shutdown_lock);
2487 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2489 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2490 PAGE_SIZE, PAGE_SIZE, 0);
2491 if (!dev->prp_page_pool)
2494 /* Optimisation for I/Os between 4k and 128k */
2495 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2497 if (!dev->prp_small_pool) {
2498 dma_pool_destroy(dev->prp_page_pool);
2504 static void nvme_release_prp_pools(struct nvme_dev *dev)
2506 dma_pool_destroy(dev->prp_page_pool);
2507 dma_pool_destroy(dev->prp_small_pool);
2510 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2512 struct nvme_dev *dev = to_nvme_dev(ctrl);
2514 nvme_dbbuf_dma_free(dev);
2515 put_device(dev->dev);
2516 if (dev->tagset.tags)
2517 blk_mq_free_tag_set(&dev->tagset);
2518 if (dev->ctrl.admin_q)
2519 blk_put_queue(dev->ctrl.admin_q);
2521 free_opal_dev(dev->ctrl.opal_dev);
2522 mempool_destroy(dev->iod_mempool);
2526 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2528 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2530 nvme_get_ctrl(&dev->ctrl);
2531 nvme_dev_disable(dev, false);
2532 nvme_kill_queues(&dev->ctrl);
2533 if (!queue_work(nvme_wq, &dev->remove_work))
2534 nvme_put_ctrl(&dev->ctrl);
2537 static void nvme_reset_work(struct work_struct *work)
2539 struct nvme_dev *dev =
2540 container_of(work, struct nvme_dev, ctrl.reset_work);
2541 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2542 int result = -ENODEV;
2543 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2545 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2549 * If we're called to reset a live controller first shut it down before
2552 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2553 nvme_dev_disable(dev, false);
2556 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2557 * initializing procedure here.
2559 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2560 dev_warn(dev->ctrl.device,
2561 "failed to mark controller CONNECTING\n");
2565 result = nvme_pci_enable(dev);
2569 result = nvme_pci_configure_admin_queue(dev);
2573 result = nvme_alloc_admin_tags(dev);
2578 * Limit the max command size to prevent iod->sg allocations going
2579 * over a single page.
2581 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2582 dev->ctrl.max_segments = NVME_MAX_SEGS;
2584 result = nvme_init_identify(&dev->ctrl);
2588 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2589 if (!dev->ctrl.opal_dev)
2590 dev->ctrl.opal_dev =
2591 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2592 else if (was_suspend)
2593 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2595 free_opal_dev(dev->ctrl.opal_dev);
2596 dev->ctrl.opal_dev = NULL;
2599 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2600 result = nvme_dbbuf_dma_alloc(dev);
2603 "unable to allocate dma for dbbuf\n");
2606 if (dev->ctrl.hmpre) {
2607 result = nvme_setup_host_mem(dev);
2612 result = nvme_setup_io_queues(dev);
2617 * Keep the controller around but remove all namespaces if we don't have
2618 * any working I/O queue.
2620 if (dev->online_queues < 2) {
2621 dev_warn(dev->ctrl.device, "IO queues not created\n");
2622 nvme_kill_queues(&dev->ctrl);
2623 nvme_remove_namespaces(&dev->ctrl);
2624 new_state = NVME_CTRL_ADMIN_ONLY;
2626 nvme_start_queues(&dev->ctrl);
2627 nvme_wait_freeze(&dev->ctrl);
2628 /* hit this only when allocate tagset fails */
2629 if (nvme_dev_add(dev))
2630 new_state = NVME_CTRL_ADMIN_ONLY;
2631 nvme_unfreeze(&dev->ctrl);
2635 * If only admin queue live, keep it to do further investigation or
2638 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2639 dev_warn(dev->ctrl.device,
2640 "failed to mark controller state %d\n", new_state);
2644 nvme_start_ctrl(&dev->ctrl);
2648 nvme_remove_dead_ctrl(dev, result);
2651 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2653 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2654 struct pci_dev *pdev = to_pci_dev(dev->dev);
2656 if (pci_get_drvdata(pdev))
2657 device_release_driver(&pdev->dev);
2658 nvme_put_ctrl(&dev->ctrl);
2661 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2663 *val = readl(to_nvme_dev(ctrl)->bar + off);
2667 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2669 writel(val, to_nvme_dev(ctrl)->bar + off);
2673 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2675 *val = readq(to_nvme_dev(ctrl)->bar + off);
2679 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2681 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2683 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2686 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2688 .module = THIS_MODULE,
2689 .flags = NVME_F_METADATA_SUPPORTED |
2691 .reg_read32 = nvme_pci_reg_read32,
2692 .reg_write32 = nvme_pci_reg_write32,
2693 .reg_read64 = nvme_pci_reg_read64,
2694 .free_ctrl = nvme_pci_free_ctrl,
2695 .submit_async_event = nvme_pci_submit_async_event,
2696 .get_address = nvme_pci_get_address,
2699 static int nvme_dev_map(struct nvme_dev *dev)
2701 struct pci_dev *pdev = to_pci_dev(dev->dev);
2703 if (pci_request_mem_regions(pdev, "nvme"))
2706 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2711 pci_release_mem_regions(pdev);
2715 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2717 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2719 * Several Samsung devices seem to drop off the PCIe bus
2720 * randomly when APST is on and uses the deepest sleep state.
2721 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2722 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2723 * 950 PRO 256GB", but it seems to be restricted to two Dell
2726 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2727 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2728 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2729 return NVME_QUIRK_NO_DEEPEST_PS;
2730 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2732 * Samsung SSD 960 EVO drops off the PCIe bus after system
2733 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2734 * within few minutes after bootup on a Coffee Lake board -
2737 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2738 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2739 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2740 return NVME_QUIRK_NO_APST;
2746 static void nvme_async_probe(void *data, async_cookie_t cookie)
2748 struct nvme_dev *dev = data;
2750 nvme_reset_ctrl_sync(&dev->ctrl);
2751 flush_work(&dev->ctrl.scan_work);
2752 nvme_put_ctrl(&dev->ctrl);
2755 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2757 int node, result = -ENOMEM;
2758 struct nvme_dev *dev;
2759 unsigned long quirks = id->driver_data;
2762 node = dev_to_node(&pdev->dev);
2763 if (node == NUMA_NO_NODE)
2764 set_dev_node(&pdev->dev, first_memory_node);
2766 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2770 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2775 dev->dev = get_device(&pdev->dev);
2776 pci_set_drvdata(pdev, dev);
2778 result = nvme_dev_map(dev);
2782 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2783 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2784 mutex_init(&dev->shutdown_lock);
2786 result = nvme_setup_prp_pools(dev);
2790 quirks |= check_vendor_combination_bug(pdev);
2793 * Double check that our mempool alloc size will cover the biggest
2794 * command we support.
2796 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2797 NVME_MAX_SEGS, true);
2798 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2800 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2802 (void *) alloc_size,
2804 if (!dev->iod_mempool) {
2809 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2812 goto release_mempool;
2814 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2816 nvme_get_ctrl(&dev->ctrl);
2817 async_schedule(nvme_async_probe, dev);
2822 mempool_destroy(dev->iod_mempool);
2824 nvme_release_prp_pools(dev);
2826 nvme_dev_unmap(dev);
2828 put_device(dev->dev);
2835 static void nvme_reset_prepare(struct pci_dev *pdev)
2837 struct nvme_dev *dev = pci_get_drvdata(pdev);
2838 nvme_dev_disable(dev, false);
2841 static void nvme_reset_done(struct pci_dev *pdev)
2843 struct nvme_dev *dev = pci_get_drvdata(pdev);
2844 nvme_reset_ctrl_sync(&dev->ctrl);
2847 static void nvme_shutdown(struct pci_dev *pdev)
2849 struct nvme_dev *dev = pci_get_drvdata(pdev);
2850 nvme_dev_disable(dev, true);
2854 * The driver's remove may be called on a device in a partially initialized
2855 * state. This function must not have any dependencies on the device state in
2858 static void nvme_remove(struct pci_dev *pdev)
2860 struct nvme_dev *dev = pci_get_drvdata(pdev);
2862 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2863 pci_set_drvdata(pdev, NULL);
2865 if (!pci_device_is_present(pdev)) {
2866 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2867 nvme_dev_disable(dev, true);
2868 nvme_dev_remove_admin(dev);
2871 flush_work(&dev->ctrl.reset_work);
2872 nvme_stop_ctrl(&dev->ctrl);
2873 nvme_remove_namespaces(&dev->ctrl);
2874 nvme_dev_disable(dev, true);
2875 nvme_release_cmb(dev);
2876 nvme_free_host_mem(dev);
2877 nvme_dev_remove_admin(dev);
2878 nvme_free_queues(dev, 0);
2879 nvme_uninit_ctrl(&dev->ctrl);
2880 nvme_release_prp_pools(dev);
2881 nvme_dev_unmap(dev);
2882 nvme_put_ctrl(&dev->ctrl);
2885 #ifdef CONFIG_PM_SLEEP
2886 static int nvme_suspend(struct device *dev)
2888 struct pci_dev *pdev = to_pci_dev(dev);
2889 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2891 nvme_dev_disable(ndev, true);
2895 static int nvme_resume(struct device *dev)
2897 struct pci_dev *pdev = to_pci_dev(dev);
2898 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2900 nvme_reset_ctrl(&ndev->ctrl);
2905 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2907 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2908 pci_channel_state_t state)
2910 struct nvme_dev *dev = pci_get_drvdata(pdev);
2913 * A frozen channel requires a reset. When detected, this method will
2914 * shutdown the controller to quiesce. The controller will be restarted
2915 * after the slot reset through driver's slot_reset callback.
2918 case pci_channel_io_normal:
2919 return PCI_ERS_RESULT_CAN_RECOVER;
2920 case pci_channel_io_frozen:
2921 dev_warn(dev->ctrl.device,
2922 "frozen state error detected, reset controller\n");
2923 nvme_dev_disable(dev, false);
2924 return PCI_ERS_RESULT_NEED_RESET;
2925 case pci_channel_io_perm_failure:
2926 dev_warn(dev->ctrl.device,
2927 "failure state error detected, request disconnect\n");
2928 return PCI_ERS_RESULT_DISCONNECT;
2930 return PCI_ERS_RESULT_NEED_RESET;
2933 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2935 struct nvme_dev *dev = pci_get_drvdata(pdev);
2937 dev_info(dev->ctrl.device, "restart after slot reset\n");
2938 pci_restore_state(pdev);
2939 nvme_reset_ctrl(&dev->ctrl);
2940 return PCI_ERS_RESULT_RECOVERED;
2943 static void nvme_error_resume(struct pci_dev *pdev)
2945 struct nvme_dev *dev = pci_get_drvdata(pdev);
2947 flush_work(&dev->ctrl.reset_work);
2950 static const struct pci_error_handlers nvme_err_handler = {
2951 .error_detected = nvme_error_detected,
2952 .slot_reset = nvme_slot_reset,
2953 .resume = nvme_error_resume,
2954 .reset_prepare = nvme_reset_prepare,
2955 .reset_done = nvme_reset_done,
2958 static const struct pci_device_id nvme_id_table[] = {
2959 { PCI_VDEVICE(INTEL, 0x0953),
2960 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2961 NVME_QUIRK_DEALLOCATE_ZEROES, },
2962 { PCI_VDEVICE(INTEL, 0x0a53),
2963 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2964 NVME_QUIRK_DEALLOCATE_ZEROES, },
2965 { PCI_VDEVICE(INTEL, 0x0a54),
2966 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2967 NVME_QUIRK_DEALLOCATE_ZEROES, },
2968 { PCI_VDEVICE(INTEL, 0x0a55),
2969 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2970 NVME_QUIRK_DEALLOCATE_ZEROES, },
2971 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2972 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2973 NVME_QUIRK_MEDIUM_PRIO_SQ },
2974 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2975 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2976 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2977 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2978 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2979 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2980 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2981 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2982 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2983 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2984 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2985 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2986 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2987 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2988 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2989 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2990 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2991 .driver_data = NVME_QUIRK_LIGHTNVM, },
2992 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2993 .driver_data = NVME_QUIRK_LIGHTNVM, },
2994 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2995 .driver_data = NVME_QUIRK_LIGHTNVM, },
2996 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2997 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2998 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3001 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3003 static struct pci_driver nvme_driver = {
3005 .id_table = nvme_id_table,
3006 .probe = nvme_probe,
3007 .remove = nvme_remove,
3008 .shutdown = nvme_shutdown,
3010 .pm = &nvme_dev_pm_ops,
3012 .sriov_configure = pci_sriov_configure_simple,
3013 .err_handler = &nvme_err_handler,
3016 static int __init nvme_init(void)
3018 return pci_register_driver(&nvme_driver);
3021 static void __exit nvme_exit(void)
3023 pci_unregister_driver(&nvme_driver);
3024 flush_workqueue(nvme_wq);
3028 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3029 MODULE_LICENSE("GPL");
3030 MODULE_VERSION("1.0");
3031 module_init(nvme_init);
3032 module_exit(nvme_exit);