1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/t10-pi.h>
22 #include <linux/types.h>
23 #include <linux/io-64-nonatomic-lo-hi.h>
24 #include <linux/sed-opal.h>
25 #include <linux/pci-p2pdma.h>
30 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
31 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
33 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
36 * These can be higher, but we need to ensure that any command doesn't
37 * require an sg allocation that needs more than a page of data.
39 #define NVME_MAX_KB_SZ 4096
40 #define NVME_MAX_SEGS 127
42 static int use_threaded_interrupts;
43 module_param(use_threaded_interrupts, int, 0);
45 static bool use_cmb_sqes = true;
46 module_param(use_cmb_sqes, bool, 0444);
47 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49 static unsigned int max_host_mem_size_mb = 128;
50 module_param(max_host_mem_size_mb, uint, 0444);
51 MODULE_PARM_DESC(max_host_mem_size_mb,
52 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
54 static unsigned int sgl_threshold = SZ_32K;
55 module_param(sgl_threshold, uint, 0644);
56 MODULE_PARM_DESC(sgl_threshold,
57 "Use SGLs when average request segment size is larger or equal to "
58 "this size. Use 0 to disable SGLs.");
60 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
61 static const struct kernel_param_ops io_queue_depth_ops = {
62 .set = io_queue_depth_set,
66 static int io_queue_depth = 1024;
67 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
68 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70 static int queue_count_set(const char *val, const struct kernel_param *kp);
71 static const struct kernel_param_ops queue_count_ops = {
72 .set = queue_count_set,
76 static int write_queues;
77 module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
78 MODULE_PARM_DESC(write_queues,
79 "Number of queues to use for writes. If not set, reads and writes "
80 "will share a queue set.");
82 static int poll_queues = 0;
83 module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
84 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
89 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
90 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
93 * Represents an NVM Express device. Each nvme_dev is a PCI function.
96 struct nvme_queue *queues;
97 struct blk_mq_tag_set tagset;
98 struct blk_mq_tag_set admin_tagset;
101 struct dma_pool *prp_page_pool;
102 struct dma_pool *prp_small_pool;
103 unsigned online_queues;
105 unsigned io_queues[HCTX_MAX_TYPES];
106 unsigned int num_vecs;
110 unsigned long bar_mapped_size;
111 struct work_struct remove_work;
112 struct mutex shutdown_lock;
118 struct nvme_ctrl ctrl;
120 mempool_t *iod_mempool;
122 /* shadow doorbell buffer support: */
124 dma_addr_t dbbuf_dbs_dma_addr;
126 dma_addr_t dbbuf_eis_dma_addr;
128 /* host memory buffer support: */
130 u32 nr_host_mem_descs;
131 dma_addr_t host_mem_descs_dma;
132 struct nvme_host_mem_buf_desc *host_mem_descs;
133 void **host_mem_desc_bufs;
136 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
140 ret = kstrtoint(val, 10, &n);
141 if (ret != 0 || n < 2)
144 return param_set_int(val, kp);
147 static int queue_count_set(const char *val, const struct kernel_param *kp)
151 ret = kstrtoint(val, 10, &n);
154 if (n > num_possible_cpus())
155 n = num_possible_cpus();
157 return param_set_int(val, kp);
160 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
162 return qid * 2 * stride;
165 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
167 return (qid * 2 + 1) * stride;
170 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
172 return container_of(ctrl, struct nvme_dev, ctrl);
176 * An NVM Express queue. Each device has at least two (one for admin
177 * commands and one for I/O commands).
180 struct nvme_dev *dev;
182 struct nvme_command *sq_cmds;
183 /* only used for poll queues: */
184 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
185 volatile struct nvme_completion *cqes;
186 struct blk_mq_tags **tags;
187 dma_addr_t sq_dma_addr;
188 dma_addr_t cq_dma_addr;
199 #define NVMEQ_ENABLED 0
200 #define NVMEQ_SQ_CMB 1
201 #define NVMEQ_DELETE_ERROR 2
202 #define NVMEQ_POLLED 3
207 struct completion delete_done;
211 * The nvme_iod describes the data in an I/O.
213 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
214 * to the actual struct scatterlist.
217 struct nvme_request req;
218 struct nvme_queue *nvmeq;
221 int npages; /* In the PRP list. 0 means small pool in use */
222 int nents; /* Used in scatterlist */
223 dma_addr_t first_dma;
224 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
225 struct scatterlist *sg;
226 struct scatterlist inline_sg[0];
230 * Check we didin't inadvertently grow the command struct
232 static inline void _nvme_check_size(void)
234 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
235 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
236 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
237 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
239 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
240 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
241 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
242 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
243 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
244 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
245 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
246 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
249 static unsigned int max_io_queues(void)
251 return num_possible_cpus() + write_queues + poll_queues;
254 static unsigned int max_queue_count(void)
256 /* IO queues + admin queue */
257 return 1 + max_io_queues();
260 static inline unsigned int nvme_dbbuf_size(u32 stride)
262 return (max_queue_count() * 8 * stride);
265 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
267 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
272 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
273 &dev->dbbuf_dbs_dma_addr,
277 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
278 &dev->dbbuf_eis_dma_addr,
280 if (!dev->dbbuf_eis) {
281 dma_free_coherent(dev->dev, mem_size,
282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
283 dev->dbbuf_dbs = NULL;
290 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
292 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
294 if (dev->dbbuf_dbs) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
297 dev->dbbuf_dbs = NULL;
299 if (dev->dbbuf_eis) {
300 dma_free_coherent(dev->dev, mem_size,
301 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
302 dev->dbbuf_eis = NULL;
306 static void nvme_dbbuf_init(struct nvme_dev *dev,
307 struct nvme_queue *nvmeq, int qid)
309 if (!dev->dbbuf_dbs || !qid)
312 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
313 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
314 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
315 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
318 static void nvme_dbbuf_set(struct nvme_dev *dev)
320 struct nvme_command c;
325 memset(&c, 0, sizeof(c));
326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
337 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
342 /* Update dbbuf and return true if an MMIO is required */
343 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
344 volatile u32 *dbbuf_ei)
350 * Ensure that the queue is written before updating
351 * the doorbell in memory
355 old_value = *dbbuf_db;
359 * Ensure that the doorbell is updated before reading the event
360 * index from memory. The controller needs to provide similar
361 * ordering to ensure the envent index is updated before reading
366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
374 * Max size of iod being embedded in the request payload
376 #define NVME_INT_PAGES 2
377 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
380 * Will slightly overestimate the number of pages needed. This is OK
381 * as it only leads to a small amount of wasted memory for the lifetime of
384 static int nvme_npages(unsigned size, struct nvme_dev *dev)
386 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
387 dev->ctrl.page_size);
388 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
392 * Calculates the number of pages needed for the SGL segments. For example a 4k
393 * page can accommodate 256 SGL descriptors.
395 static int nvme_pci_npages_sgl(unsigned int num_seg)
397 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
400 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
401 unsigned int size, unsigned int nseg, bool use_sgl)
406 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
408 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
410 return alloc_size + sizeof(struct scatterlist) * nseg;
413 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
415 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
416 NVME_INT_BYTES(dev), NVME_INT_PAGES,
419 return sizeof(struct nvme_iod) + alloc_size;
422 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
423 unsigned int hctx_idx)
425 struct nvme_dev *dev = data;
426 struct nvme_queue *nvmeq = &dev->queues[0];
428 WARN_ON(hctx_idx != 0);
429 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
430 WARN_ON(nvmeq->tags);
432 hctx->driver_data = nvmeq;
433 nvmeq->tags = &dev->admin_tagset.tags[0];
437 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
439 struct nvme_queue *nvmeq = hctx->driver_data;
444 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
445 unsigned int hctx_idx)
447 struct nvme_dev *dev = data;
448 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
451 nvmeq->tags = &dev->tagset.tags[hctx_idx];
453 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
454 hctx->driver_data = nvmeq;
458 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
459 unsigned int hctx_idx, unsigned int numa_node)
461 struct nvme_dev *dev = set->driver_data;
462 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
463 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
464 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
469 nvme_req(req)->ctrl = &dev->ctrl;
473 static int queue_irq_offset(struct nvme_dev *dev)
475 /* if we have more than 1 vec, admin queue offsets us by 1 */
476 if (dev->num_vecs > 1)
482 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
484 struct nvme_dev *dev = set->driver_data;
487 offset = queue_irq_offset(dev);
488 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
489 struct blk_mq_queue_map *map = &set->map[i];
491 map->nr_queues = dev->io_queues[i];
492 if (!map->nr_queues) {
493 BUG_ON(i == HCTX_TYPE_DEFAULT);
498 * The poll queue(s) doesn't have an IRQ (and hence IRQ
499 * affinity), so use the regular blk-mq cpu mapping
501 map->queue_offset = qoff;
502 if (i != HCTX_TYPE_POLL)
503 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
505 blk_mq_map_queues(map);
506 qoff += map->nr_queues;
507 offset += map->nr_queues;
514 * Write sq tail if we are asked to, or if the next command would wrap.
516 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
519 u16 next_tail = nvmeq->sq_tail + 1;
521 if (next_tail == nvmeq->q_depth)
523 if (next_tail != nvmeq->last_sq_tail)
527 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
528 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
529 writel(nvmeq->sq_tail, nvmeq->q_db);
530 nvmeq->last_sq_tail = nvmeq->sq_tail;
534 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
535 * @nvmeq: The queue to use
536 * @cmd: The command to send
537 * @write_sq: whether to write to the SQ doorbell
539 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
542 spin_lock(&nvmeq->sq_lock);
543 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
544 if (++nvmeq->sq_tail == nvmeq->q_depth)
546 nvme_write_sq_db(nvmeq, write_sq);
547 spin_unlock(&nvmeq->sq_lock);
550 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
552 struct nvme_queue *nvmeq = hctx->driver_data;
554 spin_lock(&nvmeq->sq_lock);
555 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
556 nvme_write_sq_db(nvmeq, true);
557 spin_unlock(&nvmeq->sq_lock);
560 static void **nvme_pci_iod_list(struct request *req)
562 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
563 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
566 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
568 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
569 int nseg = blk_rq_nr_phys_segments(req);
570 unsigned int avg_seg_size;
575 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
577 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
579 if (!iod->nvmeq->qid)
581 if (!sgl_threshold || avg_seg_size < sgl_threshold)
586 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
588 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
589 enum dma_data_direction dma_dir = rq_data_dir(req) ?
590 DMA_TO_DEVICE : DMA_FROM_DEVICE;
591 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
592 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
596 /* P2PDMA requests do not need to be unmapped */
597 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
598 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
600 if (blk_integrity_rq(req))
601 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
604 if (iod->npages == 0)
605 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
608 for (i = 0; i < iod->npages; i++) {
609 void *addr = nvme_pci_iod_list(req)[i];
612 struct nvme_sgl_desc *sg_list = addr;
615 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
617 __le64 *prp_list = addr;
619 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
622 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
623 dma_addr = next_dma_addr;
626 if (iod->sg != iod->inline_sg)
627 mempool_free(iod->sg, dev->iod_mempool);
630 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
633 struct scatterlist *sg;
635 for_each_sg(sgl, sg, nents, i) {
636 dma_addr_t phys = sg_phys(sg);
637 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
638 "dma_address:%pad dma_length:%d\n",
639 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
644 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
645 struct request *req, struct nvme_rw_command *cmnd)
647 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
648 struct dma_pool *pool;
649 int length = blk_rq_payload_bytes(req);
650 struct scatterlist *sg = iod->sg;
651 int dma_len = sg_dma_len(sg);
652 u64 dma_addr = sg_dma_address(sg);
653 u32 page_size = dev->ctrl.page_size;
654 int offset = dma_addr & (page_size - 1);
656 void **list = nvme_pci_iod_list(req);
660 length -= (page_size - offset);
666 dma_len -= (page_size - offset);
668 dma_addr += (page_size - offset);
671 dma_addr = sg_dma_address(sg);
672 dma_len = sg_dma_len(sg);
675 if (length <= page_size) {
676 iod->first_dma = dma_addr;
680 nprps = DIV_ROUND_UP(length, page_size);
681 if (nprps <= (256 / 8)) {
682 pool = dev->prp_small_pool;
685 pool = dev->prp_page_pool;
689 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
691 iod->first_dma = dma_addr;
693 return BLK_STS_RESOURCE;
696 iod->first_dma = prp_dma;
699 if (i == page_size >> 3) {
700 __le64 *old_prp_list = prp_list;
701 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
703 return BLK_STS_RESOURCE;
704 list[iod->npages++] = prp_list;
705 prp_list[0] = old_prp_list[i - 1];
706 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
709 prp_list[i++] = cpu_to_le64(dma_addr);
710 dma_len -= page_size;
711 dma_addr += page_size;
717 if (unlikely(dma_len < 0))
720 dma_addr = sg_dma_address(sg);
721 dma_len = sg_dma_len(sg);
725 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
726 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
731 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
732 "Invalid SGL for payload:%d nents:%d\n",
733 blk_rq_payload_bytes(req), iod->nents);
734 return BLK_STS_IOERR;
737 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
738 struct scatterlist *sg)
740 sge->addr = cpu_to_le64(sg_dma_address(sg));
741 sge->length = cpu_to_le32(sg_dma_len(sg));
742 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
745 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
746 dma_addr_t dma_addr, int entries)
748 sge->addr = cpu_to_le64(dma_addr);
749 if (entries < SGES_PER_PAGE) {
750 sge->length = cpu_to_le32(entries * sizeof(*sge));
751 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
753 sge->length = cpu_to_le32(PAGE_SIZE);
754 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
758 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
759 struct request *req, struct nvme_rw_command *cmd, int entries)
761 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
762 struct dma_pool *pool;
763 struct nvme_sgl_desc *sg_list;
764 struct scatterlist *sg = iod->sg;
768 /* setting the transfer type as SGL */
769 cmd->flags = NVME_CMD_SGL_METABUF;
772 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
776 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
777 pool = dev->prp_small_pool;
780 pool = dev->prp_page_pool;
784 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
787 return BLK_STS_RESOURCE;
790 nvme_pci_iod_list(req)[0] = sg_list;
791 iod->first_dma = sgl_dma;
793 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
796 if (i == SGES_PER_PAGE) {
797 struct nvme_sgl_desc *old_sg_desc = sg_list;
798 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
800 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
802 return BLK_STS_RESOURCE;
805 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
806 sg_list[i++] = *link;
807 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
810 nvme_pci_sgl_set_data(&sg_list[i++], sg);
812 } while (--entries > 0);
817 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
818 struct nvme_command *cmnd)
820 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
821 struct request_queue *q = req->q;
822 enum dma_data_direction dma_dir = rq_data_dir(req) ?
823 DMA_TO_DEVICE : DMA_FROM_DEVICE;
824 blk_status_t ret = BLK_STS_IOERR;
827 if (blk_rq_payload_bytes(req) > NVME_INT_BYTES(dev) ||
828 blk_rq_nr_phys_segments(req) > NVME_INT_PAGES) {
829 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
831 return BLK_STS_RESOURCE;
833 iod->sg = iod->inline_sg;
836 iod->use_sgl = nvme_pci_use_sgls(dev, req);
838 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
839 iod->nents = blk_rq_map_sg(q, req, iod->sg);
843 ret = BLK_STS_RESOURCE;
845 if (is_pci_p2pdma_page(sg_page(iod->sg)))
846 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
849 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
850 dma_dir, DMA_ATTR_NO_WARN);
855 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
857 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
859 if (ret != BLK_STS_OK)
863 if (blk_integrity_rq(req)) {
864 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
867 sg_init_table(&iod->meta_sg, 1);
868 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
871 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
874 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
880 nvme_unmap_data(dev, req);
885 * NOTE: ns is NULL when called on the admin queue.
887 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
888 const struct blk_mq_queue_data *bd)
890 struct nvme_ns *ns = hctx->queue->queuedata;
891 struct nvme_queue *nvmeq = hctx->driver_data;
892 struct nvme_dev *dev = nvmeq->dev;
893 struct request *req = bd->rq;
894 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
895 struct nvme_command cmnd;
903 * We should not need to do this, but we're still using this to
904 * ensure we can drain requests on a dying queue.
906 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
907 return BLK_STS_IOERR;
909 ret = nvme_setup_cmd(ns, req, &cmnd);
913 if (blk_rq_nr_phys_segments(req)) {
914 ret = nvme_map_data(dev, req, &cmnd);
919 blk_mq_start_request(req);
920 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
923 nvme_cleanup_cmd(req);
927 static void nvme_pci_complete_rq(struct request *req)
929 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
931 nvme_cleanup_cmd(req);
932 nvme_unmap_data(iod->nvmeq->dev, req);
933 nvme_complete_rq(req);
936 /* We read the CQE phase first to check if the rest of the entry is valid */
937 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
939 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
943 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
945 u16 head = nvmeq->cq_head;
947 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
949 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
952 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
954 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
957 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
958 dev_warn(nvmeq->dev->ctrl.device,
959 "invalid id %d completed on queue %d\n",
960 cqe->command_id, le16_to_cpu(cqe->sq_id));
965 * AEN requests are special as they don't time out and can
966 * survive any kind of queue freeze and often don't respond to
967 * aborts. We don't even bother to allocate a struct request
968 * for them but rather special case them here.
970 if (unlikely(nvmeq->qid == 0 &&
971 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
972 nvme_complete_async_event(&nvmeq->dev->ctrl,
973 cqe->status, &cqe->result);
977 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
978 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
979 nvme_end_request(req, cqe->status, cqe->result);
982 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
984 while (start != end) {
985 nvme_handle_cqe(nvmeq, start);
986 if (++start == nvmeq->q_depth)
991 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
993 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
995 nvmeq->cq_phase = !nvmeq->cq_phase;
1001 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1002 u16 *end, unsigned int tag)
1006 *start = nvmeq->cq_head;
1007 while (nvme_cqe_pending(nvmeq)) {
1008 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1010 nvme_update_cq_head(nvmeq);
1012 *end = nvmeq->cq_head;
1015 nvme_ring_cq_doorbell(nvmeq);
1019 static irqreturn_t nvme_irq(int irq, void *data)
1021 struct nvme_queue *nvmeq = data;
1022 irqreturn_t ret = IRQ_NONE;
1026 * The rmb/wmb pair ensures we see all updates from a previous run of
1027 * the irq handler, even if that was on another CPU.
1030 if (nvmeq->cq_head != nvmeq->last_cq_head)
1032 nvme_process_cq(nvmeq, &start, &end, -1);
1033 nvmeq->last_cq_head = nvmeq->cq_head;
1037 nvme_complete_cqes(nvmeq, start, end);
1044 static irqreturn_t nvme_irq_check(int irq, void *data)
1046 struct nvme_queue *nvmeq = data;
1047 if (nvme_cqe_pending(nvmeq))
1048 return IRQ_WAKE_THREAD;
1053 * Poll for completions any queue, including those not dedicated to polling.
1054 * Can be called from any context.
1056 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
1058 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1063 * For a poll queue we need to protect against the polling thread
1064 * using the CQ lock. For normal interrupt driven threads we have
1065 * to disable the interrupt to avoid racing with it.
1067 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) {
1068 spin_lock(&nvmeq->cq_poll_lock);
1069 found = nvme_process_cq(nvmeq, &start, &end, tag);
1070 spin_unlock(&nvmeq->cq_poll_lock);
1072 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1073 found = nvme_process_cq(nvmeq, &start, &end, tag);
1074 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1077 nvme_complete_cqes(nvmeq, start, end);
1081 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1083 struct nvme_queue *nvmeq = hctx->driver_data;
1087 if (!nvme_cqe_pending(nvmeq))
1090 spin_lock(&nvmeq->cq_poll_lock);
1091 found = nvme_process_cq(nvmeq, &start, &end, -1);
1092 spin_unlock(&nvmeq->cq_poll_lock);
1094 nvme_complete_cqes(nvmeq, start, end);
1098 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1100 struct nvme_dev *dev = to_nvme_dev(ctrl);
1101 struct nvme_queue *nvmeq = &dev->queues[0];
1102 struct nvme_command c;
1104 memset(&c, 0, sizeof(c));
1105 c.common.opcode = nvme_admin_async_event;
1106 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1107 nvme_submit_cmd(nvmeq, &c, true);
1110 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1112 struct nvme_command c;
1114 memset(&c, 0, sizeof(c));
1115 c.delete_queue.opcode = opcode;
1116 c.delete_queue.qid = cpu_to_le16(id);
1118 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1121 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1122 struct nvme_queue *nvmeq, s16 vector)
1124 struct nvme_command c;
1125 int flags = NVME_QUEUE_PHYS_CONTIG;
1127 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1128 flags |= NVME_CQ_IRQ_ENABLED;
1131 * Note: we (ab)use the fact that the prp fields survive if no data
1132 * is attached to the request.
1134 memset(&c, 0, sizeof(c));
1135 c.create_cq.opcode = nvme_admin_create_cq;
1136 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1137 c.create_cq.cqid = cpu_to_le16(qid);
1138 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1139 c.create_cq.cq_flags = cpu_to_le16(flags);
1140 c.create_cq.irq_vector = cpu_to_le16(vector);
1142 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1145 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1146 struct nvme_queue *nvmeq)
1148 struct nvme_ctrl *ctrl = &dev->ctrl;
1149 struct nvme_command c;
1150 int flags = NVME_QUEUE_PHYS_CONTIG;
1153 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1154 * set. Since URGENT priority is zeroes, it makes all queues
1157 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1158 flags |= NVME_SQ_PRIO_MEDIUM;
1161 * Note: we (ab)use the fact that the prp fields survive if no data
1162 * is attached to the request.
1164 memset(&c, 0, sizeof(c));
1165 c.create_sq.opcode = nvme_admin_create_sq;
1166 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1167 c.create_sq.sqid = cpu_to_le16(qid);
1168 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1169 c.create_sq.sq_flags = cpu_to_le16(flags);
1170 c.create_sq.cqid = cpu_to_le16(qid);
1172 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1175 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1177 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1180 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1182 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1185 static void abort_endio(struct request *req, blk_status_t error)
1187 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1188 struct nvme_queue *nvmeq = iod->nvmeq;
1190 dev_warn(nvmeq->dev->ctrl.device,
1191 "Abort status: 0x%x", nvme_req(req)->status);
1192 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1193 blk_mq_free_request(req);
1196 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1199 /* If true, indicates loss of adapter communication, possibly by a
1200 * NVMe Subsystem reset.
1202 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1204 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1205 switch (dev->ctrl.state) {
1206 case NVME_CTRL_RESETTING:
1207 case NVME_CTRL_CONNECTING:
1213 /* We shouldn't reset unless the controller is on fatal error state
1214 * _or_ if we lost the communication with it.
1216 if (!(csts & NVME_CSTS_CFS) && !nssro)
1222 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1224 /* Read a config register to help see what died. */
1228 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1230 if (result == PCIBIOS_SUCCESSFUL)
1231 dev_warn(dev->ctrl.device,
1232 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1235 dev_warn(dev->ctrl.device,
1236 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1240 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1242 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1243 struct nvme_queue *nvmeq = iod->nvmeq;
1244 struct nvme_dev *dev = nvmeq->dev;
1245 struct request *abort_req;
1246 struct nvme_command cmd;
1247 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1249 /* If PCI error recovery process is happening, we cannot reset or
1250 * the recovery mechanism will surely fail.
1253 if (pci_channel_offline(to_pci_dev(dev->dev)))
1254 return BLK_EH_RESET_TIMER;
1257 * Reset immediately if the controller is failed
1259 if (nvme_should_reset(dev, csts)) {
1260 nvme_warn_reset(dev, csts);
1261 nvme_dev_disable(dev, false);
1262 nvme_reset_ctrl(&dev->ctrl);
1267 * Did we miss an interrupt?
1269 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
1270 dev_warn(dev->ctrl.device,
1271 "I/O %d QID %d timeout, completion polled\n",
1272 req->tag, nvmeq->qid);
1277 * Shutdown immediately if controller times out while starting. The
1278 * reset work will see the pci device disabled when it gets the forced
1279 * cancellation error. All outstanding requests are completed on
1280 * shutdown, so we return BLK_EH_DONE.
1282 switch (dev->ctrl.state) {
1283 case NVME_CTRL_CONNECTING:
1284 case NVME_CTRL_RESETTING:
1285 dev_warn_ratelimited(dev->ctrl.device,
1286 "I/O %d QID %d timeout, disable controller\n",
1287 req->tag, nvmeq->qid);
1288 nvme_dev_disable(dev, false);
1289 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1296 * Shutdown the controller immediately and schedule a reset if the
1297 * command was already aborted once before and still hasn't been
1298 * returned to the driver, or if this is the admin queue.
1300 if (!nvmeq->qid || iod->aborted) {
1301 dev_warn(dev->ctrl.device,
1302 "I/O %d QID %d timeout, reset controller\n",
1303 req->tag, nvmeq->qid);
1304 nvme_dev_disable(dev, false);
1305 nvme_reset_ctrl(&dev->ctrl);
1307 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1311 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1312 atomic_inc(&dev->ctrl.abort_limit);
1313 return BLK_EH_RESET_TIMER;
1317 memset(&cmd, 0, sizeof(cmd));
1318 cmd.abort.opcode = nvme_admin_abort_cmd;
1319 cmd.abort.cid = req->tag;
1320 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1322 dev_warn(nvmeq->dev->ctrl.device,
1323 "I/O %d QID %d timeout, aborting\n",
1324 req->tag, nvmeq->qid);
1326 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1327 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1328 if (IS_ERR(abort_req)) {
1329 atomic_inc(&dev->ctrl.abort_limit);
1330 return BLK_EH_RESET_TIMER;
1333 abort_req->timeout = ADMIN_TIMEOUT;
1334 abort_req->end_io_data = NULL;
1335 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1338 * The aborted req will be completed on receiving the abort req.
1339 * We enable the timer again. If hit twice, it'll cause a device reset,
1340 * as the device then is in a faulty state.
1342 return BLK_EH_RESET_TIMER;
1345 static void nvme_free_queue(struct nvme_queue *nvmeq)
1347 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
1348 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1349 if (!nvmeq->sq_cmds)
1352 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1353 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1354 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1356 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
1357 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1361 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1365 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1366 dev->ctrl.queue_count--;
1367 nvme_free_queue(&dev->queues[i]);
1372 * nvme_suspend_queue - put queue into suspended state
1373 * @nvmeq: queue to suspend
1375 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1377 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1380 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1383 nvmeq->dev->online_queues--;
1384 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1385 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1386 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1387 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1391 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1395 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1396 nvme_suspend_queue(&dev->queues[i]);
1399 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1401 struct nvme_queue *nvmeq = &dev->queues[0];
1404 nvme_shutdown_ctrl(&dev->ctrl);
1406 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1408 nvme_poll_irqdisable(nvmeq, -1);
1411 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1414 int q_depth = dev->q_depth;
1415 unsigned q_size_aligned = roundup(q_depth * entry_size,
1416 dev->ctrl.page_size);
1418 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1419 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1420 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1421 q_depth = div_u64(mem_per_q, entry_size);
1424 * Ensure the reduced q_depth is above some threshold where it
1425 * would be better to map queues in system memory with the
1435 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1438 struct pci_dev *pdev = to_pci_dev(dev->dev);
1440 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1441 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1442 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1444 if (nvmeq->sq_dma_addr) {
1445 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1450 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1451 &nvmeq->sq_dma_addr, GFP_KERNEL);
1452 if (!nvmeq->sq_cmds)
1457 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1459 struct nvme_queue *nvmeq = &dev->queues[qid];
1461 if (dev->ctrl.queue_count > qid)
1464 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1465 &nvmeq->cq_dma_addr, GFP_KERNEL);
1469 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1473 spin_lock_init(&nvmeq->sq_lock);
1474 spin_lock_init(&nvmeq->cq_poll_lock);
1476 nvmeq->cq_phase = 1;
1477 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1478 nvmeq->q_depth = depth;
1480 dev->ctrl.queue_count++;
1485 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1486 nvmeq->cq_dma_addr);
1491 static int queue_request_irq(struct nvme_queue *nvmeq)
1493 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1494 int nr = nvmeq->dev->ctrl.instance;
1496 if (use_threaded_interrupts) {
1497 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1498 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1500 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1501 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1505 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1507 struct nvme_dev *dev = nvmeq->dev;
1510 nvmeq->last_sq_tail = 0;
1512 nvmeq->cq_phase = 1;
1513 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1514 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1515 nvme_dbbuf_init(dev, nvmeq, qid);
1516 dev->online_queues++;
1517 wmb(); /* ensure the first interrupt sees the initialization */
1520 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1522 struct nvme_dev *dev = nvmeq->dev;
1526 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1529 * A queue's vector matches the queue identifier unless the controller
1530 * has only one vector available.
1533 vector = dev->num_vecs == 1 ? 0 : qid;
1535 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1537 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1541 result = adapter_alloc_sq(dev, qid, nvmeq);
1547 nvmeq->cq_vector = vector;
1548 nvme_init_queue(nvmeq, qid);
1551 nvmeq->cq_vector = vector;
1552 result = queue_request_irq(nvmeq);
1557 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1561 dev->online_queues--;
1562 adapter_delete_sq(dev, qid);
1564 adapter_delete_cq(dev, qid);
1568 static const struct blk_mq_ops nvme_mq_admin_ops = {
1569 .queue_rq = nvme_queue_rq,
1570 .complete = nvme_pci_complete_rq,
1571 .init_hctx = nvme_admin_init_hctx,
1572 .exit_hctx = nvme_admin_exit_hctx,
1573 .init_request = nvme_init_request,
1574 .timeout = nvme_timeout,
1577 static const struct blk_mq_ops nvme_mq_ops = {
1578 .queue_rq = nvme_queue_rq,
1579 .complete = nvme_pci_complete_rq,
1580 .commit_rqs = nvme_commit_rqs,
1581 .init_hctx = nvme_init_hctx,
1582 .init_request = nvme_init_request,
1583 .map_queues = nvme_pci_map_queues,
1584 .timeout = nvme_timeout,
1588 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1590 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1592 * If the controller was reset during removal, it's possible
1593 * user requests may be waiting on a stopped queue. Start the
1594 * queue to flush these to completion.
1596 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1597 blk_cleanup_queue(dev->ctrl.admin_q);
1598 blk_mq_free_tag_set(&dev->admin_tagset);
1602 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1604 if (!dev->ctrl.admin_q) {
1605 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1606 dev->admin_tagset.nr_hw_queues = 1;
1608 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1609 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1610 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1611 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1612 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1613 dev->admin_tagset.driver_data = dev;
1615 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1617 dev->ctrl.admin_tagset = &dev->admin_tagset;
1619 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1620 if (IS_ERR(dev->ctrl.admin_q)) {
1621 blk_mq_free_tag_set(&dev->admin_tagset);
1624 if (!blk_get_queue(dev->ctrl.admin_q)) {
1625 nvme_dev_remove_admin(dev);
1626 dev->ctrl.admin_q = NULL;
1630 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1635 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1637 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1640 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1642 struct pci_dev *pdev = to_pci_dev(dev->dev);
1644 if (size <= dev->bar_mapped_size)
1646 if (size > pci_resource_len(pdev, 0))
1650 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1652 dev->bar_mapped_size = 0;
1655 dev->bar_mapped_size = size;
1656 dev->dbs = dev->bar + NVME_REG_DBS;
1661 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1665 struct nvme_queue *nvmeq;
1667 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1671 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1672 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1674 if (dev->subsystem &&
1675 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1676 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1678 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1682 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1686 nvmeq = &dev->queues[0];
1687 aqa = nvmeq->q_depth - 1;
1690 writel(aqa, dev->bar + NVME_REG_AQA);
1691 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1692 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1694 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1698 nvmeq->cq_vector = 0;
1699 nvme_init_queue(nvmeq, 0);
1700 result = queue_request_irq(nvmeq);
1702 dev->online_queues--;
1706 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1710 static int nvme_create_io_queues(struct nvme_dev *dev)
1712 unsigned i, max, rw_queues;
1715 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1716 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1722 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1723 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1724 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1725 dev->io_queues[HCTX_TYPE_READ];
1730 for (i = dev->online_queues; i <= max; i++) {
1731 bool polled = i > rw_queues;
1733 ret = nvme_create_queue(&dev->queues[i], i, polled);
1739 * Ignore failing Create SQ/CQ commands, we can continue with less
1740 * than the desired amount of queues, and even a controller without
1741 * I/O queues can still be used to issue admin commands. This might
1742 * be useful to upgrade a buggy firmware for example.
1744 return ret >= 0 ? 0 : ret;
1747 static ssize_t nvme_cmb_show(struct device *dev,
1748 struct device_attribute *attr,
1751 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1753 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1754 ndev->cmbloc, ndev->cmbsz);
1756 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1758 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1760 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1762 return 1ULL << (12 + 4 * szu);
1765 static u32 nvme_cmb_size(struct nvme_dev *dev)
1767 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1770 static void nvme_map_cmb(struct nvme_dev *dev)
1773 resource_size_t bar_size;
1774 struct pci_dev *pdev = to_pci_dev(dev->dev);
1780 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1783 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1785 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1786 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1787 bar = NVME_CMB_BIR(dev->cmbloc);
1788 bar_size = pci_resource_len(pdev, bar);
1790 if (offset > bar_size)
1794 * Controllers may support a CMB size larger than their BAR,
1795 * for example, due to being behind a bridge. Reduce the CMB to
1796 * the reported size of the BAR
1798 if (size > bar_size - offset)
1799 size = bar_size - offset;
1801 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1802 dev_warn(dev->ctrl.device,
1803 "failed to register the CMB\n");
1807 dev->cmb_size = size;
1808 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1810 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1811 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1812 pci_p2pmem_publish(pdev, true);
1814 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1815 &dev_attr_cmb.attr, NULL))
1816 dev_warn(dev->ctrl.device,
1817 "failed to add sysfs attribute for CMB\n");
1820 static inline void nvme_release_cmb(struct nvme_dev *dev)
1822 if (dev->cmb_size) {
1823 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1824 &dev_attr_cmb.attr, NULL);
1829 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1831 u64 dma_addr = dev->host_mem_descs_dma;
1832 struct nvme_command c;
1835 memset(&c, 0, sizeof(c));
1836 c.features.opcode = nvme_admin_set_features;
1837 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1838 c.features.dword11 = cpu_to_le32(bits);
1839 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1840 ilog2(dev->ctrl.page_size));
1841 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1842 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1843 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1845 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1847 dev_warn(dev->ctrl.device,
1848 "failed to set host mem (err %d, flags %#x).\n",
1854 static void nvme_free_host_mem(struct nvme_dev *dev)
1858 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1859 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1860 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1862 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1863 le64_to_cpu(desc->addr),
1864 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1867 kfree(dev->host_mem_desc_bufs);
1868 dev->host_mem_desc_bufs = NULL;
1869 dma_free_coherent(dev->dev,
1870 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1871 dev->host_mem_descs, dev->host_mem_descs_dma);
1872 dev->host_mem_descs = NULL;
1873 dev->nr_host_mem_descs = 0;
1876 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1879 struct nvme_host_mem_buf_desc *descs;
1880 u32 max_entries, len;
1881 dma_addr_t descs_dma;
1886 tmp = (preferred + chunk_size - 1);
1887 do_div(tmp, chunk_size);
1890 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1891 max_entries = dev->ctrl.hmmaxd;
1893 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1894 &descs_dma, GFP_KERNEL);
1898 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1900 goto out_free_descs;
1902 for (size = 0; size < preferred && i < max_entries; size += len) {
1903 dma_addr_t dma_addr;
1905 len = min_t(u64, chunk_size, preferred - size);
1906 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1907 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1911 descs[i].addr = cpu_to_le64(dma_addr);
1912 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1919 dev->nr_host_mem_descs = i;
1920 dev->host_mem_size = size;
1921 dev->host_mem_descs = descs;
1922 dev->host_mem_descs_dma = descs_dma;
1923 dev->host_mem_desc_bufs = bufs;
1928 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1930 dma_free_attrs(dev->dev, size, bufs[i],
1931 le64_to_cpu(descs[i].addr),
1932 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1937 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1940 dev->host_mem_descs = NULL;
1944 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1948 /* start big and work our way down */
1949 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1950 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1952 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1953 if (!min || dev->host_mem_size >= min)
1955 nvme_free_host_mem(dev);
1962 static int nvme_setup_host_mem(struct nvme_dev *dev)
1964 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1965 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1966 u64 min = (u64)dev->ctrl.hmmin * 4096;
1967 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1970 preferred = min(preferred, max);
1972 dev_warn(dev->ctrl.device,
1973 "min host memory (%lld MiB) above limit (%d MiB).\n",
1974 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1975 nvme_free_host_mem(dev);
1980 * If we already have a buffer allocated check if we can reuse it.
1982 if (dev->host_mem_descs) {
1983 if (dev->host_mem_size >= min)
1984 enable_bits |= NVME_HOST_MEM_RETURN;
1986 nvme_free_host_mem(dev);
1989 if (!dev->host_mem_descs) {
1990 if (nvme_alloc_host_mem(dev, min, preferred)) {
1991 dev_warn(dev->ctrl.device,
1992 "failed to allocate host memory buffer.\n");
1993 return 0; /* controller must work without HMB */
1996 dev_info(dev->ctrl.device,
1997 "allocated %lld MiB host memory buffer.\n",
1998 dev->host_mem_size >> ilog2(SZ_1M));
2001 ret = nvme_set_host_mem(dev, enable_bits);
2003 nvme_free_host_mem(dev);
2008 * nirqs is the number of interrupts available for write and read
2009 * queues. The core already reserved an interrupt for the admin queue.
2011 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2013 struct nvme_dev *dev = affd->priv;
2014 unsigned int nr_read_queues;
2017 * If there is no interupt available for queues, ensure that
2018 * the default queue is set to 1. The affinity set size is
2019 * also set to one, but the irq core ignores it for this case.
2021 * If only one interrupt is available or 'write_queue' == 0, combine
2022 * write and read queues.
2024 * If 'write_queues' > 0, ensure it leaves room for at least one read
2030 } else if (nrirqs == 1 || !write_queues) {
2032 } else if (write_queues >= nrirqs) {
2035 nr_read_queues = nrirqs - write_queues;
2038 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2039 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2040 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2041 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2042 affd->nr_sets = nr_read_queues ? 2 : 1;
2045 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2047 struct pci_dev *pdev = to_pci_dev(dev->dev);
2048 struct irq_affinity affd = {
2050 .calc_sets = nvme_calc_irq_sets,
2053 unsigned int irq_queues, this_p_queues;
2056 * Poll queues don't need interrupts, but we need at least one IO
2057 * queue left over for non-polled IO.
2059 this_p_queues = poll_queues;
2060 if (this_p_queues >= nr_io_queues) {
2061 this_p_queues = nr_io_queues - 1;
2064 irq_queues = nr_io_queues - this_p_queues + 1;
2066 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2068 /* Initialize for the single interrupt case */
2069 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2070 dev->io_queues[HCTX_TYPE_READ] = 0;
2072 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2073 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2076 static void nvme_disable_io_queues(struct nvme_dev *dev)
2078 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2079 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2082 static int nvme_setup_io_queues(struct nvme_dev *dev)
2084 struct nvme_queue *adminq = &dev->queues[0];
2085 struct pci_dev *pdev = to_pci_dev(dev->dev);
2086 int result, nr_io_queues;
2089 nr_io_queues = max_io_queues();
2090 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2094 if (nr_io_queues == 0)
2097 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2099 if (dev->cmb_use_sqes) {
2100 result = nvme_cmb_qdepth(dev, nr_io_queues,
2101 sizeof(struct nvme_command));
2103 dev->q_depth = result;
2105 dev->cmb_use_sqes = false;
2109 size = db_bar_size(dev, nr_io_queues);
2110 result = nvme_remap_bar(dev, size);
2113 if (!--nr_io_queues)
2116 adminq->q_db = dev->dbs;
2119 /* Deregister the admin queue's interrupt */
2120 pci_free_irq(pdev, 0, adminq);
2123 * If we enable msix early due to not intx, disable it again before
2124 * setting up the full range we need.
2126 pci_free_irq_vectors(pdev);
2128 result = nvme_setup_irqs(dev, nr_io_queues);
2132 dev->num_vecs = result;
2133 result = max(result - 1, 1);
2134 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2137 * Should investigate if there's a performance win from allocating
2138 * more queues than interrupt vectors; it might allow the submission
2139 * path to scale better, even if the receive path is limited by the
2140 * number of interrupts.
2142 result = queue_request_irq(adminq);
2145 set_bit(NVMEQ_ENABLED, &adminq->flags);
2147 result = nvme_create_io_queues(dev);
2148 if (result || dev->online_queues < 2)
2151 if (dev->online_queues - 1 < dev->max_qid) {
2152 nr_io_queues = dev->online_queues - 1;
2153 nvme_disable_io_queues(dev);
2154 nvme_suspend_io_queues(dev);
2157 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2158 dev->io_queues[HCTX_TYPE_DEFAULT],
2159 dev->io_queues[HCTX_TYPE_READ],
2160 dev->io_queues[HCTX_TYPE_POLL]);
2164 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2166 struct nvme_queue *nvmeq = req->end_io_data;
2168 blk_mq_free_request(req);
2169 complete(&nvmeq->delete_done);
2172 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2174 struct nvme_queue *nvmeq = req->end_io_data;
2177 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2179 nvme_del_queue_end(req, error);
2182 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2184 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2185 struct request *req;
2186 struct nvme_command cmd;
2188 memset(&cmd, 0, sizeof(cmd));
2189 cmd.delete_queue.opcode = opcode;
2190 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2192 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2194 return PTR_ERR(req);
2196 req->timeout = ADMIN_TIMEOUT;
2197 req->end_io_data = nvmeq;
2199 init_completion(&nvmeq->delete_done);
2200 blk_execute_rq_nowait(q, NULL, req, false,
2201 opcode == nvme_admin_delete_cq ?
2202 nvme_del_cq_end : nvme_del_queue_end);
2206 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2208 int nr_queues = dev->online_queues - 1, sent = 0;
2209 unsigned long timeout;
2212 timeout = ADMIN_TIMEOUT;
2213 while (nr_queues > 0) {
2214 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2220 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2222 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2227 /* handle any remaining CQEs */
2228 if (opcode == nvme_admin_delete_cq &&
2229 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2230 nvme_poll_irqdisable(nvmeq, -1);
2240 * return error value only when tagset allocation failed
2242 static int nvme_dev_add(struct nvme_dev *dev)
2246 if (!dev->ctrl.tagset) {
2247 dev->tagset.ops = &nvme_mq_ops;
2248 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2249 dev->tagset.nr_maps = 2; /* default + read */
2250 if (dev->io_queues[HCTX_TYPE_POLL])
2251 dev->tagset.nr_maps++;
2252 dev->tagset.timeout = NVME_IO_TIMEOUT;
2253 dev->tagset.numa_node = dev_to_node(dev->dev);
2254 dev->tagset.queue_depth =
2255 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2256 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2257 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2258 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2259 nvme_pci_cmd_size(dev, true));
2261 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2262 dev->tagset.driver_data = dev;
2264 ret = blk_mq_alloc_tag_set(&dev->tagset);
2266 dev_warn(dev->ctrl.device,
2267 "IO queues tagset allocation failed %d\n", ret);
2270 dev->ctrl.tagset = &dev->tagset;
2272 nvme_dbbuf_set(dev);
2274 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2276 /* Free previously allocated queues that are no longer usable */
2277 nvme_free_queues(dev, dev->online_queues);
2283 static int nvme_pci_enable(struct nvme_dev *dev)
2285 int result = -ENOMEM;
2286 struct pci_dev *pdev = to_pci_dev(dev->dev);
2288 if (pci_enable_device_mem(pdev))
2291 pci_set_master(pdev);
2293 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2294 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2297 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2303 * Some devices and/or platforms don't advertise or work with INTx
2304 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2305 * adjust this later.
2307 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2311 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2313 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2315 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2316 dev->dbs = dev->bar + 4096;
2319 * Temporary fix for the Apple controller found in the MacBook8,1 and
2320 * some MacBook7,1 to avoid controller resets and data loss.
2322 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2324 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2325 "set queue depth=%u to work around controller resets\n",
2327 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2328 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2329 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2331 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2332 "set queue depth=%u\n", dev->q_depth);
2337 pci_enable_pcie_error_reporting(pdev);
2338 pci_save_state(pdev);
2342 pci_disable_device(pdev);
2346 static void nvme_dev_unmap(struct nvme_dev *dev)
2350 pci_release_mem_regions(to_pci_dev(dev->dev));
2353 static void nvme_pci_disable(struct nvme_dev *dev)
2355 struct pci_dev *pdev = to_pci_dev(dev->dev);
2357 pci_free_irq_vectors(pdev);
2359 if (pci_is_enabled(pdev)) {
2360 pci_disable_pcie_error_reporting(pdev);
2361 pci_disable_device(pdev);
2365 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2368 struct pci_dev *pdev = to_pci_dev(dev->dev);
2370 mutex_lock(&dev->shutdown_lock);
2371 if (pci_is_enabled(pdev)) {
2372 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2374 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2375 dev->ctrl.state == NVME_CTRL_RESETTING)
2376 nvme_start_freeze(&dev->ctrl);
2377 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2378 pdev->error_state != pci_channel_io_normal);
2382 * Give the controller a chance to complete all entered requests if
2383 * doing a safe shutdown.
2387 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2390 nvme_stop_queues(&dev->ctrl);
2392 if (!dead && dev->ctrl.queue_count > 0) {
2393 nvme_disable_io_queues(dev);
2394 nvme_disable_admin_queue(dev, shutdown);
2396 nvme_suspend_io_queues(dev);
2397 nvme_suspend_queue(&dev->queues[0]);
2398 nvme_pci_disable(dev);
2400 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2401 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2404 * The driver will not be starting up queues again if shutting down so
2405 * must flush all entered requests to their failed completion to avoid
2406 * deadlocking blk-mq hot-cpu notifier.
2409 nvme_start_queues(&dev->ctrl);
2410 mutex_unlock(&dev->shutdown_lock);
2413 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2415 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2416 PAGE_SIZE, PAGE_SIZE, 0);
2417 if (!dev->prp_page_pool)
2420 /* Optimisation for I/Os between 4k and 128k */
2421 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2423 if (!dev->prp_small_pool) {
2424 dma_pool_destroy(dev->prp_page_pool);
2430 static void nvme_release_prp_pools(struct nvme_dev *dev)
2432 dma_pool_destroy(dev->prp_page_pool);
2433 dma_pool_destroy(dev->prp_small_pool);
2436 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2438 struct nvme_dev *dev = to_nvme_dev(ctrl);
2440 nvme_dbbuf_dma_free(dev);
2441 put_device(dev->dev);
2442 if (dev->tagset.tags)
2443 blk_mq_free_tag_set(&dev->tagset);
2444 if (dev->ctrl.admin_q)
2445 blk_put_queue(dev->ctrl.admin_q);
2447 free_opal_dev(dev->ctrl.opal_dev);
2448 mempool_destroy(dev->iod_mempool);
2452 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2454 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2456 nvme_get_ctrl(&dev->ctrl);
2457 nvme_dev_disable(dev, false);
2458 nvme_kill_queues(&dev->ctrl);
2459 if (!queue_work(nvme_wq, &dev->remove_work))
2460 nvme_put_ctrl(&dev->ctrl);
2463 static void nvme_reset_work(struct work_struct *work)
2465 struct nvme_dev *dev =
2466 container_of(work, struct nvme_dev, ctrl.reset_work);
2467 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2468 int result = -ENODEV;
2469 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2471 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2475 * If we're called to reset a live controller first shut it down before
2478 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2479 nvme_dev_disable(dev, false);
2481 mutex_lock(&dev->shutdown_lock);
2482 result = nvme_pci_enable(dev);
2486 result = nvme_pci_configure_admin_queue(dev);
2490 result = nvme_alloc_admin_tags(dev);
2495 * Limit the max command size to prevent iod->sg allocations going
2496 * over a single page.
2498 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2499 dev->ctrl.max_segments = NVME_MAX_SEGS;
2500 mutex_unlock(&dev->shutdown_lock);
2503 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2504 * initializing procedure here.
2506 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2507 dev_warn(dev->ctrl.device,
2508 "failed to mark controller CONNECTING\n");
2512 result = nvme_init_identify(&dev->ctrl);
2516 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2517 if (!dev->ctrl.opal_dev)
2518 dev->ctrl.opal_dev =
2519 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2520 else if (was_suspend)
2521 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2523 free_opal_dev(dev->ctrl.opal_dev);
2524 dev->ctrl.opal_dev = NULL;
2527 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2528 result = nvme_dbbuf_dma_alloc(dev);
2531 "unable to allocate dma for dbbuf\n");
2534 if (dev->ctrl.hmpre) {
2535 result = nvme_setup_host_mem(dev);
2540 result = nvme_setup_io_queues(dev);
2545 * Keep the controller around but remove all namespaces if we don't have
2546 * any working I/O queue.
2548 if (dev->online_queues < 2) {
2549 dev_warn(dev->ctrl.device, "IO queues not created\n");
2550 nvme_kill_queues(&dev->ctrl);
2551 nvme_remove_namespaces(&dev->ctrl);
2552 new_state = NVME_CTRL_ADMIN_ONLY;
2554 nvme_start_queues(&dev->ctrl);
2555 nvme_wait_freeze(&dev->ctrl);
2556 /* hit this only when allocate tagset fails */
2557 if (nvme_dev_add(dev))
2558 new_state = NVME_CTRL_ADMIN_ONLY;
2559 nvme_unfreeze(&dev->ctrl);
2563 * If only admin queue live, keep it to do further investigation or
2566 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2567 dev_warn(dev->ctrl.device,
2568 "failed to mark controller state %d\n", new_state);
2572 nvme_start_ctrl(&dev->ctrl);
2576 mutex_unlock(&dev->shutdown_lock);
2578 nvme_remove_dead_ctrl(dev, result);
2581 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2583 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2584 struct pci_dev *pdev = to_pci_dev(dev->dev);
2586 if (pci_get_drvdata(pdev))
2587 device_release_driver(&pdev->dev);
2588 nvme_put_ctrl(&dev->ctrl);
2591 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2593 *val = readl(to_nvme_dev(ctrl)->bar + off);
2597 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2599 writel(val, to_nvme_dev(ctrl)->bar + off);
2603 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2605 *val = readq(to_nvme_dev(ctrl)->bar + off);
2609 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2611 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2613 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2616 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2618 .module = THIS_MODULE,
2619 .flags = NVME_F_METADATA_SUPPORTED |
2621 .reg_read32 = nvme_pci_reg_read32,
2622 .reg_write32 = nvme_pci_reg_write32,
2623 .reg_read64 = nvme_pci_reg_read64,
2624 .free_ctrl = nvme_pci_free_ctrl,
2625 .submit_async_event = nvme_pci_submit_async_event,
2626 .get_address = nvme_pci_get_address,
2629 static int nvme_dev_map(struct nvme_dev *dev)
2631 struct pci_dev *pdev = to_pci_dev(dev->dev);
2633 if (pci_request_mem_regions(pdev, "nvme"))
2636 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2641 pci_release_mem_regions(pdev);
2645 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2647 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2649 * Several Samsung devices seem to drop off the PCIe bus
2650 * randomly when APST is on and uses the deepest sleep state.
2651 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2652 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2653 * 950 PRO 256GB", but it seems to be restricted to two Dell
2656 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2657 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2658 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2659 return NVME_QUIRK_NO_DEEPEST_PS;
2660 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2662 * Samsung SSD 960 EVO drops off the PCIe bus after system
2663 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2664 * within few minutes after bootup on a Coffee Lake board -
2667 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2668 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2669 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2670 return NVME_QUIRK_NO_APST;
2676 static void nvme_async_probe(void *data, async_cookie_t cookie)
2678 struct nvme_dev *dev = data;
2680 nvme_reset_ctrl_sync(&dev->ctrl);
2681 flush_work(&dev->ctrl.scan_work);
2682 nvme_put_ctrl(&dev->ctrl);
2685 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2687 int node, result = -ENOMEM;
2688 struct nvme_dev *dev;
2689 unsigned long quirks = id->driver_data;
2692 node = dev_to_node(&pdev->dev);
2693 if (node == NUMA_NO_NODE)
2694 set_dev_node(&pdev->dev, first_memory_node);
2696 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2700 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2705 dev->dev = get_device(&pdev->dev);
2706 pci_set_drvdata(pdev, dev);
2708 result = nvme_dev_map(dev);
2712 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2713 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2714 mutex_init(&dev->shutdown_lock);
2716 result = nvme_setup_prp_pools(dev);
2720 quirks |= check_vendor_combination_bug(pdev);
2723 * Double check that our mempool alloc size will cover the biggest
2724 * command we support.
2726 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2727 NVME_MAX_SEGS, true);
2728 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2730 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2732 (void *) alloc_size,
2734 if (!dev->iod_mempool) {
2739 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2742 goto release_mempool;
2744 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2746 nvme_get_ctrl(&dev->ctrl);
2747 async_schedule(nvme_async_probe, dev);
2752 mempool_destroy(dev->iod_mempool);
2754 nvme_release_prp_pools(dev);
2756 nvme_dev_unmap(dev);
2758 put_device(dev->dev);
2765 static void nvme_reset_prepare(struct pci_dev *pdev)
2767 struct nvme_dev *dev = pci_get_drvdata(pdev);
2768 nvme_dev_disable(dev, false);
2771 static void nvme_reset_done(struct pci_dev *pdev)
2773 struct nvme_dev *dev = pci_get_drvdata(pdev);
2774 nvme_reset_ctrl_sync(&dev->ctrl);
2777 static void nvme_shutdown(struct pci_dev *pdev)
2779 struct nvme_dev *dev = pci_get_drvdata(pdev);
2780 nvme_dev_disable(dev, true);
2784 * The driver's remove may be called on a device in a partially initialized
2785 * state. This function must not have any dependencies on the device state in
2788 static void nvme_remove(struct pci_dev *pdev)
2790 struct nvme_dev *dev = pci_get_drvdata(pdev);
2792 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2793 pci_set_drvdata(pdev, NULL);
2795 if (!pci_device_is_present(pdev)) {
2796 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2797 nvme_dev_disable(dev, true);
2798 nvme_dev_remove_admin(dev);
2801 flush_work(&dev->ctrl.reset_work);
2802 nvme_stop_ctrl(&dev->ctrl);
2803 nvme_remove_namespaces(&dev->ctrl);
2804 nvme_dev_disable(dev, true);
2805 nvme_release_cmb(dev);
2806 nvme_free_host_mem(dev);
2807 nvme_dev_remove_admin(dev);
2808 nvme_free_queues(dev, 0);
2809 nvme_uninit_ctrl(&dev->ctrl);
2810 nvme_release_prp_pools(dev);
2811 nvme_dev_unmap(dev);
2812 nvme_put_ctrl(&dev->ctrl);
2815 #ifdef CONFIG_PM_SLEEP
2816 static int nvme_suspend(struct device *dev)
2818 struct pci_dev *pdev = to_pci_dev(dev);
2819 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2821 nvme_dev_disable(ndev, true);
2825 static int nvme_resume(struct device *dev)
2827 struct pci_dev *pdev = to_pci_dev(dev);
2828 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2830 nvme_reset_ctrl(&ndev->ctrl);
2835 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2837 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2838 pci_channel_state_t state)
2840 struct nvme_dev *dev = pci_get_drvdata(pdev);
2843 * A frozen channel requires a reset. When detected, this method will
2844 * shutdown the controller to quiesce. The controller will be restarted
2845 * after the slot reset through driver's slot_reset callback.
2848 case pci_channel_io_normal:
2849 return PCI_ERS_RESULT_CAN_RECOVER;
2850 case pci_channel_io_frozen:
2851 dev_warn(dev->ctrl.device,
2852 "frozen state error detected, reset controller\n");
2853 nvme_dev_disable(dev, false);
2854 return PCI_ERS_RESULT_NEED_RESET;
2855 case pci_channel_io_perm_failure:
2856 dev_warn(dev->ctrl.device,
2857 "failure state error detected, request disconnect\n");
2858 return PCI_ERS_RESULT_DISCONNECT;
2860 return PCI_ERS_RESULT_NEED_RESET;
2863 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2865 struct nvme_dev *dev = pci_get_drvdata(pdev);
2867 dev_info(dev->ctrl.device, "restart after slot reset\n");
2868 pci_restore_state(pdev);
2869 nvme_reset_ctrl(&dev->ctrl);
2870 return PCI_ERS_RESULT_RECOVERED;
2873 static void nvme_error_resume(struct pci_dev *pdev)
2875 struct nvme_dev *dev = pci_get_drvdata(pdev);
2877 flush_work(&dev->ctrl.reset_work);
2880 static const struct pci_error_handlers nvme_err_handler = {
2881 .error_detected = nvme_error_detected,
2882 .slot_reset = nvme_slot_reset,
2883 .resume = nvme_error_resume,
2884 .reset_prepare = nvme_reset_prepare,
2885 .reset_done = nvme_reset_done,
2888 static const struct pci_device_id nvme_id_table[] = {
2889 { PCI_VDEVICE(INTEL, 0x0953),
2890 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2891 NVME_QUIRK_DEALLOCATE_ZEROES, },
2892 { PCI_VDEVICE(INTEL, 0x0a53),
2893 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2894 NVME_QUIRK_DEALLOCATE_ZEROES, },
2895 { PCI_VDEVICE(INTEL, 0x0a54),
2896 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2897 NVME_QUIRK_DEALLOCATE_ZEROES, },
2898 { PCI_VDEVICE(INTEL, 0x0a55),
2899 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2900 NVME_QUIRK_DEALLOCATE_ZEROES, },
2901 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2902 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2903 NVME_QUIRK_MEDIUM_PRIO_SQ },
2904 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2905 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2906 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2907 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
2908 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
2909 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2910 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2911 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2912 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2913 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2914 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2915 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2916 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2917 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2918 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2919 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2920 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2921 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2922 .driver_data = NVME_QUIRK_LIGHTNVM, },
2923 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2924 .driver_data = NVME_QUIRK_LIGHTNVM, },
2925 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2926 .driver_data = NVME_QUIRK_LIGHTNVM, },
2927 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2928 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2929 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2932 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2934 static struct pci_driver nvme_driver = {
2936 .id_table = nvme_id_table,
2937 .probe = nvme_probe,
2938 .remove = nvme_remove,
2939 .shutdown = nvme_shutdown,
2941 .pm = &nvme_dev_pm_ops,
2943 .sriov_configure = pci_sriov_configure_simple,
2944 .err_handler = &nvme_err_handler,
2947 static int __init nvme_init(void)
2949 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
2950 return pci_register_driver(&nvme_driver);
2953 static void __exit nvme_exit(void)
2955 pci_unregister_driver(&nvme_driver);
2956 flush_workqueue(nvme_wq);
2960 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2961 MODULE_LICENSE("GPL");
2962 MODULE_VERSION("1.0");
2963 module_init(nvme_init);
2964 module_exit(nvme_exit);