drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/blk-integrity.h>
  14 #include <linux/dmi.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kstrtox.h>
  19 #include <linux/memremap.h>
  20 #include <linux/mm.h>
  21 #include <linux/module.h>
  22 #include <linux/mutex.h>
  23 #include <linux/once.h>
  24 #include <linux/pci.h>
  25 #include <linux/suspend.h>
  26 #include <linux/t10-pi.h>
  27 #include <linux/types.h>
  28 #include <linux/io-64-nonatomic-lo-hi.h>
  29 #include <linux/io-64-nonatomic-hi-lo.h>
  30 #include <linux/sed-opal.h>
  31 #include <linux/pci-p2pdma.h>
  32
  33 #include "trace.h"
  34 #include "nvme.h"
  35
  36 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  37 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  38
  39 #define SGES_PER_PAGE   (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  40
  41 /*
  42  * These can be higher, but we need to ensure that any command doesn't
  43  * require an sg allocation that needs more than a page of data.
  44  */
  45 #define NVME_MAX_KB_SZ  8192
  46 #define NVME_MAX_SEGS   128
  47 #define NVME_MAX_NR_ALLOCATIONS 5
  48
  49 static int use_threaded_interrupts;
  50 module_param(use_threaded_interrupts, int, 0444);
  51
  52 static bool use_cmb_sqes = true;
  53 module_param(use_cmb_sqes, bool, 0444);
  54 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  55
  56 static unsigned int max_host_mem_size_mb = 128;
  57 module_param(max_host_mem_size_mb, uint, 0444);
  58 MODULE_PARM_DESC(max_host_mem_size_mb,
  59         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  60
  61 static unsigned int sgl_threshold = SZ_32K;
  62 module_param(sgl_threshold, uint, 0644);
  63 MODULE_PARM_DESC(sgl_threshold,
  64                 "Use SGLs when average request segment size is larger or equal to "
  65                 "this size. Use 0 to disable SGLs.");
  66
  67 #define NVME_PCI_MIN_QUEUE_SIZE 2
  68 #define NVME_PCI_MAX_QUEUE_SIZE 4095
  69 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  70 static const struct kernel_param_ops io_queue_depth_ops = {
  71         .set = io_queue_depth_set,
  72         .get = param_get_uint,
  73 };
  74
  75 static unsigned int io_queue_depth = 1024;
  76 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  77 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  78
  79 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  80 {
  81         unsigned int n;
  82         int ret;
  83
  84         ret = kstrtouint(val, 10, &n);
  85         if (ret != 0 || n > num_possible_cpus())
  86                 return -EINVAL;
  87         return param_set_uint(val, kp);
  88 }
  89
  90 static const struct kernel_param_ops io_queue_count_ops = {
  91         .set = io_queue_count_set,
  92         .get = param_get_uint,
  93 };
  94
  95 static unsigned int write_queues;
  96 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  97 MODULE_PARM_DESC(write_queues,
  98         "Number of queues to use for writes. If not set, reads and writes "
  99         "will share a queue set.");
 100
 101 static unsigned int poll_queues;
 102 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
 103 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
 104
 105 static bool noacpi;
 106 module_param(noacpi, bool, 0444);
 107 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 108
 109 struct nvme_dev;
 110 struct nvme_queue;
 111
 112 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 113 static void nvme_delete_io_queues(struct nvme_dev *dev);
 114 static void nvme_update_attrs(struct nvme_dev *dev);
 115
 116 /*
 117  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 118  */
 119 struct nvme_dev {
 120         struct nvme_queue *queues;
 121         struct blk_mq_tag_set tagset;
 122         struct blk_mq_tag_set admin_tagset;
 123         u32 __iomem *dbs;
 124         struct device *dev;
 125         struct dma_pool *prp_page_pool;
 126         struct dma_pool *prp_small_pool;
 127         unsigned online_queues;
 128         unsigned max_qid;
 129         unsigned io_queues[HCTX_MAX_TYPES];
 130         unsigned int num_vecs;
 131         u32 q_depth;
 132         int io_sqes;
 133         u32 db_stride;
 134         void __iomem *bar;
 135         unsigned long bar_mapped_size;
 136         struct mutex shutdown_lock;
 137         bool subsystem;
 138         u64 cmb_size;
 139         bool cmb_use_sqes;
 140         u32 cmbsz;
 141         u32 cmbloc;
 142         struct nvme_ctrl ctrl;
 143         u32 last_ps;
 144         bool hmb;
 145
 146         mempool_t *iod_mempool;
 147
 148         /* shadow doorbell buffer support: */
 149         __le32 *dbbuf_dbs;
 150         dma_addr_t dbbuf_dbs_dma_addr;
 151         __le32 *dbbuf_eis;
 152         dma_addr_t dbbuf_eis_dma_addr;
 153
 154         /* host memory buffer support: */
 155         u64 host_mem_size;
 156         u32 nr_host_mem_descs;
 157         dma_addr_t host_mem_descs_dma;
 158         struct nvme_host_mem_buf_desc *host_mem_descs;
 159         void **host_mem_desc_bufs;
 160         unsigned int nr_allocated_queues;
 161         unsigned int nr_write_queues;
 162         unsigned int nr_poll_queues;
 163 };
 164
 165 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 166 {
 167         return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
 168                         NVME_PCI_MAX_QUEUE_SIZE);
 169 }
 170
 171 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 172 {
 173         return qid * 2 * stride;
 174 }
 175
 176 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 177 {
 178         return (qid * 2 + 1) * stride;
 179 }
 180
 181 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 182 {
 183         return container_of(ctrl, struct nvme_dev, ctrl);
 184 }
 185
 186 /*
 187  * An NVM Express queue.  Each device has at least two (one for admin
 188  * commands and one for I/O commands).
 189  */
 190 struct nvme_queue {
 191         struct nvme_dev *dev;
 192         spinlock_t sq_lock;
 193         void *sq_cmds;
 194          /* only used for poll queues: */
 195         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 196         struct nvme_completion *cqes;
 197         dma_addr_t sq_dma_addr;
 198         dma_addr_t cq_dma_addr;
 199         u32 __iomem *q_db;
 200         u32 q_depth;
 201         u16 cq_vector;
 202         u16 sq_tail;
 203         u16 last_sq_tail;
 204         u16 cq_head;
 205         u16 qid;
 206         u8 cq_phase;
 207         u8 sqes;
 208         unsigned long flags;
 209 #define NVMEQ_ENABLED           0
 210 #define NVMEQ_SQ_CMB            1
 211 #define NVMEQ_DELETE_ERROR      2
 212 #define NVMEQ_POLLED            3
 213         __le32 *dbbuf_sq_db;
 214         __le32 *dbbuf_cq_db;
 215         __le32 *dbbuf_sq_ei;
 216         __le32 *dbbuf_cq_ei;
 217         struct completion delete_done;
 218 };
 219
 220 union nvme_descriptor {
 221         struct nvme_sgl_desc    *sg_list;
 222         __le64                  *prp_list;
 223 };
 224
 225 /*
 226  * The nvme_iod describes the data in an I/O.
 227  *
 228  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 229  * to the actual struct scatterlist.
 230  */
 231 struct nvme_iod {
 232         struct nvme_request req;
 233         struct nvme_command cmd;
 234         bool aborted;
 235         s8 nr_allocations;      /* PRP list pool allocations. 0 means small
 236                                    pool in use */
 237         unsigned int dma_len;   /* length of single DMA segment mapping */
 238         dma_addr_t first_dma;
 239         dma_addr_t meta_dma;
 240         struct sg_table sgt;
 241         union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
 242 };
 243
 244 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 245 {
 246         return dev->nr_allocated_queues * 8 * dev->db_stride;
 247 }
 248
 249 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 250 {
 251         unsigned int mem_size = nvme_dbbuf_size(dev);
 252
 253         if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
 254                 return;
 255
 256         if (dev->dbbuf_dbs) {
 257                 /*
 258                  * Clear the dbbuf memory so the driver doesn't observe stale
 259                  * values from the previous instantiation.
 260                  */
 261                 memset(dev->dbbuf_dbs, 0, mem_size);
 262                 memset(dev->dbbuf_eis, 0, mem_size);
 263                 return;
 264         }
 265
 266         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 267                                             &dev->dbbuf_dbs_dma_addr,
 268                                             GFP_KERNEL);
 269         if (!dev->dbbuf_dbs)
 270                 goto fail;
 271         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 272                                             &dev->dbbuf_eis_dma_addr,
 273                                             GFP_KERNEL);
 274         if (!dev->dbbuf_eis)
 275                 goto fail_free_dbbuf_dbs;
 276         return;
 277
 278 fail_free_dbbuf_dbs:
 279         dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
 280                           dev->dbbuf_dbs_dma_addr);
 281         dev->dbbuf_dbs = NULL;
 282 fail:
 283         dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
 284 }
 285
 286 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 287 {
 288         unsigned int mem_size = nvme_dbbuf_size(dev);
 289
 290         if (dev->dbbuf_dbs) {
 291                 dma_free_coherent(dev->dev, mem_size,
 292                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 293                 dev->dbbuf_dbs = NULL;
 294         }
 295         if (dev->dbbuf_eis) {
 296                 dma_free_coherent(dev->dev, mem_size,
 297                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 298                 dev->dbbuf_eis = NULL;
 299         }
 300 }
 301
 302 static void nvme_dbbuf_init(struct nvme_dev *dev,
 303                             struct nvme_queue *nvmeq, int qid)
 304 {
 305         if (!dev->dbbuf_dbs || !qid)
 306                 return;
 307
 308         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 309         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 310         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 311         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 312 }
 313
 314 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 315 {
 316         if (!nvmeq->qid)
 317                 return;
 318
 319         nvmeq->dbbuf_sq_db = NULL;
 320         nvmeq->dbbuf_cq_db = NULL;
 321         nvmeq->dbbuf_sq_ei = NULL;
 322         nvmeq->dbbuf_cq_ei = NULL;
 323 }
 324
 325 static void nvme_dbbuf_set(struct nvme_dev *dev)
 326 {
 327         struct nvme_command c = { };
 328         unsigned int i;
 329
 330         if (!dev->dbbuf_dbs)
 331                 return;
 332
 333         c.dbbuf.opcode = nvme_admin_dbbuf;
 334         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 335         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 336
 337         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 338                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 339                 /* Free memory and continue on */
 340                 nvme_dbbuf_dma_free(dev);
 341
 342                 for (i = 1; i <= dev->online_queues; i++)
 343                         nvme_dbbuf_free(&dev->queues[i]);
 344         }
 345 }
 346
 347 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 348 {
 349         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 350 }
 351
 352 /* Update dbbuf and return true if an MMIO is required */
 353 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
 354                                               volatile __le32 *dbbuf_ei)
 355 {
 356         if (dbbuf_db) {
 357                 u16 old_value, event_idx;
 358
 359                 /*
 360                  * Ensure that the queue is written before updating
 361                  * the doorbell in memory
 362                  */
 363                 wmb();
 364
 365                 old_value = le32_to_cpu(*dbbuf_db);
 366                 *dbbuf_db = cpu_to_le32(value);
 367
 368                 /*
 369                  * Ensure that the doorbell is updated before reading the event
 370                  * index from memory.  The controller needs to provide similar
 371                  * ordering to ensure the envent index is updated before reading
 372                  * the doorbell.
 373                  */
 374                 mb();
 375
 376                 event_idx = le32_to_cpu(*dbbuf_ei);
 377                 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
 378                         return false;
 379         }
 380
 381         return true;
 382 }
 383
 384 /*
 385  * Will slightly overestimate the number of pages needed.  This is OK
 386  * as it only leads to a small amount of wasted memory for the lifetime of
 387  * the I/O.
 388  */
 389 static int nvme_pci_npages_prp(void)
 390 {
 391         unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
 392         unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
 393         return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
 394 }
 395
 396 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 397                                 unsigned int hctx_idx)
 398 {
 399         struct nvme_dev *dev = to_nvme_dev(data);
 400         struct nvme_queue *nvmeq = &dev->queues[0];
 401
 402         WARN_ON(hctx_idx != 0);
 403         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 404
 405         hctx->driver_data = nvmeq;
 406         return 0;
 407 }
 408
 409 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 410                           unsigned int hctx_idx)
 411 {
 412         struct nvme_dev *dev = to_nvme_dev(data);
 413         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 414
 415         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 416         hctx->driver_data = nvmeq;
 417         return 0;
 418 }
 419
 420 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
 421                 struct request *req, unsigned int hctx_idx,
 422                 unsigned int numa_node)
 423 {
 424         struct nvme_dev *dev = to_nvme_dev(set->driver_data);
 425         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 426
 427         nvme_req(req)->ctrl = &dev->ctrl;
 428         nvme_req(req)->cmd = &iod->cmd;
 429         return 0;
 430 }
 431
 432 static int queue_irq_offset(struct nvme_dev *dev)
 433 {
 434         /* if we have more than 1 vec, admin queue offsets us by 1 */
 435         if (dev->num_vecs > 1)
 436                 return 1;
 437
 438         return 0;
 439 }
 440
 441 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
 442 {
 443         struct nvme_dev *dev = to_nvme_dev(set->driver_data);
 444         int i, qoff, offset;
 445
 446         offset = queue_irq_offset(dev);
 447         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 448                 struct blk_mq_queue_map *map = &set->map[i];
 449
 450                 map->nr_queues = dev->io_queues[i];
 451                 if (!map->nr_queues) {
 452                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 453                         continue;
 454                 }
 455
 456                 /*
 457                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 458                  * affinity), so use the regular blk-mq cpu mapping
 459                  */
 460                 map->queue_offset = qoff;
 461                 if (i != HCTX_TYPE_POLL && offset)
 462                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 463                 else
 464                         blk_mq_map_queues(map);
 465                 qoff += map->nr_queues;
 466                 offset += map->nr_queues;
 467         }
 468 }
 469
 470 /*
 471  * Write sq tail if we are asked to, or if the next command would wrap.
 472  */
 473 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 474 {
 475         if (!write_sq) {
 476                 u16 next_tail = nvmeq->sq_tail + 1;
 477
 478                 if (next_tail == nvmeq->q_depth)
 479                         next_tail = 0;
 480                 if (next_tail != nvmeq->last_sq_tail)
 481                         return;
 482         }
 483
 484         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 485                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 486                 writel(nvmeq->sq_tail, nvmeq->q_db);
 487         nvmeq->last_sq_tail = nvmeq->sq_tail;
 488 }
 489
 490 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
 491                                     struct nvme_command *cmd)
 492 {
 493         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 494                 absolute_pointer(cmd), sizeof(*cmd));
 495         if (++nvmeq->sq_tail == nvmeq->q_depth)
 496                 nvmeq->sq_tail = 0;
 497 }
 498
 499 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 500 {
 501         struct nvme_queue *nvmeq = hctx->driver_data;
 502
 503         spin_lock(&nvmeq->sq_lock);
 504         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 505                 nvme_write_sq_db(nvmeq, true);
 506         spin_unlock(&nvmeq->sq_lock);
 507 }
 508
 509 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
 510                                      int nseg)
 511 {
 512         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 513         unsigned int avg_seg_size;
 514
 515         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 516
 517         if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 518                 return false;
 519         if (!nvmeq->qid)
 520                 return false;
 521         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 522                 return false;
 523         return true;
 524 }
 525
 526 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 527 {
 528         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 529         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 530         dma_addr_t dma_addr = iod->first_dma;
 531         int i;
 532
 533         for (i = 0; i < iod->nr_allocations; i++) {
 534                 __le64 *prp_list = iod->list[i].prp_list;
 535                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 536
 537                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 538                 dma_addr = next_dma_addr;
 539         }
 540 }
 541
 542 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 543 {
 544         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 545
 546         if (iod->dma_len) {
 547                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 548                                rq_dma_dir(req));
 549                 return;
 550         }
 551
 552         WARN_ON_ONCE(!iod->sgt.nents);
 553
 554         dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
 555
 556         if (iod->nr_allocations == 0)
 557                 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
 558                               iod->first_dma);
 559         else if (iod->nr_allocations == 1)
 560                 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
 561                               iod->first_dma);
 562         else
 563                 nvme_free_prps(dev, req);
 564         mempool_free(iod->sgt.sgl, dev->iod_mempool);
 565 }
 566
 567 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 568 {
 569         int i;
 570         struct scatterlist *sg;
 571
 572         for_each_sg(sgl, sg, nents, i) {
 573                 dma_addr_t phys = sg_phys(sg);
 574                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 575                         "dma_address:%pad dma_length:%d\n",
 576                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 577                         sg_dma_len(sg));
 578         }
 579 }
 580
 581 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 582                 struct request *req, struct nvme_rw_command *cmnd)
 583 {
 584         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 585         struct dma_pool *pool;
 586         int length = blk_rq_payload_bytes(req);
 587         struct scatterlist *sg = iod->sgt.sgl;
 588         int dma_len = sg_dma_len(sg);
 589         u64 dma_addr = sg_dma_address(sg);
 590         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 591         __le64 *prp_list;
 592         dma_addr_t prp_dma;
 593         int nprps, i;
 594
 595         length -= (NVME_CTRL_PAGE_SIZE - offset);
 596         if (length <= 0) {
 597                 iod->first_dma = 0;
 598                 goto done;
 599         }
 600
 601         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 602         if (dma_len) {
 603                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 604         } else {
 605                 sg = sg_next(sg);
 606                 dma_addr = sg_dma_address(sg);
 607                 dma_len = sg_dma_len(sg);
 608         }
 609
 610         if (length <= NVME_CTRL_PAGE_SIZE) {
 611                 iod->first_dma = dma_addr;
 612                 goto done;
 613         }
 614
 615         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 616         if (nprps <= (256 / 8)) {
 617                 pool = dev->prp_small_pool;
 618                 iod->nr_allocations = 0;
 619         } else {
 620                 pool = dev->prp_page_pool;
 621                 iod->nr_allocations = 1;
 622         }
 623
 624         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 625         if (!prp_list) {
 626                 iod->nr_allocations = -1;
 627                 return BLK_STS_RESOURCE;
 628         }
 629         iod->list[0].prp_list = prp_list;
 630         iod->first_dma = prp_dma;
 631         i = 0;
 632         for (;;) {
 633                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 634                         __le64 *old_prp_list = prp_list;
 635                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 636                         if (!prp_list)
 637                                 goto free_prps;
 638                         iod->list[iod->nr_allocations++].prp_list = prp_list;
 639                         prp_list[0] = old_prp_list[i - 1];
 640                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 641                         i = 1;
 642                 }
 643                 prp_list[i++] = cpu_to_le64(dma_addr);
 644                 dma_len -= NVME_CTRL_PAGE_SIZE;
 645                 dma_addr += NVME_CTRL_PAGE_SIZE;
 646                 length -= NVME_CTRL_PAGE_SIZE;
 647                 if (length <= 0)
 648                         break;
 649                 if (dma_len > 0)
 650                         continue;
 651                 if (unlikely(dma_len < 0))
 652                         goto bad_sgl;
 653                 sg = sg_next(sg);
 654                 dma_addr = sg_dma_address(sg);
 655                 dma_len = sg_dma_len(sg);
 656         }
 657 done:
 658         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
 659         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 660         return BLK_STS_OK;
 661 free_prps:
 662         nvme_free_prps(dev, req);
 663         return BLK_STS_RESOURCE;
 664 bad_sgl:
 665         WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
 666                         "Invalid SGL for payload:%d nents:%d\n",
 667                         blk_rq_payload_bytes(req), iod->sgt.nents);
 668         return BLK_STS_IOERR;
 669 }
 670
 671 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 672                 struct scatterlist *sg)
 673 {
 674         sge->addr = cpu_to_le64(sg_dma_address(sg));
 675         sge->length = cpu_to_le32(sg_dma_len(sg));
 676         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 677 }
 678
 679 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 680                 dma_addr_t dma_addr, int entries)
 681 {
 682         sge->addr = cpu_to_le64(dma_addr);
 683         sge->length = cpu_to_le32(entries * sizeof(*sge));
 684         sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 685 }
 686
 687 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 688                 struct request *req, struct nvme_rw_command *cmd)
 689 {
 690         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 691         struct dma_pool *pool;
 692         struct nvme_sgl_desc *sg_list;
 693         struct scatterlist *sg = iod->sgt.sgl;
 694         unsigned int entries = iod->sgt.nents;
 695         dma_addr_t sgl_dma;
 696         int i = 0;
 697
 698         /* setting the transfer type as SGL */
 699         cmd->flags = NVME_CMD_SGL_METABUF;
 700
 701         if (entries == 1) {
 702                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 703                 return BLK_STS_OK;
 704         }
 705
 706         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 707                 pool = dev->prp_small_pool;
 708                 iod->nr_allocations = 0;
 709         } else {
 710                 pool = dev->prp_page_pool;
 711                 iod->nr_allocations = 1;
 712         }
 713
 714         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 715         if (!sg_list) {
 716                 iod->nr_allocations = -1;
 717                 return BLK_STS_RESOURCE;
 718         }
 719
 720         iod->list[0].sg_list = sg_list;
 721         iod->first_dma = sgl_dma;
 722
 723         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 724         do {
 725                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 726                 sg = sg_next(sg);
 727         } while (--entries > 0);
 728
 729         return BLK_STS_OK;
 730 }
 731
 732 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 733                 struct request *req, struct nvme_rw_command *cmnd,
 734                 struct bio_vec *bv)
 735 {
 736         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 737         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 738         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 739
 740         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 741         if (dma_mapping_error(dev->dev, iod->first_dma))
 742                 return BLK_STS_RESOURCE;
 743         iod->dma_len = bv->bv_len;
 744
 745         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 746         if (bv->bv_len > first_prp_len)
 747                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 748         else
 749                 cmnd->dptr.prp2 = 0;
 750         return BLK_STS_OK;
 751 }
 752
 753 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 754                 struct request *req, struct nvme_rw_command *cmnd,
 755                 struct bio_vec *bv)
 756 {
 757         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 758
 759         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 760         if (dma_mapping_error(dev->dev, iod->first_dma))
 761                 return BLK_STS_RESOURCE;
 762         iod->dma_len = bv->bv_len;
 763
 764         cmnd->flags = NVME_CMD_SGL_METABUF;
 765         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 766         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 767         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 768         return BLK_STS_OK;
 769 }
 770
 771 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 772                 struct nvme_command *cmnd)
 773 {
 774         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 775         blk_status_t ret = BLK_STS_RESOURCE;
 776         int rc;
 777
 778         if (blk_rq_nr_phys_segments(req) == 1) {
 779                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 780                 struct bio_vec bv = req_bvec(req);
 781
 782                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 783                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 784                                 return nvme_setup_prp_simple(dev, req,
 785                                                              &cmnd->rw, &bv);
 786
 787                         if (nvmeq->qid && sgl_threshold &&
 788                             nvme_ctrl_sgl_supported(&dev->ctrl))
 789                                 return nvme_setup_sgl_simple(dev, req,
 790                                                              &cmnd->rw, &bv);
 791                 }
 792         }
 793
 794         iod->dma_len = 0;
 795         iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 796         if (!iod->sgt.sgl)
 797                 return BLK_STS_RESOURCE;
 798         sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
 799         iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
 800         if (!iod->sgt.orig_nents)
 801                 goto out_free_sg;
 802
 803         rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
 804                              DMA_ATTR_NO_WARN);
 805         if (rc) {
 806                 if (rc == -EREMOTEIO)
 807                         ret = BLK_STS_TARGET;
 808                 goto out_free_sg;
 809         }
 810
 811         if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
 812                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
 813         else
 814                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 815         if (ret != BLK_STS_OK)
 816                 goto out_unmap_sg;
 817         return BLK_STS_OK;
 818
 819 out_unmap_sg:
 820         dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
 821 out_free_sg:
 822         mempool_free(iod->sgt.sgl, dev->iod_mempool);
 823         return ret;
 824 }
 825
 826 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 827                 struct nvme_command *cmnd)
 828 {
 829         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 830
 831         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 832                         rq_dma_dir(req), 0);
 833         if (dma_mapping_error(dev->dev, iod->meta_dma))
 834                 return BLK_STS_IOERR;
 835         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 836         return BLK_STS_OK;
 837 }
 838
 839 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
 840 {
 841         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 842         blk_status_t ret;
 843
 844         iod->aborted = false;
 845         iod->nr_allocations = -1;
 846         iod->sgt.nents = 0;
 847
 848         ret = nvme_setup_cmd(req->q->queuedata, req);
 849         if (ret)
 850                 return ret;
 851
 852         if (blk_rq_nr_phys_segments(req)) {
 853                 ret = nvme_map_data(dev, req, &iod->cmd);
 854                 if (ret)
 855                         goto out_free_cmd;
 856         }
 857
 858         if (blk_integrity_rq(req)) {
 859                 ret = nvme_map_metadata(dev, req, &iod->cmd);
 860                 if (ret)
 861                         goto out_unmap_data;
 862         }
 863
 864         nvme_start_request(req);
 865         return BLK_STS_OK;
 866 out_unmap_data:
 867         nvme_unmap_data(dev, req);
 868 out_free_cmd:
 869         nvme_cleanup_cmd(req);
 870         return ret;
 871 }
 872
 873 /*
 874  * NOTE: ns is NULL when called on the admin queue.
 875  */
 876 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 877                          const struct blk_mq_queue_data *bd)
 878 {
 879         struct nvme_queue *nvmeq = hctx->driver_data;
 880         struct nvme_dev *dev = nvmeq->dev;
 881         struct request *req = bd->rq;
 882         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 883         blk_status_t ret;
 884
 885         /*
 886          * We should not need to do this, but we're still using this to
 887          * ensure we can drain requests on a dying queue.
 888          */
 889         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 890                 return BLK_STS_IOERR;
 891
 892         if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
 893                 return nvme_fail_nonready_command(&dev->ctrl, req);
 894
 895         ret = nvme_prep_rq(dev, req);
 896         if (unlikely(ret))
 897                 return ret;
 898         spin_lock(&nvmeq->sq_lock);
 899         nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 900         nvme_write_sq_db(nvmeq, bd->last);
 901         spin_unlock(&nvmeq->sq_lock);
 902         return BLK_STS_OK;
 903 }
 904
 905 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
 906 {
 907         spin_lock(&nvmeq->sq_lock);
 908         while (!rq_list_empty(*rqlist)) {
 909                 struct request *req = rq_list_pop(rqlist);
 910                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 911
 912                 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 913         }
 914         nvme_write_sq_db(nvmeq, true);
 915         spin_unlock(&nvmeq->sq_lock);
 916 }
 917
 918 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
 919 {
 920         /*
 921          * We should not need to do this, but we're still using this to
 922          * ensure we can drain requests on a dying queue.
 923          */
 924         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 925                 return false;
 926         if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
 927                 return false;
 928
 929         req->mq_hctx->tags->rqs[req->tag] = req;
 930         return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
 931 }
 932
 933 static void nvme_queue_rqs(struct request **rqlist)
 934 {
 935         struct request *req, *next, *prev = NULL;
 936         struct request *requeue_list = NULL;
 937
 938         rq_list_for_each_safe(rqlist, req, next) {
 939                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 940
 941                 if (!nvme_prep_rq_batch(nvmeq, req)) {
 942                         /* detach 'req' and add to remainder list */
 943                         rq_list_move(rqlist, &requeue_list, req, prev);
 944
 945                         req = prev;
 946                         if (!req)
 947                                 continue;
 948                 }
 949
 950                 if (!next || req->mq_hctx != next->mq_hctx) {
 951                         /* detach rest of list, and submit */
 952                         req->rq_next = NULL;
 953                         nvme_submit_cmds(nvmeq, rqlist);
 954                         *rqlist = next;
 955                         prev = NULL;
 956                 } else
 957                         prev = req;
 958         }
 959
 960         *rqlist = requeue_list;
 961 }
 962
 963 static __always_inline void nvme_pci_unmap_rq(struct request *req)
 964 {
 965         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 966         struct nvme_dev *dev = nvmeq->dev;
 967
 968         if (blk_integrity_rq(req)) {
 969                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 970
 971                 dma_unmap_page(dev->dev, iod->meta_dma,
 972                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
 973         }
 974
 975         if (blk_rq_nr_phys_segments(req))
 976                 nvme_unmap_data(dev, req);
 977 }
 978
 979 static void nvme_pci_complete_rq(struct request *req)
 980 {
 981         nvme_pci_unmap_rq(req);
 982         nvme_complete_rq(req);
 983 }
 984
 985 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
 986 {
 987         nvme_complete_batch(iob, nvme_pci_unmap_rq);
 988 }
 989
 990 /* We read the CQE phase first to check if the rest of the entry is valid */
 991 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 992 {
 993         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 994
 995         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 996 }
 997
 998 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 999 {
1000         u16 head = nvmeq->cq_head;
1001
1002         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1003                                               nvmeq->dbbuf_cq_ei))
1004                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1005 }
1006
1007 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1008 {
1009         if (!nvmeq->qid)
1010                 return nvmeq->dev->admin_tagset.tags[0];
1011         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1012 }
1013
1014 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1015                                    struct io_comp_batch *iob, u16 idx)
1016 {
1017         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1018         __u16 command_id = READ_ONCE(cqe->command_id);
1019         struct request *req;
1020
1021         /*
1022          * AEN requests are special as they don't time out and can
1023          * survive any kind of queue freeze and often don't respond to
1024          * aborts.  We don't even bother to allocate a struct request
1025          * for them but rather special case them here.
1026          */
1027         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1028                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1029                                 cqe->status, &cqe->result);
1030                 return;
1031         }
1032
1033         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1034         if (unlikely(!req)) {
1035                 dev_warn(nvmeq->dev->ctrl.device,
1036                         "invalid id %d completed on queue %d\n",
1037                         command_id, le16_to_cpu(cqe->sq_id));
1038                 return;
1039         }
1040
1041         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1042         if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1043             !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1044                                         nvme_pci_complete_batch))
1045                 nvme_pci_complete_rq(req);
1046 }
1047
1048 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1049 {
1050         u32 tmp = nvmeq->cq_head + 1;
1051
1052         if (tmp == nvmeq->q_depth) {
1053                 nvmeq->cq_head = 0;
1054                 nvmeq->cq_phase ^= 1;
1055         } else {
1056                 nvmeq->cq_head = tmp;
1057         }
1058 }
1059
1060 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1061                                struct io_comp_batch *iob)
1062 {
1063         int found = 0;
1064
1065         while (nvme_cqe_pending(nvmeq)) {
1066                 found++;
1067                 /*
1068                  * load-load control dependency between phase and the rest of
1069                  * the cqe requires a full read memory barrier
1070                  */
1071                 dma_rmb();
1072                 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1073                 nvme_update_cq_head(nvmeq);
1074         }
1075
1076         if (found)
1077                 nvme_ring_cq_doorbell(nvmeq);
1078         return found;
1079 }
1080
1081 static irqreturn_t nvme_irq(int irq, void *data)
1082 {
1083         struct nvme_queue *nvmeq = data;
1084         DEFINE_IO_COMP_BATCH(iob);
1085
1086         if (nvme_poll_cq(nvmeq, &iob)) {
1087                 if (!rq_list_empty(iob.req_list))
1088                         nvme_pci_complete_batch(&iob);
1089                 return IRQ_HANDLED;
1090         }
1091         return IRQ_NONE;
1092 }
1093
1094 static irqreturn_t nvme_irq_check(int irq, void *data)
1095 {
1096         struct nvme_queue *nvmeq = data;
1097
1098         if (nvme_cqe_pending(nvmeq))
1099                 return IRQ_WAKE_THREAD;
1100         return IRQ_NONE;
1101 }
1102
1103 /*
1104  * Poll for completions for any interrupt driven queue
1105  * Can be called from any context.
1106  */
1107 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1108 {
1109         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1110
1111         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1112
1113         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1114         nvme_poll_cq(nvmeq, NULL);
1115         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1116 }
1117
1118 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1119 {
1120         struct nvme_queue *nvmeq = hctx->driver_data;
1121         bool found;
1122
1123         if (!nvme_cqe_pending(nvmeq))
1124                 return 0;
1125
1126         spin_lock(&nvmeq->cq_poll_lock);
1127         found = nvme_poll_cq(nvmeq, iob);
1128         spin_unlock(&nvmeq->cq_poll_lock);
1129
1130         return found;
1131 }
1132
1133 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1134 {
1135         struct nvme_dev *dev = to_nvme_dev(ctrl);
1136         struct nvme_queue *nvmeq = &dev->queues[0];
1137         struct nvme_command c = { };
1138
1139         c.common.opcode = nvme_admin_async_event;
1140         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1141
1142         spin_lock(&nvmeq->sq_lock);
1143         nvme_sq_copy_cmd(nvmeq, &c);
1144         nvme_write_sq_db(nvmeq, true);
1145         spin_unlock(&nvmeq->sq_lock);
1146 }
1147
1148 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1149 {
1150         struct nvme_command c = { };
1151
1152         c.delete_queue.opcode = opcode;
1153         c.delete_queue.qid = cpu_to_le16(id);
1154
1155         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1156 }
1157
1158 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1159                 struct nvme_queue *nvmeq, s16 vector)
1160 {
1161         struct nvme_command c = { };
1162         int flags = NVME_QUEUE_PHYS_CONTIG;
1163
1164         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1165                 flags |= NVME_CQ_IRQ_ENABLED;
1166
1167         /*
1168          * Note: we (ab)use the fact that the prp fields survive if no data
1169          * is attached to the request.
1170          */
1171         c.create_cq.opcode = nvme_admin_create_cq;
1172         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1173         c.create_cq.cqid = cpu_to_le16(qid);
1174         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1175         c.create_cq.cq_flags = cpu_to_le16(flags);
1176         c.create_cq.irq_vector = cpu_to_le16(vector);
1177
1178         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1179 }
1180
1181 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1182                                                 struct nvme_queue *nvmeq)
1183 {
1184         struct nvme_ctrl *ctrl = &dev->ctrl;
1185         struct nvme_command c = { };
1186         int flags = NVME_QUEUE_PHYS_CONTIG;
1187
1188         /*
1189          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1190          * set. Since URGENT priority is zeroes, it makes all queues
1191          * URGENT.
1192          */
1193         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1194                 flags |= NVME_SQ_PRIO_MEDIUM;
1195
1196         /*
1197          * Note: we (ab)use the fact that the prp fields survive if no data
1198          * is attached to the request.
1199          */
1200         c.create_sq.opcode = nvme_admin_create_sq;
1201         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1202         c.create_sq.sqid = cpu_to_le16(qid);
1203         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1204         c.create_sq.sq_flags = cpu_to_le16(flags);
1205         c.create_sq.cqid = cpu_to_le16(qid);
1206
1207         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1208 }
1209
1210 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1211 {
1212         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1213 }
1214
1215 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1216 {
1217         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1218 }
1219
1220 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1221 {
1222         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1223
1224         dev_warn(nvmeq->dev->ctrl.device,
1225                  "Abort status: 0x%x", nvme_req(req)->status);
1226         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1227         blk_mq_free_request(req);
1228         return RQ_END_IO_NONE;
1229 }
1230
1231 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1232 {
1233         /* If true, indicates loss of adapter communication, possibly by a
1234          * NVMe Subsystem reset.
1235          */
1236         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1237
1238         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1239         switch (dev->ctrl.state) {
1240         case NVME_CTRL_RESETTING:
1241         case NVME_CTRL_CONNECTING:
1242                 return false;
1243         default:
1244                 break;
1245         }
1246
1247         /* We shouldn't reset unless the controller is on fatal error state
1248          * _or_ if we lost the communication with it.
1249          */
1250         if (!(csts & NVME_CSTS_CFS) && !nssro)
1251                 return false;
1252
1253         return true;
1254 }
1255
1256 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1257 {
1258         /* Read a config register to help see what died. */
1259         u16 pci_status;
1260         int result;
1261
1262         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1263                                       &pci_status);
1264         if (result == PCIBIOS_SUCCESSFUL)
1265                 dev_warn(dev->ctrl.device,
1266                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1267                          csts, pci_status);
1268         else
1269                 dev_warn(dev->ctrl.device,
1270                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1271                          csts, result);
1272
1273         if (csts != ~0)
1274                 return;
1275
1276         dev_warn(dev->ctrl.device,
1277                  "Does your device have a faulty power saving mode enabled?\n");
1278         dev_warn(dev->ctrl.device,
1279                  "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
1280 }
1281
1282 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1283 {
1284         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1285         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1286         struct nvme_dev *dev = nvmeq->dev;
1287         struct request *abort_req;
1288         struct nvme_command cmd = { };
1289         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1290
1291         /* If PCI error recovery process is happening, we cannot reset or
1292          * the recovery mechanism will surely fail.
1293          */
1294         mb();
1295         if (pci_channel_offline(to_pci_dev(dev->dev)))
1296                 return BLK_EH_RESET_TIMER;
1297
1298         /*
1299          * Reset immediately if the controller is failed
1300          */
1301         if (nvme_should_reset(dev, csts)) {
1302                 nvme_warn_reset(dev, csts);
1303                 nvme_dev_disable(dev, false);
1304                 nvme_reset_ctrl(&dev->ctrl);
1305                 return BLK_EH_DONE;
1306         }
1307
1308         /*
1309          * Did we miss an interrupt?
1310          */
1311         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1312                 nvme_poll(req->mq_hctx, NULL);
1313         else
1314                 nvme_poll_irqdisable(nvmeq);
1315
1316         if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1317                 dev_warn(dev->ctrl.device,
1318                          "I/O %d QID %d timeout, completion polled\n",
1319                          req->tag, nvmeq->qid);
1320                 return BLK_EH_DONE;
1321         }
1322
1323         /*
1324          * Shutdown immediately if controller times out while starting. The
1325          * reset work will see the pci device disabled when it gets the forced
1326          * cancellation error. All outstanding requests are completed on
1327          * shutdown, so we return BLK_EH_DONE.
1328          */
1329         switch (dev->ctrl.state) {
1330         case NVME_CTRL_CONNECTING:
1331                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1332                 fallthrough;
1333         case NVME_CTRL_DELETING:
1334                 dev_warn_ratelimited(dev->ctrl.device,
1335                          "I/O %d QID %d timeout, disable controller\n",
1336                          req->tag, nvmeq->qid);
1337                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1338                 nvme_dev_disable(dev, true);
1339                 return BLK_EH_DONE;
1340         case NVME_CTRL_RESETTING:
1341                 return BLK_EH_RESET_TIMER;
1342         default:
1343                 break;
1344         }
1345
1346         /*
1347          * Shutdown the controller immediately and schedule a reset if the
1348          * command was already aborted once before and still hasn't been
1349          * returned to the driver, or if this is the admin queue.
1350          */
1351         if (!nvmeq->qid || iod->aborted) {
1352                 dev_warn(dev->ctrl.device,
1353                          "I/O %d QID %d timeout, reset controller\n",
1354                          req->tag, nvmeq->qid);
1355                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1356                 nvme_dev_disable(dev, false);
1357                 nvme_reset_ctrl(&dev->ctrl);
1358
1359                 return BLK_EH_DONE;
1360         }
1361
1362         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1363                 atomic_inc(&dev->ctrl.abort_limit);
1364                 return BLK_EH_RESET_TIMER;
1365         }
1366         iod->aborted = true;
1367
1368         cmd.abort.opcode = nvme_admin_abort_cmd;
1369         cmd.abort.cid = nvme_cid(req);
1370         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1371
1372         dev_warn(nvmeq->dev->ctrl.device,
1373                 "I/O %d (%s) QID %d timeout, aborting\n",
1374                  req->tag,
1375                  nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1376                  nvmeq->qid);
1377
1378         abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1379                                          BLK_MQ_REQ_NOWAIT);
1380         if (IS_ERR(abort_req)) {
1381                 atomic_inc(&dev->ctrl.abort_limit);
1382                 return BLK_EH_RESET_TIMER;
1383         }
1384         nvme_init_request(abort_req, &cmd);
1385
1386         abort_req->end_io = abort_endio;
1387         abort_req->end_io_data = NULL;
1388         blk_execute_rq_nowait(abort_req, false);
1389
1390         /*
1391          * The aborted req will be completed on receiving the abort req.
1392          * We enable the timer again. If hit twice, it'll cause a device reset,
1393          * as the device then is in a faulty state.
1394          */
1395         return BLK_EH_RESET_TIMER;
1396 }
1397
1398 static void nvme_free_queue(struct nvme_queue *nvmeq)
1399 {
1400         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1401                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1402         if (!nvmeq->sq_cmds)
1403                 return;
1404
1405         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1406                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1407                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1408         } else {
1409                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1410                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1411         }
1412 }
1413
1414 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1415 {
1416         int i;
1417
1418         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1419                 dev->ctrl.queue_count--;
1420                 nvme_free_queue(&dev->queues[i]);
1421         }
1422 }
1423
1424 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1425 {
1426         struct nvme_queue *nvmeq = &dev->queues[qid];
1427
1428         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1429                 return;
1430
1431         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1432         mb();
1433
1434         nvmeq->dev->online_queues--;
1435         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1436                 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
1437         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1438                 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
1439 }
1440
1441 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1442 {
1443         int i;
1444
1445         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1446                 nvme_suspend_queue(dev, i);
1447 }
1448
1449 /*
1450  * Called only on a device that has been disabled and after all other threads
1451  * that can check this device's completion queues have synced, except
1452  * nvme_poll(). This is the last chance for the driver to see a natural
1453  * completion before nvme_cancel_request() terminates all incomplete requests.
1454  */
1455 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1456 {
1457         int i;
1458
1459         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1460                 spin_lock(&dev->queues[i].cq_poll_lock);
1461                 nvme_poll_cq(&dev->queues[i], NULL);
1462                 spin_unlock(&dev->queues[i].cq_poll_lock);
1463         }
1464 }
1465
1466 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1467                                 int entry_size)
1468 {
1469         int q_depth = dev->q_depth;
1470         unsigned q_size_aligned = roundup(q_depth * entry_size,
1471                                           NVME_CTRL_PAGE_SIZE);
1472
1473         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1474                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1475
1476                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1477                 q_depth = div_u64(mem_per_q, entry_size);
1478
1479                 /*
1480                  * Ensure the reduced q_depth is above some threshold where it
1481                  * would be better to map queues in system memory with the
1482                  * original depth
1483                  */
1484                 if (q_depth < 64)
1485                         return -ENOMEM;
1486         }
1487
1488         return q_depth;
1489 }
1490
1491 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1492                                 int qid)
1493 {
1494         struct pci_dev *pdev = to_pci_dev(dev->dev);
1495
1496         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1497                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1498                 if (nvmeq->sq_cmds) {
1499                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1500                                                         nvmeq->sq_cmds);
1501                         if (nvmeq->sq_dma_addr) {
1502                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1503                                 return 0;
1504                         }
1505
1506                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1507                 }
1508         }
1509
1510         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1511                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1512         if (!nvmeq->sq_cmds)
1513                 return -ENOMEM;
1514         return 0;
1515 }
1516
1517 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1518 {
1519         struct nvme_queue *nvmeq = &dev->queues[qid];
1520
1521         if (dev->ctrl.queue_count > qid)
1522                 return 0;
1523
1524         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1525         nvmeq->q_depth = depth;
1526         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1527                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1528         if (!nvmeq->cqes)
1529                 goto free_nvmeq;
1530
1531         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1532                 goto free_cqdma;
1533
1534         nvmeq->dev = dev;
1535         spin_lock_init(&nvmeq->sq_lock);
1536         spin_lock_init(&nvmeq->cq_poll_lock);
1537         nvmeq->cq_head = 0;
1538         nvmeq->cq_phase = 1;
1539         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1540         nvmeq->qid = qid;
1541         dev->ctrl.queue_count++;
1542
1543         return 0;
1544
1545  free_cqdma:
1546         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1547                           nvmeq->cq_dma_addr);
1548  free_nvmeq:
1549         return -ENOMEM;
1550 }
1551
1552 static int queue_request_irq(struct nvme_queue *nvmeq)
1553 {
1554         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1555         int nr = nvmeq->dev->ctrl.instance;
1556
1557         if (use_threaded_interrupts) {
1558                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1559                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1560         } else {
1561                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1562                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1563         }
1564 }
1565
1566 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1567 {
1568         struct nvme_dev *dev = nvmeq->dev;
1569
1570         nvmeq->sq_tail = 0;
1571         nvmeq->last_sq_tail = 0;
1572         nvmeq->cq_head = 0;
1573         nvmeq->cq_phase = 1;
1574         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1575         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1576         nvme_dbbuf_init(dev, nvmeq, qid);
1577         dev->online_queues++;
1578         wmb(); /* ensure the first interrupt sees the initialization */
1579 }
1580
1581 /*
1582  * Try getting shutdown_lock while setting up IO queues.
1583  */
1584 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1585 {
1586         /*
1587          * Give up if the lock is being held by nvme_dev_disable.
1588          */
1589         if (!mutex_trylock(&dev->shutdown_lock))
1590                 return -ENODEV;
1591
1592         /*
1593          * Controller is in wrong state, fail early.
1594          */
1595         if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1596                 mutex_unlock(&dev->shutdown_lock);
1597                 return -ENODEV;
1598         }
1599
1600         return 0;
1601 }
1602
1603 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1604 {
1605         struct nvme_dev *dev = nvmeq->dev;
1606         int result;
1607         u16 vector = 0;
1608
1609         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1610
1611         /*
1612          * A queue's vector matches the queue identifier unless the controller
1613          * has only one vector available.
1614          */
1615         if (!polled)
1616                 vector = dev->num_vecs == 1 ? 0 : qid;
1617         else
1618                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1619
1620         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1621         if (result)
1622                 return result;
1623
1624         result = adapter_alloc_sq(dev, qid, nvmeq);
1625         if (result < 0)
1626                 return result;
1627         if (result)
1628                 goto release_cq;
1629
1630         nvmeq->cq_vector = vector;
1631
1632         result = nvme_setup_io_queues_trylock(dev);
1633         if (result)
1634                 return result;
1635         nvme_init_queue(nvmeq, qid);
1636         if (!polled) {
1637                 result = queue_request_irq(nvmeq);
1638                 if (result < 0)
1639                         goto release_sq;
1640         }
1641
1642         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1643         mutex_unlock(&dev->shutdown_lock);
1644         return result;
1645
1646 release_sq:
1647         dev->online_queues--;
1648         mutex_unlock(&dev->shutdown_lock);
1649         adapter_delete_sq(dev, qid);
1650 release_cq:
1651         adapter_delete_cq(dev, qid);
1652         return result;
1653 }
1654
1655 static const struct blk_mq_ops nvme_mq_admin_ops = {
1656         .queue_rq       = nvme_queue_rq,
1657         .complete       = nvme_pci_complete_rq,
1658         .init_hctx      = nvme_admin_init_hctx,
1659         .init_request   = nvme_pci_init_request,
1660         .timeout        = nvme_timeout,
1661 };
1662
1663 static const struct blk_mq_ops nvme_mq_ops = {
1664         .queue_rq       = nvme_queue_rq,
1665         .queue_rqs      = nvme_queue_rqs,
1666         .complete       = nvme_pci_complete_rq,
1667         .commit_rqs     = nvme_commit_rqs,
1668         .init_hctx      = nvme_init_hctx,
1669         .init_request   = nvme_pci_init_request,
1670         .map_queues     = nvme_pci_map_queues,
1671         .timeout        = nvme_timeout,
1672         .poll           = nvme_poll,
1673 };
1674
1675 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1676 {
1677         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1678                 /*
1679                  * If the controller was reset during removal, it's possible
1680                  * user requests may be waiting on a stopped queue. Start the
1681                  * queue to flush these to completion.
1682                  */
1683                 nvme_unquiesce_admin_queue(&dev->ctrl);
1684                 nvme_remove_admin_tag_set(&dev->ctrl);
1685         }
1686 }
1687
1688 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1689 {
1690         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1691 }
1692
1693 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1694 {
1695         struct pci_dev *pdev = to_pci_dev(dev->dev);
1696
1697         if (size <= dev->bar_mapped_size)
1698                 return 0;
1699         if (size > pci_resource_len(pdev, 0))
1700                 return -ENOMEM;
1701         if (dev->bar)
1702                 iounmap(dev->bar);
1703         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1704         if (!dev->bar) {
1705                 dev->bar_mapped_size = 0;
1706                 return -ENOMEM;
1707         }
1708         dev->bar_mapped_size = size;
1709         dev->dbs = dev->bar + NVME_REG_DBS;
1710
1711         return 0;
1712 }
1713
1714 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1715 {
1716         int result;
1717         u32 aqa;
1718         struct nvme_queue *nvmeq;
1719
1720         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1721         if (result < 0)
1722                 return result;
1723
1724         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1725                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1726
1727         if (dev->subsystem &&
1728             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1729                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1730
1731         /*
1732          * If the device has been passed off to us in an enabled state, just
1733          * clear the enabled bit.  The spec says we should set the 'shutdown
1734          * notification bits', but doing so may cause the device to complete
1735          * commands to the admin queue ... and we don't know what memory that
1736          * might be pointing at!
1737          */
1738         result = nvme_disable_ctrl(&dev->ctrl, false);
1739         if (result < 0)
1740                 return result;
1741
1742         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1743         if (result)
1744                 return result;
1745
1746         dev->ctrl.numa_node = dev_to_node(dev->dev);
1747
1748         nvmeq = &dev->queues[0];
1749         aqa = nvmeq->q_depth - 1;
1750         aqa |= aqa << 16;
1751
1752         writel(aqa, dev->bar + NVME_REG_AQA);
1753         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1754         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1755
1756         result = nvme_enable_ctrl(&dev->ctrl);
1757         if (result)
1758                 return result;
1759
1760         nvmeq->cq_vector = 0;
1761         nvme_init_queue(nvmeq, 0);
1762         result = queue_request_irq(nvmeq);
1763         if (result) {
1764                 dev->online_queues--;
1765                 return result;
1766         }
1767
1768         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1769         return result;
1770 }
1771
1772 static int nvme_create_io_queues(struct nvme_dev *dev)
1773 {
1774         unsigned i, max, rw_queues;
1775         int ret = 0;
1776
1777         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1778                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1779                         ret = -ENOMEM;
1780                         break;
1781                 }
1782         }
1783
1784         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1785         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1786                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1787                                 dev->io_queues[HCTX_TYPE_READ];
1788         } else {
1789                 rw_queues = max;
1790         }
1791
1792         for (i = dev->online_queues; i <= max; i++) {
1793                 bool polled = i > rw_queues;
1794
1795                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1796                 if (ret)
1797                         break;
1798         }
1799
1800         /*
1801          * Ignore failing Create SQ/CQ commands, we can continue with less
1802          * than the desired amount of queues, and even a controller without
1803          * I/O queues can still be used to issue admin commands.  This might
1804          * be useful to upgrade a buggy firmware for example.
1805          */
1806         return ret >= 0 ? 0 : ret;
1807 }
1808
1809 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1810 {
1811         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1812
1813         return 1ULL << (12 + 4 * szu);
1814 }
1815
1816 static u32 nvme_cmb_size(struct nvme_dev *dev)
1817 {
1818         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1819 }
1820
1821 static void nvme_map_cmb(struct nvme_dev *dev)
1822 {
1823         u64 size, offset;
1824         resource_size_t bar_size;
1825         struct pci_dev *pdev = to_pci_dev(dev->dev);
1826         int bar;
1827
1828         if (dev->cmb_size)
1829                 return;
1830
1831         if (NVME_CAP_CMBS(dev->ctrl.cap))
1832                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1833
1834         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1835         if (!dev->cmbsz)
1836                 return;
1837         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1838
1839         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1840         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1841         bar = NVME_CMB_BIR(dev->cmbloc);
1842         bar_size = pci_resource_len(pdev, bar);
1843
1844         if (offset > bar_size)
1845                 return;
1846
1847         /*
1848          * Tell the controller about the host side address mapping the CMB,
1849          * and enable CMB decoding for the NVMe 1.4+ scheme:
1850          */
1851         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1852                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1853                              (pci_bus_address(pdev, bar) + offset),
1854                              dev->bar + NVME_REG_CMBMSC);
1855         }
1856
1857         /*
1858          * Controllers may support a CMB size larger than their BAR,
1859          * for example, due to being behind a bridge. Reduce the CMB to
1860          * the reported size of the BAR
1861          */
1862         if (size > bar_size - offset)
1863                 size = bar_size - offset;
1864
1865         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1866                 dev_warn(dev->ctrl.device,
1867                          "failed to register the CMB\n");
1868                 return;
1869         }
1870
1871         dev->cmb_size = size;
1872         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1873
1874         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1875                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1876                 pci_p2pmem_publish(pdev, true);
1877
1878         nvme_update_attrs(dev);
1879 }
1880
1881 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1882 {
1883         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1884         u64 dma_addr = dev->host_mem_descs_dma;
1885         struct nvme_command c = { };
1886         int ret;
1887
1888         c.features.opcode       = nvme_admin_set_features;
1889         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1890         c.features.dword11      = cpu_to_le32(bits);
1891         c.features.dword12      = cpu_to_le32(host_mem_size);
1892         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1893         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1894         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1895
1896         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1897         if (ret) {
1898                 dev_warn(dev->ctrl.device,
1899                          "failed to set host mem (err %d, flags %#x).\n",
1900                          ret, bits);
1901         } else
1902                 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1903
1904         return ret;
1905 }
1906
1907 static void nvme_free_host_mem(struct nvme_dev *dev)
1908 {
1909         int i;
1910
1911         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1912                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1913                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1914
1915                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1916                                le64_to_cpu(desc->addr),
1917                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1918         }
1919
1920         kfree(dev->host_mem_desc_bufs);
1921         dev->host_mem_desc_bufs = NULL;
1922         dma_free_coherent(dev->dev,
1923                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1924                         dev->host_mem_descs, dev->host_mem_descs_dma);
1925         dev->host_mem_descs = NULL;
1926         dev->nr_host_mem_descs = 0;
1927 }
1928
1929 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1930                 u32 chunk_size)
1931 {
1932         struct nvme_host_mem_buf_desc *descs;
1933         u32 max_entries, len;
1934         dma_addr_t descs_dma;
1935         int i = 0;
1936         void **bufs;
1937         u64 size, tmp;
1938
1939         tmp = (preferred + chunk_size - 1);
1940         do_div(tmp, chunk_size);
1941         max_entries = tmp;
1942
1943         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1944                 max_entries = dev->ctrl.hmmaxd;
1945
1946         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1947                                    &descs_dma, GFP_KERNEL);
1948         if (!descs)
1949                 goto out;
1950
1951         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1952         if (!bufs)
1953                 goto out_free_descs;
1954
1955         for (size = 0; size < preferred && i < max_entries; size += len) {
1956                 dma_addr_t dma_addr;
1957
1958                 len = min_t(u64, chunk_size, preferred - size);
1959                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1960                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1961                 if (!bufs[i])
1962                         break;
1963
1964                 descs[i].addr = cpu_to_le64(dma_addr);
1965                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1966                 i++;
1967         }
1968
1969         if (!size)
1970                 goto out_free_bufs;
1971
1972         dev->nr_host_mem_descs = i;
1973         dev->host_mem_size = size;
1974         dev->host_mem_descs = descs;
1975         dev->host_mem_descs_dma = descs_dma;
1976         dev->host_mem_desc_bufs = bufs;
1977         return 0;
1978
1979 out_free_bufs:
1980         while (--i >= 0) {
1981                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1982
1983                 dma_free_attrs(dev->dev, size, bufs[i],
1984                                le64_to_cpu(descs[i].addr),
1985                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1986         }
1987
1988         kfree(bufs);
1989 out_free_descs:
1990         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1991                         descs_dma);
1992 out:
1993         dev->host_mem_descs = NULL;
1994         return -ENOMEM;
1995 }
1996
1997 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1998 {
1999         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2000         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2001         u64 chunk_size;
2002
2003         /* start big and work our way down */
2004         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2005                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2006                         if (!min || dev->host_mem_size >= min)
2007                                 return 0;
2008                         nvme_free_host_mem(dev);
2009                 }
2010         }
2011
2012         return -ENOMEM;
2013 }
2014
2015 static int nvme_setup_host_mem(struct nvme_dev *dev)
2016 {
2017         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2018         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2019         u64 min = (u64)dev->ctrl.hmmin * 4096;
2020         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2021         int ret;
2022
2023         if (!dev->ctrl.hmpre)
2024                 return 0;
2025
2026         preferred = min(preferred, max);
2027         if (min > max) {
2028                 dev_warn(dev->ctrl.device,
2029                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2030                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2031                 nvme_free_host_mem(dev);
2032                 return 0;
2033         }
2034
2035         /*
2036          * If we already have a buffer allocated check if we can reuse it.
2037          */
2038         if (dev->host_mem_descs) {
2039                 if (dev->host_mem_size >= min)
2040                         enable_bits |= NVME_HOST_MEM_RETURN;
2041                 else
2042                         nvme_free_host_mem(dev);
2043         }
2044
2045         if (!dev->host_mem_descs) {
2046                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2047                         dev_warn(dev->ctrl.device,
2048                                 "failed to allocate host memory buffer.\n");
2049                         return 0; /* controller must work without HMB */
2050                 }
2051
2052                 dev_info(dev->ctrl.device,
2053                         "allocated %lld MiB host memory buffer.\n",
2054                         dev->host_mem_size >> ilog2(SZ_1M));
2055         }
2056
2057         ret = nvme_set_host_mem(dev, enable_bits);
2058         if (ret)
2059                 nvme_free_host_mem(dev);
2060         return ret;
2061 }
2062
2063 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2064                 char *buf)
2065 {
2066         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2067
2068         return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2069                        ndev->cmbloc, ndev->cmbsz);
2070 }
2071 static DEVICE_ATTR_RO(cmb);
2072
2073 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2074                 char *buf)
2075 {
2076         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2077
2078         return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2079 }
2080 static DEVICE_ATTR_RO(cmbloc);
2081
2082 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2083                 char *buf)
2084 {
2085         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2086
2087         return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2088 }
2089 static DEVICE_ATTR_RO(cmbsz);
2090
2091 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2092                         char *buf)
2093 {
2094         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2095
2096         return sysfs_emit(buf, "%d\n", ndev->hmb);
2097 }
2098
2099 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2100                          const char *buf, size_t count)
2101 {
2102         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2103         bool new;
2104         int ret;
2105
2106         if (kstrtobool(buf, &new) < 0)
2107                 return -EINVAL;
2108
2109         if (new == ndev->hmb)
2110                 return count;
2111
2112         if (new) {
2113                 ret = nvme_setup_host_mem(ndev);
2114         } else {
2115                 ret = nvme_set_host_mem(ndev, 0);
2116                 if (!ret)
2117                         nvme_free_host_mem(ndev);
2118         }
2119
2120         if (ret < 0)
2121                 return ret;
2122
2123         return count;
2124 }
2125 static DEVICE_ATTR_RW(hmb);
2126
2127 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2128                 struct attribute *a, int n)
2129 {
2130         struct nvme_ctrl *ctrl =
2131                 dev_get_drvdata(container_of(kobj, struct device, kobj));
2132         struct nvme_dev *dev = to_nvme_dev(ctrl);
2133
2134         if (a == &dev_attr_cmb.attr ||
2135             a == &dev_attr_cmbloc.attr ||
2136             a == &dev_attr_cmbsz.attr) {
2137                 if (!dev->cmbsz)
2138                         return 0;
2139         }
2140         if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2141                 return 0;
2142
2143         return a->mode;
2144 }
2145
2146 static struct attribute *nvme_pci_attrs[] = {
2147         &dev_attr_cmb.attr,
2148         &dev_attr_cmbloc.attr,
2149         &dev_attr_cmbsz.attr,
2150         &dev_attr_hmb.attr,
2151         NULL,
2152 };
2153
2154 static const struct attribute_group nvme_pci_dev_attrs_group = {
2155         .attrs          = nvme_pci_attrs,
2156         .is_visible     = nvme_pci_attrs_are_visible,
2157 };
2158
2159 static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2160         &nvme_dev_attrs_group,
2161         &nvme_pci_dev_attrs_group,
2162         NULL,
2163 };
2164
2165 static void nvme_update_attrs(struct nvme_dev *dev)
2166 {
2167         sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2168 }
2169
2170 /*
2171  * nirqs is the number of interrupts available for write and read
2172  * queues. The core already reserved an interrupt for the admin queue.
2173  */
2174 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2175 {
2176         struct nvme_dev *dev = affd->priv;
2177         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2178
2179         /*
2180          * If there is no interrupt available for queues, ensure that
2181          * the default queue is set to 1. The affinity set size is
2182          * also set to one, but the irq core ignores it for this case.
2183          *
2184          * If only one interrupt is available or 'write_queue' == 0, combine
2185          * write and read queues.
2186          *
2187          * If 'write_queues' > 0, ensure it leaves room for at least one read
2188          * queue.
2189          */
2190         if (!nrirqs) {
2191                 nrirqs = 1;
2192                 nr_read_queues = 0;
2193         } else if (nrirqs == 1 || !nr_write_queues) {
2194                 nr_read_queues = 0;
2195         } else if (nr_write_queues >= nrirqs) {
2196                 nr_read_queues = 1;
2197         } else {
2198                 nr_read_queues = nrirqs - nr_write_queues;
2199         }
2200
2201         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2202         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2203         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2204         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2205         affd->nr_sets = nr_read_queues ? 2 : 1;
2206 }
2207
2208 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2209 {
2210         struct pci_dev *pdev = to_pci_dev(dev->dev);
2211         struct irq_affinity affd = {
2212                 .pre_vectors    = 1,
2213                 .calc_sets      = nvme_calc_irq_sets,
2214                 .priv           = dev,
2215         };
2216         unsigned int irq_queues, poll_queues;
2217
2218         /*
2219          * Poll queues don't need interrupts, but we need at least one I/O queue
2220          * left over for non-polled I/O.
2221          */
2222         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2223         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2224
2225         /*
2226          * Initialize for the single interrupt case, will be updated in
2227          * nvme_calc_irq_sets().
2228          */
2229         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2230         dev->io_queues[HCTX_TYPE_READ] = 0;
2231
2232         /*
2233          * We need interrupts for the admin queue and each non-polled I/O queue,
2234          * but some Apple controllers require all queues to use the first
2235          * vector.
2236          */
2237         irq_queues = 1;
2238         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2239                 irq_queues += (nr_io_queues - poll_queues);
2240         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2241                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2242 }
2243
2244 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2245 {
2246         /*
2247          * If tags are shared with admin queue (Apple bug), then
2248          * make sure we only use one IO queue.
2249          */
2250         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2251                 return 1;
2252         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2253 }
2254
2255 static int nvme_setup_io_queues(struct nvme_dev *dev)
2256 {
2257         struct nvme_queue *adminq = &dev->queues[0];
2258         struct pci_dev *pdev = to_pci_dev(dev->dev);
2259         unsigned int nr_io_queues;
2260         unsigned long size;
2261         int result;
2262
2263         /*
2264          * Sample the module parameters once at reset time so that we have
2265          * stable values to work with.
2266          */
2267         dev->nr_write_queues = write_queues;
2268         dev->nr_poll_queues = poll_queues;
2269
2270         nr_io_queues = dev->nr_allocated_queues - 1;
2271         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2272         if (result < 0)
2273                 return result;
2274
2275         if (nr_io_queues == 0)
2276                 return 0;
2277
2278         /*
2279          * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2280          * from set to unset. If there is a window to it is truely freed,
2281          * pci_free_irq_vectors() jumping into this window will crash.
2282          * And take lock to avoid racing with pci_free_irq_vectors() in
2283          * nvme_dev_disable() path.
2284          */
2285         result = nvme_setup_io_queues_trylock(dev);
2286         if (result)
2287                 return result;
2288         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2289                 pci_free_irq(pdev, 0, adminq);
2290
2291         if (dev->cmb_use_sqes) {
2292                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2293                                 sizeof(struct nvme_command));
2294                 if (result > 0) {
2295                         dev->q_depth = result;
2296                         dev->ctrl.sqsize = result - 1;
2297                 } else {
2298                         dev->cmb_use_sqes = false;
2299                 }
2300         }
2301
2302         do {
2303                 size = db_bar_size(dev, nr_io_queues);
2304                 result = nvme_remap_bar(dev, size);
2305                 if (!result)
2306                         break;
2307                 if (!--nr_io_queues) {
2308                         result = -ENOMEM;
2309                         goto out_unlock;
2310                 }
2311         } while (1);
2312         adminq->q_db = dev->dbs;
2313
2314  retry:
2315         /* Deregister the admin queue's interrupt */
2316         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2317                 pci_free_irq(pdev, 0, adminq);
2318
2319         /*
2320          * If we enable msix early due to not intx, disable it again before
2321          * setting up the full range we need.
2322          */
2323         pci_free_irq_vectors(pdev);
2324
2325         result = nvme_setup_irqs(dev, nr_io_queues);
2326         if (result <= 0) {
2327                 result = -EIO;
2328                 goto out_unlock;
2329         }
2330
2331         dev->num_vecs = result;
2332         result = max(result - 1, 1);
2333         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2334
2335         /*
2336          * Should investigate if there's a performance win from allocating
2337          * more queues than interrupt vectors; it might allow the submission
2338          * path to scale better, even if the receive path is limited by the
2339          * number of interrupts.
2340          */
2341         result = queue_request_irq(adminq);
2342         if (result)
2343                 goto out_unlock;
2344         set_bit(NVMEQ_ENABLED, &adminq->flags);
2345         mutex_unlock(&dev->shutdown_lock);
2346
2347         result = nvme_create_io_queues(dev);
2348         if (result || dev->online_queues < 2)
2349                 return result;
2350
2351         if (dev->online_queues - 1 < dev->max_qid) {
2352                 nr_io_queues = dev->online_queues - 1;
2353                 nvme_delete_io_queues(dev);
2354                 result = nvme_setup_io_queues_trylock(dev);
2355                 if (result)
2356                         return result;
2357                 nvme_suspend_io_queues(dev);
2358                 goto retry;
2359         }
2360         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2361                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2362                                         dev->io_queues[HCTX_TYPE_READ],
2363                                         dev->io_queues[HCTX_TYPE_POLL]);
2364         return 0;
2365 out_unlock:
2366         mutex_unlock(&dev->shutdown_lock);
2367         return result;
2368 }
2369
2370 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2371                                              blk_status_t error)
2372 {
2373         struct nvme_queue *nvmeq = req->end_io_data;
2374
2375         blk_mq_free_request(req);
2376         complete(&nvmeq->delete_done);
2377         return RQ_END_IO_NONE;
2378 }
2379
2380 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2381                                           blk_status_t error)
2382 {
2383         struct nvme_queue *nvmeq = req->end_io_data;
2384
2385         if (error)
2386                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2387
2388         return nvme_del_queue_end(req, error);
2389 }
2390
2391 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2392 {
2393         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2394         struct request *req;
2395         struct nvme_command cmd = { };
2396
2397         cmd.delete_queue.opcode = opcode;
2398         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2399
2400         req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2401         if (IS_ERR(req))
2402                 return PTR_ERR(req);
2403         nvme_init_request(req, &cmd);
2404
2405         if (opcode == nvme_admin_delete_cq)
2406                 req->end_io = nvme_del_cq_end;
2407         else
2408                 req->end_io = nvme_del_queue_end;
2409         req->end_io_data = nvmeq;
2410
2411         init_completion(&nvmeq->delete_done);
2412         blk_execute_rq_nowait(req, false);
2413         return 0;
2414 }
2415
2416 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2417 {
2418         int nr_queues = dev->online_queues - 1, sent = 0;
2419         unsigned long timeout;
2420
2421  retry:
2422         timeout = NVME_ADMIN_TIMEOUT;
2423         while (nr_queues > 0) {
2424                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2425                         break;
2426                 nr_queues--;
2427                 sent++;
2428         }
2429         while (sent) {
2430                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2431
2432                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2433                                 timeout);
2434                 if (timeout == 0)
2435                         return false;
2436
2437                 sent--;
2438                 if (nr_queues)
2439                         goto retry;
2440         }
2441         return true;
2442 }
2443
2444 static void nvme_delete_io_queues(struct nvme_dev *dev)
2445 {
2446         if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2447                 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2448 }
2449
2450 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2451 {
2452         if (dev->io_queues[HCTX_TYPE_POLL])
2453                 return 3;
2454         if (dev->io_queues[HCTX_TYPE_READ])
2455                 return 2;
2456         return 1;
2457 }
2458
2459 static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2460 {
2461         blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2462         /* free previously allocated queues that are no longer usable */
2463         nvme_free_queues(dev, dev->online_queues);
2464 }
2465
2466 static int nvme_pci_enable(struct nvme_dev *dev)
2467 {
2468         int result = -ENOMEM;
2469         struct pci_dev *pdev = to_pci_dev(dev->dev);
2470
2471         if (pci_enable_device_mem(pdev))
2472                 return result;
2473
2474         pci_set_master(pdev);
2475
2476         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2477                 result = -ENODEV;
2478                 goto disable;
2479         }
2480
2481         /*
2482          * Some devices and/or platforms don't advertise or work with INTx
2483          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2484          * adjust this later.
2485          */
2486         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2487         if (result < 0)
2488                 goto disable;
2489
2490         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2491
2492         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2493                                 io_queue_depth);
2494         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2495         dev->dbs = dev->bar + 4096;
2496
2497         /*
2498          * Some Apple controllers require a non-standard SQE size.
2499          * Interestingly they also seem to ignore the CC:IOSQES register
2500          * so we don't bother updating it here.
2501          */
2502         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2503                 dev->io_sqes = 7;
2504         else
2505                 dev->io_sqes = NVME_NVM_IOSQES;
2506
2507         /*
2508          * Temporary fix for the Apple controller found in the MacBook8,1 and
2509          * some MacBook7,1 to avoid controller resets and data loss.
2510          */
2511         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2512                 dev->q_depth = 2;
2513                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2514                         "set queue depth=%u to work around controller resets\n",
2515                         dev->q_depth);
2516         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2517                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2518                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2519                 dev->q_depth = 64;
2520                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2521                         "set queue depth=%u\n", dev->q_depth);
2522         }
2523
2524         /*
2525          * Controllers with the shared tags quirk need the IO queue to be
2526          * big enough so that we get 32 tags for the admin queue
2527          */
2528         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2529             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2530                 dev->q_depth = NVME_AQ_DEPTH + 2;
2531                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2532                          dev->q_depth);
2533         }
2534         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2535
2536         nvme_map_cmb(dev);
2537
2538         pci_enable_pcie_error_reporting(pdev);
2539         pci_save_state(pdev);
2540
2541         result = nvme_pci_configure_admin_queue(dev);
2542         if (result)
2543                 goto free_irq;
2544         return result;
2545
2546  free_irq:
2547         pci_free_irq_vectors(pdev);
2548  disable:
2549         pci_disable_device(pdev);
2550         return result;
2551 }
2552
2553 static void nvme_dev_unmap(struct nvme_dev *dev)
2554 {
2555         if (dev->bar)
2556                 iounmap(dev->bar);
2557         pci_release_mem_regions(to_pci_dev(dev->dev));
2558 }
2559
2560 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2561 {
2562         struct pci_dev *pdev = to_pci_dev(dev->dev);
2563         u32 csts;
2564
2565         if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2566                 return true;
2567         if (pdev->error_state != pci_channel_io_normal)
2568                 return true;
2569
2570         csts = readl(dev->bar + NVME_REG_CSTS);
2571         return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2572 }
2573
2574 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2575 {
2576         struct pci_dev *pdev = to_pci_dev(dev->dev);
2577         bool dead;
2578
2579         mutex_lock(&dev->shutdown_lock);
2580         dead = nvme_pci_ctrl_is_dead(dev);
2581         if (dev->ctrl.state == NVME_CTRL_LIVE ||
2582             dev->ctrl.state == NVME_CTRL_RESETTING) {
2583                 if (pci_is_enabled(pdev))
2584                         nvme_start_freeze(&dev->ctrl);
2585                 /*
2586                  * Give the controller a chance to complete all entered requests
2587                  * if doing a safe shutdown.
2588                  */
2589                 if (!dead && shutdown)
2590                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2591         }
2592
2593         nvme_quiesce_io_queues(&dev->ctrl);
2594
2595         if (!dead && dev->ctrl.queue_count > 0) {
2596                 nvme_delete_io_queues(dev);
2597                 nvme_disable_ctrl(&dev->ctrl, shutdown);
2598                 nvme_poll_irqdisable(&dev->queues[0]);
2599         }
2600         nvme_suspend_io_queues(dev);
2601         nvme_suspend_queue(dev, 0);
2602         pci_free_irq_vectors(pdev);
2603         if (pci_is_enabled(pdev)) {
2604                 pci_disable_pcie_error_reporting(pdev);
2605                 pci_disable_device(pdev);
2606         }
2607         nvme_reap_pending_cqes(dev);
2608
2609         nvme_cancel_tagset(&dev->ctrl);
2610         nvme_cancel_admin_tagset(&dev->ctrl);
2611
2612         /*
2613          * The driver will not be starting up queues again if shutting down so
2614          * must flush all entered requests to their failed completion to avoid
2615          * deadlocking blk-mq hot-cpu notifier.
2616          */
2617         if (shutdown) {
2618                 nvme_unquiesce_io_queues(&dev->ctrl);
2619                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2620                         nvme_unquiesce_admin_queue(&dev->ctrl);
2621         }
2622         mutex_unlock(&dev->shutdown_lock);
2623 }
2624
2625 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2626 {
2627         if (!nvme_wait_reset(&dev->ctrl))
2628                 return -EBUSY;
2629         nvme_dev_disable(dev, shutdown);
2630         return 0;
2631 }
2632
2633 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2634 {
2635         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2636                                                 NVME_CTRL_PAGE_SIZE,
2637                                                 NVME_CTRL_PAGE_SIZE, 0);
2638         if (!dev->prp_page_pool)
2639                 return -ENOMEM;
2640
2641         /* Optimisation for I/Os between 4k and 128k */
2642         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2643                                                 256, 256, 0);
2644         if (!dev->prp_small_pool) {
2645                 dma_pool_destroy(dev->prp_page_pool);
2646                 return -ENOMEM;
2647         }
2648         return 0;
2649 }
2650
2651 static void nvme_release_prp_pools(struct nvme_dev *dev)
2652 {
2653         dma_pool_destroy(dev->prp_page_pool);
2654         dma_pool_destroy(dev->prp_small_pool);
2655 }
2656
2657 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2658 {
2659         size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2660
2661         dev->iod_mempool = mempool_create_node(1,
2662                         mempool_kmalloc, mempool_kfree,
2663                         (void *)alloc_size, GFP_KERNEL,
2664                         dev_to_node(dev->dev));
2665         if (!dev->iod_mempool)
2666                 return -ENOMEM;
2667         return 0;
2668 }
2669
2670 static void nvme_free_tagset(struct nvme_dev *dev)
2671 {
2672         if (dev->tagset.tags)
2673                 nvme_remove_io_tag_set(&dev->ctrl);
2674         dev->ctrl.tagset = NULL;
2675 }
2676
2677 /* pairs with nvme_pci_alloc_dev */
2678 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2679 {
2680         struct nvme_dev *dev = to_nvme_dev(ctrl);
2681
2682         nvme_free_tagset(dev);
2683         put_device(dev->dev);
2684         kfree(dev->queues);
2685         kfree(dev);
2686 }
2687
2688 static void nvme_reset_work(struct work_struct *work)
2689 {
2690         struct nvme_dev *dev =
2691                 container_of(work, struct nvme_dev, ctrl.reset_work);
2692         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2693         int result;
2694
2695         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2696                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2697                          dev->ctrl.state);
2698                 return;
2699         }
2700
2701         /*
2702          * If we're called to reset a live controller first shut it down before
2703          * moving on.
2704          */
2705         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2706                 nvme_dev_disable(dev, false);
2707         nvme_sync_queues(&dev->ctrl);
2708
2709         mutex_lock(&dev->shutdown_lock);
2710         result = nvme_pci_enable(dev);
2711         if (result)
2712                 goto out_unlock;
2713         nvme_unquiesce_admin_queue(&dev->ctrl);
2714         mutex_unlock(&dev->shutdown_lock);
2715
2716         /*
2717          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2718          * initializing procedure here.
2719          */
2720         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2721                 dev_warn(dev->ctrl.device,
2722                         "failed to mark controller CONNECTING\n");
2723                 result = -EBUSY;
2724                 goto out;
2725         }
2726
2727         result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
2728         if (result)
2729                 goto out;
2730
2731         nvme_dbbuf_dma_alloc(dev);
2732
2733         result = nvme_setup_host_mem(dev);
2734         if (result < 0)
2735                 goto out;
2736
2737         result = nvme_setup_io_queues(dev);
2738         if (result)
2739                 goto out;
2740
2741         /*
2742          * Freeze and update the number of I/O queues as thos might have
2743          * changed.  If there are no I/O queues left after this reset, keep the
2744          * controller around but remove all namespaces.
2745          */
2746         if (dev->online_queues > 1) {
2747                 nvme_unquiesce_io_queues(&dev->ctrl);
2748                 nvme_wait_freeze(&dev->ctrl);
2749                 nvme_pci_update_nr_queues(dev);
2750                 nvme_dbbuf_set(dev);
2751                 nvme_unfreeze(&dev->ctrl);
2752         } else {
2753                 dev_warn(dev->ctrl.device, "IO queues lost\n");
2754                 nvme_mark_namespaces_dead(&dev->ctrl);
2755                 nvme_unquiesce_io_queues(&dev->ctrl);
2756                 nvme_remove_namespaces(&dev->ctrl);
2757                 nvme_free_tagset(dev);
2758         }
2759
2760         /*
2761          * If only admin queue live, keep it to do further investigation or
2762          * recovery.
2763          */
2764         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2765                 dev_warn(dev->ctrl.device,
2766                         "failed to mark controller live state\n");
2767                 result = -ENODEV;
2768                 goto out;
2769         }
2770
2771         nvme_start_ctrl(&dev->ctrl);
2772         return;
2773
2774  out_unlock:
2775         mutex_unlock(&dev->shutdown_lock);
2776  out:
2777         /*
2778          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2779          * may be holding this pci_dev's device lock.
2780          */
2781         dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2782                  result);
2783         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2784         nvme_dev_disable(dev, true);
2785         nvme_mark_namespaces_dead(&dev->ctrl);
2786         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2787 }
2788
2789 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2790 {
2791         *val = readl(to_nvme_dev(ctrl)->bar + off);
2792         return 0;
2793 }
2794
2795 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2796 {
2797         writel(val, to_nvme_dev(ctrl)->bar + off);
2798         return 0;
2799 }
2800
2801 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2802 {
2803         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2804         return 0;
2805 }
2806
2807 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2808 {
2809         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2810
2811         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2812 }
2813
2814 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2815 {
2816         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2817         struct nvme_subsystem *subsys = ctrl->subsys;
2818
2819         dev_err(ctrl->device,
2820                 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2821                 pdev->vendor, pdev->device,
2822                 nvme_strlen(subsys->model, sizeof(subsys->model)),
2823                 subsys->model, nvme_strlen(subsys->firmware_rev,
2824                                            sizeof(subsys->firmware_rev)),
2825                 subsys->firmware_rev);
2826 }
2827
2828 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2829 {
2830         struct nvme_dev *dev = to_nvme_dev(ctrl);
2831
2832         return dma_pci_p2pdma_supported(dev->dev);
2833 }
2834
2835 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2836         .name                   = "pcie",
2837         .module                 = THIS_MODULE,
2838         .flags                  = NVME_F_METADATA_SUPPORTED,
2839         .dev_attr_groups        = nvme_pci_dev_attr_groups,
2840         .reg_read32             = nvme_pci_reg_read32,
2841         .reg_write32            = nvme_pci_reg_write32,
2842         .reg_read64             = nvme_pci_reg_read64,
2843         .free_ctrl              = nvme_pci_free_ctrl,
2844         .submit_async_event     = nvme_pci_submit_async_event,
2845         .get_address            = nvme_pci_get_address,
2846         .print_device_info      = nvme_pci_print_device_info,
2847         .supports_pci_p2pdma    = nvme_pci_supports_pci_p2pdma,
2848 };
2849
2850 static int nvme_dev_map(struct nvme_dev *dev)
2851 {
2852         struct pci_dev *pdev = to_pci_dev(dev->dev);
2853
2854         if (pci_request_mem_regions(pdev, "nvme"))
2855                 return -ENODEV;
2856
2857         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2858                 goto release;
2859
2860         return 0;
2861   release:
2862         pci_release_mem_regions(pdev);
2863         return -ENODEV;
2864 }
2865
2866 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2867 {
2868         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2869                 /*
2870                  * Several Samsung devices seem to drop off the PCIe bus
2871                  * randomly when APST is on and uses the deepest sleep state.
2872                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2873                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2874                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2875                  * laptops.
2876                  */
2877                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2878                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2879                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2880                         return NVME_QUIRK_NO_DEEPEST_PS;
2881         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2882                 /*
2883                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2884                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2885                  * within few minutes after bootup on a Coffee Lake board -
2886                  * ASUS PRIME Z370-A
2887                  */
2888                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2889                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2890                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2891                         return NVME_QUIRK_NO_APST;
2892         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2893                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2894                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2895                 /*
2896                  * Forcing to use host managed nvme power settings for
2897                  * lowest idle power with quick resume latency on
2898                  * Samsung and Toshiba SSDs based on suspend behavior
2899                  * on Coffee Lake board for LENOVO C640
2900                  */
2901                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2902                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2903                         return NVME_QUIRK_SIMPLE_SUSPEND;
2904         }
2905
2906         return 0;
2907 }
2908
2909 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2910                 const struct pci_device_id *id)
2911 {
2912         unsigned long quirks = id->driver_data;
2913         int node = dev_to_node(&pdev->dev);
2914         struct nvme_dev *dev;
2915         int ret = -ENOMEM;
2916
2917         if (node == NUMA_NO_NODE)
2918                 set_dev_node(&pdev->dev, first_memory_node);
2919
2920         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2921         if (!dev)
2922                 return ERR_PTR(-ENOMEM);
2923         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2924         mutex_init(&dev->shutdown_lock);
2925
2926         dev->nr_write_queues = write_queues;
2927         dev->nr_poll_queues = poll_queues;
2928         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2929         dev->queues = kcalloc_node(dev->nr_allocated_queues,
2930                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2931         if (!dev->queues)
2932                 goto out_free_dev;
2933
2934         dev->dev = get_device(&pdev->dev);
2935
2936         quirks |= check_vendor_combination_bug(pdev);
2937         if (!noacpi && acpi_storage_d3(&pdev->dev)) {
2938                 /*
2939                  * Some systems use a bios work around to ask for D3 on
2940                  * platforms that support kernel managed suspend.
2941                  */
2942                 dev_info(&pdev->dev,
2943                          "platform quirk: setting simple suspend\n");
2944                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2945         }
2946         ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2947                              quirks);
2948         if (ret)
2949                 goto out_put_device;
2950
2951         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2952                 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
2953         else
2954                 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2955         dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2956         dma_set_max_seg_size(&pdev->dev, 0xffffffff);
2957
2958         /*
2959          * Limit the max command size to prevent iod->sg allocations going
2960          * over a single page.
2961          */
2962         dev->ctrl.max_hw_sectors = min_t(u32,
2963                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9);
2964         dev->ctrl.max_segments = NVME_MAX_SEGS;
2965
2966         /*
2967          * There is no support for SGLs for metadata (yet), so we are limited to
2968          * a single integrity segment for the separate metadata pointer.
2969          */
2970         dev->ctrl.max_integrity_segments = 1;
2971         return dev;
2972
2973 out_put_device:
2974         put_device(dev->dev);
2975         kfree(dev->queues);
2976 out_free_dev:
2977         kfree(dev);
2978         return ERR_PTR(ret);
2979 }
2980
2981 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2982 {
2983         struct nvme_dev *dev;
2984         int result = -ENOMEM;
2985
2986         dev = nvme_pci_alloc_dev(pdev, id);
2987         if (IS_ERR(dev))
2988                 return PTR_ERR(dev);
2989
2990         result = nvme_dev_map(dev);
2991         if (result)
2992                 goto out_uninit_ctrl;
2993
2994         result = nvme_setup_prp_pools(dev);
2995         if (result)
2996                 goto out_dev_unmap;
2997
2998         result = nvme_pci_alloc_iod_mempool(dev);
2999         if (result)
3000                 goto out_release_prp_pools;
3001
3002         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3003
3004         result = nvme_pci_enable(dev);
3005         if (result)
3006                 goto out_release_iod_mempool;
3007
3008         result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3009                                 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
3010         if (result)
3011                 goto out_disable;
3012
3013         /*
3014          * Mark the controller as connecting before sending admin commands to
3015          * allow the timeout handler to do the right thing.
3016          */
3017         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3018                 dev_warn(dev->ctrl.device,
3019                         "failed to mark controller CONNECTING\n");
3020                 result = -EBUSY;
3021                 goto out_disable;
3022         }
3023
3024         result = nvme_init_ctrl_finish(&dev->ctrl, false);
3025         if (result)
3026                 goto out_disable;
3027
3028         nvme_dbbuf_dma_alloc(dev);
3029
3030         result = nvme_setup_host_mem(dev);
3031         if (result < 0)
3032                 goto out_disable;
3033
3034         result = nvme_setup_io_queues(dev);
3035         if (result)
3036                 goto out_disable;
3037
3038         if (dev->online_queues > 1) {
3039                 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3040                                 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3041                 nvme_dbbuf_set(dev);
3042         }
3043
3044         if (!dev->ctrl.tagset)
3045                 dev_warn(dev->ctrl.device, "IO queues not created\n");
3046
3047         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3048                 dev_warn(dev->ctrl.device,
3049                         "failed to mark controller live state\n");
3050                 result = -ENODEV;
3051                 goto out_disable;
3052         }
3053
3054         pci_set_drvdata(pdev, dev);
3055
3056         nvme_start_ctrl(&dev->ctrl);
3057         nvme_put_ctrl(&dev->ctrl);
3058         flush_work(&dev->ctrl.scan_work);
3059         return 0;
3060
3061 out_disable:
3062         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3063         nvme_dev_disable(dev, true);
3064         nvme_free_host_mem(dev);
3065         nvme_dev_remove_admin(dev);
3066         nvme_dbbuf_dma_free(dev);
3067         nvme_free_queues(dev, 0);
3068 out_release_iod_mempool:
3069         mempool_destroy(dev->iod_mempool);
3070 out_release_prp_pools:
3071         nvme_release_prp_pools(dev);
3072 out_dev_unmap:
3073         nvme_dev_unmap(dev);
3074 out_uninit_ctrl:
3075         nvme_uninit_ctrl(&dev->ctrl);
3076         nvme_put_ctrl(&dev->ctrl);
3077         return result;
3078 }
3079
3080 static void nvme_reset_prepare(struct pci_dev *pdev)
3081 {
3082         struct nvme_dev *dev = pci_get_drvdata(pdev);
3083
3084         /*
3085          * We don't need to check the return value from waiting for the reset
3086          * state as pci_dev device lock is held, making it impossible to race
3087          * with ->remove().
3088          */
3089         nvme_disable_prepare_reset(dev, false);
3090         nvme_sync_queues(&dev->ctrl);
3091 }
3092
3093 static void nvme_reset_done(struct pci_dev *pdev)
3094 {
3095         struct nvme_dev *dev = pci_get_drvdata(pdev);
3096
3097         if (!nvme_try_sched_reset(&dev->ctrl))
3098                 flush_work(&dev->ctrl.reset_work);
3099 }
3100
3101 static void nvme_shutdown(struct pci_dev *pdev)
3102 {
3103         struct nvme_dev *dev = pci_get_drvdata(pdev);
3104
3105         nvme_disable_prepare_reset(dev, true);
3106 }
3107
3108 /*
3109  * The driver's remove may be called on a device in a partially initialized
3110  * state. This function must not have any dependencies on the device state in
3111  * order to proceed.
3112  */
3113 static void nvme_remove(struct pci_dev *pdev)
3114 {
3115         struct nvme_dev *dev = pci_get_drvdata(pdev);
3116
3117         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3118         pci_set_drvdata(pdev, NULL);
3119
3120         if (!pci_device_is_present(pdev)) {
3121                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3122                 nvme_dev_disable(dev, true);
3123         }
3124
3125         flush_work(&dev->ctrl.reset_work);
3126         nvme_stop_ctrl(&dev->ctrl);
3127         nvme_remove_namespaces(&dev->ctrl);
3128         nvme_dev_disable(dev, true);
3129         nvme_free_host_mem(dev);
3130         nvme_dev_remove_admin(dev);
3131         nvme_dbbuf_dma_free(dev);
3132         nvme_free_queues(dev, 0);
3133         mempool_destroy(dev->iod_mempool);
3134         nvme_release_prp_pools(dev);
3135         nvme_dev_unmap(dev);
3136         nvme_uninit_ctrl(&dev->ctrl);
3137 }
3138
3139 #ifdef CONFIG_PM_SLEEP
3140 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3141 {
3142         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3143 }
3144
3145 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3146 {
3147         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3148 }
3149
3150 static int nvme_resume(struct device *dev)
3151 {
3152         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3153         struct nvme_ctrl *ctrl = &ndev->ctrl;
3154
3155         if (ndev->last_ps == U32_MAX ||
3156             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3157                 goto reset;
3158         if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3159                 goto reset;
3160
3161         return 0;
3162 reset:
3163         return nvme_try_sched_reset(ctrl);
3164 }
3165
3166 static int nvme_suspend(struct device *dev)
3167 {
3168         struct pci_dev *pdev = to_pci_dev(dev);
3169         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3170         struct nvme_ctrl *ctrl = &ndev->ctrl;
3171         int ret = -EBUSY;
3172
3173         ndev->last_ps = U32_MAX;
3174
3175         /*
3176          * The platform does not remove power for a kernel managed suspend so
3177          * use host managed nvme power settings for lowest idle power if
3178          * possible. This should have quicker resume latency than a full device
3179          * shutdown.  But if the firmware is involved after the suspend or the
3180          * device does not support any non-default power states, shut down the
3181          * device fully.
3182          *
3183          * If ASPM is not enabled for the device, shut down the device and allow
3184          * the PCI bus layer to put it into D3 in order to take the PCIe link
3185          * down, so as to allow the platform to achieve its minimum low-power
3186          * state (which may not be possible if the link is up).
3187          */
3188         if (pm_suspend_via_firmware() || !ctrl->npss ||
3189             !pcie_aspm_enabled(pdev) ||
3190             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3191                 return nvme_disable_prepare_reset(ndev, true);
3192
3193         nvme_start_freeze(ctrl);
3194         nvme_wait_freeze(ctrl);
3195         nvme_sync_queues(ctrl);
3196
3197         if (ctrl->state != NVME_CTRL_LIVE)
3198                 goto unfreeze;
3199
3200         /*
3201          * Host memory access may not be successful in a system suspend state,
3202          * but the specification allows the controller to access memory in a
3203          * non-operational power state.
3204          */
3205         if (ndev->hmb) {
3206                 ret = nvme_set_host_mem(ndev, 0);
3207                 if (ret < 0)
3208                         goto unfreeze;
3209         }
3210
3211         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3212         if (ret < 0)
3213                 goto unfreeze;
3214
3215         /*
3216          * A saved state prevents pci pm from generically controlling the
3217          * device's power. If we're using protocol specific settings, we don't
3218          * want pci interfering.
3219          */
3220         pci_save_state(pdev);
3221
3222         ret = nvme_set_power_state(ctrl, ctrl->npss);
3223         if (ret < 0)
3224                 goto unfreeze;
3225
3226         if (ret) {
3227                 /* discard the saved state */
3228                 pci_load_saved_state(pdev, NULL);
3229
3230                 /*
3231                  * Clearing npss forces a controller reset on resume. The
3232                  * correct value will be rediscovered then.
3233                  */
3234                 ret = nvme_disable_prepare_reset(ndev, true);
3235                 ctrl->npss = 0;
3236         }
3237 unfreeze:
3238         nvme_unfreeze(ctrl);
3239         return ret;
3240 }
3241
3242 static int nvme_simple_suspend(struct device *dev)
3243 {
3244         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3245
3246         return nvme_disable_prepare_reset(ndev, true);
3247 }
3248
3249 static int nvme_simple_resume(struct device *dev)
3250 {
3251         struct pci_dev *pdev = to_pci_dev(dev);
3252         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3253
3254         return nvme_try_sched_reset(&ndev->ctrl);
3255 }
3256
3257 static const struct dev_pm_ops nvme_dev_pm_ops = {
3258         .suspend        = nvme_suspend,
3259         .resume         = nvme_resume,
3260         .freeze         = nvme_simple_suspend,
3261         .thaw           = nvme_simple_resume,
3262         .poweroff       = nvme_simple_suspend,
3263         .restore        = nvme_simple_resume,
3264 };
3265 #endif /* CONFIG_PM_SLEEP */
3266
3267 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3268                                                 pci_channel_state_t state)
3269 {
3270         struct nvme_dev *dev = pci_get_drvdata(pdev);
3271
3272         /*
3273          * A frozen channel requires a reset. When detected, this method will
3274          * shutdown the controller to quiesce. The controller will be restarted
3275          * after the slot reset through driver's slot_reset callback.
3276          */
3277         switch (state) {
3278         case pci_channel_io_normal:
3279                 return PCI_ERS_RESULT_CAN_RECOVER;
3280         case pci_channel_io_frozen:
3281                 dev_warn(dev->ctrl.device,
3282                         "frozen state error detected, reset controller\n");
3283                 nvme_dev_disable(dev, false);
3284                 return PCI_ERS_RESULT_NEED_RESET;
3285         case pci_channel_io_perm_failure:
3286                 dev_warn(dev->ctrl.device,
3287                         "failure state error detected, request disconnect\n");
3288                 return PCI_ERS_RESULT_DISCONNECT;
3289         }
3290         return PCI_ERS_RESULT_NEED_RESET;
3291 }
3292
3293 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3294 {
3295         struct nvme_dev *dev = pci_get_drvdata(pdev);
3296
3297         dev_info(dev->ctrl.device, "restart after slot reset\n");
3298         pci_restore_state(pdev);
3299         nvme_reset_ctrl(&dev->ctrl);
3300         return PCI_ERS_RESULT_RECOVERED;
3301 }
3302
3303 static void nvme_error_resume(struct pci_dev *pdev)
3304 {
3305         struct nvme_dev *dev = pci_get_drvdata(pdev);
3306
3307         flush_work(&dev->ctrl.reset_work);
3308 }
3309
3310 static const struct pci_error_handlers nvme_err_handler = {
3311         .error_detected = nvme_error_detected,
3312         .slot_reset     = nvme_slot_reset,
3313         .resume         = nvme_error_resume,
3314         .reset_prepare  = nvme_reset_prepare,
3315         .reset_done     = nvme_reset_done,
3316 };
3317
3318 static const struct pci_device_id nvme_id_table[] = {
3319         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3320                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3321                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3322         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3323                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3324                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3325         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3326                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3327                                 NVME_QUIRK_DEALLOCATE_ZEROES |
3328                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3329         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3330                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3331                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3332         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3333                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3334                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3335                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3336                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3337         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3338                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3339         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3340                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3341                                 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3342                                 NVME_QUIRK_BOGUS_NID, },
3343         { PCI_VDEVICE(REDHAT, 0x0010),  /* Qemu emulated controller */
3344                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3345         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3346                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3347                                 NVME_QUIRK_BOGUS_NID, },
3348         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3349                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3350                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3351         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3352                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3353         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3354                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3355         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3356                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3357         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3358                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3359         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3360                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3361                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3362                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3363         { PCI_DEVICE(0x1987, 0x5012),   /* Phison E12 */
3364                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3365         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3366                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3367                                 NVME_QUIRK_BOGUS_NID, },
3368         { PCI_DEVICE(0x1987, 0x5019),  /* phison E19 */
3369                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3370         { PCI_DEVICE(0x1987, 0x5021),   /* Phison E21 */
3371                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3372         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3373                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3374                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3375         { PCI_DEVICE(0x1cc1, 0x33f8),   /* ADATA IM2P33F8ABR1 1 TB */
3376                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3377         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3378                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3379                                 NVME_QUIRK_BOGUS_NID, },
3380         { PCI_DEVICE(0x10ec, 0x5763),  /* ADATA SX6000PNP */
3381                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3382         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3383                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3384                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3385          { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3386                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3387          { PCI_DEVICE(0x1344, 0x6001),   /* Micron Nitro NVMe */
3388                  .driver_data = NVME_QUIRK_BOGUS_NID, },
3389         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3390                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3391         { PCI_DEVICE(0x1c5c, 0x174a),   /* SK Hynix P31 SSD */
3392                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3393         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3394                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3395         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3396                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3397         { PCI_DEVICE(0x144d, 0xa80b),   /* Samsung PM9B1 256G and 512G */
3398                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3399         { PCI_DEVICE(0x144d, 0xa809),   /* Samsung MZALQ256HBJD 256G */
3400                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3401         { PCI_DEVICE(0x1cc4, 0x6303),   /* UMIS RPJTJ512MGE1QDY 512G */
3402                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3403         { PCI_DEVICE(0x1cc4, 0x6302),   /* UMIS RPJTJ256MGE1QDY 256G */
3404                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3405         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3406                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3407         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3408                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3409         { PCI_DEVICE(0x2646, 0x5018),   /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3410                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3411         { PCI_DEVICE(0x2646, 0x5016),   /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3412                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3413         { PCI_DEVICE(0x2646, 0x501A),   /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3414                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3415         { PCI_DEVICE(0x2646, 0x501B),   /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3416                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3417         { PCI_DEVICE(0x2646, 0x501E),   /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3418                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3419         { PCI_DEVICE(0x1f40, 0x1202),   /* Netac Technologies Co. NV3000 NVMe SSD */
3420                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3421         { PCI_DEVICE(0x1f40, 0x5236),   /* Netac Technologies Co. NV7000 NVMe SSD */
3422                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3423         { PCI_DEVICE(0x1e4B, 0x1001),   /* MAXIO MAP1001 */
3424                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3425         { PCI_DEVICE(0x1e4B, 0x1002),   /* MAXIO MAP1002 */
3426                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3427         { PCI_DEVICE(0x1e4B, 0x1202),   /* MAXIO MAP1202 */
3428                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3429         { PCI_DEVICE(0x1cc1, 0x5350),   /* ADATA XPG GAMMIX S50 */
3430                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3431         { PCI_DEVICE(0x1dbe, 0x5236),   /* ADATA XPG GAMMIX S70 */
3432                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3433         { PCI_DEVICE(0x1e49, 0x0021),   /* ZHITAI TiPro5000 NVMe SSD */
3434                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3435         { PCI_DEVICE(0x1e49, 0x0041),   /* ZHITAI TiPro7000 NVMe SSD */
3436                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3437         { PCI_DEVICE(0xc0a9, 0x540a),   /* Crucial P2 */
3438                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3439         { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3440                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3441         { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3442                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3443         { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3444                 .driver_data = NVME_QUIRK_BOGUS_NID |
3445                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3446         { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3447                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3448         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3449                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3450         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3451                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3452         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3453                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3454         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3455                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3456         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3457                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3458         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3459                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3460         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3461                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3462         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3463         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3464                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3465                                 NVME_QUIRK_128_BYTES_SQES |
3466                                 NVME_QUIRK_SHARED_TAGS |
3467                                 NVME_QUIRK_SKIP_CID_GEN |
3468                                 NVME_QUIRK_IDENTIFY_CNS },
3469         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3470         { 0, }
3471 };
3472 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3473
3474 static struct pci_driver nvme_driver = {
3475         .name           = "nvme",
3476         .id_table       = nvme_id_table,
3477         .probe          = nvme_probe,
3478         .remove         = nvme_remove,
3479         .shutdown       = nvme_shutdown,
3480         .driver         = {
3481                 .probe_type     = PROBE_PREFER_ASYNCHRONOUS,
3482 #ifdef CONFIG_PM_SLEEP
3483                 .pm             = &nvme_dev_pm_ops,
3484 #endif
3485         },
3486         .sriov_configure = pci_sriov_configure_simple,
3487         .err_handler    = &nvme_err_handler,
3488 };
3489
3490 static int __init nvme_init(void)
3491 {
3492         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3493         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3494         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3495         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3496         BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
3497         BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3498         BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
3499
3500         return pci_register_driver(&nvme_driver);
3501 }
3502
3503 static void __exit nvme_exit(void)
3504 {
3505         pci_unregister_driver(&nvme_driver);
3506         flush_workqueue(nvme_wq);
3507 }
3508
3509 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3510 MODULE_LICENSE("GPL");
3511 MODULE_VERSION("1.0");
3512 module_init(nvme_init);
3513 module_exit(nvme_exit);