nvme: use offset instead of a struct for registers
[linux-2.6-block.git] / drivers / nvme / host / pci.c
1 /*
2  * NVM Express device driver
3  * Copyright (c) 2011-2014, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  */
14
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
31 #include <linux/list_sort.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/types.h>
42 #include <linux/pr.h>
43 #include <scsi/sg.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <asm/unaligned.h>
46
47 #include <uapi/linux/nvme_ioctl.h>
48 #include "nvme.h"
49
50 #define NVME_MINORS             (1U << MINORBITS)
51 #define NVME_Q_DEPTH            1024
52 #define NVME_AQ_DEPTH           256
53 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
54 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
55 #define SHUTDOWN_TIMEOUT        (shutdown_timeout * HZ)
56
57 unsigned char admin_timeout = 60;
58 module_param(admin_timeout, byte, 0644);
59 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
60
61 unsigned char nvme_io_timeout = 30;
62 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
63 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
64
65 static unsigned char shutdown_timeout = 5;
66 module_param(shutdown_timeout, byte, 0644);
67 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
68
69 static int nvme_major;
70 module_param(nvme_major, int, 0);
71
72 static int nvme_char_major;
73 module_param(nvme_char_major, int, 0);
74
75 static int use_threaded_interrupts;
76 module_param(use_threaded_interrupts, int, 0);
77
78 static bool use_cmb_sqes = true;
79 module_param(use_cmb_sqes, bool, 0644);
80 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
81
82 static DEFINE_SPINLOCK(dev_list_lock);
83 static LIST_HEAD(dev_list);
84 static struct task_struct *nvme_thread;
85 static struct workqueue_struct *nvme_workq;
86 static wait_queue_head_t nvme_kthread_wait;
87
88 static struct class *nvme_class;
89
90 static int __nvme_reset(struct nvme_dev *dev);
91 static int nvme_reset(struct nvme_dev *dev);
92 static void nvme_process_cq(struct nvme_queue *nvmeq);
93 static void nvme_dead_ctrl(struct nvme_dev *dev);
94
95 struct async_cmd_info {
96         struct kthread_work work;
97         struct kthread_worker *worker;
98         struct request *req;
99         u32 result;
100         int status;
101         void *ctx;
102 };
103
104 /*
105  * An NVM Express queue.  Each device has at least two (one for admin
106  * commands and one for I/O commands).
107  */
108 struct nvme_queue {
109         struct device *q_dmadev;
110         struct nvme_dev *dev;
111         char irqname[24];       /* nvme4294967295-65535\0 */
112         spinlock_t q_lock;
113         struct nvme_command *sq_cmds;
114         struct nvme_command __iomem *sq_cmds_io;
115         volatile struct nvme_completion *cqes;
116         struct blk_mq_tags **tags;
117         dma_addr_t sq_dma_addr;
118         dma_addr_t cq_dma_addr;
119         u32 __iomem *q_db;
120         u16 q_depth;
121         s16 cq_vector;
122         u16 sq_head;
123         u16 sq_tail;
124         u16 cq_head;
125         u16 qid;
126         u8 cq_phase;
127         u8 cqe_seen;
128         struct async_cmd_info cmdinfo;
129 };
130
131 /*
132  * The nvme_iod describes the data in an I/O, including the list of PRP
133  * entries.  You can't see it in this data structure because C doesn't let
134  * me express that.  Use nvme_alloc_iod to ensure there's enough space
135  * allocated to store the PRP list.
136  */
137 struct nvme_iod {
138         unsigned long private;  /* For the use of the submitter of the I/O */
139         int npages;             /* In the PRP list. 0 means small pool in use */
140         int offset;             /* Of PRP list */
141         int nents;              /* Used in scatterlist */
142         int length;             /* Of data, in bytes */
143         dma_addr_t first_dma;
144         struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
145         struct scatterlist sg[0];
146 };
147
148 /*
149  * Check we didin't inadvertently grow the command struct
150  */
151 static inline void _nvme_check_size(void)
152 {
153         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
154         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
155         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
156         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
157         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
158         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
159         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
160         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
161         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
162         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
163         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
164         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
165 }
166
167 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
168                                                 struct nvme_completion *);
169
170 struct nvme_cmd_info {
171         nvme_completion_fn fn;
172         void *ctx;
173         int aborted;
174         struct nvme_queue *nvmeq;
175         struct nvme_iod iod[0];
176 };
177
178 /*
179  * Max size of iod being embedded in the request payload
180  */
181 #define NVME_INT_PAGES          2
182 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->page_size)
183 #define NVME_INT_MASK           0x01
184
185 /*
186  * Will slightly overestimate the number of pages needed.  This is OK
187  * as it only leads to a small amount of wasted memory for the lifetime of
188  * the I/O.
189  */
190 static int nvme_npages(unsigned size, struct nvme_dev *dev)
191 {
192         unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
193         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
194 }
195
196 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
197 {
198         unsigned int ret = sizeof(struct nvme_cmd_info);
199
200         ret += sizeof(struct nvme_iod);
201         ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
202         ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
203
204         return ret;
205 }
206
207 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
208                                 unsigned int hctx_idx)
209 {
210         struct nvme_dev *dev = data;
211         struct nvme_queue *nvmeq = dev->queues[0];
212
213         WARN_ON(hctx_idx != 0);
214         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
215         WARN_ON(nvmeq->tags);
216
217         hctx->driver_data = nvmeq;
218         nvmeq->tags = &dev->admin_tagset.tags[0];
219         return 0;
220 }
221
222 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
223 {
224         struct nvme_queue *nvmeq = hctx->driver_data;
225
226         nvmeq->tags = NULL;
227 }
228
229 static int nvme_admin_init_request(void *data, struct request *req,
230                                 unsigned int hctx_idx, unsigned int rq_idx,
231                                 unsigned int numa_node)
232 {
233         struct nvme_dev *dev = data;
234         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
235         struct nvme_queue *nvmeq = dev->queues[0];
236
237         BUG_ON(!nvmeq);
238         cmd->nvmeq = nvmeq;
239         return 0;
240 }
241
242 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
243                           unsigned int hctx_idx)
244 {
245         struct nvme_dev *dev = data;
246         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
247
248         if (!nvmeq->tags)
249                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
250
251         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
252         hctx->driver_data = nvmeq;
253         return 0;
254 }
255
256 static int nvme_init_request(void *data, struct request *req,
257                                 unsigned int hctx_idx, unsigned int rq_idx,
258                                 unsigned int numa_node)
259 {
260         struct nvme_dev *dev = data;
261         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
262         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
263
264         BUG_ON(!nvmeq);
265         cmd->nvmeq = nvmeq;
266         return 0;
267 }
268
269 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
270                                 nvme_completion_fn handler)
271 {
272         cmd->fn = handler;
273         cmd->ctx = ctx;
274         cmd->aborted = 0;
275         blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
276 }
277
278 static void *iod_get_private(struct nvme_iod *iod)
279 {
280         return (void *) (iod->private & ~0x1UL);
281 }
282
283 /*
284  * If bit 0 is set, the iod is embedded in the request payload.
285  */
286 static bool iod_should_kfree(struct nvme_iod *iod)
287 {
288         return (iod->private & NVME_INT_MASK) == 0;
289 }
290
291 /* Special values must be less than 0x1000 */
292 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
293 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
294 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
295 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
296
297 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
298                                                 struct nvme_completion *cqe)
299 {
300         if (ctx == CMD_CTX_CANCELLED)
301                 return;
302         if (ctx == CMD_CTX_COMPLETED) {
303                 dev_warn(nvmeq->q_dmadev,
304                                 "completed id %d twice on queue %d\n",
305                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
306                 return;
307         }
308         if (ctx == CMD_CTX_INVALID) {
309                 dev_warn(nvmeq->q_dmadev,
310                                 "invalid id %d completed on queue %d\n",
311                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
312                 return;
313         }
314         dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
315 }
316
317 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
318 {
319         void *ctx;
320
321         if (fn)
322                 *fn = cmd->fn;
323         ctx = cmd->ctx;
324         cmd->fn = special_completion;
325         cmd->ctx = CMD_CTX_CANCELLED;
326         return ctx;
327 }
328
329 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
330                                                 struct nvme_completion *cqe)
331 {
332         u32 result = le32_to_cpup(&cqe->result);
333         u16 status = le16_to_cpup(&cqe->status) >> 1;
334
335         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
336                 ++nvmeq->dev->event_limit;
337         if (status != NVME_SC_SUCCESS)
338                 return;
339
340         switch (result & 0xff07) {
341         case NVME_AER_NOTICE_NS_CHANGED:
342                 dev_info(nvmeq->q_dmadev, "rescanning\n");
343                 schedule_work(&nvmeq->dev->scan_work);
344         default:
345                 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
346         }
347 }
348
349 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
350                                                 struct nvme_completion *cqe)
351 {
352         struct request *req = ctx;
353
354         u16 status = le16_to_cpup(&cqe->status) >> 1;
355         u32 result = le32_to_cpup(&cqe->result);
356
357         blk_mq_free_request(req);
358
359         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
360         ++nvmeq->dev->abort_limit;
361 }
362
363 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
364                                                 struct nvme_completion *cqe)
365 {
366         struct async_cmd_info *cmdinfo = ctx;
367         cmdinfo->result = le32_to_cpup(&cqe->result);
368         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
369         queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
370         blk_mq_free_request(cmdinfo->req);
371 }
372
373 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
374                                   unsigned int tag)
375 {
376         struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
377
378         return blk_mq_rq_to_pdu(req);
379 }
380
381 /*
382  * Called with local interrupts disabled and the q_lock held.  May not sleep.
383  */
384 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
385                                                 nvme_completion_fn *fn)
386 {
387         struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
388         void *ctx;
389         if (tag >= nvmeq->q_depth) {
390                 *fn = special_completion;
391                 return CMD_CTX_INVALID;
392         }
393         if (fn)
394                 *fn = cmd->fn;
395         ctx = cmd->ctx;
396         cmd->fn = special_completion;
397         cmd->ctx = CMD_CTX_COMPLETED;
398         return ctx;
399 }
400
401 /**
402  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
403  * @nvmeq: The queue to use
404  * @cmd: The command to send
405  *
406  * Safe to use from interrupt context
407  */
408 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
409                                                 struct nvme_command *cmd)
410 {
411         u16 tail = nvmeq->sq_tail;
412
413         if (nvmeq->sq_cmds_io)
414                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
415         else
416                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
417
418         if (++tail == nvmeq->q_depth)
419                 tail = 0;
420         writel(tail, nvmeq->q_db);
421         nvmeq->sq_tail = tail;
422 }
423
424 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
425 {
426         unsigned long flags;
427         spin_lock_irqsave(&nvmeq->q_lock, flags);
428         __nvme_submit_cmd(nvmeq, cmd);
429         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
430 }
431
432 static __le64 **iod_list(struct nvme_iod *iod)
433 {
434         return ((void *)iod) + iod->offset;
435 }
436
437 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
438                             unsigned nseg, unsigned long private)
439 {
440         iod->private = private;
441         iod->offset = offsetof(struct nvme_iod, sg[nseg]);
442         iod->npages = -1;
443         iod->length = nbytes;
444         iod->nents = 0;
445 }
446
447 static struct nvme_iod *
448 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
449                  unsigned long priv, gfp_t gfp)
450 {
451         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
452                                 sizeof(__le64 *) * nvme_npages(bytes, dev) +
453                                 sizeof(struct scatterlist) * nseg, gfp);
454
455         if (iod)
456                 iod_init(iod, bytes, nseg, priv);
457
458         return iod;
459 }
460
461 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
462                                        gfp_t gfp)
463 {
464         unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
465                                                 sizeof(struct nvme_dsm_range);
466         struct nvme_iod *iod;
467
468         if (rq->nr_phys_segments <= NVME_INT_PAGES &&
469             size <= NVME_INT_BYTES(dev)) {
470                 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
471
472                 iod = cmd->iod;
473                 iod_init(iod, size, rq->nr_phys_segments,
474                                 (unsigned long) rq | NVME_INT_MASK);
475                 return iod;
476         }
477
478         return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
479                                 (unsigned long) rq, gfp);
480 }
481
482 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
483 {
484         const int last_prp = dev->page_size / 8 - 1;
485         int i;
486         __le64 **list = iod_list(iod);
487         dma_addr_t prp_dma = iod->first_dma;
488
489         if (iod->npages == 0)
490                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
491         for (i = 0; i < iod->npages; i++) {
492                 __le64 *prp_list = list[i];
493                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
494                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
495                 prp_dma = next_prp_dma;
496         }
497
498         if (iod_should_kfree(iod))
499                 kfree(iod);
500 }
501
502 static int nvme_error_status(u16 status)
503 {
504         switch (status & 0x7ff) {
505         case NVME_SC_SUCCESS:
506                 return 0;
507         case NVME_SC_CAP_EXCEEDED:
508                 return -ENOSPC;
509         default:
510                 return -EIO;
511         }
512 }
513
514 #ifdef CONFIG_BLK_DEV_INTEGRITY
515 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
516 {
517         if (be32_to_cpu(pi->ref_tag) == v)
518                 pi->ref_tag = cpu_to_be32(p);
519 }
520
521 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
522 {
523         if (be32_to_cpu(pi->ref_tag) == p)
524                 pi->ref_tag = cpu_to_be32(v);
525 }
526
527 /**
528  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
529  *
530  * The virtual start sector is the one that was originally submitted by the
531  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
532  * start sector may be different. Remap protection information to match the
533  * physical LBA on writes, and back to the original seed on reads.
534  *
535  * Type 0 and 3 do not have a ref tag, so no remapping required.
536  */
537 static void nvme_dif_remap(struct request *req,
538                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
539 {
540         struct nvme_ns *ns = req->rq_disk->private_data;
541         struct bio_integrity_payload *bip;
542         struct t10_pi_tuple *pi;
543         void *p, *pmap;
544         u32 i, nlb, ts, phys, virt;
545
546         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
547                 return;
548
549         bip = bio_integrity(req->bio);
550         if (!bip)
551                 return;
552
553         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
554
555         p = pmap;
556         virt = bip_get_seed(bip);
557         phys = nvme_block_nr(ns, blk_rq_pos(req));
558         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
559         ts = ns->disk->queue->integrity.tuple_size;
560
561         for (i = 0; i < nlb; i++, virt++, phys++) {
562                 pi = (struct t10_pi_tuple *)p;
563                 dif_swap(phys, virt, pi);
564                 p += ts;
565         }
566         kunmap_atomic(pmap);
567 }
568
569 static void nvme_init_integrity(struct nvme_ns *ns)
570 {
571         struct blk_integrity integrity;
572
573         switch (ns->pi_type) {
574         case NVME_NS_DPS_PI_TYPE3:
575                 integrity.profile = &t10_pi_type3_crc;
576                 break;
577         case NVME_NS_DPS_PI_TYPE1:
578         case NVME_NS_DPS_PI_TYPE2:
579                 integrity.profile = &t10_pi_type1_crc;
580                 break;
581         default:
582                 integrity.profile = NULL;
583                 break;
584         }
585         integrity.tuple_size = ns->ms;
586         blk_integrity_register(ns->disk, &integrity);
587         blk_queue_max_integrity_segments(ns->queue, 1);
588 }
589 #else /* CONFIG_BLK_DEV_INTEGRITY */
590 static void nvme_dif_remap(struct request *req,
591                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
592 {
593 }
594 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
595 {
596 }
597 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
598 {
599 }
600 static void nvme_init_integrity(struct nvme_ns *ns)
601 {
602 }
603 #endif
604
605 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
606                                                 struct nvme_completion *cqe)
607 {
608         struct nvme_iod *iod = ctx;
609         struct request *req = iod_get_private(iod);
610         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
611         u16 status = le16_to_cpup(&cqe->status) >> 1;
612         bool requeue = false;
613         int error = 0;
614
615         if (unlikely(status)) {
616                 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
617                     && (jiffies - req->start_time) < req->timeout) {
618                         unsigned long flags;
619
620                         requeue = true;
621                         blk_mq_requeue_request(req);
622                         spin_lock_irqsave(req->q->queue_lock, flags);
623                         if (!blk_queue_stopped(req->q))
624                                 blk_mq_kick_requeue_list(req->q);
625                         spin_unlock_irqrestore(req->q->queue_lock, flags);
626                         goto release_iod;
627                 }
628
629                 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
630                         if (cmd_rq->ctx == CMD_CTX_CANCELLED)
631                                 error = -EINTR;
632                         else
633                                 error = status;
634                 } else {
635                         error = nvme_error_status(status);
636                 }
637         }
638
639         if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
640                 u32 result = le32_to_cpup(&cqe->result);
641                 req->special = (void *)(uintptr_t)result;
642         }
643
644         if (cmd_rq->aborted)
645                 dev_warn(nvmeq->dev->dev,
646                         "completing aborted command with status:%04x\n",
647                         error);
648
649 release_iod:
650         if (iod->nents) {
651                 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
652                         rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
653                 if (blk_integrity_rq(req)) {
654                         if (!rq_data_dir(req))
655                                 nvme_dif_remap(req, nvme_dif_complete);
656                         dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
657                                 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
658                 }
659         }
660         nvme_free_iod(nvmeq->dev, iod);
661
662         if (likely(!requeue))
663                 blk_mq_complete_request(req, error);
664 }
665
666 /* length is in bytes.  gfp flags indicates whether we may sleep. */
667 static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
668                 int total_len, gfp_t gfp)
669 {
670         struct dma_pool *pool;
671         int length = total_len;
672         struct scatterlist *sg = iod->sg;
673         int dma_len = sg_dma_len(sg);
674         u64 dma_addr = sg_dma_address(sg);
675         u32 page_size = dev->page_size;
676         int offset = dma_addr & (page_size - 1);
677         __le64 *prp_list;
678         __le64 **list = iod_list(iod);
679         dma_addr_t prp_dma;
680         int nprps, i;
681
682         length -= (page_size - offset);
683         if (length <= 0)
684                 return total_len;
685
686         dma_len -= (page_size - offset);
687         if (dma_len) {
688                 dma_addr += (page_size - offset);
689         } else {
690                 sg = sg_next(sg);
691                 dma_addr = sg_dma_address(sg);
692                 dma_len = sg_dma_len(sg);
693         }
694
695         if (length <= page_size) {
696                 iod->first_dma = dma_addr;
697                 return total_len;
698         }
699
700         nprps = DIV_ROUND_UP(length, page_size);
701         if (nprps <= (256 / 8)) {
702                 pool = dev->prp_small_pool;
703                 iod->npages = 0;
704         } else {
705                 pool = dev->prp_page_pool;
706                 iod->npages = 1;
707         }
708
709         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
710         if (!prp_list) {
711                 iod->first_dma = dma_addr;
712                 iod->npages = -1;
713                 return (total_len - length) + page_size;
714         }
715         list[0] = prp_list;
716         iod->first_dma = prp_dma;
717         i = 0;
718         for (;;) {
719                 if (i == page_size >> 3) {
720                         __le64 *old_prp_list = prp_list;
721                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
722                         if (!prp_list)
723                                 return total_len - length;
724                         list[iod->npages++] = prp_list;
725                         prp_list[0] = old_prp_list[i - 1];
726                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
727                         i = 1;
728                 }
729                 prp_list[i++] = cpu_to_le64(dma_addr);
730                 dma_len -= page_size;
731                 dma_addr += page_size;
732                 length -= page_size;
733                 if (length <= 0)
734                         break;
735                 if (dma_len > 0)
736                         continue;
737                 BUG_ON(dma_len < 0);
738                 sg = sg_next(sg);
739                 dma_addr = sg_dma_address(sg);
740                 dma_len = sg_dma_len(sg);
741         }
742
743         return total_len;
744 }
745
746 static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
747                 struct nvme_iod *iod)
748 {
749         struct nvme_command cmnd;
750
751         memcpy(&cmnd, req->cmd, sizeof(cmnd));
752         cmnd.rw.command_id = req->tag;
753         if (req->nr_phys_segments) {
754                 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
755                 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
756         }
757
758         __nvme_submit_cmd(nvmeq, &cmnd);
759 }
760
761 /*
762  * We reuse the small pool to allocate the 16-byte range here as it is not
763  * worth having a special pool for these or additional cases to handle freeing
764  * the iod.
765  */
766 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
767                 struct request *req, struct nvme_iod *iod)
768 {
769         struct nvme_dsm_range *range =
770                                 (struct nvme_dsm_range *)iod_list(iod)[0];
771         struct nvme_command cmnd;
772
773         range->cattr = cpu_to_le32(0);
774         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
775         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
776
777         memset(&cmnd, 0, sizeof(cmnd));
778         cmnd.dsm.opcode = nvme_cmd_dsm;
779         cmnd.dsm.command_id = req->tag;
780         cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
781         cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
782         cmnd.dsm.nr = 0;
783         cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
784
785         __nvme_submit_cmd(nvmeq, &cmnd);
786 }
787
788 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
789                                                                 int cmdid)
790 {
791         struct nvme_command cmnd;
792
793         memset(&cmnd, 0, sizeof(cmnd));
794         cmnd.common.opcode = nvme_cmd_flush;
795         cmnd.common.command_id = cmdid;
796         cmnd.common.nsid = cpu_to_le32(ns->ns_id);
797
798         __nvme_submit_cmd(nvmeq, &cmnd);
799 }
800
801 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
802                                                         struct nvme_ns *ns)
803 {
804         struct request *req = iod_get_private(iod);
805         struct nvme_command cmnd;
806         u16 control = 0;
807         u32 dsmgmt = 0;
808
809         if (req->cmd_flags & REQ_FUA)
810                 control |= NVME_RW_FUA;
811         if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
812                 control |= NVME_RW_LR;
813
814         if (req->cmd_flags & REQ_RAHEAD)
815                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
816
817         memset(&cmnd, 0, sizeof(cmnd));
818         cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
819         cmnd.rw.command_id = req->tag;
820         cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
821         cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
822         cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
823         cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
824         cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
825
826         if (ns->ms) {
827                 switch (ns->pi_type) {
828                 case NVME_NS_DPS_PI_TYPE3:
829                         control |= NVME_RW_PRINFO_PRCHK_GUARD;
830                         break;
831                 case NVME_NS_DPS_PI_TYPE1:
832                 case NVME_NS_DPS_PI_TYPE2:
833                         control |= NVME_RW_PRINFO_PRCHK_GUARD |
834                                         NVME_RW_PRINFO_PRCHK_REF;
835                         cmnd.rw.reftag = cpu_to_le32(
836                                         nvme_block_nr(ns, blk_rq_pos(req)));
837                         break;
838                 }
839                 if (blk_integrity_rq(req))
840                         cmnd.rw.metadata =
841                                 cpu_to_le64(sg_dma_address(iod->meta_sg));
842                 else
843                         control |= NVME_RW_PRINFO_PRACT;
844         }
845
846         cmnd.rw.control = cpu_to_le16(control);
847         cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
848
849         __nvme_submit_cmd(nvmeq, &cmnd);
850
851         return 0;
852 }
853
854 /*
855  * NOTE: ns is NULL when called on the admin queue.
856  */
857 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
858                          const struct blk_mq_queue_data *bd)
859 {
860         struct nvme_ns *ns = hctx->queue->queuedata;
861         struct nvme_queue *nvmeq = hctx->driver_data;
862         struct nvme_dev *dev = nvmeq->dev;
863         struct request *req = bd->rq;
864         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
865         struct nvme_iod *iod;
866         enum dma_data_direction dma_dir;
867
868         /*
869          * If formated with metadata, require the block layer provide a buffer
870          * unless this namespace is formated such that the metadata can be
871          * stripped/generated by the controller with PRACT=1.
872          */
873         if (ns && ns->ms && !blk_integrity_rq(req)) {
874                 if (!(ns->pi_type && ns->ms == 8) &&
875                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
876                         blk_mq_complete_request(req, -EFAULT);
877                         return BLK_MQ_RQ_QUEUE_OK;
878                 }
879         }
880
881         iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
882         if (!iod)
883                 return BLK_MQ_RQ_QUEUE_BUSY;
884
885         if (req->cmd_flags & REQ_DISCARD) {
886                 void *range;
887                 /*
888                  * We reuse the small pool to allocate the 16-byte range here
889                  * as it is not worth having a special pool for these or
890                  * additional cases to handle freeing the iod.
891                  */
892                 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
893                                                 &iod->first_dma);
894                 if (!range)
895                         goto retry_cmd;
896                 iod_list(iod)[0] = (__le64 *)range;
897                 iod->npages = 0;
898         } else if (req->nr_phys_segments) {
899                 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
900
901                 sg_init_table(iod->sg, req->nr_phys_segments);
902                 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
903                 if (!iod->nents)
904                         goto error_cmd;
905
906                 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
907                         goto retry_cmd;
908
909                 if (blk_rq_bytes(req) !=
910                     nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
911                         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
912                         goto retry_cmd;
913                 }
914                 if (blk_integrity_rq(req)) {
915                         if (blk_rq_count_integrity_sg(req->q, req->bio) != 1) {
916                                 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
917                                                 dma_dir);
918                                 goto error_cmd;
919                         }
920
921                         sg_init_table(iod->meta_sg, 1);
922                         if (blk_rq_map_integrity_sg(
923                                         req->q, req->bio, iod->meta_sg) != 1) {
924                                 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
925                                                 dma_dir);
926                                 goto error_cmd;
927                         }
928
929                         if (rq_data_dir(req))
930                                 nvme_dif_remap(req, nvme_dif_prep);
931
932                         if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir)) {
933                                 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
934                                                 dma_dir);
935                                 goto error_cmd;
936                         }
937                 }
938         }
939
940         nvme_set_info(cmd, iod, req_completion);
941         spin_lock_irq(&nvmeq->q_lock);
942         if (req->cmd_type == REQ_TYPE_DRV_PRIV)
943                 nvme_submit_priv(nvmeq, req, iod);
944         else if (req->cmd_flags & REQ_DISCARD)
945                 nvme_submit_discard(nvmeq, ns, req, iod);
946         else if (req->cmd_flags & REQ_FLUSH)
947                 nvme_submit_flush(nvmeq, ns, req->tag);
948         else
949                 nvme_submit_iod(nvmeq, iod, ns);
950
951         nvme_process_cq(nvmeq);
952         spin_unlock_irq(&nvmeq->q_lock);
953         return BLK_MQ_RQ_QUEUE_OK;
954
955  error_cmd:
956         nvme_free_iod(dev, iod);
957         return BLK_MQ_RQ_QUEUE_ERROR;
958  retry_cmd:
959         nvme_free_iod(dev, iod);
960         return BLK_MQ_RQ_QUEUE_BUSY;
961 }
962
963 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
964 {
965         u16 head, phase;
966
967         head = nvmeq->cq_head;
968         phase = nvmeq->cq_phase;
969
970         for (;;) {
971                 void *ctx;
972                 nvme_completion_fn fn;
973                 struct nvme_completion cqe = nvmeq->cqes[head];
974                 if ((le16_to_cpu(cqe.status) & 1) != phase)
975                         break;
976                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
977                 if (++head == nvmeq->q_depth) {
978                         head = 0;
979                         phase = !phase;
980                 }
981                 if (tag && *tag == cqe.command_id)
982                         *tag = -1;
983                 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
984                 fn(nvmeq, ctx, &cqe);
985         }
986
987         /* If the controller ignores the cq head doorbell and continuously
988          * writes to the queue, it is theoretically possible to wrap around
989          * the queue twice and mistakenly return IRQ_NONE.  Linux only
990          * requires that 0.1% of your interrupts are handled, so this isn't
991          * a big problem.
992          */
993         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
994                 return;
995
996         if (likely(nvmeq->cq_vector >= 0))
997                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
998         nvmeq->cq_head = head;
999         nvmeq->cq_phase = phase;
1000
1001         nvmeq->cqe_seen = 1;
1002 }
1003
1004 static void nvme_process_cq(struct nvme_queue *nvmeq)
1005 {
1006         __nvme_process_cq(nvmeq, NULL);
1007 }
1008
1009 static irqreturn_t nvme_irq(int irq, void *data)
1010 {
1011         irqreturn_t result;
1012         struct nvme_queue *nvmeq = data;
1013         spin_lock(&nvmeq->q_lock);
1014         nvme_process_cq(nvmeq);
1015         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1016         nvmeq->cqe_seen = 0;
1017         spin_unlock(&nvmeq->q_lock);
1018         return result;
1019 }
1020
1021 static irqreturn_t nvme_irq_check(int irq, void *data)
1022 {
1023         struct nvme_queue *nvmeq = data;
1024         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
1025         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1026                 return IRQ_NONE;
1027         return IRQ_WAKE_THREAD;
1028 }
1029
1030 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1031 {
1032         struct nvme_queue *nvmeq = hctx->driver_data;
1033
1034         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
1035             nvmeq->cq_phase) {
1036                 spin_lock_irq(&nvmeq->q_lock);
1037                 __nvme_process_cq(nvmeq, &tag);
1038                 spin_unlock_irq(&nvmeq->q_lock);
1039
1040                 if (tag == -1)
1041                         return 1;
1042         }
1043
1044         return 0;
1045 }
1046
1047 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1048 {
1049         struct nvme_queue *nvmeq = dev->queues[0];
1050         struct nvme_command c;
1051         struct nvme_cmd_info *cmd_info;
1052         struct request *req;
1053
1054         req = blk_mq_alloc_request(dev->admin_q, WRITE,
1055                         BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED);
1056         if (IS_ERR(req))
1057                 return PTR_ERR(req);
1058
1059         req->cmd_flags |= REQ_NO_TIMEOUT;
1060         cmd_info = blk_mq_rq_to_pdu(req);
1061         nvme_set_info(cmd_info, NULL, async_req_completion);
1062
1063         memset(&c, 0, sizeof(c));
1064         c.common.opcode = nvme_admin_async_event;
1065         c.common.command_id = req->tag;
1066
1067         blk_mq_free_request(req);
1068         __nvme_submit_cmd(nvmeq, &c);
1069         return 0;
1070 }
1071
1072 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1073                         struct nvme_command *cmd,
1074                         struct async_cmd_info *cmdinfo, unsigned timeout)
1075 {
1076         struct nvme_queue *nvmeq = dev->queues[0];
1077         struct request *req;
1078         struct nvme_cmd_info *cmd_rq;
1079
1080         req = blk_mq_alloc_request(dev->admin_q, WRITE, 0);
1081         if (IS_ERR(req))
1082                 return PTR_ERR(req);
1083
1084         req->timeout = timeout;
1085         cmd_rq = blk_mq_rq_to_pdu(req);
1086         cmdinfo->req = req;
1087         nvme_set_info(cmd_rq, cmdinfo, async_completion);
1088         cmdinfo->status = -EINTR;
1089
1090         cmd->common.command_id = req->tag;
1091
1092         nvme_submit_cmd(nvmeq, cmd);
1093         return 0;
1094 }
1095
1096 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1097 {
1098         struct nvme_command c;
1099
1100         memset(&c, 0, sizeof(c));
1101         c.delete_queue.opcode = opcode;
1102         c.delete_queue.qid = cpu_to_le16(id);
1103
1104         return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1105 }
1106
1107 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1108                                                 struct nvme_queue *nvmeq)
1109 {
1110         struct nvme_command c;
1111         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1112
1113         /*
1114          * Note: we (ab)use the fact the the prp fields survive if no data
1115          * is attached to the request.
1116          */
1117         memset(&c, 0, sizeof(c));
1118         c.create_cq.opcode = nvme_admin_create_cq;
1119         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1120         c.create_cq.cqid = cpu_to_le16(qid);
1121         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1122         c.create_cq.cq_flags = cpu_to_le16(flags);
1123         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1124
1125         return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1126 }
1127
1128 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1129                                                 struct nvme_queue *nvmeq)
1130 {
1131         struct nvme_command c;
1132         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1133
1134         /*
1135          * Note: we (ab)use the fact the the prp fields survive if no data
1136          * is attached to the request.
1137          */
1138         memset(&c, 0, sizeof(c));
1139         c.create_sq.opcode = nvme_admin_create_sq;
1140         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1141         c.create_sq.sqid = cpu_to_le16(qid);
1142         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1143         c.create_sq.sq_flags = cpu_to_le16(flags);
1144         c.create_sq.cqid = cpu_to_le16(qid);
1145
1146         return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1147 }
1148
1149 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1150 {
1151         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1152 }
1153
1154 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1155 {
1156         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1157 }
1158
1159 /**
1160  * nvme_abort_req - Attempt aborting a request
1161  *
1162  * Schedule controller reset if the command was already aborted once before and
1163  * still hasn't been returned to the driver, or if this is the admin queue.
1164  */
1165 static void nvme_abort_req(struct request *req)
1166 {
1167         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1168         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1169         struct nvme_dev *dev = nvmeq->dev;
1170         struct request *abort_req;
1171         struct nvme_cmd_info *abort_cmd;
1172         struct nvme_command cmd;
1173
1174         if (!nvmeq->qid || cmd_rq->aborted) {
1175                 spin_lock(&dev_list_lock);
1176                 if (!__nvme_reset(dev)) {
1177                         dev_warn(dev->dev,
1178                                  "I/O %d QID %d timeout, reset controller\n",
1179                                  req->tag, nvmeq->qid);
1180                 }
1181                 spin_unlock(&dev_list_lock);
1182                 return;
1183         }
1184
1185         if (!dev->abort_limit)
1186                 return;
1187
1188         abort_req = blk_mq_alloc_request(dev->admin_q, WRITE,
1189                         BLK_MQ_REQ_NOWAIT);
1190         if (IS_ERR(abort_req))
1191                 return;
1192
1193         abort_cmd = blk_mq_rq_to_pdu(abort_req);
1194         nvme_set_info(abort_cmd, abort_req, abort_completion);
1195
1196         memset(&cmd, 0, sizeof(cmd));
1197         cmd.abort.opcode = nvme_admin_abort_cmd;
1198         cmd.abort.cid = req->tag;
1199         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1200         cmd.abort.command_id = abort_req->tag;
1201
1202         --dev->abort_limit;
1203         cmd_rq->aborted = 1;
1204
1205         dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1206                                                         nvmeq->qid);
1207         nvme_submit_cmd(dev->queues[0], &cmd);
1208 }
1209
1210 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1211 {
1212         struct nvme_queue *nvmeq = data;
1213         void *ctx;
1214         nvme_completion_fn fn;
1215         struct nvme_cmd_info *cmd;
1216         struct nvme_completion cqe;
1217
1218         if (!blk_mq_request_started(req))
1219                 return;
1220
1221         cmd = blk_mq_rq_to_pdu(req);
1222
1223         if (cmd->ctx == CMD_CTX_CANCELLED)
1224                 return;
1225
1226         if (blk_queue_dying(req->q))
1227                 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1228         else
1229                 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1230
1231
1232         dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1233                                                 req->tag, nvmeq->qid);
1234         ctx = cancel_cmd_info(cmd, &fn);
1235         fn(nvmeq, ctx, &cqe);
1236 }
1237
1238 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1239 {
1240         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1241         struct nvme_queue *nvmeq = cmd->nvmeq;
1242
1243         dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1244                                                         nvmeq->qid);
1245         spin_lock_irq(&nvmeq->q_lock);
1246         nvme_abort_req(req);
1247         spin_unlock_irq(&nvmeq->q_lock);
1248
1249         /*
1250          * The aborted req will be completed on receiving the abort req.
1251          * We enable the timer again. If hit twice, it'll cause a device reset,
1252          * as the device then is in a faulty state.
1253          */
1254         return BLK_EH_RESET_TIMER;
1255 }
1256
1257 static void nvme_free_queue(struct nvme_queue *nvmeq)
1258 {
1259         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1260                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1261         if (nvmeq->sq_cmds)
1262                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1263                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1264         kfree(nvmeq);
1265 }
1266
1267 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1268 {
1269         int i;
1270
1271         for (i = dev->queue_count - 1; i >= lowest; i--) {
1272                 struct nvme_queue *nvmeq = dev->queues[i];
1273                 dev->queue_count--;
1274                 dev->queues[i] = NULL;
1275                 nvme_free_queue(nvmeq);
1276         }
1277 }
1278
1279 /**
1280  * nvme_suspend_queue - put queue into suspended state
1281  * @nvmeq - queue to suspend
1282  */
1283 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1284 {
1285         int vector;
1286
1287         spin_lock_irq(&nvmeq->q_lock);
1288         if (nvmeq->cq_vector == -1) {
1289                 spin_unlock_irq(&nvmeq->q_lock);
1290                 return 1;
1291         }
1292         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1293         nvmeq->dev->online_queues--;
1294         nvmeq->cq_vector = -1;
1295         spin_unlock_irq(&nvmeq->q_lock);
1296
1297         if (!nvmeq->qid && nvmeq->dev->admin_q)
1298                 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1299
1300         irq_set_affinity_hint(vector, NULL);
1301         free_irq(vector, nvmeq);
1302
1303         return 0;
1304 }
1305
1306 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1307 {
1308         spin_lock_irq(&nvmeq->q_lock);
1309         if (nvmeq->tags && *nvmeq->tags)
1310                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1311         spin_unlock_irq(&nvmeq->q_lock);
1312 }
1313
1314 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1315 {
1316         struct nvme_queue *nvmeq = dev->queues[qid];
1317
1318         if (!nvmeq)
1319                 return;
1320         if (nvme_suspend_queue(nvmeq))
1321                 return;
1322
1323         /* Don't tell the adapter to delete the admin queue.
1324          * Don't tell a removed adapter to delete IO queues. */
1325         if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) {
1326                 adapter_delete_sq(dev, qid);
1327                 adapter_delete_cq(dev, qid);
1328         }
1329
1330         spin_lock_irq(&nvmeq->q_lock);
1331         nvme_process_cq(nvmeq);
1332         spin_unlock_irq(&nvmeq->q_lock);
1333 }
1334
1335 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1336                                 int entry_size)
1337 {
1338         int q_depth = dev->q_depth;
1339         unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1340
1341         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1342                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1343                 mem_per_q = round_down(mem_per_q, dev->page_size);
1344                 q_depth = div_u64(mem_per_q, entry_size);
1345
1346                 /*
1347                  * Ensure the reduced q_depth is above some threshold where it
1348                  * would be better to map queues in system memory with the
1349                  * original depth
1350                  */
1351                 if (q_depth < 64)
1352                         return -ENOMEM;
1353         }
1354
1355         return q_depth;
1356 }
1357
1358 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1359                                 int qid, int depth)
1360 {
1361         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1362                 unsigned offset = (qid - 1) *
1363                                         roundup(SQ_SIZE(depth), dev->page_size);
1364                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1365                 nvmeq->sq_cmds_io = dev->cmb + offset;
1366         } else {
1367                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1368                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1369                 if (!nvmeq->sq_cmds)
1370                         return -ENOMEM;
1371         }
1372
1373         return 0;
1374 }
1375
1376 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1377                                                         int depth)
1378 {
1379         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1380         if (!nvmeq)
1381                 return NULL;
1382
1383         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1384                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1385         if (!nvmeq->cqes)
1386                 goto free_nvmeq;
1387
1388         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1389                 goto free_cqdma;
1390
1391         nvmeq->q_dmadev = dev->dev;
1392         nvmeq->dev = dev;
1393         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1394                         dev->instance, qid);
1395         spin_lock_init(&nvmeq->q_lock);
1396         nvmeq->cq_head = 0;
1397         nvmeq->cq_phase = 1;
1398         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1399         nvmeq->q_depth = depth;
1400         nvmeq->qid = qid;
1401         nvmeq->cq_vector = -1;
1402         dev->queues[qid] = nvmeq;
1403
1404         /* make sure queue descriptor is set before queue count, for kthread */
1405         mb();
1406         dev->queue_count++;
1407
1408         return nvmeq;
1409
1410  free_cqdma:
1411         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1412                                                         nvmeq->cq_dma_addr);
1413  free_nvmeq:
1414         kfree(nvmeq);
1415         return NULL;
1416 }
1417
1418 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1419                                                         const char *name)
1420 {
1421         if (use_threaded_interrupts)
1422                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1423                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1424                                         name, nvmeq);
1425         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1426                                 IRQF_SHARED, name, nvmeq);
1427 }
1428
1429 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1430 {
1431         struct nvme_dev *dev = nvmeq->dev;
1432
1433         spin_lock_irq(&nvmeq->q_lock);
1434         nvmeq->sq_tail = 0;
1435         nvmeq->cq_head = 0;
1436         nvmeq->cq_phase = 1;
1437         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1438         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1439         dev->online_queues++;
1440         spin_unlock_irq(&nvmeq->q_lock);
1441 }
1442
1443 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1444 {
1445         struct nvme_dev *dev = nvmeq->dev;
1446         int result;
1447
1448         nvmeq->cq_vector = qid - 1;
1449         result = adapter_alloc_cq(dev, qid, nvmeq);
1450         if (result < 0)
1451                 return result;
1452
1453         result = adapter_alloc_sq(dev, qid, nvmeq);
1454         if (result < 0)
1455                 goto release_cq;
1456
1457         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1458         if (result < 0)
1459                 goto release_sq;
1460
1461         nvme_init_queue(nvmeq, qid);
1462         return result;
1463
1464  release_sq:
1465         adapter_delete_sq(dev, qid);
1466  release_cq:
1467         adapter_delete_cq(dev, qid);
1468         return result;
1469 }
1470
1471 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1472 {
1473         unsigned long timeout;
1474         u32 bit = enabled ? NVME_CSTS_RDY : 0;
1475
1476         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1477
1478         while ((readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_RDY) != bit) {
1479                 msleep(100);
1480                 if (fatal_signal_pending(current))
1481                         return -EINTR;
1482                 if (time_after(jiffies, timeout)) {
1483                         dev_err(dev->dev,
1484                                 "Device not ready; aborting %s\n", enabled ?
1485                                                 "initialisation" : "reset");
1486                         return -ENODEV;
1487                 }
1488         }
1489
1490         return 0;
1491 }
1492
1493 /*
1494  * If the device has been passed off to us in an enabled state, just clear
1495  * the enabled bit.  The spec says we should set the 'shutdown notification
1496  * bits', but doing so may cause the device to complete commands to the
1497  * admin queue ... and we don't know what memory that might be pointing at!
1498  */
1499 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1500 {
1501         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1502         dev->ctrl_config &= ~NVME_CC_ENABLE;
1503         writel(dev->ctrl_config, dev->bar + NVME_REG_CC);
1504
1505         return nvme_wait_ready(dev, cap, false);
1506 }
1507
1508 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1509 {
1510         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1511         dev->ctrl_config |= NVME_CC_ENABLE;
1512         writel(dev->ctrl_config, dev->bar + NVME_REG_CC);
1513
1514         return nvme_wait_ready(dev, cap, true);
1515 }
1516
1517 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1518 {
1519         unsigned long timeout;
1520
1521         dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1522         dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1523
1524         writel(dev->ctrl_config, dev->bar + NVME_REG_CC);
1525
1526         timeout = SHUTDOWN_TIMEOUT + jiffies;
1527         while ((readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_SHST_MASK) !=
1528                                                         NVME_CSTS_SHST_CMPLT) {
1529                 msleep(100);
1530                 if (fatal_signal_pending(current))
1531                         return -EINTR;
1532                 if (time_after(jiffies, timeout)) {
1533                         dev_err(dev->dev,
1534                                 "Device shutdown incomplete; abort shutdown\n");
1535                         return -ENODEV;
1536                 }
1537         }
1538
1539         return 0;
1540 }
1541
1542 static struct blk_mq_ops nvme_mq_admin_ops = {
1543         .queue_rq       = nvme_queue_rq,
1544         .map_queue      = blk_mq_map_queue,
1545         .init_hctx      = nvme_admin_init_hctx,
1546         .exit_hctx      = nvme_admin_exit_hctx,
1547         .init_request   = nvme_admin_init_request,
1548         .timeout        = nvme_timeout,
1549 };
1550
1551 static struct blk_mq_ops nvme_mq_ops = {
1552         .queue_rq       = nvme_queue_rq,
1553         .map_queue      = blk_mq_map_queue,
1554         .init_hctx      = nvme_init_hctx,
1555         .init_request   = nvme_init_request,
1556         .timeout        = nvme_timeout,
1557         .poll           = nvme_poll,
1558 };
1559
1560 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1561 {
1562         if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1563                 blk_cleanup_queue(dev->admin_q);
1564                 blk_mq_free_tag_set(&dev->admin_tagset);
1565         }
1566 }
1567
1568 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1569 {
1570         if (!dev->admin_q) {
1571                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1572                 dev->admin_tagset.nr_hw_queues = 1;
1573                 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1574                 dev->admin_tagset.reserved_tags = 1;
1575                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1576                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1577                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1578                 dev->admin_tagset.driver_data = dev;
1579
1580                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1581                         return -ENOMEM;
1582
1583                 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1584                 if (IS_ERR(dev->admin_q)) {
1585                         blk_mq_free_tag_set(&dev->admin_tagset);
1586                         return -ENOMEM;
1587                 }
1588                 if (!blk_get_queue(dev->admin_q)) {
1589                         nvme_dev_remove_admin(dev);
1590                         dev->admin_q = NULL;
1591                         return -ENODEV;
1592                 }
1593         } else
1594                 blk_mq_unfreeze_queue(dev->admin_q);
1595
1596         return 0;
1597 }
1598
1599 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1600 {
1601         int result;
1602         u32 aqa;
1603         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1604         struct nvme_queue *nvmeq;
1605         /*
1606          * default to a 4K page size, with the intention to update this
1607          * path in the future to accomodate architectures with differing
1608          * kernel and IO page sizes.
1609          */
1610         unsigned page_shift = 12;
1611         unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1612
1613         if (page_shift < dev_page_min) {
1614                 dev_err(dev->dev,
1615                                 "Minimum device page size (%u) too large for "
1616                                 "host (%u)\n", 1 << dev_page_min,
1617                                 1 << page_shift);
1618                 return -ENODEV;
1619         }
1620
1621         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1622                                                 NVME_CAP_NSSRC(cap) : 0;
1623
1624         if (dev->subsystem &&
1625             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1626                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1627
1628         result = nvme_disable_ctrl(dev, cap);
1629         if (result < 0)
1630                 return result;
1631
1632         nvmeq = dev->queues[0];
1633         if (!nvmeq) {
1634                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1635                 if (!nvmeq)
1636                         return -ENOMEM;
1637         }
1638
1639         aqa = nvmeq->q_depth - 1;
1640         aqa |= aqa << 16;
1641
1642         dev->page_size = 1 << page_shift;
1643
1644         dev->ctrl_config = NVME_CC_CSS_NVM;
1645         dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1646         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1647         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1648
1649         writel(aqa, dev->bar + NVME_REG_AQA);
1650         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1651         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1652
1653         result = nvme_enable_ctrl(dev, cap);
1654         if (result)
1655                 goto free_nvmeq;
1656
1657         nvmeq->cq_vector = 0;
1658         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1659         if (result) {
1660                 nvmeq->cq_vector = -1;
1661                 goto free_nvmeq;
1662         }
1663
1664         return result;
1665
1666  free_nvmeq:
1667         nvme_free_queues(dev, 0);
1668         return result;
1669 }
1670
1671 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1672 {
1673         struct nvme_dev *dev = ns->dev;
1674         struct nvme_user_io io;
1675         struct nvme_command c;
1676         unsigned length, meta_len;
1677         int status, write;
1678         dma_addr_t meta_dma = 0;
1679         void *meta = NULL;
1680         void __user *metadata;
1681
1682         if (copy_from_user(&io, uio, sizeof(io)))
1683                 return -EFAULT;
1684
1685         switch (io.opcode) {
1686         case nvme_cmd_write:
1687         case nvme_cmd_read:
1688         case nvme_cmd_compare:
1689                 break;
1690         default:
1691                 return -EINVAL;
1692         }
1693
1694         length = (io.nblocks + 1) << ns->lba_shift;
1695         meta_len = (io.nblocks + 1) * ns->ms;
1696         metadata = (void __user *)(uintptr_t)io.metadata;
1697         write = io.opcode & 1;
1698
1699         if (ns->ext) {
1700                 length += meta_len;
1701                 meta_len = 0;
1702         }
1703         if (meta_len) {
1704                 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1705                         return -EINVAL;
1706
1707                 meta = dma_alloc_coherent(dev->dev, meta_len,
1708                                                 &meta_dma, GFP_KERNEL);
1709
1710                 if (!meta) {
1711                         status = -ENOMEM;
1712                         goto unmap;
1713                 }
1714                 if (write) {
1715                         if (copy_from_user(meta, metadata, meta_len)) {
1716                                 status = -EFAULT;
1717                                 goto unmap;
1718                         }
1719                 }
1720         }
1721
1722         memset(&c, 0, sizeof(c));
1723         c.rw.opcode = io.opcode;
1724         c.rw.flags = io.flags;
1725         c.rw.nsid = cpu_to_le32(ns->ns_id);
1726         c.rw.slba = cpu_to_le64(io.slba);
1727         c.rw.length = cpu_to_le16(io.nblocks);
1728         c.rw.control = cpu_to_le16(io.control);
1729         c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1730         c.rw.reftag = cpu_to_le32(io.reftag);
1731         c.rw.apptag = cpu_to_le16(io.apptag);
1732         c.rw.appmask = cpu_to_le16(io.appmask);
1733         c.rw.metadata = cpu_to_le64(meta_dma);
1734
1735         status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1736                         (void __user *)(uintptr_t)io.addr, length, NULL, 0);
1737  unmap:
1738         if (meta) {
1739                 if (status == NVME_SC_SUCCESS && !write) {
1740                         if (copy_to_user(metadata, meta, meta_len))
1741                                 status = -EFAULT;
1742                 }
1743                 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
1744         }
1745         return status;
1746 }
1747
1748 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1749                         struct nvme_passthru_cmd __user *ucmd)
1750 {
1751         struct nvme_passthru_cmd cmd;
1752         struct nvme_command c;
1753         unsigned timeout = 0;
1754         int status;
1755
1756         if (!capable(CAP_SYS_ADMIN))
1757                 return -EACCES;
1758         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1759                 return -EFAULT;
1760
1761         memset(&c, 0, sizeof(c));
1762         c.common.opcode = cmd.opcode;
1763         c.common.flags = cmd.flags;
1764         c.common.nsid = cpu_to_le32(cmd.nsid);
1765         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1766         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1767         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1768         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1769         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1770         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1771         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1772         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1773
1774         if (cmd.timeout_ms)
1775                 timeout = msecs_to_jiffies(cmd.timeout_ms);
1776
1777         status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
1778                         NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1779                         &cmd.result, timeout);
1780         if (status >= 0) {
1781                 if (put_user(cmd.result, &ucmd->result))
1782                         return -EFAULT;
1783         }
1784
1785         return status;
1786 }
1787
1788 static int nvme_subsys_reset(struct nvme_dev *dev)
1789 {
1790         if (!dev->subsystem)
1791                 return -ENOTTY;
1792
1793         writel(0x4E564D65, dev->bar + NVME_REG_NSSR); /* "NVMe" */
1794         return 0;
1795 }
1796
1797 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1798                                                         unsigned long arg)
1799 {
1800         struct nvme_ns *ns = bdev->bd_disk->private_data;
1801
1802         switch (cmd) {
1803         case NVME_IOCTL_ID:
1804                 force_successful_syscall_return();
1805                 return ns->ns_id;
1806         case NVME_IOCTL_ADMIN_CMD:
1807                 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1808         case NVME_IOCTL_IO_CMD:
1809                 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1810         case NVME_IOCTL_SUBMIT_IO:
1811                 return nvme_submit_io(ns, (void __user *)arg);
1812         case SG_GET_VERSION_NUM:
1813                 return nvme_sg_get_version_num((void __user *)arg);
1814         case SG_IO:
1815                 return nvme_sg_io(ns, (void __user *)arg);
1816         default:
1817                 return -ENOTTY;
1818         }
1819 }
1820
1821 #ifdef CONFIG_COMPAT
1822 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1823                                         unsigned int cmd, unsigned long arg)
1824 {
1825         switch (cmd) {
1826         case SG_IO:
1827                 return -ENOIOCTLCMD;
1828         }
1829         return nvme_ioctl(bdev, mode, cmd, arg);
1830 }
1831 #else
1832 #define nvme_compat_ioctl       NULL
1833 #endif
1834
1835 static void nvme_free_dev(struct kref *kref);
1836 static void nvme_free_ns(struct kref *kref)
1837 {
1838         struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1839
1840         if (ns->type == NVME_NS_LIGHTNVM)
1841                 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
1842
1843         spin_lock(&dev_list_lock);
1844         ns->disk->private_data = NULL;
1845         spin_unlock(&dev_list_lock);
1846
1847         kref_put(&ns->dev->kref, nvme_free_dev);
1848         put_disk(ns->disk);
1849         kfree(ns);
1850 }
1851
1852 static int nvme_open(struct block_device *bdev, fmode_t mode)
1853 {
1854         int ret = 0;
1855         struct nvme_ns *ns;
1856
1857         spin_lock(&dev_list_lock);
1858         ns = bdev->bd_disk->private_data;
1859         if (!ns)
1860                 ret = -ENXIO;
1861         else if (!kref_get_unless_zero(&ns->kref))
1862                 ret = -ENXIO;
1863         spin_unlock(&dev_list_lock);
1864
1865         return ret;
1866 }
1867
1868 static void nvme_release(struct gendisk *disk, fmode_t mode)
1869 {
1870         struct nvme_ns *ns = disk->private_data;
1871         kref_put(&ns->kref, nvme_free_ns);
1872 }
1873
1874 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1875 {
1876         /* some standard values */
1877         geo->heads = 1 << 6;
1878         geo->sectors = 1 << 5;
1879         geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1880         return 0;
1881 }
1882
1883 static void nvme_config_discard(struct nvme_ns *ns)
1884 {
1885         u32 logical_block_size = queue_logical_block_size(ns->queue);
1886         ns->queue->limits.discard_zeroes_data = 0;
1887         ns->queue->limits.discard_alignment = logical_block_size;
1888         ns->queue->limits.discard_granularity = logical_block_size;
1889         blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
1890         queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1891 }
1892
1893 static int nvme_revalidate_disk(struct gendisk *disk)
1894 {
1895         struct nvme_ns *ns = disk->private_data;
1896         struct nvme_dev *dev = ns->dev;
1897         struct nvme_id_ns *id;
1898         u8 lbaf, pi_type;
1899         u16 old_ms;
1900         unsigned short bs;
1901
1902         if (nvme_identify_ns(dev, ns->ns_id, &id)) {
1903                 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
1904                                                 dev->instance, ns->ns_id);
1905                 return -ENODEV;
1906         }
1907         if (id->ncap == 0) {
1908                 kfree(id);
1909                 return -ENODEV;
1910         }
1911
1912         if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
1913                 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
1914                         dev_warn(dev->dev,
1915                                 "%s: LightNVM init failure\n", __func__);
1916                         kfree(id);
1917                         return -ENODEV;
1918                 }
1919                 ns->type = NVME_NS_LIGHTNVM;
1920         }
1921
1922         old_ms = ns->ms;
1923         lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1924         ns->lba_shift = id->lbaf[lbaf].ds;
1925         ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
1926         ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
1927
1928         /*
1929          * If identify namespace failed, use default 512 byte block size so
1930          * block layer can use before failing read/write for 0 capacity.
1931          */
1932         if (ns->lba_shift == 0)
1933                 ns->lba_shift = 9;
1934         bs = 1 << ns->lba_shift;
1935
1936         /* XXX: PI implementation requires metadata equal t10 pi tuple size */
1937         pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
1938                                         id->dps & NVME_NS_DPS_PI_MASK : 0;
1939
1940         blk_mq_freeze_queue(disk->queue);
1941         if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
1942                                 ns->ms != old_ms ||
1943                                 bs != queue_logical_block_size(disk->queue) ||
1944                                 (ns->ms && ns->ext)))
1945                 blk_integrity_unregister(disk);
1946
1947         ns->pi_type = pi_type;
1948         blk_queue_logical_block_size(ns->queue, bs);
1949
1950         if (ns->ms && !ns->ext)
1951                 nvme_init_integrity(ns);
1952
1953         if ((ns->ms && !(ns->ms == 8 && ns->pi_type) &&
1954                                                 !blk_get_integrity(disk)) ||
1955                                                 ns->type == NVME_NS_LIGHTNVM)
1956                 set_capacity(disk, 0);
1957         else
1958                 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1959
1960         if (dev->oncs & NVME_CTRL_ONCS_DSM)
1961                 nvme_config_discard(ns);
1962         blk_mq_unfreeze_queue(disk->queue);
1963
1964         kfree(id);
1965         return 0;
1966 }
1967
1968 static char nvme_pr_type(enum pr_type type)
1969 {
1970         switch (type) {
1971         case PR_WRITE_EXCLUSIVE:
1972                 return 1;
1973         case PR_EXCLUSIVE_ACCESS:
1974                 return 2;
1975         case PR_WRITE_EXCLUSIVE_REG_ONLY:
1976                 return 3;
1977         case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1978                 return 4;
1979         case PR_WRITE_EXCLUSIVE_ALL_REGS:
1980                 return 5;
1981         case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1982                 return 6;
1983         default:
1984                 return 0;
1985         }
1986 };
1987
1988 static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1989                                 u64 key, u64 sa_key, u8 op)
1990 {
1991         struct nvme_ns *ns = bdev->bd_disk->private_data;
1992         struct nvme_command c;
1993         u8 data[16] = { 0, };
1994
1995         put_unaligned_le64(key, &data[0]);
1996         put_unaligned_le64(sa_key, &data[8]);
1997
1998         memset(&c, 0, sizeof(c));
1999         c.common.opcode = op;
2000         c.common.nsid = cpu_to_le32(ns->ns_id);
2001         c.common.cdw10[0] = cpu_to_le32(cdw10);
2002
2003         return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2004 }
2005
2006 static int nvme_pr_register(struct block_device *bdev, u64 old,
2007                 u64 new, unsigned flags)
2008 {
2009         u32 cdw10;
2010
2011         if (flags & ~PR_FL_IGNORE_KEY)
2012                 return -EOPNOTSUPP;
2013
2014         cdw10 = old ? 2 : 0;
2015         cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2016         cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2017         return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2018 }
2019
2020 static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2021                 enum pr_type type, unsigned flags)
2022 {
2023         u32 cdw10;
2024
2025         if (flags & ~PR_FL_IGNORE_KEY)
2026                 return -EOPNOTSUPP;
2027
2028         cdw10 = nvme_pr_type(type) << 8;
2029         cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2030         return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2031 }
2032
2033 static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2034                 enum pr_type type, bool abort)
2035 {
2036         u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
2037         return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2038 }
2039
2040 static int nvme_pr_clear(struct block_device *bdev, u64 key)
2041 {
2042         u32 cdw10 = 1 | (key ? 1 << 3 : 0);
2043         return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2044 }
2045
2046 static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2047 {
2048         u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
2049         return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2050 }
2051
2052 static const struct pr_ops nvme_pr_ops = {
2053         .pr_register    = nvme_pr_register,
2054         .pr_reserve     = nvme_pr_reserve,
2055         .pr_release     = nvme_pr_release,
2056         .pr_preempt     = nvme_pr_preempt,
2057         .pr_clear       = nvme_pr_clear,
2058 };
2059
2060 static const struct block_device_operations nvme_fops = {
2061         .owner          = THIS_MODULE,
2062         .ioctl          = nvme_ioctl,
2063         .compat_ioctl   = nvme_compat_ioctl,
2064         .open           = nvme_open,
2065         .release        = nvme_release,
2066         .getgeo         = nvme_getgeo,
2067         .revalidate_disk= nvme_revalidate_disk,
2068         .pr_ops         = &nvme_pr_ops,
2069 };
2070
2071 static int nvme_kthread(void *data)
2072 {
2073         struct nvme_dev *dev, *next;
2074
2075         while (!kthread_should_stop()) {
2076                 set_current_state(TASK_INTERRUPTIBLE);
2077                 spin_lock(&dev_list_lock);
2078                 list_for_each_entry_safe(dev, next, &dev_list, node) {
2079                         int i;
2080                         u32 csts = readl(dev->bar + NVME_REG_CSTS);
2081
2082                         if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2083                                                         csts & NVME_CSTS_CFS) {
2084                                 if (!__nvme_reset(dev)) {
2085                                         dev_warn(dev->dev,
2086                                                 "Failed status: %x, reset controller\n",
2087                                                 readl(dev->bar + NVME_REG_CSTS));
2088                                 }
2089                                 continue;
2090                         }
2091                         for (i = 0; i < dev->queue_count; i++) {
2092                                 struct nvme_queue *nvmeq = dev->queues[i];
2093                                 if (!nvmeq)
2094                                         continue;
2095                                 spin_lock_irq(&nvmeq->q_lock);
2096                                 nvme_process_cq(nvmeq);
2097
2098                                 while ((i == 0) && (dev->event_limit > 0)) {
2099                                         if (nvme_submit_async_admin_req(dev))
2100                                                 break;
2101                                         dev->event_limit--;
2102                                 }
2103                                 spin_unlock_irq(&nvmeq->q_lock);
2104                         }
2105                 }
2106                 spin_unlock(&dev_list_lock);
2107                 schedule_timeout(round_jiffies_relative(HZ));
2108         }
2109         return 0;
2110 }
2111
2112 static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
2113 {
2114         struct nvme_ns *ns;
2115         struct gendisk *disk;
2116         int node = dev_to_node(dev->dev);
2117
2118         ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2119         if (!ns)
2120                 return;
2121
2122         ns->queue = blk_mq_init_queue(&dev->tagset);
2123         if (IS_ERR(ns->queue))
2124                 goto out_free_ns;
2125         queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2126         queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2127         ns->dev = dev;
2128         ns->queue->queuedata = ns;
2129
2130         disk = alloc_disk_node(0, node);
2131         if (!disk)
2132                 goto out_free_queue;
2133
2134         kref_init(&ns->kref);
2135         ns->ns_id = nsid;
2136         ns->disk = disk;
2137         ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2138         list_add_tail(&ns->list, &dev->namespaces);
2139
2140         blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
2141         if (dev->max_hw_sectors) {
2142                 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
2143                 blk_queue_max_segments(ns->queue,
2144                         (dev->max_hw_sectors / (dev->page_size >> 9)) + 1);
2145         }
2146         if (dev->stripe_size)
2147                 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
2148         if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2149                 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
2150         blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
2151
2152         disk->major = nvme_major;
2153         disk->first_minor = 0;
2154         disk->fops = &nvme_fops;
2155         disk->private_data = ns;
2156         disk->queue = ns->queue;
2157         disk->driverfs_dev = dev->device;
2158         disk->flags = GENHD_FL_EXT_DEVT;
2159         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
2160
2161         /*
2162          * Initialize capacity to 0 until we establish the namespace format and
2163          * setup integrity extentions if necessary. The revalidate_disk after
2164          * add_disk allows the driver to register with integrity if the format
2165          * requires it.
2166          */
2167         set_capacity(disk, 0);
2168         if (nvme_revalidate_disk(ns->disk))
2169                 goto out_free_disk;
2170
2171         kref_get(&dev->kref);
2172         if (ns->type != NVME_NS_LIGHTNVM) {
2173                 add_disk(ns->disk);
2174                 if (ns->ms) {
2175                         struct block_device *bd = bdget_disk(ns->disk, 0);
2176                         if (!bd)
2177                                 return;
2178                         if (blkdev_get(bd, FMODE_READ, NULL)) {
2179                                 bdput(bd);
2180                                 return;
2181                         }
2182                         blkdev_reread_part(bd);
2183                         blkdev_put(bd, FMODE_READ);
2184                 }
2185         }
2186         return;
2187  out_free_disk:
2188         kfree(disk);
2189         list_del(&ns->list);
2190  out_free_queue:
2191         blk_cleanup_queue(ns->queue);
2192  out_free_ns:
2193         kfree(ns);
2194 }
2195
2196 /*
2197  * Create I/O queues.  Failing to create an I/O queue is not an issue,
2198  * we can continue with less than the desired amount of queues, and
2199  * even a controller without I/O queues an still be used to issue
2200  * admin commands.  This might be useful to upgrade a buggy firmware
2201  * for example.
2202  */
2203 static void nvme_create_io_queues(struct nvme_dev *dev)
2204 {
2205         unsigned i;
2206
2207         for (i = dev->queue_count; i <= dev->max_qid; i++)
2208                 if (!nvme_alloc_queue(dev, i, dev->q_depth))
2209                         break;
2210
2211         for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2212                 if (nvme_create_queue(dev->queues[i], i)) {
2213                         nvme_free_queues(dev, i);
2214                         break;
2215                 }
2216 }
2217
2218 static int set_queue_count(struct nvme_dev *dev, int count)
2219 {
2220         int status;
2221         u32 result;
2222         u32 q_count = (count - 1) | ((count - 1) << 16);
2223
2224         status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
2225                                                                 &result);
2226         if (status < 0)
2227                 return status;
2228         if (status > 0) {
2229                 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
2230                 return 0;
2231         }
2232         return min(result & 0xffff, result >> 16) + 1;
2233 }
2234
2235 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2236 {
2237         u64 szu, size, offset;
2238         u32 cmbloc;
2239         resource_size_t bar_size;
2240         struct pci_dev *pdev = to_pci_dev(dev->dev);
2241         void __iomem *cmb;
2242         dma_addr_t dma_addr;
2243
2244         if (!use_cmb_sqes)
2245                 return NULL;
2246
2247         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
2248         if (!(NVME_CMB_SZ(dev->cmbsz)))
2249                 return NULL;
2250
2251         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
2252
2253         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2254         size = szu * NVME_CMB_SZ(dev->cmbsz);
2255         offset = szu * NVME_CMB_OFST(cmbloc);
2256         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2257
2258         if (offset > bar_size)
2259                 return NULL;
2260
2261         /*
2262          * Controllers may support a CMB size larger than their BAR,
2263          * for example, due to being behind a bridge. Reduce the CMB to
2264          * the reported size of the BAR
2265          */
2266         if (size > bar_size - offset)
2267                 size = bar_size - offset;
2268
2269         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2270         cmb = ioremap_wc(dma_addr, size);
2271         if (!cmb)
2272                 return NULL;
2273
2274         dev->cmb_dma_addr = dma_addr;
2275         dev->cmb_size = size;
2276         return cmb;
2277 }
2278
2279 static inline void nvme_release_cmb(struct nvme_dev *dev)
2280 {
2281         if (dev->cmb) {
2282                 iounmap(dev->cmb);
2283                 dev->cmb = NULL;
2284         }
2285 }
2286
2287 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2288 {
2289         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2290 }
2291
2292 static int nvme_setup_io_queues(struct nvme_dev *dev)
2293 {
2294         struct nvme_queue *adminq = dev->queues[0];
2295         struct pci_dev *pdev = to_pci_dev(dev->dev);
2296         int result, i, vecs, nr_io_queues, size;
2297
2298         nr_io_queues = num_possible_cpus();
2299         result = set_queue_count(dev, nr_io_queues);
2300         if (result <= 0)
2301                 return result;
2302         if (result < nr_io_queues)
2303                 nr_io_queues = result;
2304
2305         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2306                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2307                                 sizeof(struct nvme_command));
2308                 if (result > 0)
2309                         dev->q_depth = result;
2310                 else
2311                         nvme_release_cmb(dev);
2312         }
2313
2314         size = db_bar_size(dev, nr_io_queues);
2315         if (size > 8192) {
2316                 iounmap(dev->bar);
2317                 do {
2318                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2319                         if (dev->bar)
2320                                 break;
2321                         if (!--nr_io_queues)
2322                                 return -ENOMEM;
2323                         size = db_bar_size(dev, nr_io_queues);
2324                 } while (1);
2325                 dev->dbs = dev->bar + 4096;
2326                 adminq->q_db = dev->dbs;
2327         }
2328
2329         /* Deregister the admin queue's interrupt */
2330         free_irq(dev->entry[0].vector, adminq);
2331
2332         /*
2333          * If we enable msix early due to not intx, disable it again before
2334          * setting up the full range we need.
2335          */
2336         if (!pdev->irq)
2337                 pci_disable_msix(pdev);
2338
2339         for (i = 0; i < nr_io_queues; i++)
2340                 dev->entry[i].entry = i;
2341         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2342         if (vecs < 0) {
2343                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2344                 if (vecs < 0) {
2345                         vecs = 1;
2346                 } else {
2347                         for (i = 0; i < vecs; i++)
2348                                 dev->entry[i].vector = i + pdev->irq;
2349                 }
2350         }
2351
2352         /*
2353          * Should investigate if there's a performance win from allocating
2354          * more queues than interrupt vectors; it might allow the submission
2355          * path to scale better, even if the receive path is limited by the
2356          * number of interrupts.
2357          */
2358         nr_io_queues = vecs;
2359         dev->max_qid = nr_io_queues;
2360
2361         result = queue_request_irq(dev, adminq, adminq->irqname);
2362         if (result) {
2363                 adminq->cq_vector = -1;
2364                 goto free_queues;
2365         }
2366
2367         /* Free previously allocated queues that are no longer usable */
2368         nvme_free_queues(dev, nr_io_queues + 1);
2369         nvme_create_io_queues(dev);
2370
2371         return 0;
2372
2373  free_queues:
2374         nvme_free_queues(dev, 1);
2375         return result;
2376 }
2377
2378 static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2379 {
2380         struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2381         struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2382
2383         return nsa->ns_id - nsb->ns_id;
2384 }
2385
2386 static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2387 {
2388         struct nvme_ns *ns;
2389
2390         list_for_each_entry(ns, &dev->namespaces, list) {
2391                 if (ns->ns_id == nsid)
2392                         return ns;
2393                 if (ns->ns_id > nsid)
2394                         break;
2395         }
2396         return NULL;
2397 }
2398
2399 static inline bool nvme_io_incapable(struct nvme_dev *dev)
2400 {
2401         return (!dev->bar ||
2402                 readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_CFS ||
2403                 dev->online_queues < 2);
2404 }
2405
2406 static void nvme_ns_remove(struct nvme_ns *ns)
2407 {
2408         bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2409
2410         if (kill)
2411                 blk_set_queue_dying(ns->queue);
2412         if (ns->disk->flags & GENHD_FL_UP)
2413                 del_gendisk(ns->disk);
2414         if (kill || !blk_queue_dying(ns->queue)) {
2415                 blk_mq_abort_requeue_list(ns->queue);
2416                 blk_cleanup_queue(ns->queue);
2417         }
2418         list_del_init(&ns->list);
2419         kref_put(&ns->kref, nvme_free_ns);
2420 }
2421
2422 static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2423 {
2424         struct nvme_ns *ns, *next;
2425         unsigned i;
2426
2427         for (i = 1; i <= nn; i++) {
2428                 ns = nvme_find_ns(dev, i);
2429                 if (ns) {
2430                         if (revalidate_disk(ns->disk))
2431                                 nvme_ns_remove(ns);
2432                 } else
2433                         nvme_alloc_ns(dev, i);
2434         }
2435         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2436                 if (ns->ns_id > nn)
2437                         nvme_ns_remove(ns);
2438         }
2439         list_sort(NULL, &dev->namespaces, ns_cmp);
2440 }
2441
2442 static void nvme_set_irq_hints(struct nvme_dev *dev)
2443 {
2444         struct nvme_queue *nvmeq;
2445         int i;
2446
2447         for (i = 0; i < dev->online_queues; i++) {
2448                 nvmeq = dev->queues[i];
2449
2450                 if (!nvmeq->tags || !(*nvmeq->tags))
2451                         continue;
2452
2453                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2454                                         blk_mq_tags_cpumask(*nvmeq->tags));
2455         }
2456 }
2457
2458 static void nvme_dev_scan(struct work_struct *work)
2459 {
2460         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2461         struct nvme_id_ctrl *ctrl;
2462
2463         if (!dev->tagset.tags)
2464                 return;
2465         if (nvme_identify_ctrl(dev, &ctrl))
2466                 return;
2467         nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2468         kfree(ctrl);
2469         nvme_set_irq_hints(dev);
2470 }
2471
2472 /*
2473  * Return: error value if an error occurred setting up the queues or calling
2474  * Identify Device.  0 if these succeeded, even if adding some of the
2475  * namespaces failed.  At the moment, these failures are silent.  TBD which
2476  * failures should be reported.
2477  */
2478 static int nvme_dev_add(struct nvme_dev *dev)
2479 {
2480         struct pci_dev *pdev = to_pci_dev(dev->dev);
2481         int res;
2482         struct nvme_id_ctrl *ctrl;
2483         int shift = NVME_CAP_MPSMIN(lo_hi_readq(dev->bar + NVME_REG_CAP)) + 12;
2484
2485         res = nvme_identify_ctrl(dev, &ctrl);
2486         if (res) {
2487                 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
2488                 return -EIO;
2489         }
2490
2491         dev->oncs = le16_to_cpup(&ctrl->oncs);
2492         dev->abort_limit = ctrl->acl + 1;
2493         dev->vwc = ctrl->vwc;
2494         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2495         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2496         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2497         if (ctrl->mdts)
2498                 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2499         else
2500                 dev->max_hw_sectors = UINT_MAX;
2501         if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2502                         (pdev->device == 0x0953) && ctrl->vs[3]) {
2503                 unsigned int max_hw_sectors;
2504
2505                 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2506                 max_hw_sectors = dev->stripe_size >> (shift - 9);
2507                 if (dev->max_hw_sectors) {
2508                         dev->max_hw_sectors = min(max_hw_sectors,
2509                                                         dev->max_hw_sectors);
2510                 } else
2511                         dev->max_hw_sectors = max_hw_sectors;
2512         }
2513         kfree(ctrl);
2514
2515         if (!dev->tagset.tags) {
2516                 dev->tagset.ops = &nvme_mq_ops;
2517                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2518                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2519                 dev->tagset.numa_node = dev_to_node(dev->dev);
2520                 dev->tagset.queue_depth =
2521                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2522                 dev->tagset.cmd_size = nvme_cmd_size(dev);
2523                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2524                 dev->tagset.driver_data = dev;
2525
2526                 if (blk_mq_alloc_tag_set(&dev->tagset))
2527                         return 0;
2528         }
2529         schedule_work(&dev->scan_work);
2530         return 0;
2531 }
2532
2533 static int nvme_dev_map(struct nvme_dev *dev)
2534 {
2535         u64 cap;
2536         int bars, result = -ENOMEM;
2537         struct pci_dev *pdev = to_pci_dev(dev->dev);
2538
2539         if (pci_enable_device_mem(pdev))
2540                 return result;
2541
2542         dev->entry[0].vector = pdev->irq;
2543         pci_set_master(pdev);
2544         bars = pci_select_bars(pdev, IORESOURCE_MEM);
2545         if (!bars)
2546                 goto disable_pci;
2547
2548         if (pci_request_selected_regions(pdev, bars, "nvme"))
2549                 goto disable_pci;
2550
2551         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2552             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2553                 goto disable;
2554
2555         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2556         if (!dev->bar)
2557                 goto disable;
2558
2559         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2560                 result = -ENODEV;
2561                 goto unmap;
2562         }
2563
2564         /*
2565          * Some devices don't advertse INTx interrupts, pre-enable a single
2566          * MSIX vec for setup. We'll adjust this later.
2567          */
2568         if (!pdev->irq) {
2569                 result = pci_enable_msix(pdev, dev->entry, 1);
2570                 if (result < 0)
2571                         goto unmap;
2572         }
2573
2574         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2575
2576         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2577         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2578         dev->dbs = dev->bar + 4096;
2579         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
2580                 dev->cmb = nvme_map_cmb(dev);
2581
2582         return 0;
2583
2584  unmap:
2585         iounmap(dev->bar);
2586         dev->bar = NULL;
2587  disable:
2588         pci_release_regions(pdev);
2589  disable_pci:
2590         pci_disable_device(pdev);
2591         return result;
2592 }
2593
2594 static void nvme_dev_unmap(struct nvme_dev *dev)
2595 {
2596         struct pci_dev *pdev = to_pci_dev(dev->dev);
2597
2598         if (pdev->msi_enabled)
2599                 pci_disable_msi(pdev);
2600         else if (pdev->msix_enabled)
2601                 pci_disable_msix(pdev);
2602
2603         if (dev->bar) {
2604                 iounmap(dev->bar);
2605                 dev->bar = NULL;
2606                 pci_release_regions(pdev);
2607         }
2608
2609         if (pci_is_enabled(pdev))
2610                 pci_disable_device(pdev);
2611 }
2612
2613 struct nvme_delq_ctx {
2614         struct task_struct *waiter;
2615         struct kthread_worker *worker;
2616         atomic_t refcount;
2617 };
2618
2619 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2620 {
2621         dq->waiter = current;
2622         mb();
2623
2624         for (;;) {
2625                 set_current_state(TASK_KILLABLE);
2626                 if (!atomic_read(&dq->refcount))
2627                         break;
2628                 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2629                                         fatal_signal_pending(current)) {
2630                         /*
2631                          * Disable the controller first since we can't trust it
2632                          * at this point, but leave the admin queue enabled
2633                          * until all queue deletion requests are flushed.
2634                          * FIXME: This may take a while if there are more h/w
2635                          * queues than admin tags.
2636                          */
2637                         set_current_state(TASK_RUNNING);
2638                         nvme_disable_ctrl(dev,
2639                                 lo_hi_readq(dev->bar + NVME_REG_CAP));
2640                         nvme_clear_queue(dev->queues[0]);
2641                         flush_kthread_worker(dq->worker);
2642                         nvme_disable_queue(dev, 0);
2643                         return;
2644                 }
2645         }
2646         set_current_state(TASK_RUNNING);
2647 }
2648
2649 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2650 {
2651         atomic_dec(&dq->refcount);
2652         if (dq->waiter)
2653                 wake_up_process(dq->waiter);
2654 }
2655
2656 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2657 {
2658         atomic_inc(&dq->refcount);
2659         return dq;
2660 }
2661
2662 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2663 {
2664         struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2665         nvme_put_dq(dq);
2666
2667         spin_lock_irq(&nvmeq->q_lock);
2668         nvme_process_cq(nvmeq);
2669         spin_unlock_irq(&nvmeq->q_lock);
2670 }
2671
2672 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2673                                                 kthread_work_func_t fn)
2674 {
2675         struct nvme_command c;
2676
2677         memset(&c, 0, sizeof(c));
2678         c.delete_queue.opcode = opcode;
2679         c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2680
2681         init_kthread_work(&nvmeq->cmdinfo.work, fn);
2682         return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2683                                                                 ADMIN_TIMEOUT);
2684 }
2685
2686 static void nvme_del_cq_work_handler(struct kthread_work *work)
2687 {
2688         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2689                                                         cmdinfo.work);
2690         nvme_del_queue_end(nvmeq);
2691 }
2692
2693 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2694 {
2695         return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2696                                                 nvme_del_cq_work_handler);
2697 }
2698
2699 static void nvme_del_sq_work_handler(struct kthread_work *work)
2700 {
2701         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2702                                                         cmdinfo.work);
2703         int status = nvmeq->cmdinfo.status;
2704
2705         if (!status)
2706                 status = nvme_delete_cq(nvmeq);
2707         if (status)
2708                 nvme_del_queue_end(nvmeq);
2709 }
2710
2711 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2712 {
2713         return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2714                                                 nvme_del_sq_work_handler);
2715 }
2716
2717 static void nvme_del_queue_start(struct kthread_work *work)
2718 {
2719         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2720                                                         cmdinfo.work);
2721         if (nvme_delete_sq(nvmeq))
2722                 nvme_del_queue_end(nvmeq);
2723 }
2724
2725 static void nvme_disable_io_queues(struct nvme_dev *dev)
2726 {
2727         int i;
2728         DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2729         struct nvme_delq_ctx dq;
2730         struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2731                                         &worker, "nvme%d", dev->instance);
2732
2733         if (IS_ERR(kworker_task)) {
2734                 dev_err(dev->dev,
2735                         "Failed to create queue del task\n");
2736                 for (i = dev->queue_count - 1; i > 0; i--)
2737                         nvme_disable_queue(dev, i);
2738                 return;
2739         }
2740
2741         dq.waiter = NULL;
2742         atomic_set(&dq.refcount, 0);
2743         dq.worker = &worker;
2744         for (i = dev->queue_count - 1; i > 0; i--) {
2745                 struct nvme_queue *nvmeq = dev->queues[i];
2746
2747                 if (nvme_suspend_queue(nvmeq))
2748                         continue;
2749                 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2750                 nvmeq->cmdinfo.worker = dq.worker;
2751                 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2752                 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2753         }
2754         nvme_wait_dq(&dq, dev);
2755         kthread_stop(kworker_task);
2756 }
2757
2758 /*
2759 * Remove the node from the device list and check
2760 * for whether or not we need to stop the nvme_thread.
2761 */
2762 static void nvme_dev_list_remove(struct nvme_dev *dev)
2763 {
2764         struct task_struct *tmp = NULL;
2765
2766         spin_lock(&dev_list_lock);
2767         list_del_init(&dev->node);
2768         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2769                 tmp = nvme_thread;
2770                 nvme_thread = NULL;
2771         }
2772         spin_unlock(&dev_list_lock);
2773
2774         if (tmp)
2775                 kthread_stop(tmp);
2776 }
2777
2778 static void nvme_freeze_queues(struct nvme_dev *dev)
2779 {
2780         struct nvme_ns *ns;
2781
2782         list_for_each_entry(ns, &dev->namespaces, list) {
2783                 blk_mq_freeze_queue_start(ns->queue);
2784
2785                 spin_lock_irq(ns->queue->queue_lock);
2786                 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2787                 spin_unlock_irq(ns->queue->queue_lock);
2788
2789                 blk_mq_cancel_requeue_work(ns->queue);
2790                 blk_mq_stop_hw_queues(ns->queue);
2791         }
2792 }
2793
2794 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2795 {
2796         struct nvme_ns *ns;
2797
2798         list_for_each_entry(ns, &dev->namespaces, list) {
2799                 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2800                 blk_mq_unfreeze_queue(ns->queue);
2801                 blk_mq_start_stopped_hw_queues(ns->queue, true);
2802                 blk_mq_kick_requeue_list(ns->queue);
2803         }
2804 }
2805
2806 static void nvme_dev_shutdown(struct nvme_dev *dev)
2807 {
2808         int i;
2809         u32 csts = -1;
2810
2811         nvme_dev_list_remove(dev);
2812
2813         if (dev->bar) {
2814                 nvme_freeze_queues(dev);
2815                 csts = readl(dev->bar + NVME_REG_CSTS);
2816         }
2817         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2818                 for (i = dev->queue_count - 1; i >= 0; i--) {
2819                         struct nvme_queue *nvmeq = dev->queues[i];
2820                         nvme_suspend_queue(nvmeq);
2821                 }
2822         } else {
2823                 nvme_disable_io_queues(dev);
2824                 nvme_shutdown_ctrl(dev);
2825                 nvme_disable_queue(dev, 0);
2826         }
2827         nvme_dev_unmap(dev);
2828
2829         for (i = dev->queue_count - 1; i >= 0; i--)
2830                 nvme_clear_queue(dev->queues[i]);
2831 }
2832
2833 static void nvme_dev_remove(struct nvme_dev *dev)
2834 {
2835         struct nvme_ns *ns, *next;
2836
2837         list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2838                 nvme_ns_remove(ns);
2839 }
2840
2841 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2842 {
2843         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2844                                                 PAGE_SIZE, PAGE_SIZE, 0);
2845         if (!dev->prp_page_pool)
2846                 return -ENOMEM;
2847
2848         /* Optimisation for I/Os between 4k and 128k */
2849         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2850                                                 256, 256, 0);
2851         if (!dev->prp_small_pool) {
2852                 dma_pool_destroy(dev->prp_page_pool);
2853                 return -ENOMEM;
2854         }
2855         return 0;
2856 }
2857
2858 static void nvme_release_prp_pools(struct nvme_dev *dev)
2859 {
2860         dma_pool_destroy(dev->prp_page_pool);
2861         dma_pool_destroy(dev->prp_small_pool);
2862 }
2863
2864 static DEFINE_IDA(nvme_instance_ida);
2865
2866 static int nvme_set_instance(struct nvme_dev *dev)
2867 {
2868         int instance, error;
2869
2870         do {
2871                 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2872                         return -ENODEV;
2873
2874                 spin_lock(&dev_list_lock);
2875                 error = ida_get_new(&nvme_instance_ida, &instance);
2876                 spin_unlock(&dev_list_lock);
2877         } while (error == -EAGAIN);
2878
2879         if (error)
2880                 return -ENODEV;
2881
2882         dev->instance = instance;
2883         return 0;
2884 }
2885
2886 static void nvme_release_instance(struct nvme_dev *dev)
2887 {
2888         spin_lock(&dev_list_lock);
2889         ida_remove(&nvme_instance_ida, dev->instance);
2890         spin_unlock(&dev_list_lock);
2891 }
2892
2893 static void nvme_free_dev(struct kref *kref)
2894 {
2895         struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2896
2897         put_device(dev->dev);
2898         put_device(dev->device);
2899         nvme_release_instance(dev);
2900         if (dev->tagset.tags)
2901                 blk_mq_free_tag_set(&dev->tagset);
2902         if (dev->admin_q)
2903                 blk_put_queue(dev->admin_q);
2904         kfree(dev->queues);
2905         kfree(dev->entry);
2906         kfree(dev);
2907 }
2908
2909 static int nvme_dev_open(struct inode *inode, struct file *f)
2910 {
2911         struct nvme_dev *dev;
2912         int instance = iminor(inode);
2913         int ret = -ENODEV;
2914
2915         spin_lock(&dev_list_lock);
2916         list_for_each_entry(dev, &dev_list, node) {
2917                 if (dev->instance == instance) {
2918                         if (!dev->admin_q) {
2919                                 ret = -EWOULDBLOCK;
2920                                 break;
2921                         }
2922                         if (!kref_get_unless_zero(&dev->kref))
2923                                 break;
2924                         f->private_data = dev;
2925                         ret = 0;
2926                         break;
2927                 }
2928         }
2929         spin_unlock(&dev_list_lock);
2930
2931         return ret;
2932 }
2933
2934 static int nvme_dev_release(struct inode *inode, struct file *f)
2935 {
2936         struct nvme_dev *dev = f->private_data;
2937         kref_put(&dev->kref, nvme_free_dev);
2938         return 0;
2939 }
2940
2941 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2942 {
2943         struct nvme_dev *dev = f->private_data;
2944         struct nvme_ns *ns;
2945
2946         switch (cmd) {
2947         case NVME_IOCTL_ADMIN_CMD:
2948                 return nvme_user_cmd(dev, NULL, (void __user *)arg);
2949         case NVME_IOCTL_IO_CMD:
2950                 if (list_empty(&dev->namespaces))
2951                         return -ENOTTY;
2952                 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2953                 return nvme_user_cmd(dev, ns, (void __user *)arg);
2954         case NVME_IOCTL_RESET:
2955                 dev_warn(dev->dev, "resetting controller\n");
2956                 return nvme_reset(dev);
2957         case NVME_IOCTL_SUBSYS_RESET:
2958                 return nvme_subsys_reset(dev);
2959         default:
2960                 return -ENOTTY;
2961         }
2962 }
2963
2964 static const struct file_operations nvme_dev_fops = {
2965         .owner          = THIS_MODULE,
2966         .open           = nvme_dev_open,
2967         .release        = nvme_dev_release,
2968         .unlocked_ioctl = nvme_dev_ioctl,
2969         .compat_ioctl   = nvme_dev_ioctl,
2970 };
2971
2972 static void nvme_probe_work(struct work_struct *work)
2973 {
2974         struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
2975         bool start_thread = false;
2976         int result;
2977
2978         result = nvme_dev_map(dev);
2979         if (result)
2980                 goto out;
2981
2982         result = nvme_configure_admin_queue(dev);
2983         if (result)
2984                 goto unmap;
2985
2986         spin_lock(&dev_list_lock);
2987         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2988                 start_thread = true;
2989                 nvme_thread = NULL;
2990         }
2991         list_add(&dev->node, &dev_list);
2992         spin_unlock(&dev_list_lock);
2993
2994         if (start_thread) {
2995                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2996                 wake_up_all(&nvme_kthread_wait);
2997         } else
2998                 wait_event_killable(nvme_kthread_wait, nvme_thread);
2999
3000         if (IS_ERR_OR_NULL(nvme_thread)) {
3001                 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3002                 goto disable;
3003         }
3004
3005         nvme_init_queue(dev->queues[0], 0);
3006         result = nvme_alloc_admin_tags(dev);
3007         if (result)
3008                 goto disable;
3009
3010         result = nvme_setup_io_queues(dev);
3011         if (result)
3012                 goto free_tags;
3013
3014         dev->event_limit = 1;
3015
3016         /*
3017          * Keep the controller around but remove all namespaces if we don't have
3018          * any working I/O queue.
3019          */
3020         if (dev->online_queues < 2) {
3021                 dev_warn(dev->dev, "IO queues not created\n");
3022                 nvme_dev_remove(dev);
3023         } else {
3024                 nvme_unfreeze_queues(dev);
3025                 nvme_dev_add(dev);
3026         }
3027
3028         return;
3029
3030  free_tags:
3031         nvme_dev_remove_admin(dev);
3032         blk_put_queue(dev->admin_q);
3033         dev->admin_q = NULL;
3034         dev->queues[0]->tags = NULL;
3035  disable:
3036         nvme_disable_queue(dev, 0);
3037         nvme_dev_list_remove(dev);
3038  unmap:
3039         nvme_dev_unmap(dev);
3040  out:
3041         if (!work_busy(&dev->reset_work))
3042                 nvme_dead_ctrl(dev);
3043 }
3044
3045 static int nvme_remove_dead_ctrl(void *arg)
3046 {
3047         struct nvme_dev *dev = (struct nvme_dev *)arg;
3048         struct pci_dev *pdev = to_pci_dev(dev->dev);
3049
3050         if (pci_get_drvdata(pdev))
3051                 pci_stop_and_remove_bus_device_locked(pdev);
3052         kref_put(&dev->kref, nvme_free_dev);
3053         return 0;
3054 }
3055
3056 static void nvme_dead_ctrl(struct nvme_dev *dev)
3057 {
3058         dev_warn(dev->dev, "Device failed to resume\n");
3059         kref_get(&dev->kref);
3060         if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3061                                                 dev->instance))) {
3062                 dev_err(dev->dev,
3063                         "Failed to start controller remove task\n");
3064                 kref_put(&dev->kref, nvme_free_dev);
3065         }
3066 }
3067
3068 static void nvme_reset_work(struct work_struct *ws)
3069 {
3070         struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
3071         bool in_probe = work_busy(&dev->probe_work);
3072
3073         nvme_dev_shutdown(dev);
3074
3075         /* Synchronize with device probe so that work will see failure status
3076          * and exit gracefully without trying to schedule another reset */
3077         flush_work(&dev->probe_work);
3078
3079         /* Fail this device if reset occured during probe to avoid
3080          * infinite initialization loops. */
3081         if (in_probe) {
3082                 nvme_dead_ctrl(dev);
3083                 return;
3084         }
3085         /* Schedule device resume asynchronously so the reset work is available
3086          * to cleanup errors that may occur during reinitialization */
3087         schedule_work(&dev->probe_work);
3088 }
3089
3090 static int __nvme_reset(struct nvme_dev *dev)
3091 {
3092         if (work_pending(&dev->reset_work))
3093                 return -EBUSY;
3094         list_del_init(&dev->node);
3095         queue_work(nvme_workq, &dev->reset_work);
3096         return 0;
3097 }
3098
3099 static int nvme_reset(struct nvme_dev *dev)
3100 {
3101         int ret;
3102
3103         if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3104                 return -ENODEV;
3105
3106         spin_lock(&dev_list_lock);
3107         ret = __nvme_reset(dev);
3108         spin_unlock(&dev_list_lock);
3109
3110         if (!ret) {
3111                 flush_work(&dev->reset_work);
3112                 flush_work(&dev->probe_work);
3113                 return 0;
3114         }
3115
3116         return ret;
3117 }
3118
3119 static ssize_t nvme_sysfs_reset(struct device *dev,
3120                                 struct device_attribute *attr, const char *buf,
3121                                 size_t count)
3122 {
3123         struct nvme_dev *ndev = dev_get_drvdata(dev);
3124         int ret;
3125
3126         ret = nvme_reset(ndev);
3127         if (ret < 0)
3128                 return ret;
3129
3130         return count;
3131 }
3132 static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3133
3134 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3135 {
3136         int node, result = -ENOMEM;
3137         struct nvme_dev *dev;
3138
3139         node = dev_to_node(&pdev->dev);
3140         if (node == NUMA_NO_NODE)
3141                 set_dev_node(&pdev->dev, 0);
3142
3143         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3144         if (!dev)
3145                 return -ENOMEM;
3146         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3147                                                         GFP_KERNEL, node);
3148         if (!dev->entry)
3149                 goto free;
3150         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3151                                                         GFP_KERNEL, node);
3152         if (!dev->queues)
3153                 goto free;
3154
3155         INIT_LIST_HEAD(&dev->namespaces);
3156         INIT_WORK(&dev->reset_work, nvme_reset_work);
3157         dev->dev = get_device(&pdev->dev);
3158         pci_set_drvdata(pdev, dev);
3159         result = nvme_set_instance(dev);
3160         if (result)
3161                 goto put_pci;
3162
3163         result = nvme_setup_prp_pools(dev);
3164         if (result)
3165                 goto release;
3166
3167         kref_init(&dev->kref);
3168         dev->device = device_create(nvme_class, &pdev->dev,
3169                                 MKDEV(nvme_char_major, dev->instance),
3170                                 dev, "nvme%d", dev->instance);
3171         if (IS_ERR(dev->device)) {
3172                 result = PTR_ERR(dev->device);
3173                 goto release_pools;
3174         }
3175         get_device(dev->device);
3176         dev_set_drvdata(dev->device, dev);
3177
3178         result = device_create_file(dev->device, &dev_attr_reset_controller);
3179         if (result)
3180                 goto put_dev;
3181
3182         INIT_LIST_HEAD(&dev->node);
3183         INIT_WORK(&dev->scan_work, nvme_dev_scan);
3184         INIT_WORK(&dev->probe_work, nvme_probe_work);
3185         schedule_work(&dev->probe_work);
3186         return 0;
3187
3188  put_dev:
3189         device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3190         put_device(dev->device);
3191  release_pools:
3192         nvme_release_prp_pools(dev);
3193  release:
3194         nvme_release_instance(dev);
3195  put_pci:
3196         put_device(dev->dev);
3197  free:
3198         kfree(dev->queues);
3199         kfree(dev->entry);
3200         kfree(dev);
3201         return result;
3202 }
3203
3204 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3205 {
3206         struct nvme_dev *dev = pci_get_drvdata(pdev);
3207
3208         if (prepare)
3209                 nvme_dev_shutdown(dev);
3210         else
3211                 schedule_work(&dev->probe_work);
3212 }
3213
3214 static void nvme_shutdown(struct pci_dev *pdev)
3215 {
3216         struct nvme_dev *dev = pci_get_drvdata(pdev);
3217         nvme_dev_shutdown(dev);
3218 }
3219
3220 static void nvme_remove(struct pci_dev *pdev)
3221 {
3222         struct nvme_dev *dev = pci_get_drvdata(pdev);
3223
3224         spin_lock(&dev_list_lock);
3225         list_del_init(&dev->node);
3226         spin_unlock(&dev_list_lock);
3227
3228         pci_set_drvdata(pdev, NULL);
3229         flush_work(&dev->probe_work);
3230         flush_work(&dev->reset_work);
3231         flush_work(&dev->scan_work);
3232         device_remove_file(dev->device, &dev_attr_reset_controller);
3233         nvme_dev_remove(dev);
3234         nvme_dev_shutdown(dev);
3235         nvme_dev_remove_admin(dev);
3236         device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3237         nvme_free_queues(dev, 0);
3238         nvme_release_cmb(dev);
3239         nvme_release_prp_pools(dev);
3240         kref_put(&dev->kref, nvme_free_dev);
3241 }
3242
3243 /* These functions are yet to be implemented */
3244 #define nvme_error_detected NULL
3245 #define nvme_dump_registers NULL
3246 #define nvme_link_reset NULL
3247 #define nvme_slot_reset NULL
3248 #define nvme_error_resume NULL
3249
3250 #ifdef CONFIG_PM_SLEEP
3251 static int nvme_suspend(struct device *dev)
3252 {
3253         struct pci_dev *pdev = to_pci_dev(dev);
3254         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3255
3256         nvme_dev_shutdown(ndev);
3257         return 0;
3258 }
3259
3260 static int nvme_resume(struct device *dev)
3261 {
3262         struct pci_dev *pdev = to_pci_dev(dev);
3263         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3264
3265         schedule_work(&ndev->probe_work);
3266         return 0;
3267 }
3268 #endif
3269
3270 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
3271
3272 static const struct pci_error_handlers nvme_err_handler = {
3273         .error_detected = nvme_error_detected,
3274         .mmio_enabled   = nvme_dump_registers,
3275         .link_reset     = nvme_link_reset,
3276         .slot_reset     = nvme_slot_reset,
3277         .resume         = nvme_error_resume,
3278         .reset_notify   = nvme_reset_notify,
3279 };
3280
3281 /* Move to pci_ids.h later */
3282 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
3283
3284 static const struct pci_device_id nvme_id_table[] = {
3285         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3286         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
3287         { 0, }
3288 };
3289 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3290
3291 static struct pci_driver nvme_driver = {
3292         .name           = "nvme",
3293         .id_table       = nvme_id_table,
3294         .probe          = nvme_probe,
3295         .remove         = nvme_remove,
3296         .shutdown       = nvme_shutdown,
3297         .driver         = {
3298                 .pm     = &nvme_dev_pm_ops,
3299         },
3300         .err_handler    = &nvme_err_handler,
3301 };
3302
3303 static int __init nvme_init(void)
3304 {
3305         int result;
3306
3307         init_waitqueue_head(&nvme_kthread_wait);
3308
3309         nvme_workq = create_singlethread_workqueue("nvme");
3310         if (!nvme_workq)
3311                 return -ENOMEM;
3312
3313         result = register_blkdev(nvme_major, "nvme");
3314         if (result < 0)
3315                 goto kill_workq;
3316         else if (result > 0)
3317                 nvme_major = result;
3318
3319         result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3320                                                         &nvme_dev_fops);
3321         if (result < 0)
3322                 goto unregister_blkdev;
3323         else if (result > 0)
3324                 nvme_char_major = result;
3325
3326         nvme_class = class_create(THIS_MODULE, "nvme");
3327         if (IS_ERR(nvme_class)) {
3328                 result = PTR_ERR(nvme_class);
3329                 goto unregister_chrdev;
3330         }
3331
3332         result = pci_register_driver(&nvme_driver);
3333         if (result)
3334                 goto destroy_class;
3335         return 0;
3336
3337  destroy_class:
3338         class_destroy(nvme_class);
3339  unregister_chrdev:
3340         __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3341  unregister_blkdev:
3342         unregister_blkdev(nvme_major, "nvme");
3343  kill_workq:
3344         destroy_workqueue(nvme_workq);
3345         return result;
3346 }
3347
3348 static void __exit nvme_exit(void)
3349 {
3350         pci_unregister_driver(&nvme_driver);
3351         unregister_blkdev(nvme_major, "nvme");
3352         destroy_workqueue(nvme_workq);
3353         class_destroy(nvme_class);
3354         __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3355         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
3356         _nvme_check_size();
3357 }
3358
3359 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3360 MODULE_LICENSE("GPL");
3361 MODULE_VERSION("1.0");
3362 module_init(nvme_init);
3363 module_exit(nvme_exit);