2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/blk-mq-pci.h>
19 #include <linux/dmi.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/once.h>
27 #include <linux/pci.h>
28 #include <linux/t10-pi.h>
29 #include <linux/types.h>
30 #include <linux/io-64-nonatomic-lo-hi.h>
31 #include <linux/sed-opal.h>
35 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
36 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
38 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
40 static int use_threaded_interrupts;
41 module_param(use_threaded_interrupts, int, 0);
43 static bool use_cmb_sqes = true;
44 module_param(use_cmb_sqes, bool, 0644);
45 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
47 static unsigned int max_host_mem_size_mb = 128;
48 module_param(max_host_mem_size_mb, uint, 0444);
49 MODULE_PARM_DESC(max_host_mem_size_mb,
50 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
52 static unsigned int sgl_threshold = SZ_32K;
53 module_param(sgl_threshold, uint, 0644);
54 MODULE_PARM_DESC(sgl_threshold,
55 "Use SGLs when average request segment size is larger or equal to "
56 "this size. Use 0 to disable SGLs.");
58 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
59 static const struct kernel_param_ops io_queue_depth_ops = {
60 .set = io_queue_depth_set,
64 static int io_queue_depth = 1024;
65 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
66 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
71 static void nvme_process_cq(struct nvme_queue *nvmeq);
72 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
78 struct nvme_queue *queues;
79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
85 unsigned online_queues;
87 unsigned int num_vecs;
91 unsigned long bar_mapped_size;
92 struct work_struct remove_work;
93 struct mutex shutdown_lock;
96 pci_bus_addr_t cmb_bus_addr;
100 struct nvme_ctrl ctrl;
101 struct completion ioq_wait;
103 /* shadow doorbell buffer support: */
105 dma_addr_t dbbuf_dbs_dma_addr;
107 dma_addr_t dbbuf_eis_dma_addr;
109 /* host memory buffer support: */
111 u32 nr_host_mem_descs;
112 dma_addr_t host_mem_descs_dma;
113 struct nvme_host_mem_buf_desc *host_mem_descs;
114 void **host_mem_desc_bufs;
117 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
121 ret = kstrtoint(val, 10, &n);
122 if (ret != 0 || n < 2)
125 return param_set_int(val, kp);
128 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
130 return qid * 2 * stride;
133 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
135 return (qid * 2 + 1) * stride;
138 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
140 return container_of(ctrl, struct nvme_dev, ctrl);
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
148 struct device *q_dmadev;
149 struct nvme_dev *dev;
151 struct nvme_command *sq_cmds;
152 struct nvme_command __iomem *sq_cmds_io;
153 volatile struct nvme_completion *cqes;
154 struct blk_mq_tags **tags;
155 dma_addr_t sq_dma_addr;
156 dma_addr_t cq_dma_addr;
172 * The nvme_iod describes the data in an I/O, including the list of PRP
173 * entries. You can't see it in this data structure because C doesn't let
174 * me express that. Use nvme_init_iod to ensure there's enough space
175 * allocated to store the PRP list.
178 struct nvme_request req;
179 struct nvme_queue *nvmeq;
182 int npages; /* In the PRP list. 0 means small pool in use */
183 int nents; /* Used in scatterlist */
184 int length; /* Of data, in bytes */
185 dma_addr_t first_dma;
186 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
187 struct scatterlist *sg;
188 struct scatterlist inline_sg[0];
192 * Check we didin't inadvertently grow the command struct
194 static inline void _nvme_check_size(void)
196 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
205 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
206 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
207 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
208 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
211 static inline unsigned int nvme_dbbuf_size(u32 stride)
213 return ((num_possible_cpus() + 1) * 8 * stride);
216 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
218 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
223 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
224 &dev->dbbuf_dbs_dma_addr,
228 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
229 &dev->dbbuf_eis_dma_addr,
231 if (!dev->dbbuf_eis) {
232 dma_free_coherent(dev->dev, mem_size,
233 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
234 dev->dbbuf_dbs = NULL;
241 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
243 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
245 if (dev->dbbuf_dbs) {
246 dma_free_coherent(dev->dev, mem_size,
247 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
248 dev->dbbuf_dbs = NULL;
250 if (dev->dbbuf_eis) {
251 dma_free_coherent(dev->dev, mem_size,
252 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
253 dev->dbbuf_eis = NULL;
257 static void nvme_dbbuf_init(struct nvme_dev *dev,
258 struct nvme_queue *nvmeq, int qid)
260 if (!dev->dbbuf_dbs || !qid)
263 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
266 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
269 static void nvme_dbbuf_set(struct nvme_dev *dev)
271 struct nvme_command c;
276 memset(&c, 0, sizeof(c));
277 c.dbbuf.opcode = nvme_admin_dbbuf;
278 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
279 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
281 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
282 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
283 /* Free memory and continue on */
284 nvme_dbbuf_dma_free(dev);
288 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
290 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
293 /* Update dbbuf and return true if an MMIO is required */
294 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
295 volatile u32 *dbbuf_ei)
301 * Ensure that the queue is written before updating
302 * the doorbell in memory
306 old_value = *dbbuf_db;
309 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
317 * Max size of iod being embedded in the request payload
319 #define NVME_INT_PAGES 2
320 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
323 * Will slightly overestimate the number of pages needed. This is OK
324 * as it only leads to a small amount of wasted memory for the lifetime of
327 static int nvme_npages(unsigned size, struct nvme_dev *dev)
329 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
330 dev->ctrl.page_size);
331 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
335 * Calculates the number of pages needed for the SGL segments. For example a 4k
336 * page can accommodate 256 SGL descriptors.
338 static int nvme_pci_npages_sgl(unsigned int num_seg)
340 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
343 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
344 unsigned int size, unsigned int nseg, bool use_sgl)
349 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
351 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
353 return alloc_size + sizeof(struct scatterlist) * nseg;
356 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
358 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
359 NVME_INT_BYTES(dev), NVME_INT_PAGES,
362 return sizeof(struct nvme_iod) + alloc_size;
365 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
366 unsigned int hctx_idx)
368 struct nvme_dev *dev = data;
369 struct nvme_queue *nvmeq = &dev->queues[0];
371 WARN_ON(hctx_idx != 0);
372 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
373 WARN_ON(nvmeq->tags);
375 hctx->driver_data = nvmeq;
376 nvmeq->tags = &dev->admin_tagset.tags[0];
380 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
382 struct nvme_queue *nvmeq = hctx->driver_data;
387 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
388 unsigned int hctx_idx)
390 struct nvme_dev *dev = data;
391 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
394 nvmeq->tags = &dev->tagset.tags[hctx_idx];
396 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
397 hctx->driver_data = nvmeq;
401 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
402 unsigned int hctx_idx, unsigned int numa_node)
404 struct nvme_dev *dev = set->driver_data;
405 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
406 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
407 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
414 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
416 struct nvme_dev *dev = set->driver_data;
418 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
419 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
423 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
424 * @nvmeq: The queue to use
425 * @cmd: The command to send
427 * Safe to use from interrupt context
429 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
430 struct nvme_command *cmd)
432 u16 tail = nvmeq->sq_tail;
434 if (nvmeq->sq_cmds_io)
435 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
437 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
439 if (++tail == nvmeq->q_depth)
441 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
443 writel(tail, nvmeq->q_db);
444 nvmeq->sq_tail = tail;
447 static void **nvme_pci_iod_list(struct request *req)
449 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
450 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
453 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
455 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
456 int nseg = blk_rq_nr_phys_segments(req);
457 unsigned int avg_seg_size;
462 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
464 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
466 if (!iod->nvmeq->qid)
468 if (!sgl_threshold || avg_seg_size < sgl_threshold)
473 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
475 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
476 int nseg = blk_rq_nr_phys_segments(rq);
477 unsigned int size = blk_rq_payload_bytes(rq);
479 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
481 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
482 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
485 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
487 return BLK_STS_RESOURCE;
489 iod->sg = iod->inline_sg;
500 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
502 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
503 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
504 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
508 if (iod->npages == 0)
509 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
512 for (i = 0; i < iod->npages; i++) {
513 void *addr = nvme_pci_iod_list(req)[i];
516 struct nvme_sgl_desc *sg_list = addr;
519 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
521 __le64 *prp_list = addr;
523 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
526 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
527 dma_addr = next_dma_addr;
530 if (iod->sg != iod->inline_sg)
534 #ifdef CONFIG_BLK_DEV_INTEGRITY
535 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
537 if (be32_to_cpu(pi->ref_tag) == v)
538 pi->ref_tag = cpu_to_be32(p);
541 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
543 if (be32_to_cpu(pi->ref_tag) == p)
544 pi->ref_tag = cpu_to_be32(v);
548 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
550 * The virtual start sector is the one that was originally submitted by the
551 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
552 * start sector may be different. Remap protection information to match the
553 * physical LBA on writes, and back to the original seed on reads.
555 * Type 0 and 3 do not have a ref tag, so no remapping required.
557 static void nvme_dif_remap(struct request *req,
558 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
560 struct nvme_ns *ns = req->rq_disk->private_data;
561 struct bio_integrity_payload *bip;
562 struct t10_pi_tuple *pi;
564 u32 i, nlb, ts, phys, virt;
566 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
569 bip = bio_integrity(req->bio);
573 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
576 virt = bip_get_seed(bip);
577 phys = nvme_block_nr(ns, blk_rq_pos(req));
578 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
579 ts = ns->disk->queue->integrity.tuple_size;
581 for (i = 0; i < nlb; i++, virt++, phys++) {
582 pi = (struct t10_pi_tuple *)p;
583 dif_swap(phys, virt, pi);
588 #else /* CONFIG_BLK_DEV_INTEGRITY */
589 static void nvme_dif_remap(struct request *req,
590 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
593 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
596 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
601 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
604 struct scatterlist *sg;
606 for_each_sg(sgl, sg, nents, i) {
607 dma_addr_t phys = sg_phys(sg);
608 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
609 "dma_address:%pad dma_length:%d\n",
610 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
615 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
616 struct request *req, struct nvme_rw_command *cmnd)
618 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
619 struct dma_pool *pool;
620 int length = blk_rq_payload_bytes(req);
621 struct scatterlist *sg = iod->sg;
622 int dma_len = sg_dma_len(sg);
623 u64 dma_addr = sg_dma_address(sg);
624 u32 page_size = dev->ctrl.page_size;
625 int offset = dma_addr & (page_size - 1);
627 void **list = nvme_pci_iod_list(req);
631 length -= (page_size - offset);
637 dma_len -= (page_size - offset);
639 dma_addr += (page_size - offset);
642 dma_addr = sg_dma_address(sg);
643 dma_len = sg_dma_len(sg);
646 if (length <= page_size) {
647 iod->first_dma = dma_addr;
651 nprps = DIV_ROUND_UP(length, page_size);
652 if (nprps <= (256 / 8)) {
653 pool = dev->prp_small_pool;
656 pool = dev->prp_page_pool;
660 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
662 iod->first_dma = dma_addr;
664 return BLK_STS_RESOURCE;
667 iod->first_dma = prp_dma;
670 if (i == page_size >> 3) {
671 __le64 *old_prp_list = prp_list;
672 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
674 return BLK_STS_RESOURCE;
675 list[iod->npages++] = prp_list;
676 prp_list[0] = old_prp_list[i - 1];
677 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
680 prp_list[i++] = cpu_to_le64(dma_addr);
681 dma_len -= page_size;
682 dma_addr += page_size;
688 if (unlikely(dma_len < 0))
691 dma_addr = sg_dma_address(sg);
692 dma_len = sg_dma_len(sg);
696 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
697 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
702 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
703 "Invalid SGL for payload:%d nents:%d\n",
704 blk_rq_payload_bytes(req), iod->nents);
705 return BLK_STS_IOERR;
708 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
709 struct scatterlist *sg)
711 sge->addr = cpu_to_le64(sg_dma_address(sg));
712 sge->length = cpu_to_le32(sg_dma_len(sg));
713 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
716 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
717 dma_addr_t dma_addr, int entries)
719 sge->addr = cpu_to_le64(dma_addr);
720 if (entries < SGES_PER_PAGE) {
721 sge->length = cpu_to_le32(entries * sizeof(*sge));
722 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
724 sge->length = cpu_to_le32(PAGE_SIZE);
725 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
729 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
730 struct request *req, struct nvme_rw_command *cmd, int entries)
732 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
733 struct dma_pool *pool;
734 struct nvme_sgl_desc *sg_list;
735 struct scatterlist *sg = iod->sg;
739 /* setting the transfer type as SGL */
740 cmd->flags = NVME_CMD_SGL_METABUF;
743 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
747 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
748 pool = dev->prp_small_pool;
751 pool = dev->prp_page_pool;
755 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
758 return BLK_STS_RESOURCE;
761 nvme_pci_iod_list(req)[0] = sg_list;
762 iod->first_dma = sgl_dma;
764 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
767 if (i == SGES_PER_PAGE) {
768 struct nvme_sgl_desc *old_sg_desc = sg_list;
769 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
771 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
773 return BLK_STS_RESOURCE;
776 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
777 sg_list[i++] = *link;
778 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
781 nvme_pci_sgl_set_data(&sg_list[i++], sg);
783 } while (--entries > 0);
788 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
789 struct nvme_command *cmnd)
791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
792 struct request_queue *q = req->q;
793 enum dma_data_direction dma_dir = rq_data_dir(req) ?
794 DMA_TO_DEVICE : DMA_FROM_DEVICE;
795 blk_status_t ret = BLK_STS_IOERR;
798 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
799 iod->nents = blk_rq_map_sg(q, req, iod->sg);
803 ret = BLK_STS_RESOURCE;
804 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
810 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
812 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
814 if (ret != BLK_STS_OK)
818 if (blk_integrity_rq(req)) {
819 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
822 sg_init_table(&iod->meta_sg, 1);
823 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
826 if (req_op(req) == REQ_OP_WRITE)
827 nvme_dif_remap(req, nvme_dif_prep);
829 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
833 if (blk_integrity_rq(req))
834 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
838 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
843 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
845 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
846 enum dma_data_direction dma_dir = rq_data_dir(req) ?
847 DMA_TO_DEVICE : DMA_FROM_DEVICE;
850 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
851 if (blk_integrity_rq(req)) {
852 if (req_op(req) == REQ_OP_READ)
853 nvme_dif_remap(req, nvme_dif_complete);
854 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
858 nvme_cleanup_cmd(req);
859 nvme_free_iod(dev, req);
863 * NOTE: ns is NULL when called on the admin queue.
865 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
866 const struct blk_mq_queue_data *bd)
868 struct nvme_ns *ns = hctx->queue->queuedata;
869 struct nvme_queue *nvmeq = hctx->driver_data;
870 struct nvme_dev *dev = nvmeq->dev;
871 struct request *req = bd->rq;
872 struct nvme_command cmnd;
875 ret = nvme_setup_cmd(ns, req, &cmnd);
879 ret = nvme_init_iod(req, dev);
883 if (blk_rq_nr_phys_segments(req)) {
884 ret = nvme_map_data(dev, req, &cmnd);
886 goto out_cleanup_iod;
889 blk_mq_start_request(req);
891 spin_lock_irq(&nvmeq->q_lock);
892 if (unlikely(nvmeq->cq_vector < 0)) {
894 spin_unlock_irq(&nvmeq->q_lock);
895 goto out_cleanup_iod;
897 __nvme_submit_cmd(nvmeq, &cmnd);
898 nvme_process_cq(nvmeq);
899 spin_unlock_irq(&nvmeq->q_lock);
902 nvme_free_iod(dev, req);
904 nvme_cleanup_cmd(req);
908 static void nvme_pci_complete_rq(struct request *req)
910 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
912 nvme_unmap_data(iod->nvmeq->dev, req);
913 nvme_complete_rq(req);
916 /* We read the CQE phase first to check if the rest of the entry is valid */
917 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
920 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
923 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
925 u16 head = nvmeq->cq_head;
927 if (likely(nvmeq->cq_vector >= 0)) {
928 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
930 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
934 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
935 struct nvme_completion *cqe)
939 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
940 dev_warn(nvmeq->dev->ctrl.device,
941 "invalid id %d completed on queue %d\n",
942 cqe->command_id, le16_to_cpu(cqe->sq_id));
947 * AEN requests are special as they don't time out and can
948 * survive any kind of queue freeze and often don't respond to
949 * aborts. We don't even bother to allocate a struct request
950 * for them but rather special case them here.
952 if (unlikely(nvmeq->qid == 0 &&
953 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
954 nvme_complete_async_event(&nvmeq->dev->ctrl,
955 cqe->status, &cqe->result);
960 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
961 nvme_end_request(req, cqe->status, cqe->result);
964 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
965 struct nvme_completion *cqe)
967 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
968 *cqe = nvmeq->cqes[nvmeq->cq_head];
970 if (++nvmeq->cq_head == nvmeq->q_depth) {
972 nvmeq->cq_phase = !nvmeq->cq_phase;
979 static void nvme_process_cq(struct nvme_queue *nvmeq)
981 struct nvme_completion cqe;
984 while (nvme_read_cqe(nvmeq, &cqe)) {
985 nvme_handle_cqe(nvmeq, &cqe);
990 nvme_ring_cq_doorbell(nvmeq);
993 static irqreturn_t nvme_irq(int irq, void *data)
996 struct nvme_queue *nvmeq = data;
997 spin_lock(&nvmeq->q_lock);
998 nvme_process_cq(nvmeq);
999 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1000 nvmeq->cqe_seen = 0;
1001 spin_unlock(&nvmeq->q_lock);
1005 static irqreturn_t nvme_irq_check(int irq, void *data)
1007 struct nvme_queue *nvmeq = data;
1008 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1009 return IRQ_WAKE_THREAD;
1013 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
1015 struct nvme_completion cqe;
1016 int found = 0, consumed = 0;
1018 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
1021 spin_lock_irq(&nvmeq->q_lock);
1022 while (nvme_read_cqe(nvmeq, &cqe)) {
1023 nvme_handle_cqe(nvmeq, &cqe);
1026 if (tag == cqe.command_id) {
1033 nvme_ring_cq_doorbell(nvmeq);
1034 spin_unlock_irq(&nvmeq->q_lock);
1039 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1041 struct nvme_queue *nvmeq = hctx->driver_data;
1043 return __nvme_poll(nvmeq, tag);
1046 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1048 struct nvme_dev *dev = to_nvme_dev(ctrl);
1049 struct nvme_queue *nvmeq = &dev->queues[0];
1050 struct nvme_command c;
1052 memset(&c, 0, sizeof(c));
1053 c.common.opcode = nvme_admin_async_event;
1054 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1056 spin_lock_irq(&nvmeq->q_lock);
1057 __nvme_submit_cmd(nvmeq, &c);
1058 spin_unlock_irq(&nvmeq->q_lock);
1061 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1063 struct nvme_command c;
1065 memset(&c, 0, sizeof(c));
1066 c.delete_queue.opcode = opcode;
1067 c.delete_queue.qid = cpu_to_le16(id);
1069 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1072 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1073 struct nvme_queue *nvmeq)
1075 struct nvme_command c;
1076 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1079 * Note: we (ab)use the fact that the prp fields survive if no data
1080 * is attached to the request.
1082 memset(&c, 0, sizeof(c));
1083 c.create_cq.opcode = nvme_admin_create_cq;
1084 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1085 c.create_cq.cqid = cpu_to_le16(qid);
1086 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1087 c.create_cq.cq_flags = cpu_to_le16(flags);
1088 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1090 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1093 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1094 struct nvme_queue *nvmeq)
1096 struct nvme_command c;
1097 int flags = NVME_QUEUE_PHYS_CONTIG;
1100 * Note: we (ab)use the fact that the prp fields survive if no data
1101 * is attached to the request.
1103 memset(&c, 0, sizeof(c));
1104 c.create_sq.opcode = nvme_admin_create_sq;
1105 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1106 c.create_sq.sqid = cpu_to_le16(qid);
1107 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1108 c.create_sq.sq_flags = cpu_to_le16(flags);
1109 c.create_sq.cqid = cpu_to_le16(qid);
1111 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1114 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1116 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1119 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1121 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1124 static void abort_endio(struct request *req, blk_status_t error)
1126 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1127 struct nvme_queue *nvmeq = iod->nvmeq;
1129 dev_warn(nvmeq->dev->ctrl.device,
1130 "Abort status: 0x%x", nvme_req(req)->status);
1131 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1132 blk_mq_free_request(req);
1135 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1138 /* If true, indicates loss of adapter communication, possibly by a
1139 * NVMe Subsystem reset.
1141 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1143 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1144 switch (dev->ctrl.state) {
1145 case NVME_CTRL_RESETTING:
1146 case NVME_CTRL_CONNECTING:
1152 /* We shouldn't reset unless the controller is on fatal error state
1153 * _or_ if we lost the communication with it.
1155 if (!(csts & NVME_CSTS_CFS) && !nssro)
1161 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1163 /* Read a config register to help see what died. */
1167 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1169 if (result == PCIBIOS_SUCCESSFUL)
1170 dev_warn(dev->ctrl.device,
1171 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1174 dev_warn(dev->ctrl.device,
1175 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1179 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1181 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1182 struct nvme_queue *nvmeq = iod->nvmeq;
1183 struct nvme_dev *dev = nvmeq->dev;
1184 struct request *abort_req;
1185 struct nvme_command cmd;
1186 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1188 /* If PCI error recovery process is happening, we cannot reset or
1189 * the recovery mechanism will surely fail.
1192 if (pci_channel_offline(to_pci_dev(dev->dev)))
1193 return BLK_EH_RESET_TIMER;
1196 * Reset immediately if the controller is failed
1198 if (nvme_should_reset(dev, csts)) {
1199 nvme_warn_reset(dev, csts);
1200 nvme_dev_disable(dev, false);
1201 nvme_reset_ctrl(&dev->ctrl);
1202 return BLK_EH_HANDLED;
1206 * Did we miss an interrupt?
1208 if (__nvme_poll(nvmeq, req->tag)) {
1209 dev_warn(dev->ctrl.device,
1210 "I/O %d QID %d timeout, completion polled\n",
1211 req->tag, nvmeq->qid);
1212 return BLK_EH_HANDLED;
1216 * Shutdown immediately if controller times out while starting. The
1217 * reset work will see the pci device disabled when it gets the forced
1218 * cancellation error. All outstanding requests are completed on
1219 * shutdown, so we return BLK_EH_HANDLED.
1221 switch (dev->ctrl.state) {
1222 case NVME_CTRL_CONNECTING:
1223 case NVME_CTRL_RESETTING:
1224 dev_warn(dev->ctrl.device,
1225 "I/O %d QID %d timeout, disable controller\n",
1226 req->tag, nvmeq->qid);
1227 nvme_dev_disable(dev, false);
1228 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1229 return BLK_EH_HANDLED;
1235 * Shutdown the controller immediately and schedule a reset if the
1236 * command was already aborted once before and still hasn't been
1237 * returned to the driver, or if this is the admin queue.
1239 if (!nvmeq->qid || iod->aborted) {
1240 dev_warn(dev->ctrl.device,
1241 "I/O %d QID %d timeout, reset controller\n",
1242 req->tag, nvmeq->qid);
1243 nvme_dev_disable(dev, false);
1244 nvme_reset_ctrl(&dev->ctrl);
1247 * Mark the request as handled, since the inline shutdown
1248 * forces all outstanding requests to complete.
1250 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1251 return BLK_EH_HANDLED;
1254 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1255 atomic_inc(&dev->ctrl.abort_limit);
1256 return BLK_EH_RESET_TIMER;
1260 memset(&cmd, 0, sizeof(cmd));
1261 cmd.abort.opcode = nvme_admin_abort_cmd;
1262 cmd.abort.cid = req->tag;
1263 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1265 dev_warn(nvmeq->dev->ctrl.device,
1266 "I/O %d QID %d timeout, aborting\n",
1267 req->tag, nvmeq->qid);
1269 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1270 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1271 if (IS_ERR(abort_req)) {
1272 atomic_inc(&dev->ctrl.abort_limit);
1273 return BLK_EH_RESET_TIMER;
1276 abort_req->timeout = ADMIN_TIMEOUT;
1277 abort_req->end_io_data = NULL;
1278 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1281 * The aborted req will be completed on receiving the abort req.
1282 * We enable the timer again. If hit twice, it'll cause a device reset,
1283 * as the device then is in a faulty state.
1285 return BLK_EH_RESET_TIMER;
1288 static void nvme_free_queue(struct nvme_queue *nvmeq)
1290 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1291 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1293 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1294 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1297 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1301 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1302 dev->ctrl.queue_count--;
1303 nvme_free_queue(&dev->queues[i]);
1308 * nvme_suspend_queue - put queue into suspended state
1309 * @nvmeq - queue to suspend
1311 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1315 spin_lock_irq(&nvmeq->q_lock);
1316 if (nvmeq->cq_vector == -1) {
1317 spin_unlock_irq(&nvmeq->q_lock);
1320 vector = nvmeq->cq_vector;
1321 nvmeq->dev->online_queues--;
1322 nvmeq->cq_vector = -1;
1323 spin_unlock_irq(&nvmeq->q_lock);
1325 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1326 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1328 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1333 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1335 struct nvme_queue *nvmeq = &dev->queues[0];
1338 nvme_shutdown_ctrl(&dev->ctrl);
1340 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1342 spin_lock_irq(&nvmeq->q_lock);
1343 nvme_process_cq(nvmeq);
1344 spin_unlock_irq(&nvmeq->q_lock);
1347 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1350 int q_depth = dev->q_depth;
1351 unsigned q_size_aligned = roundup(q_depth * entry_size,
1352 dev->ctrl.page_size);
1354 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1355 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1356 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1357 q_depth = div_u64(mem_per_q, entry_size);
1360 * Ensure the reduced q_depth is above some threshold where it
1361 * would be better to map queues in system memory with the
1371 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1374 /* CMB SQEs will be mapped before creation */
1375 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1378 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1379 &nvmeq->sq_dma_addr, GFP_KERNEL);
1380 if (!nvmeq->sq_cmds)
1385 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1387 struct nvme_queue *nvmeq = &dev->queues[qid];
1389 if (dev->ctrl.queue_count > qid)
1392 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1393 &nvmeq->cq_dma_addr, GFP_KERNEL);
1397 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1400 nvmeq->q_dmadev = dev->dev;
1402 spin_lock_init(&nvmeq->q_lock);
1404 nvmeq->cq_phase = 1;
1405 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1406 nvmeq->q_depth = depth;
1408 nvmeq->cq_vector = -1;
1409 dev->ctrl.queue_count++;
1414 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1415 nvmeq->cq_dma_addr);
1420 static int queue_request_irq(struct nvme_queue *nvmeq)
1422 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1423 int nr = nvmeq->dev->ctrl.instance;
1425 if (use_threaded_interrupts) {
1426 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1427 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1429 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1430 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1434 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1436 struct nvme_dev *dev = nvmeq->dev;
1438 spin_lock_irq(&nvmeq->q_lock);
1441 nvmeq->cq_phase = 1;
1442 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1443 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1444 nvme_dbbuf_init(dev, nvmeq, qid);
1445 dev->online_queues++;
1446 spin_unlock_irq(&nvmeq->q_lock);
1449 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1451 struct nvme_dev *dev = nvmeq->dev;
1454 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1455 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1456 dev->ctrl.page_size);
1457 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1458 nvmeq->sq_cmds_io = dev->cmb + offset;
1462 * A queue's vector matches the queue identifier unless the controller
1463 * has only one vector available.
1465 nvmeq->cq_vector = dev->num_vecs == 1 ? 0 : qid;
1466 result = adapter_alloc_cq(dev, qid, nvmeq);
1468 goto release_vector;
1470 result = adapter_alloc_sq(dev, qid, nvmeq);
1474 nvme_init_queue(nvmeq, qid);
1475 result = queue_request_irq(nvmeq);
1482 dev->online_queues--;
1483 adapter_delete_sq(dev, qid);
1485 adapter_delete_cq(dev, qid);
1487 nvmeq->cq_vector = -1;
1491 static const struct blk_mq_ops nvme_mq_admin_ops = {
1492 .queue_rq = nvme_queue_rq,
1493 .complete = nvme_pci_complete_rq,
1494 .init_hctx = nvme_admin_init_hctx,
1495 .exit_hctx = nvme_admin_exit_hctx,
1496 .init_request = nvme_init_request,
1497 .timeout = nvme_timeout,
1500 static const struct blk_mq_ops nvme_mq_ops = {
1501 .queue_rq = nvme_queue_rq,
1502 .complete = nvme_pci_complete_rq,
1503 .init_hctx = nvme_init_hctx,
1504 .init_request = nvme_init_request,
1505 .map_queues = nvme_pci_map_queues,
1506 .timeout = nvme_timeout,
1510 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1512 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1514 * If the controller was reset during removal, it's possible
1515 * user requests may be waiting on a stopped queue. Start the
1516 * queue to flush these to completion.
1518 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1519 blk_cleanup_queue(dev->ctrl.admin_q);
1520 blk_mq_free_tag_set(&dev->admin_tagset);
1524 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1526 if (!dev->ctrl.admin_q) {
1527 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1528 dev->admin_tagset.nr_hw_queues = 1;
1530 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1531 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1532 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1533 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1534 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1535 dev->admin_tagset.driver_data = dev;
1537 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1539 dev->ctrl.admin_tagset = &dev->admin_tagset;
1541 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1542 if (IS_ERR(dev->ctrl.admin_q)) {
1543 blk_mq_free_tag_set(&dev->admin_tagset);
1546 if (!blk_get_queue(dev->ctrl.admin_q)) {
1547 nvme_dev_remove_admin(dev);
1548 dev->ctrl.admin_q = NULL;
1552 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1557 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1559 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1562 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1564 struct pci_dev *pdev = to_pci_dev(dev->dev);
1566 if (size <= dev->bar_mapped_size)
1568 if (size > pci_resource_len(pdev, 0))
1572 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1574 dev->bar_mapped_size = 0;
1577 dev->bar_mapped_size = size;
1578 dev->dbs = dev->bar + NVME_REG_DBS;
1583 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1587 struct nvme_queue *nvmeq;
1589 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1593 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1594 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1596 if (dev->subsystem &&
1597 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1598 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1600 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1604 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1608 nvmeq = &dev->queues[0];
1609 aqa = nvmeq->q_depth - 1;
1612 writel(aqa, dev->bar + NVME_REG_AQA);
1613 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1614 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1616 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1620 nvmeq->cq_vector = 0;
1621 nvme_init_queue(nvmeq, 0);
1622 result = queue_request_irq(nvmeq);
1624 nvmeq->cq_vector = -1;
1631 static int nvme_create_io_queues(struct nvme_dev *dev)
1636 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1637 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1643 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1644 for (i = dev->online_queues; i <= max; i++) {
1645 ret = nvme_create_queue(&dev->queues[i], i);
1651 * Ignore failing Create SQ/CQ commands, we can continue with less
1652 * than the desired amount of queues, and even a controller without
1653 * I/O queues can still be used to issue admin commands. This might
1654 * be useful to upgrade a buggy firmware for example.
1656 return ret >= 0 ? 0 : ret;
1659 static ssize_t nvme_cmb_show(struct device *dev,
1660 struct device_attribute *attr,
1663 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1665 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1666 ndev->cmbloc, ndev->cmbsz);
1668 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1670 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1672 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1674 return 1ULL << (12 + 4 * szu);
1677 static u32 nvme_cmb_size(struct nvme_dev *dev)
1679 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1682 static void nvme_map_cmb(struct nvme_dev *dev)
1685 resource_size_t bar_size;
1686 struct pci_dev *pdev = to_pci_dev(dev->dev);
1689 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1692 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1697 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1698 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1699 bar = NVME_CMB_BIR(dev->cmbloc);
1700 bar_size = pci_resource_len(pdev, bar);
1702 if (offset > bar_size)
1706 * Controllers may support a CMB size larger than their BAR,
1707 * for example, due to being behind a bridge. Reduce the CMB to
1708 * the reported size of the BAR
1710 if (size > bar_size - offset)
1711 size = bar_size - offset;
1713 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1716 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1717 dev->cmb_size = size;
1719 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1720 &dev_attr_cmb.attr, NULL))
1721 dev_warn(dev->ctrl.device,
1722 "failed to add sysfs attribute for CMB\n");
1725 static inline void nvme_release_cmb(struct nvme_dev *dev)
1730 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1731 &dev_attr_cmb.attr, NULL);
1736 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1738 u64 dma_addr = dev->host_mem_descs_dma;
1739 struct nvme_command c;
1742 memset(&c, 0, sizeof(c));
1743 c.features.opcode = nvme_admin_set_features;
1744 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1745 c.features.dword11 = cpu_to_le32(bits);
1746 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1747 ilog2(dev->ctrl.page_size));
1748 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1749 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1750 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1752 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1754 dev_warn(dev->ctrl.device,
1755 "failed to set host mem (err %d, flags %#x).\n",
1761 static void nvme_free_host_mem(struct nvme_dev *dev)
1765 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1766 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1767 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1769 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1770 le64_to_cpu(desc->addr));
1773 kfree(dev->host_mem_desc_bufs);
1774 dev->host_mem_desc_bufs = NULL;
1775 dma_free_coherent(dev->dev,
1776 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1777 dev->host_mem_descs, dev->host_mem_descs_dma);
1778 dev->host_mem_descs = NULL;
1779 dev->nr_host_mem_descs = 0;
1782 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1785 struct nvme_host_mem_buf_desc *descs;
1786 u32 max_entries, len;
1787 dma_addr_t descs_dma;
1792 tmp = (preferred + chunk_size - 1);
1793 do_div(tmp, chunk_size);
1796 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1797 max_entries = dev->ctrl.hmmaxd;
1799 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1800 &descs_dma, GFP_KERNEL);
1804 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1806 goto out_free_descs;
1808 for (size = 0; size < preferred && i < max_entries; size += len) {
1809 dma_addr_t dma_addr;
1811 len = min_t(u64, chunk_size, preferred - size);
1812 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1813 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1817 descs[i].addr = cpu_to_le64(dma_addr);
1818 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1825 dev->nr_host_mem_descs = i;
1826 dev->host_mem_size = size;
1827 dev->host_mem_descs = descs;
1828 dev->host_mem_descs_dma = descs_dma;
1829 dev->host_mem_desc_bufs = bufs;
1834 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1836 dma_free_coherent(dev->dev, size, bufs[i],
1837 le64_to_cpu(descs[i].addr));
1842 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1845 dev->host_mem_descs = NULL;
1849 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1853 /* start big and work our way down */
1854 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1855 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1857 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1858 if (!min || dev->host_mem_size >= min)
1860 nvme_free_host_mem(dev);
1867 static int nvme_setup_host_mem(struct nvme_dev *dev)
1869 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1870 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1871 u64 min = (u64)dev->ctrl.hmmin * 4096;
1872 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1875 preferred = min(preferred, max);
1877 dev_warn(dev->ctrl.device,
1878 "min host memory (%lld MiB) above limit (%d MiB).\n",
1879 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1880 nvme_free_host_mem(dev);
1885 * If we already have a buffer allocated check if we can reuse it.
1887 if (dev->host_mem_descs) {
1888 if (dev->host_mem_size >= min)
1889 enable_bits |= NVME_HOST_MEM_RETURN;
1891 nvme_free_host_mem(dev);
1894 if (!dev->host_mem_descs) {
1895 if (nvme_alloc_host_mem(dev, min, preferred)) {
1896 dev_warn(dev->ctrl.device,
1897 "failed to allocate host memory buffer.\n");
1898 return 0; /* controller must work without HMB */
1901 dev_info(dev->ctrl.device,
1902 "allocated %lld MiB host memory buffer.\n",
1903 dev->host_mem_size >> ilog2(SZ_1M));
1906 ret = nvme_set_host_mem(dev, enable_bits);
1908 nvme_free_host_mem(dev);
1912 static int nvme_setup_io_queues(struct nvme_dev *dev)
1914 struct nvme_queue *adminq = &dev->queues[0];
1915 struct pci_dev *pdev = to_pci_dev(dev->dev);
1916 int result, nr_io_queues;
1919 struct irq_affinity affd = {
1923 nr_io_queues = num_possible_cpus();
1924 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1928 if (nr_io_queues == 0)
1931 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1932 result = nvme_cmb_qdepth(dev, nr_io_queues,
1933 sizeof(struct nvme_command));
1935 dev->q_depth = result;
1937 nvme_release_cmb(dev);
1941 size = db_bar_size(dev, nr_io_queues);
1942 result = nvme_remap_bar(dev, size);
1945 if (!--nr_io_queues)
1948 adminq->q_db = dev->dbs;
1950 /* Deregister the admin queue's interrupt */
1951 pci_free_irq(pdev, 0, adminq);
1954 * If we enable msix early due to not intx, disable it again before
1955 * setting up the full range we need.
1957 pci_free_irq_vectors(pdev);
1958 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1959 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1962 dev->num_vecs = result;
1963 dev->max_qid = max(result - 1, 1);
1966 * Should investigate if there's a performance win from allocating
1967 * more queues than interrupt vectors; it might allow the submission
1968 * path to scale better, even if the receive path is limited by the
1969 * number of interrupts.
1972 result = queue_request_irq(adminq);
1974 adminq->cq_vector = -1;
1977 return nvme_create_io_queues(dev);
1980 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1982 struct nvme_queue *nvmeq = req->end_io_data;
1984 blk_mq_free_request(req);
1985 complete(&nvmeq->dev->ioq_wait);
1988 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1990 struct nvme_queue *nvmeq = req->end_io_data;
1993 unsigned long flags;
1996 * We might be called with the AQ q_lock held
1997 * and the I/O queue q_lock should always
1998 * nest inside the AQ one.
2000 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
2001 SINGLE_DEPTH_NESTING);
2002 nvme_process_cq(nvmeq);
2003 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
2006 nvme_del_queue_end(req, error);
2009 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2011 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2012 struct request *req;
2013 struct nvme_command cmd;
2015 memset(&cmd, 0, sizeof(cmd));
2016 cmd.delete_queue.opcode = opcode;
2017 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2019 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2021 return PTR_ERR(req);
2023 req->timeout = ADMIN_TIMEOUT;
2024 req->end_io_data = nvmeq;
2026 blk_execute_rq_nowait(q, NULL, req, false,
2027 opcode == nvme_admin_delete_cq ?
2028 nvme_del_cq_end : nvme_del_queue_end);
2032 static void nvme_disable_io_queues(struct nvme_dev *dev)
2034 int pass, queues = dev->online_queues - 1;
2035 unsigned long timeout;
2036 u8 opcode = nvme_admin_delete_sq;
2038 for (pass = 0; pass < 2; pass++) {
2039 int sent = 0, i = queues;
2041 reinit_completion(&dev->ioq_wait);
2043 timeout = ADMIN_TIMEOUT;
2044 for (; i > 0; i--, sent++)
2045 if (nvme_delete_queue(&dev->queues[i], opcode))
2049 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2055 opcode = nvme_admin_delete_cq;
2060 * return error value only when tagset allocation failed
2062 static int nvme_dev_add(struct nvme_dev *dev)
2066 if (!dev->ctrl.tagset) {
2067 dev->tagset.ops = &nvme_mq_ops;
2068 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2069 dev->tagset.timeout = NVME_IO_TIMEOUT;
2070 dev->tagset.numa_node = dev_to_node(dev->dev);
2071 dev->tagset.queue_depth =
2072 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2073 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2074 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2075 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2076 nvme_pci_cmd_size(dev, true));
2078 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2079 dev->tagset.driver_data = dev;
2081 ret = blk_mq_alloc_tag_set(&dev->tagset);
2083 dev_warn(dev->ctrl.device,
2084 "IO queues tagset allocation failed %d\n", ret);
2087 dev->ctrl.tagset = &dev->tagset;
2089 nvme_dbbuf_set(dev);
2091 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2093 /* Free previously allocated queues that are no longer usable */
2094 nvme_free_queues(dev, dev->online_queues);
2100 static int nvme_pci_enable(struct nvme_dev *dev)
2102 int result = -ENOMEM;
2103 struct pci_dev *pdev = to_pci_dev(dev->dev);
2105 if (pci_enable_device_mem(pdev))
2108 pci_set_master(pdev);
2110 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2111 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2114 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2120 * Some devices and/or platforms don't advertise or work with INTx
2121 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2122 * adjust this later.
2124 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2128 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2130 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2132 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2133 dev->dbs = dev->bar + 4096;
2136 * Temporary fix for the Apple controller found in the MacBook8,1 and
2137 * some MacBook7,1 to avoid controller resets and data loss.
2139 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2141 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2142 "set queue depth=%u to work around controller resets\n",
2144 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2145 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2146 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2148 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2149 "set queue depth=%u\n", dev->q_depth);
2154 pci_enable_pcie_error_reporting(pdev);
2155 pci_save_state(pdev);
2159 pci_disable_device(pdev);
2163 static void nvme_dev_unmap(struct nvme_dev *dev)
2167 pci_release_mem_regions(to_pci_dev(dev->dev));
2170 static void nvme_pci_disable(struct nvme_dev *dev)
2172 struct pci_dev *pdev = to_pci_dev(dev->dev);
2174 nvme_release_cmb(dev);
2175 pci_free_irq_vectors(pdev);
2177 if (pci_is_enabled(pdev)) {
2178 pci_disable_pcie_error_reporting(pdev);
2179 pci_disable_device(pdev);
2183 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2187 struct pci_dev *pdev = to_pci_dev(dev->dev);
2189 mutex_lock(&dev->shutdown_lock);
2190 if (pci_is_enabled(pdev)) {
2191 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2193 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2194 dev->ctrl.state == NVME_CTRL_RESETTING)
2195 nvme_start_freeze(&dev->ctrl);
2196 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2197 pdev->error_state != pci_channel_io_normal);
2201 * Give the controller a chance to complete all entered requests if
2202 * doing a safe shutdown.
2206 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2209 nvme_stop_queues(&dev->ctrl);
2211 if (!dead && dev->ctrl.queue_count > 0) {
2213 * If the controller is still alive tell it to stop using the
2214 * host memory buffer. In theory the shutdown / reset should
2215 * make sure that it doesn't access the host memoery anymore,
2216 * but I'd rather be safe than sorry..
2218 if (dev->host_mem_descs)
2219 nvme_set_host_mem(dev, 0);
2220 nvme_disable_io_queues(dev);
2221 nvme_disable_admin_queue(dev, shutdown);
2223 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2224 nvme_suspend_queue(&dev->queues[i]);
2226 nvme_pci_disable(dev);
2228 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2229 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2232 * The driver will not be starting up queues again if shutting down so
2233 * must flush all entered requests to their failed completion to avoid
2234 * deadlocking blk-mq hot-cpu notifier.
2237 nvme_start_queues(&dev->ctrl);
2238 mutex_unlock(&dev->shutdown_lock);
2241 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2243 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2244 PAGE_SIZE, PAGE_SIZE, 0);
2245 if (!dev->prp_page_pool)
2248 /* Optimisation for I/Os between 4k and 128k */
2249 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2251 if (!dev->prp_small_pool) {
2252 dma_pool_destroy(dev->prp_page_pool);
2258 static void nvme_release_prp_pools(struct nvme_dev *dev)
2260 dma_pool_destroy(dev->prp_page_pool);
2261 dma_pool_destroy(dev->prp_small_pool);
2264 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2266 struct nvme_dev *dev = to_nvme_dev(ctrl);
2268 nvme_dbbuf_dma_free(dev);
2269 put_device(dev->dev);
2270 if (dev->tagset.tags)
2271 blk_mq_free_tag_set(&dev->tagset);
2272 if (dev->ctrl.admin_q)
2273 blk_put_queue(dev->ctrl.admin_q);
2275 free_opal_dev(dev->ctrl.opal_dev);
2279 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2281 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2283 nvme_get_ctrl(&dev->ctrl);
2284 nvme_dev_disable(dev, false);
2285 if (!queue_work(nvme_wq, &dev->remove_work))
2286 nvme_put_ctrl(&dev->ctrl);
2289 static void nvme_reset_work(struct work_struct *work)
2291 struct nvme_dev *dev =
2292 container_of(work, struct nvme_dev, ctrl.reset_work);
2293 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2294 int result = -ENODEV;
2295 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2297 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2301 * If we're called to reset a live controller first shut it down before
2304 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2305 nvme_dev_disable(dev, false);
2308 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2309 * initializing procedure here.
2311 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2312 dev_warn(dev->ctrl.device,
2313 "failed to mark controller CONNECTING\n");
2317 result = nvme_pci_enable(dev);
2321 result = nvme_pci_configure_admin_queue(dev);
2325 result = nvme_alloc_admin_tags(dev);
2329 result = nvme_init_identify(&dev->ctrl);
2333 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2334 if (!dev->ctrl.opal_dev)
2335 dev->ctrl.opal_dev =
2336 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2337 else if (was_suspend)
2338 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2340 free_opal_dev(dev->ctrl.opal_dev);
2341 dev->ctrl.opal_dev = NULL;
2344 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2345 result = nvme_dbbuf_dma_alloc(dev);
2348 "unable to allocate dma for dbbuf\n");
2351 if (dev->ctrl.hmpre) {
2352 result = nvme_setup_host_mem(dev);
2357 result = nvme_setup_io_queues(dev);
2362 * Keep the controller around but remove all namespaces if we don't have
2363 * any working I/O queue.
2365 if (dev->online_queues < 2) {
2366 dev_warn(dev->ctrl.device, "IO queues not created\n");
2367 nvme_kill_queues(&dev->ctrl);
2368 nvme_remove_namespaces(&dev->ctrl);
2369 new_state = NVME_CTRL_ADMIN_ONLY;
2371 nvme_start_queues(&dev->ctrl);
2372 nvme_wait_freeze(&dev->ctrl);
2373 /* hit this only when allocate tagset fails */
2374 if (nvme_dev_add(dev))
2375 new_state = NVME_CTRL_ADMIN_ONLY;
2376 nvme_unfreeze(&dev->ctrl);
2380 * If only admin queue live, keep it to do further investigation or
2383 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2384 dev_warn(dev->ctrl.device,
2385 "failed to mark controller state %d\n", new_state);
2389 nvme_start_ctrl(&dev->ctrl);
2393 nvme_remove_dead_ctrl(dev, result);
2396 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2398 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2399 struct pci_dev *pdev = to_pci_dev(dev->dev);
2401 nvme_kill_queues(&dev->ctrl);
2402 if (pci_get_drvdata(pdev))
2403 device_release_driver(&pdev->dev);
2404 nvme_put_ctrl(&dev->ctrl);
2407 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2409 *val = readl(to_nvme_dev(ctrl)->bar + off);
2413 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2415 writel(val, to_nvme_dev(ctrl)->bar + off);
2419 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2421 *val = readq(to_nvme_dev(ctrl)->bar + off);
2425 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2427 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2429 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2432 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2434 .module = THIS_MODULE,
2435 .flags = NVME_F_METADATA_SUPPORTED,
2436 .reg_read32 = nvme_pci_reg_read32,
2437 .reg_write32 = nvme_pci_reg_write32,
2438 .reg_read64 = nvme_pci_reg_read64,
2439 .free_ctrl = nvme_pci_free_ctrl,
2440 .submit_async_event = nvme_pci_submit_async_event,
2441 .get_address = nvme_pci_get_address,
2444 static int nvme_dev_map(struct nvme_dev *dev)
2446 struct pci_dev *pdev = to_pci_dev(dev->dev);
2448 if (pci_request_mem_regions(pdev, "nvme"))
2451 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2456 pci_release_mem_regions(pdev);
2460 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2462 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2464 * Several Samsung devices seem to drop off the PCIe bus
2465 * randomly when APST is on and uses the deepest sleep state.
2466 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2467 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2468 * 950 PRO 256GB", but it seems to be restricted to two Dell
2471 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2472 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2473 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2474 return NVME_QUIRK_NO_DEEPEST_PS;
2475 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2477 * Samsung SSD 960 EVO drops off the PCIe bus after system
2478 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2479 * within few minutes after bootup on a Coffee Lake board -
2482 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2483 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2484 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2485 return NVME_QUIRK_NO_APST;
2491 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2493 int node, result = -ENOMEM;
2494 struct nvme_dev *dev;
2495 unsigned long quirks = id->driver_data;
2497 node = dev_to_node(&pdev->dev);
2498 if (node == NUMA_NO_NODE)
2499 set_dev_node(&pdev->dev, first_memory_node);
2501 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2505 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2506 sizeof(struct nvme_queue), GFP_KERNEL, node);
2510 dev->dev = get_device(&pdev->dev);
2511 pci_set_drvdata(pdev, dev);
2513 result = nvme_dev_map(dev);
2517 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2518 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2519 mutex_init(&dev->shutdown_lock);
2520 init_completion(&dev->ioq_wait);
2522 result = nvme_setup_prp_pools(dev);
2526 quirks |= check_vendor_combination_bug(pdev);
2528 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2533 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2535 nvme_reset_ctrl(&dev->ctrl);
2540 nvme_release_prp_pools(dev);
2542 nvme_dev_unmap(dev);
2544 put_device(dev->dev);
2551 static void nvme_reset_prepare(struct pci_dev *pdev)
2553 struct nvme_dev *dev = pci_get_drvdata(pdev);
2554 nvme_dev_disable(dev, false);
2557 static void nvme_reset_done(struct pci_dev *pdev)
2559 struct nvme_dev *dev = pci_get_drvdata(pdev);
2560 nvme_reset_ctrl_sync(&dev->ctrl);
2563 static void nvme_shutdown(struct pci_dev *pdev)
2565 struct nvme_dev *dev = pci_get_drvdata(pdev);
2566 nvme_dev_disable(dev, true);
2570 * The driver's remove may be called on a device in a partially initialized
2571 * state. This function must not have any dependencies on the device state in
2574 static void nvme_remove(struct pci_dev *pdev)
2576 struct nvme_dev *dev = pci_get_drvdata(pdev);
2578 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2580 cancel_work_sync(&dev->ctrl.reset_work);
2581 pci_set_drvdata(pdev, NULL);
2583 if (!pci_device_is_present(pdev)) {
2584 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2585 nvme_dev_disable(dev, false);
2588 flush_work(&dev->ctrl.reset_work);
2589 nvme_stop_ctrl(&dev->ctrl);
2590 nvme_remove_namespaces(&dev->ctrl);
2591 nvme_dev_disable(dev, true);
2592 nvme_free_host_mem(dev);
2593 nvme_dev_remove_admin(dev);
2594 nvme_free_queues(dev, 0);
2595 nvme_uninit_ctrl(&dev->ctrl);
2596 nvme_release_prp_pools(dev);
2597 nvme_dev_unmap(dev);
2598 nvme_put_ctrl(&dev->ctrl);
2601 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2606 if (pci_vfs_assigned(pdev)) {
2607 dev_warn(&pdev->dev,
2608 "Cannot disable SR-IOV VFs while assigned\n");
2611 pci_disable_sriov(pdev);
2615 ret = pci_enable_sriov(pdev, numvfs);
2616 return ret ? ret : numvfs;
2619 #ifdef CONFIG_PM_SLEEP
2620 static int nvme_suspend(struct device *dev)
2622 struct pci_dev *pdev = to_pci_dev(dev);
2623 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2625 nvme_dev_disable(ndev, true);
2629 static int nvme_resume(struct device *dev)
2631 struct pci_dev *pdev = to_pci_dev(dev);
2632 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2634 nvme_reset_ctrl(&ndev->ctrl);
2639 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2641 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2642 pci_channel_state_t state)
2644 struct nvme_dev *dev = pci_get_drvdata(pdev);
2647 * A frozen channel requires a reset. When detected, this method will
2648 * shutdown the controller to quiesce. The controller will be restarted
2649 * after the slot reset through driver's slot_reset callback.
2652 case pci_channel_io_normal:
2653 return PCI_ERS_RESULT_CAN_RECOVER;
2654 case pci_channel_io_frozen:
2655 dev_warn(dev->ctrl.device,
2656 "frozen state error detected, reset controller\n");
2657 nvme_dev_disable(dev, false);
2658 return PCI_ERS_RESULT_NEED_RESET;
2659 case pci_channel_io_perm_failure:
2660 dev_warn(dev->ctrl.device,
2661 "failure state error detected, request disconnect\n");
2662 return PCI_ERS_RESULT_DISCONNECT;
2664 return PCI_ERS_RESULT_NEED_RESET;
2667 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2669 struct nvme_dev *dev = pci_get_drvdata(pdev);
2671 dev_info(dev->ctrl.device, "restart after slot reset\n");
2672 pci_restore_state(pdev);
2673 nvme_reset_ctrl(&dev->ctrl);
2674 return PCI_ERS_RESULT_RECOVERED;
2677 static void nvme_error_resume(struct pci_dev *pdev)
2679 pci_cleanup_aer_uncorrect_error_status(pdev);
2682 static const struct pci_error_handlers nvme_err_handler = {
2683 .error_detected = nvme_error_detected,
2684 .slot_reset = nvme_slot_reset,
2685 .resume = nvme_error_resume,
2686 .reset_prepare = nvme_reset_prepare,
2687 .reset_done = nvme_reset_done,
2690 static const struct pci_device_id nvme_id_table[] = {
2691 { PCI_VDEVICE(INTEL, 0x0953),
2692 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2693 NVME_QUIRK_DEALLOCATE_ZEROES, },
2694 { PCI_VDEVICE(INTEL, 0x0a53),
2695 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2696 NVME_QUIRK_DEALLOCATE_ZEROES, },
2697 { PCI_VDEVICE(INTEL, 0x0a54),
2698 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2699 NVME_QUIRK_DEALLOCATE_ZEROES, },
2700 { PCI_VDEVICE(INTEL, 0x0a55),
2701 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2702 NVME_QUIRK_DEALLOCATE_ZEROES, },
2703 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2704 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2705 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2706 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2707 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2708 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2709 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2710 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2711 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2712 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2713 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2714 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2715 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2716 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2717 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2718 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2719 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2720 .driver_data = NVME_QUIRK_LIGHTNVM, },
2721 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2722 .driver_data = NVME_QUIRK_LIGHTNVM, },
2723 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2724 .driver_data = NVME_QUIRK_LIGHTNVM, },
2725 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2726 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2727 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2730 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2732 static struct pci_driver nvme_driver = {
2734 .id_table = nvme_id_table,
2735 .probe = nvme_probe,
2736 .remove = nvme_remove,
2737 .shutdown = nvme_shutdown,
2739 .pm = &nvme_dev_pm_ops,
2741 .sriov_configure = nvme_pci_sriov_configure,
2742 .err_handler = &nvme_err_handler,
2745 static int __init nvme_init(void)
2747 return pci_register_driver(&nvme_driver);
2750 static void __exit nvme_exit(void)
2752 pci_unregister_driver(&nvme_driver);
2753 flush_workqueue(nvme_wq);
2757 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2758 MODULE_LICENSE("GPL");
2759 MODULE_VERSION("1.0");
2760 module_init(nvme_init);
2761 module_exit(nvme_exit);