drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/bitops.h>
  16 #include <linux/blkdev.h>
  17 #include <linux/blk-mq.h>
  18 #include <linux/cpu.h>
  19 #include <linux/delay.h>
  20 #include <linux/errno.h>
  21 #include <linux/fs.h>
  22 #include <linux/genhd.h>
  23 #include <linux/hdreg.h>
  24 #include <linux/idr.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kthread.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/types.h>
  42 #include <linux/io-64-nonatomic-lo-hi.h>
  43 #include <asm/unaligned.h>
  44
  45 #include "nvme.h"
  46
  47 #define NVME_Q_DEPTH            1024
  48 #define NVME_AQ_DEPTH           256
  49 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  50 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  51
  52 unsigned char admin_timeout = 60;
  53 module_param(admin_timeout, byte, 0644);
  54 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  55
  56 unsigned char nvme_io_timeout = 30;
  57 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  58 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  59
  60 unsigned char shutdown_timeout = 5;
  61 module_param(shutdown_timeout, byte, 0644);
  62 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  63
  64 static int use_threaded_interrupts;
  65 module_param(use_threaded_interrupts, int, 0);
  66
  67 static bool use_cmb_sqes = true;
  68 module_param(use_cmb_sqes, bool, 0644);
  69 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  70
  71 static LIST_HEAD(dev_list);
  72 static struct task_struct *nvme_thread;
  73 static struct workqueue_struct *nvme_workq;
  74 static wait_queue_head_t nvme_kthread_wait;
  75
  76 struct nvme_dev;
  77 struct nvme_queue;
  78 struct nvme_iod;
  79
  80 static int nvme_reset(struct nvme_dev *dev);
  81 static void nvme_process_cq(struct nvme_queue *nvmeq);
  82 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod);
  83 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
  84 static void nvme_dev_shutdown(struct nvme_dev *dev);
  85
  86 struct async_cmd_info {
  87         struct kthread_work work;
  88         struct kthread_worker *worker;
  89         struct request *req;
  90         u32 result;
  91         int status;
  92         void *ctx;
  93 };
  94
  95 /*
  96  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  97  */
  98 struct nvme_dev {
  99         struct list_head node;
 100         struct nvme_queue **queues;
 101         struct blk_mq_tag_set tagset;
 102         struct blk_mq_tag_set admin_tagset;
 103         u32 __iomem *dbs;
 104         struct device *dev;
 105         struct dma_pool *prp_page_pool;
 106         struct dma_pool *prp_small_pool;
 107         unsigned queue_count;
 108         unsigned online_queues;
 109         unsigned max_qid;
 110         int q_depth;
 111         u32 db_stride;
 112         struct msix_entry *entry;
 113         void __iomem *bar;
 114         struct work_struct reset_work;
 115         struct work_struct scan_work;
 116         struct work_struct remove_work;
 117         struct mutex shutdown_lock;
 118         bool subsystem;
 119         void __iomem *cmb;
 120         dma_addr_t cmb_dma_addr;
 121         u64 cmb_size;
 122         u32 cmbsz;
 123         unsigned long flags;
 124 #define NVME_CTRL_RESETTING    0
 125
 126         struct nvme_ctrl ctrl;
 127 };
 128
 129 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 130 {
 131         return container_of(ctrl, struct nvme_dev, ctrl);
 132 }
 133
 134 /*
 135  * An NVM Express queue.  Each device has at least two (one for admin
 136  * commands and one for I/O commands).
 137  */
 138 struct nvme_queue {
 139         struct device *q_dmadev;
 140         struct nvme_dev *dev;
 141         char irqname[24];       /* nvme4294967295-65535\0 */
 142         spinlock_t q_lock;
 143         struct nvme_command *sq_cmds;
 144         struct nvme_command __iomem *sq_cmds_io;
 145         volatile struct nvme_completion *cqes;
 146         struct blk_mq_tags **tags;
 147         dma_addr_t sq_dma_addr;
 148         dma_addr_t cq_dma_addr;
 149         u32 __iomem *q_db;
 150         u16 q_depth;
 151         s16 cq_vector;
 152         u16 sq_head;
 153         u16 sq_tail;
 154         u16 cq_head;
 155         u16 qid;
 156         u8 cq_phase;
 157         u8 cqe_seen;
 158         struct async_cmd_info cmdinfo;
 159 };
 160
 161 /*
 162  * The nvme_iod describes the data in an I/O, including the list of PRP
 163  * entries.  You can't see it in this data structure because C doesn't let
 164  * me express that.  Use nvme_alloc_iod to ensure there's enough space
 165  * allocated to store the PRP list.
 166  */
 167 struct nvme_iod {
 168         unsigned long private;  /* For the use of the submitter of the I/O */
 169         int npages;             /* In the PRP list. 0 means small pool in use */
 170         int offset;             /* Of PRP list */
 171         int nents;              /* Used in scatterlist */
 172         int length;             /* Of data, in bytes */
 173         dma_addr_t first_dma;
 174         struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
 175         struct scatterlist sg[0];
 176 };
 177
 178 /*
 179  * Check we didin't inadvertently grow the command struct
 180  */
 181 static inline void _nvme_check_size(void)
 182 {
 183         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 184         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 185         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 186         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 187         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 188         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 189         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 190         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 191         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 192         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 193         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 194         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 195 }
 196
 197 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
 198                                                 struct nvme_completion *);
 199
 200 struct nvme_cmd_info {
 201         nvme_completion_fn fn;
 202         void *ctx;
 203         int aborted;
 204         struct nvme_queue *nvmeq;
 205         struct nvme_iod iod[0];
 206 };
 207
 208 /*
 209  * Max size of iod being embedded in the request payload
 210  */
 211 #define NVME_INT_PAGES          2
 212 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 213 #define NVME_INT_MASK           0x01
 214
 215 /*
 216  * Will slightly overestimate the number of pages needed.  This is OK
 217  * as it only leads to a small amount of wasted memory for the lifetime of
 218  * the I/O.
 219  */
 220 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 221 {
 222         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 223                                       dev->ctrl.page_size);
 224         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 225 }
 226
 227 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 228 {
 229         unsigned int ret = sizeof(struct nvme_cmd_info);
 230
 231         ret += sizeof(struct nvme_iod);
 232         ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
 233         ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
 234
 235         return ret;
 236 }
 237
 238 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 239                                 unsigned int hctx_idx)
 240 {
 241         struct nvme_dev *dev = data;
 242         struct nvme_queue *nvmeq = dev->queues[0];
 243
 244         WARN_ON(hctx_idx != 0);
 245         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 246         WARN_ON(nvmeq->tags);
 247
 248         hctx->driver_data = nvmeq;
 249         nvmeq->tags = &dev->admin_tagset.tags[0];
 250         return 0;
 251 }
 252
 253 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 254 {
 255         struct nvme_queue *nvmeq = hctx->driver_data;
 256
 257         nvmeq->tags = NULL;
 258 }
 259
 260 static int nvme_admin_init_request(void *data, struct request *req,
 261                                 unsigned int hctx_idx, unsigned int rq_idx,
 262                                 unsigned int numa_node)
 263 {
 264         struct nvme_dev *dev = data;
 265         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 266         struct nvme_queue *nvmeq = dev->queues[0];
 267
 268         BUG_ON(!nvmeq);
 269         cmd->nvmeq = nvmeq;
 270         return 0;
 271 }
 272
 273 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 274                           unsigned int hctx_idx)
 275 {
 276         struct nvme_dev *dev = data;
 277         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 278
 279         if (!nvmeq->tags)
 280                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 281
 282         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 283         hctx->driver_data = nvmeq;
 284         return 0;
 285 }
 286
 287 static int nvme_init_request(void *data, struct request *req,
 288                                 unsigned int hctx_idx, unsigned int rq_idx,
 289                                 unsigned int numa_node)
 290 {
 291         struct nvme_dev *dev = data;
 292         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 293         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 294
 295         BUG_ON(!nvmeq);
 296         cmd->nvmeq = nvmeq;
 297         return 0;
 298 }
 299
 300 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
 301                                 nvme_completion_fn handler)
 302 {
 303         cmd->fn = handler;
 304         cmd->ctx = ctx;
 305         cmd->aborted = 0;
 306         blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
 307 }
 308
 309 static void *iod_get_private(struct nvme_iod *iod)
 310 {
 311         return (void *) (iod->private & ~0x1UL);
 312 }
 313
 314 /*
 315  * If bit 0 is set, the iod is embedded in the request payload.
 316  */
 317 static bool iod_should_kfree(struct nvme_iod *iod)
 318 {
 319         return (iod->private & NVME_INT_MASK) == 0;
 320 }
 321
 322 /* Special values must be less than 0x1000 */
 323 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
 324 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 325 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 326 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 327
 328 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
 329                                                 struct nvme_completion *cqe)
 330 {
 331         if (ctx == CMD_CTX_CANCELLED)
 332                 return;
 333         if (ctx == CMD_CTX_COMPLETED) {
 334                 dev_warn(nvmeq->q_dmadev,
 335                                 "completed id %d twice on queue %d\n",
 336                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 337                 return;
 338         }
 339         if (ctx == CMD_CTX_INVALID) {
 340                 dev_warn(nvmeq->q_dmadev,
 341                                 "invalid id %d completed on queue %d\n",
 342                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 343                 return;
 344         }
 345         dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
 346 }
 347
 348 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
 349 {
 350         void *ctx;
 351
 352         if (fn)
 353                 *fn = cmd->fn;
 354         ctx = cmd->ctx;
 355         cmd->fn = special_completion;
 356         cmd->ctx = CMD_CTX_CANCELLED;
 357         return ctx;
 358 }
 359
 360 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
 361                                                 struct nvme_completion *cqe)
 362 {
 363         u32 result = le32_to_cpup(&cqe->result);
 364         u16 status = le16_to_cpup(&cqe->status) >> 1;
 365
 366         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 367                 ++nvmeq->dev->ctrl.event_limit;
 368         if (status != NVME_SC_SUCCESS)
 369                 return;
 370
 371         switch (result & 0xff07) {
 372         case NVME_AER_NOTICE_NS_CHANGED:
 373                 dev_info(nvmeq->q_dmadev, "rescanning\n");
 374                 queue_work(nvme_workq, &nvmeq->dev->scan_work);
 375         default:
 376                 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
 377         }
 378 }
 379
 380 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
 381                                                 struct nvme_completion *cqe)
 382 {
 383         struct request *req = ctx;
 384
 385         u16 status = le16_to_cpup(&cqe->status) >> 1;
 386         u32 result = le32_to_cpup(&cqe->result);
 387
 388         blk_mq_free_request(req);
 389
 390         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
 391         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 392 }
 393
 394 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
 395                                                 struct nvme_completion *cqe)
 396 {
 397         struct async_cmd_info *cmdinfo = ctx;
 398         cmdinfo->result = le32_to_cpup(&cqe->result);
 399         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 400         queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
 401         blk_mq_free_request(cmdinfo->req);
 402 }
 403
 404 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
 405                                   unsigned int tag)
 406 {
 407         struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
 408
 409         return blk_mq_rq_to_pdu(req);
 410 }
 411
 412 /*
 413  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 414  */
 415 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
 416                                                 nvme_completion_fn *fn)
 417 {
 418         struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
 419         void *ctx;
 420         if (tag >= nvmeq->q_depth) {
 421                 *fn = special_completion;
 422                 return CMD_CTX_INVALID;
 423         }
 424         if (fn)
 425                 *fn = cmd->fn;
 426         ctx = cmd->ctx;
 427         cmd->fn = special_completion;
 428         cmd->ctx = CMD_CTX_COMPLETED;
 429         return ctx;
 430 }
 431
 432 /**
 433  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 434  * @nvmeq: The queue to use
 435  * @cmd: The command to send
 436  *
 437  * Safe to use from interrupt context
 438  */
 439 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 440                                                 struct nvme_command *cmd)
 441 {
 442         u16 tail = nvmeq->sq_tail;
 443
 444         if (nvmeq->sq_cmds_io)
 445                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 446         else
 447                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 448
 449         if (++tail == nvmeq->q_depth)
 450                 tail = 0;
 451         writel(tail, nvmeq->q_db);
 452         nvmeq->sq_tail = tail;
 453 }
 454
 455 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 456 {
 457         unsigned long flags;
 458         spin_lock_irqsave(&nvmeq->q_lock, flags);
 459         __nvme_submit_cmd(nvmeq, cmd);
 460         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 461 }
 462
 463 static __le64 **iod_list(struct nvme_iod *iod)
 464 {
 465         return ((void *)iod) + iod->offset;
 466 }
 467
 468 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
 469                             unsigned nseg, unsigned long private)
 470 {
 471         iod->private = private;
 472         iod->offset = offsetof(struct nvme_iod, sg[nseg]);
 473         iod->npages = -1;
 474         iod->length = nbytes;
 475         iod->nents = 0;
 476 }
 477
 478 static struct nvme_iod *
 479 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
 480                  unsigned long priv, gfp_t gfp)
 481 {
 482         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
 483                                 sizeof(__le64 *) * nvme_npages(bytes, dev) +
 484                                 sizeof(struct scatterlist) * nseg, gfp);
 485
 486         if (iod)
 487                 iod_init(iod, bytes, nseg, priv);
 488
 489         return iod;
 490 }
 491
 492 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
 493                                        gfp_t gfp)
 494 {
 495         unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
 496                                                 sizeof(struct nvme_dsm_range);
 497         struct nvme_iod *iod;
 498
 499         if (rq->nr_phys_segments <= NVME_INT_PAGES &&
 500             size <= NVME_INT_BYTES(dev)) {
 501                 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
 502
 503                 iod = cmd->iod;
 504                 iod_init(iod, size, rq->nr_phys_segments,
 505                                 (unsigned long) rq | NVME_INT_MASK);
 506                 return iod;
 507         }
 508
 509         return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
 510                                 (unsigned long) rq, gfp);
 511 }
 512
 513 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
 514 {
 515         const int last_prp = dev->ctrl.page_size / 8 - 1;
 516         int i;
 517         __le64 **list = iod_list(iod);
 518         dma_addr_t prp_dma = iod->first_dma;
 519
 520         if (iod->npages == 0)
 521                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 522         for (i = 0; i < iod->npages; i++) {
 523                 __le64 *prp_list = list[i];
 524                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 525                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 526                 prp_dma = next_prp_dma;
 527         }
 528
 529         if (iod_should_kfree(iod))
 530                 kfree(iod);
 531 }
 532
 533 #ifdef CONFIG_BLK_DEV_INTEGRITY
 534 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 535 {
 536         if (be32_to_cpu(pi->ref_tag) == v)
 537                 pi->ref_tag = cpu_to_be32(p);
 538 }
 539
 540 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 541 {
 542         if (be32_to_cpu(pi->ref_tag) == p)
 543                 pi->ref_tag = cpu_to_be32(v);
 544 }
 545
 546 /**
 547  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 548  *
 549  * The virtual start sector is the one that was originally submitted by the
 550  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 551  * start sector may be different. Remap protection information to match the
 552  * physical LBA on writes, and back to the original seed on reads.
 553  *
 554  * Type 0 and 3 do not have a ref tag, so no remapping required.
 555  */
 556 static void nvme_dif_remap(struct request *req,
 557                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 558 {
 559         struct nvme_ns *ns = req->rq_disk->private_data;
 560         struct bio_integrity_payload *bip;
 561         struct t10_pi_tuple *pi;
 562         void *p, *pmap;
 563         u32 i, nlb, ts, phys, virt;
 564
 565         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 566                 return;
 567
 568         bip = bio_integrity(req->bio);
 569         if (!bip)
 570                 return;
 571
 572         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 573
 574         p = pmap;
 575         virt = bip_get_seed(bip);
 576         phys = nvme_block_nr(ns, blk_rq_pos(req));
 577         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 578         ts = ns->disk->queue->integrity.tuple_size;
 579
 580         for (i = 0; i < nlb; i++, virt++, phys++) {
 581                 pi = (struct t10_pi_tuple *)p;
 582                 dif_swap(phys, virt, pi);
 583                 p += ts;
 584         }
 585         kunmap_atomic(pmap);
 586 }
 587 #else /* CONFIG_BLK_DEV_INTEGRITY */
 588 static void nvme_dif_remap(struct request *req,
 589                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 590 {
 591 }
 592 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 593 {
 594 }
 595 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 596 {
 597 }
 598 #endif
 599
 600 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
 601                                                 struct nvme_completion *cqe)
 602 {
 603         struct nvme_iod *iod = ctx;
 604         struct request *req = iod_get_private(iod);
 605         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
 606         u16 status = le16_to_cpup(&cqe->status) >> 1;
 607         int error = 0;
 608
 609         if (unlikely(status)) {
 610                 if (nvme_req_needs_retry(req, status)) {
 611                         nvme_unmap_data(nvmeq->dev, iod);
 612                         nvme_requeue_req(req);
 613                         return;
 614                 }
 615
 616                 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 617                         if (cmd_rq->ctx == CMD_CTX_CANCELLED)
 618                                 error = NVME_SC_CANCELLED;
 619                         else
 620                                 error = status;
 621                 } else {
 622                         error = nvme_error_status(status);
 623                 }
 624         }
 625
 626         if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 627                 u32 result = le32_to_cpup(&cqe->result);
 628                 req->special = (void *)(uintptr_t)result;
 629         }
 630
 631         if (cmd_rq->aborted)
 632                 dev_warn(nvmeq->dev->dev,
 633                         "completing aborted command with status:%04x\n",
 634                         error);
 635
 636         nvme_unmap_data(nvmeq->dev, iod);
 637         blk_mq_complete_request(req, error);
 638 }
 639
 640 static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
 641                 int total_len)
 642 {
 643         struct dma_pool *pool;
 644         int length = total_len;
 645         struct scatterlist *sg = iod->sg;
 646         int dma_len = sg_dma_len(sg);
 647         u64 dma_addr = sg_dma_address(sg);
 648         u32 page_size = dev->ctrl.page_size;
 649         int offset = dma_addr & (page_size - 1);
 650         __le64 *prp_list;
 651         __le64 **list = iod_list(iod);
 652         dma_addr_t prp_dma;
 653         int nprps, i;
 654
 655         length -= (page_size - offset);
 656         if (length <= 0)
 657                 return true;
 658
 659         dma_len -= (page_size - offset);
 660         if (dma_len) {
 661                 dma_addr += (page_size - offset);
 662         } else {
 663                 sg = sg_next(sg);
 664                 dma_addr = sg_dma_address(sg);
 665                 dma_len = sg_dma_len(sg);
 666         }
 667
 668         if (length <= page_size) {
 669                 iod->first_dma = dma_addr;
 670                 return true;
 671         }
 672
 673         nprps = DIV_ROUND_UP(length, page_size);
 674         if (nprps <= (256 / 8)) {
 675                 pool = dev->prp_small_pool;
 676                 iod->npages = 0;
 677         } else {
 678                 pool = dev->prp_page_pool;
 679                 iod->npages = 1;
 680         }
 681
 682         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 683         if (!prp_list) {
 684                 iod->first_dma = dma_addr;
 685                 iod->npages = -1;
 686                 return false;
 687         }
 688         list[0] = prp_list;
 689         iod->first_dma = prp_dma;
 690         i = 0;
 691         for (;;) {
 692                 if (i == page_size >> 3) {
 693                         __le64 *old_prp_list = prp_list;
 694                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 695                         if (!prp_list)
 696                                 return false;
 697                         list[iod->npages++] = prp_list;
 698                         prp_list[0] = old_prp_list[i - 1];
 699                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 700                         i = 1;
 701                 }
 702                 prp_list[i++] = cpu_to_le64(dma_addr);
 703                 dma_len -= page_size;
 704                 dma_addr += page_size;
 705                 length -= page_size;
 706                 if (length <= 0)
 707                         break;
 708                 if (dma_len > 0)
 709                         continue;
 710                 BUG_ON(dma_len < 0);
 711                 sg = sg_next(sg);
 712                 dma_addr = sg_dma_address(sg);
 713                 dma_len = sg_dma_len(sg);
 714         }
 715
 716         return true;
 717 }
 718
 719 static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod,
 720                 struct nvme_command *cmnd)
 721 {
 722         struct request *req = iod_get_private(iod);
 723         struct request_queue *q = req->q;
 724         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 725                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 726         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 727
 728         sg_init_table(iod->sg, req->nr_phys_segments);
 729         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 730         if (!iod->nents)
 731                 goto out;
 732
 733         ret = BLK_MQ_RQ_QUEUE_BUSY;
 734         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 735                 goto out;
 736
 737         if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req)))
 738                 goto out_unmap;
 739
 740         ret = BLK_MQ_RQ_QUEUE_ERROR;
 741         if (blk_integrity_rq(req)) {
 742                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 743                         goto out_unmap;
 744
 745                 sg_init_table(iod->meta_sg, 1);
 746                 if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1)
 747                         goto out_unmap;
 748
 749                 if (rq_data_dir(req))
 750                         nvme_dif_remap(req, nvme_dif_prep);
 751
 752                 if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir))
 753                         goto out_unmap;
 754         }
 755
 756         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 757         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 758         if (blk_integrity_rq(req))
 759                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
 760         return BLK_MQ_RQ_QUEUE_OK;
 761
 762 out_unmap:
 763         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 764 out:
 765         return ret;
 766 }
 767
 768 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod)
 769 {
 770         struct request *req = iod_get_private(iod);
 771         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 772                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 773
 774         if (iod->nents) {
 775                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 776                 if (blk_integrity_rq(req)) {
 777                         if (!rq_data_dir(req))
 778                                 nvme_dif_remap(req, nvme_dif_complete);
 779                         dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir);
 780                 }
 781         }
 782
 783         nvme_free_iod(dev, iod);
 784 }
 785
 786 /*
 787  * We reuse the small pool to allocate the 16-byte range here as it is not
 788  * worth having a special pool for these or additional cases to handle freeing
 789  * the iod.
 790  */
 791 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 792                 struct nvme_iod *iod, struct nvme_command *cmnd)
 793 {
 794         struct request *req = iod_get_private(iod);
 795         struct nvme_dsm_range *range;
 796
 797         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 798                                                 &iod->first_dma);
 799         if (!range)
 800                 return BLK_MQ_RQ_QUEUE_BUSY;
 801         iod_list(iod)[0] = (__le64 *)range;
 802         iod->npages = 0;
 803
 804         range->cattr = cpu_to_le32(0);
 805         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 806         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 807
 808         memset(cmnd, 0, sizeof(*cmnd));
 809         cmnd->dsm.opcode = nvme_cmd_dsm;
 810         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 811         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 812         cmnd->dsm.nr = 0;
 813         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 814         return BLK_MQ_RQ_QUEUE_OK;
 815 }
 816
 817 /*
 818  * NOTE: ns is NULL when called on the admin queue.
 819  */
 820 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 821                          const struct blk_mq_queue_data *bd)
 822 {
 823         struct nvme_ns *ns = hctx->queue->queuedata;
 824         struct nvme_queue *nvmeq = hctx->driver_data;
 825         struct nvme_dev *dev = nvmeq->dev;
 826         struct request *req = bd->rq;
 827         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 828         struct nvme_iod *iod;
 829         struct nvme_command cmnd;
 830         int ret = BLK_MQ_RQ_QUEUE_OK;
 831
 832         /*
 833          * If formated with metadata, require the block layer provide a buffer
 834          * unless this namespace is formated such that the metadata can be
 835          * stripped/generated by the controller with PRACT=1.
 836          */
 837         if (ns && ns->ms && !blk_integrity_rq(req)) {
 838                 if (!(ns->pi_type && ns->ms == 8) &&
 839                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 840                         blk_mq_complete_request(req, -EFAULT);
 841                         return BLK_MQ_RQ_QUEUE_OK;
 842                 }
 843         }
 844
 845         iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
 846         if (!iod)
 847                 return BLK_MQ_RQ_QUEUE_BUSY;
 848
 849         if (req->cmd_flags & REQ_DISCARD) {
 850                 ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd);
 851         } else {
 852                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 853                         memcpy(&cmnd, req->cmd, sizeof(cmnd));
 854                 else if (req->cmd_flags & REQ_FLUSH)
 855                         nvme_setup_flush(ns, &cmnd);
 856                 else
 857                         nvme_setup_rw(ns, req, &cmnd);
 858
 859                 if (req->nr_phys_segments)
 860                         ret = nvme_map_data(dev, iod, &cmnd);
 861         }
 862
 863         if (ret)
 864                 goto out;
 865
 866         cmnd.common.command_id = req->tag;
 867         nvme_set_info(cmd, iod, req_completion);
 868
 869         spin_lock_irq(&nvmeq->q_lock);
 870         __nvme_submit_cmd(nvmeq, &cmnd);
 871         nvme_process_cq(nvmeq);
 872         spin_unlock_irq(&nvmeq->q_lock);
 873         return BLK_MQ_RQ_QUEUE_OK;
 874 out:
 875         nvme_free_iod(dev, iod);
 876         return ret;
 877 }
 878
 879 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 880 {
 881         u16 head, phase;
 882
 883         head = nvmeq->cq_head;
 884         phase = nvmeq->cq_phase;
 885
 886         for (;;) {
 887                 void *ctx;
 888                 nvme_completion_fn fn;
 889                 struct nvme_completion cqe = nvmeq->cqes[head];
 890                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 891                         break;
 892                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 893                 if (++head == nvmeq->q_depth) {
 894                         head = 0;
 895                         phase = !phase;
 896                 }
 897                 if (tag && *tag == cqe.command_id)
 898                         *tag = -1;
 899                 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
 900                 fn(nvmeq, ctx, &cqe);
 901         }
 902
 903         /* If the controller ignores the cq head doorbell and continuously
 904          * writes to the queue, it is theoretically possible to wrap around
 905          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 906          * requires that 0.1% of your interrupts are handled, so this isn't
 907          * a big problem.
 908          */
 909         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 910                 return;
 911
 912         if (likely(nvmeq->cq_vector >= 0))
 913                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 914         nvmeq->cq_head = head;
 915         nvmeq->cq_phase = phase;
 916
 917         nvmeq->cqe_seen = 1;
 918 }
 919
 920 static void nvme_process_cq(struct nvme_queue *nvmeq)
 921 {
 922         __nvme_process_cq(nvmeq, NULL);
 923 }
 924
 925 static irqreturn_t nvme_irq(int irq, void *data)
 926 {
 927         irqreturn_t result;
 928         struct nvme_queue *nvmeq = data;
 929         spin_lock(&nvmeq->q_lock);
 930         nvme_process_cq(nvmeq);
 931         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 932         nvmeq->cqe_seen = 0;
 933         spin_unlock(&nvmeq->q_lock);
 934         return result;
 935 }
 936
 937 static irqreturn_t nvme_irq_check(int irq, void *data)
 938 {
 939         struct nvme_queue *nvmeq = data;
 940         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 941         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 942                 return IRQ_NONE;
 943         return IRQ_WAKE_THREAD;
 944 }
 945
 946 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 947 {
 948         struct nvme_queue *nvmeq = hctx->driver_data;
 949
 950         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 951             nvmeq->cq_phase) {
 952                 spin_lock_irq(&nvmeq->q_lock);
 953                 __nvme_process_cq(nvmeq, &tag);
 954                 spin_unlock_irq(&nvmeq->q_lock);
 955
 956                 if (tag == -1)
 957                         return 1;
 958         }
 959
 960         return 0;
 961 }
 962
 963 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
 964 {
 965         struct nvme_queue *nvmeq = dev->queues[0];
 966         struct nvme_command c;
 967         struct nvme_cmd_info *cmd_info;
 968         struct request *req;
 969
 970         req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE,
 971                         BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED);
 972         if (IS_ERR(req))
 973                 return PTR_ERR(req);
 974
 975         req->cmd_flags |= REQ_NO_TIMEOUT;
 976         cmd_info = blk_mq_rq_to_pdu(req);
 977         nvme_set_info(cmd_info, NULL, async_req_completion);
 978
 979         memset(&c, 0, sizeof(c));
 980         c.common.opcode = nvme_admin_async_event;
 981         c.common.command_id = req->tag;
 982
 983         blk_mq_free_request(req);
 984         __nvme_submit_cmd(nvmeq, &c);
 985         return 0;
 986 }
 987
 988 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
 989                         struct nvme_command *cmd,
 990                         struct async_cmd_info *cmdinfo, unsigned timeout)
 991 {
 992         struct nvme_queue *nvmeq = dev->queues[0];
 993         struct request *req;
 994         struct nvme_cmd_info *cmd_rq;
 995
 996         req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0);
 997         if (IS_ERR(req))
 998                 return PTR_ERR(req);
 999
1000         req->timeout = timeout;
1001         cmd_rq = blk_mq_rq_to_pdu(req);
1002         cmdinfo->req = req;
1003         nvme_set_info(cmd_rq, cmdinfo, async_completion);
1004         cmdinfo->status = -EINTR;
1005
1006         cmd->common.command_id = req->tag;
1007
1008         nvme_submit_cmd(nvmeq, cmd);
1009         return 0;
1010 }
1011
1012 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1013 {
1014         struct nvme_command c;
1015
1016         memset(&c, 0, sizeof(c));
1017         c.delete_queue.opcode = opcode;
1018         c.delete_queue.qid = cpu_to_le16(id);
1019
1020         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1021 }
1022
1023 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1024                                                 struct nvme_queue *nvmeq)
1025 {
1026         struct nvme_command c;
1027         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1028
1029         /*
1030          * Note: we (ab)use the fact the the prp fields survive if no data
1031          * is attached to the request.
1032          */
1033         memset(&c, 0, sizeof(c));
1034         c.create_cq.opcode = nvme_admin_create_cq;
1035         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1036         c.create_cq.cqid = cpu_to_le16(qid);
1037         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1038         c.create_cq.cq_flags = cpu_to_le16(flags);
1039         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1040
1041         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1042 }
1043
1044 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1045                                                 struct nvme_queue *nvmeq)
1046 {
1047         struct nvme_command c;
1048         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1049
1050         /*
1051          * Note: we (ab)use the fact the the prp fields survive if no data
1052          * is attached to the request.
1053          */
1054         memset(&c, 0, sizeof(c));
1055         c.create_sq.opcode = nvme_admin_create_sq;
1056         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1057         c.create_sq.sqid = cpu_to_le16(qid);
1058         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1059         c.create_sq.sq_flags = cpu_to_le16(flags);
1060         c.create_sq.cqid = cpu_to_le16(qid);
1061
1062         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1063 }
1064
1065 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1066 {
1067         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1068 }
1069
1070 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1071 {
1072         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1073 }
1074
1075 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1076 {
1077         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1078         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1079         struct nvme_dev *dev = nvmeq->dev;
1080         struct request *abort_req;
1081         struct nvme_cmd_info *abort_cmd;
1082         struct nvme_command cmd;
1083
1084         /*
1085          * Shutdown immediately if controller times out while starting. The
1086          * reset work will see the pci device disabled when it gets the forced
1087          * cancellation error. All outstanding requests are completed on
1088          * shutdown, so we return BLK_EH_HANDLED.
1089          */
1090         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
1091                 dev_warn(dev->dev,
1092                          "I/O %d QID %d timeout, disable controller\n",
1093                          req->tag, nvmeq->qid);
1094                 nvme_dev_shutdown(dev);
1095                 req->errors = NVME_SC_CANCELLED;
1096                 return BLK_EH_HANDLED;
1097         }
1098
1099         /*
1100          * Shutdown the controller immediately and schedule a reset if the
1101          * command was already aborted once before and still hasn't been
1102          * returned to the driver, or if this is the admin queue.
1103          */
1104         if (!nvmeq->qid || cmd_rq->aborted) {
1105                 dev_warn(dev->dev,
1106                          "I/O %d QID %d timeout, reset controller\n",
1107                          req->tag, nvmeq->qid);
1108                 nvme_dev_shutdown(dev);
1109                 queue_work(nvme_workq, &dev->reset_work);
1110
1111                 /*
1112                  * Mark the request as handled, since the inline shutdown
1113                  * forces all outstanding requests to complete.
1114                  */
1115                 req->errors = NVME_SC_CANCELLED;
1116                 return BLK_EH_HANDLED;
1117         }
1118
1119         if (atomic_dec_and_test(&dev->ctrl.abort_limit))
1120                 return BLK_EH_RESET_TIMER;
1121
1122         abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE,
1123                         BLK_MQ_REQ_NOWAIT);
1124         if (IS_ERR(abort_req)) {
1125                 atomic_inc(&dev->ctrl.abort_limit);
1126                 return BLK_EH_RESET_TIMER;
1127         }
1128
1129         abort_cmd = blk_mq_rq_to_pdu(abort_req);
1130         nvme_set_info(abort_cmd, abort_req, abort_completion);
1131
1132         memset(&cmd, 0, sizeof(cmd));
1133         cmd.abort.opcode = nvme_admin_abort_cmd;
1134         cmd.abort.cid = req->tag;
1135         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1136         cmd.abort.command_id = abort_req->tag;
1137
1138         cmd_rq->aborted = 1;
1139
1140         dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n",
1141                                  req->tag, nvmeq->qid);
1142         nvme_submit_cmd(dev->queues[0], &cmd);
1143
1144         /*
1145          * The aborted req will be completed on receiving the abort req.
1146          * We enable the timer again. If hit twice, it'll cause a device reset,
1147          * as the device then is in a faulty state.
1148          */
1149         return BLK_EH_RESET_TIMER;
1150 }
1151
1152 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1153 {
1154         struct nvme_queue *nvmeq = data;
1155         void *ctx;
1156         nvme_completion_fn fn;
1157         struct nvme_cmd_info *cmd;
1158         struct nvme_completion cqe;
1159
1160         if (!blk_mq_request_started(req))
1161                 return;
1162
1163         cmd = blk_mq_rq_to_pdu(req);
1164
1165         if (cmd->ctx == CMD_CTX_CANCELLED)
1166                 return;
1167
1168         if (blk_queue_dying(req->q))
1169                 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1170         else
1171                 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1172
1173
1174         dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1175                                                 req->tag, nvmeq->qid);
1176         ctx = cancel_cmd_info(cmd, &fn);
1177         fn(nvmeq, ctx, &cqe);
1178 }
1179
1180 static void nvme_free_queue(struct nvme_queue *nvmeq)
1181 {
1182         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1183                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1184         if (nvmeq->sq_cmds)
1185                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1186                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1187         kfree(nvmeq);
1188 }
1189
1190 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1191 {
1192         int i;
1193
1194         for (i = dev->queue_count - 1; i >= lowest; i--) {
1195                 struct nvme_queue *nvmeq = dev->queues[i];
1196                 dev->queue_count--;
1197                 dev->queues[i] = NULL;
1198                 nvme_free_queue(nvmeq);
1199         }
1200 }
1201
1202 /**
1203  * nvme_suspend_queue - put queue into suspended state
1204  * @nvmeq - queue to suspend
1205  */
1206 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1207 {
1208         int vector;
1209
1210         spin_lock_irq(&nvmeq->q_lock);
1211         if (nvmeq->cq_vector == -1) {
1212                 spin_unlock_irq(&nvmeq->q_lock);
1213                 return 1;
1214         }
1215         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1216         nvmeq->dev->online_queues--;
1217         nvmeq->cq_vector = -1;
1218         spin_unlock_irq(&nvmeq->q_lock);
1219
1220         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1221                 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q);
1222
1223         irq_set_affinity_hint(vector, NULL);
1224         free_irq(vector, nvmeq);
1225
1226         return 0;
1227 }
1228
1229 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1230 {
1231         spin_lock_irq(&nvmeq->q_lock);
1232         if (nvmeq->tags && *nvmeq->tags)
1233                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1234         spin_unlock_irq(&nvmeq->q_lock);
1235 }
1236
1237 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1238 {
1239         struct nvme_queue *nvmeq = dev->queues[qid];
1240
1241         if (!nvmeq)
1242                 return;
1243         if (nvme_suspend_queue(nvmeq))
1244                 return;
1245
1246         /* Don't tell the adapter to delete the admin queue.
1247          * Don't tell a removed adapter to delete IO queues. */
1248         if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) {
1249                 adapter_delete_sq(dev, qid);
1250                 adapter_delete_cq(dev, qid);
1251         }
1252
1253         spin_lock_irq(&nvmeq->q_lock);
1254         nvme_process_cq(nvmeq);
1255         spin_unlock_irq(&nvmeq->q_lock);
1256 }
1257
1258 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1259                                 int entry_size)
1260 {
1261         int q_depth = dev->q_depth;
1262         unsigned q_size_aligned = roundup(q_depth * entry_size,
1263                                           dev->ctrl.page_size);
1264
1265         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1266                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1267                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1268                 q_depth = div_u64(mem_per_q, entry_size);
1269
1270                 /*
1271                  * Ensure the reduced q_depth is above some threshold where it
1272                  * would be better to map queues in system memory with the
1273                  * original depth
1274                  */
1275                 if (q_depth < 64)
1276                         return -ENOMEM;
1277         }
1278
1279         return q_depth;
1280 }
1281
1282 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1283                                 int qid, int depth)
1284 {
1285         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1286                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1287                                                       dev->ctrl.page_size);
1288                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1289                 nvmeq->sq_cmds_io = dev->cmb + offset;
1290         } else {
1291                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1292                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1293                 if (!nvmeq->sq_cmds)
1294                         return -ENOMEM;
1295         }
1296
1297         return 0;
1298 }
1299
1300 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1301                                                         int depth)
1302 {
1303         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1304         if (!nvmeq)
1305                 return NULL;
1306
1307         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1308                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1309         if (!nvmeq->cqes)
1310                 goto free_nvmeq;
1311
1312         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1313                 goto free_cqdma;
1314
1315         nvmeq->q_dmadev = dev->dev;
1316         nvmeq->dev = dev;
1317         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1318                         dev->ctrl.instance, qid);
1319         spin_lock_init(&nvmeq->q_lock);
1320         nvmeq->cq_head = 0;
1321         nvmeq->cq_phase = 1;
1322         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1323         nvmeq->q_depth = depth;
1324         nvmeq->qid = qid;
1325         nvmeq->cq_vector = -1;
1326         dev->queues[qid] = nvmeq;
1327
1328         /* make sure queue descriptor is set before queue count, for kthread */
1329         mb();
1330         dev->queue_count++;
1331
1332         return nvmeq;
1333
1334  free_cqdma:
1335         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1336                                                         nvmeq->cq_dma_addr);
1337  free_nvmeq:
1338         kfree(nvmeq);
1339         return NULL;
1340 }
1341
1342 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1343                                                         const char *name)
1344 {
1345         if (use_threaded_interrupts)
1346                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1347                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1348                                         name, nvmeq);
1349         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1350                                 IRQF_SHARED, name, nvmeq);
1351 }
1352
1353 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1354 {
1355         struct nvme_dev *dev = nvmeq->dev;
1356
1357         spin_lock_irq(&nvmeq->q_lock);
1358         nvmeq->sq_tail = 0;
1359         nvmeq->cq_head = 0;
1360         nvmeq->cq_phase = 1;
1361         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1362         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1363         dev->online_queues++;
1364         spin_unlock_irq(&nvmeq->q_lock);
1365 }
1366
1367 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1368 {
1369         struct nvme_dev *dev = nvmeq->dev;
1370         int result;
1371
1372         nvmeq->cq_vector = qid - 1;
1373         result = adapter_alloc_cq(dev, qid, nvmeq);
1374         if (result < 0)
1375                 return result;
1376
1377         result = adapter_alloc_sq(dev, qid, nvmeq);
1378         if (result < 0)
1379                 goto release_cq;
1380
1381         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1382         if (result < 0)
1383                 goto release_sq;
1384
1385         nvme_init_queue(nvmeq, qid);
1386         return result;
1387
1388  release_sq:
1389         adapter_delete_sq(dev, qid);
1390  release_cq:
1391         adapter_delete_cq(dev, qid);
1392         return result;
1393 }
1394
1395 static struct blk_mq_ops nvme_mq_admin_ops = {
1396         .queue_rq       = nvme_queue_rq,
1397         .map_queue      = blk_mq_map_queue,
1398         .init_hctx      = nvme_admin_init_hctx,
1399         .exit_hctx      = nvme_admin_exit_hctx,
1400         .init_request   = nvme_admin_init_request,
1401         .timeout        = nvme_timeout,
1402 };
1403
1404 static struct blk_mq_ops nvme_mq_ops = {
1405         .queue_rq       = nvme_queue_rq,
1406         .map_queue      = blk_mq_map_queue,
1407         .init_hctx      = nvme_init_hctx,
1408         .init_request   = nvme_init_request,
1409         .timeout        = nvme_timeout,
1410         .poll           = nvme_poll,
1411 };
1412
1413 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1414 {
1415         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1416                 blk_cleanup_queue(dev->ctrl.admin_q);
1417                 blk_mq_free_tag_set(&dev->admin_tagset);
1418         }
1419 }
1420
1421 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1422 {
1423         if (!dev->ctrl.admin_q) {
1424                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1425                 dev->admin_tagset.nr_hw_queues = 1;
1426                 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH;
1427                 dev->admin_tagset.reserved_tags = 1;
1428                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1429                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1430                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1431                 dev->admin_tagset.driver_data = dev;
1432
1433                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1434                         return -ENOMEM;
1435
1436                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1437                 if (IS_ERR(dev->ctrl.admin_q)) {
1438                         blk_mq_free_tag_set(&dev->admin_tagset);
1439                         return -ENOMEM;
1440                 }
1441                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1442                         nvme_dev_remove_admin(dev);
1443                         dev->ctrl.admin_q = NULL;
1444                         return -ENODEV;
1445                 }
1446         } else
1447                 blk_mq_unfreeze_queue(dev->ctrl.admin_q);
1448
1449         return 0;
1450 }
1451
1452 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1453 {
1454         int result;
1455         u32 aqa;
1456         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1457         struct nvme_queue *nvmeq;
1458
1459         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1460                                                 NVME_CAP_NSSRC(cap) : 0;
1461
1462         if (dev->subsystem &&
1463             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1464                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1465
1466         result = nvme_disable_ctrl(&dev->ctrl, cap);
1467         if (result < 0)
1468                 return result;
1469
1470         nvmeq = dev->queues[0];
1471         if (!nvmeq) {
1472                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1473                 if (!nvmeq)
1474                         return -ENOMEM;
1475         }
1476
1477         aqa = nvmeq->q_depth - 1;
1478         aqa |= aqa << 16;
1479
1480         writel(aqa, dev->bar + NVME_REG_AQA);
1481         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1482         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1483
1484         result = nvme_enable_ctrl(&dev->ctrl, cap);
1485         if (result)
1486                 goto free_nvmeq;
1487
1488         nvmeq->cq_vector = 0;
1489         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1490         if (result) {
1491                 nvmeq->cq_vector = -1;
1492                 goto free_nvmeq;
1493         }
1494
1495         return result;
1496
1497  free_nvmeq:
1498         nvme_free_queues(dev, 0);
1499         return result;
1500 }
1501
1502 static int nvme_kthread(void *data)
1503 {
1504         struct nvme_dev *dev, *next;
1505
1506         while (!kthread_should_stop()) {
1507                 set_current_state(TASK_INTERRUPTIBLE);
1508                 spin_lock(&dev_list_lock);
1509                 list_for_each_entry_safe(dev, next, &dev_list, node) {
1510                         int i;
1511                         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1512
1513                         /*
1514                          * Skip controllers currently under reset.
1515                          */
1516                         if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1517                                 continue;
1518
1519                         if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1520                                                         csts & NVME_CSTS_CFS) {
1521                                 if (queue_work(nvme_workq, &dev->reset_work)) {
1522                                         dev_warn(dev->dev,
1523                                                 "Failed status: %x, reset controller\n",
1524                                                 readl(dev->bar + NVME_REG_CSTS));
1525                                 }
1526                                 continue;
1527                         }
1528                         for (i = 0; i < dev->queue_count; i++) {
1529                                 struct nvme_queue *nvmeq = dev->queues[i];
1530                                 if (!nvmeq)
1531                                         continue;
1532                                 spin_lock_irq(&nvmeq->q_lock);
1533                                 nvme_process_cq(nvmeq);
1534
1535                                 while (i == 0 && dev->ctrl.event_limit > 0) {
1536                                         if (nvme_submit_async_admin_req(dev))
1537                                                 break;
1538                                         dev->ctrl.event_limit--;
1539                                 }
1540                                 spin_unlock_irq(&nvmeq->q_lock);
1541                         }
1542                 }
1543                 spin_unlock(&dev_list_lock);
1544                 schedule_timeout(round_jiffies_relative(HZ));
1545         }
1546         return 0;
1547 }
1548
1549 static int nvme_create_io_queues(struct nvme_dev *dev)
1550 {
1551         unsigned i;
1552         int ret = 0;
1553
1554         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1555                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1556                         ret = -ENOMEM;
1557                         break;
1558                 }
1559         }
1560
1561         for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
1562                 ret = nvme_create_queue(dev->queues[i], i);
1563                 if (ret) {
1564                         nvme_free_queues(dev, i);
1565                         break;
1566                 }
1567         }
1568
1569         /*
1570          * Ignore failing Create SQ/CQ commands, we can continue with less
1571          * than the desired aount of queues, and even a controller without
1572          * I/O queues an still be used to issue admin commands.  This might
1573          * be useful to upgrade a buggy firmware for example.
1574          */
1575         return ret >= 0 ? 0 : ret;
1576 }
1577
1578 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1579 {
1580         u64 szu, size, offset;
1581         u32 cmbloc;
1582         resource_size_t bar_size;
1583         struct pci_dev *pdev = to_pci_dev(dev->dev);
1584         void __iomem *cmb;
1585         dma_addr_t dma_addr;
1586
1587         if (!use_cmb_sqes)
1588                 return NULL;
1589
1590         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1591         if (!(NVME_CMB_SZ(dev->cmbsz)))
1592                 return NULL;
1593
1594         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1595
1596         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1597         size = szu * NVME_CMB_SZ(dev->cmbsz);
1598         offset = szu * NVME_CMB_OFST(cmbloc);
1599         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1600
1601         if (offset > bar_size)
1602                 return NULL;
1603
1604         /*
1605          * Controllers may support a CMB size larger than their BAR,
1606          * for example, due to being behind a bridge. Reduce the CMB to
1607          * the reported size of the BAR
1608          */
1609         if (size > bar_size - offset)
1610                 size = bar_size - offset;
1611
1612         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1613         cmb = ioremap_wc(dma_addr, size);
1614         if (!cmb)
1615                 return NULL;
1616
1617         dev->cmb_dma_addr = dma_addr;
1618         dev->cmb_size = size;
1619         return cmb;
1620 }
1621
1622 static inline void nvme_release_cmb(struct nvme_dev *dev)
1623 {
1624         if (dev->cmb) {
1625                 iounmap(dev->cmb);
1626                 dev->cmb = NULL;
1627         }
1628 }
1629
1630 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1631 {
1632         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1633 }
1634
1635 static int nvme_setup_io_queues(struct nvme_dev *dev)
1636 {
1637         struct nvme_queue *adminq = dev->queues[0];
1638         struct pci_dev *pdev = to_pci_dev(dev->dev);
1639         int result, i, vecs, nr_io_queues, size;
1640
1641         nr_io_queues = num_possible_cpus();
1642         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1643         if (result < 0)
1644                 return result;
1645
1646         /*
1647          * Degraded controllers might return an error when setting the queue
1648          * count.  We still want to be able to bring them online and offer
1649          * access to the admin queue, as that might be only way to fix them up.
1650          */
1651         if (result > 0) {
1652                 dev_err(dev->dev, "Could not set queue count (%d)\n", result);
1653                 nr_io_queues = 0;
1654                 result = 0;
1655         }
1656
1657         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1658                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1659                                 sizeof(struct nvme_command));
1660                 if (result > 0)
1661                         dev->q_depth = result;
1662                 else
1663                         nvme_release_cmb(dev);
1664         }
1665
1666         size = db_bar_size(dev, nr_io_queues);
1667         if (size > 8192) {
1668                 iounmap(dev->bar);
1669                 do {
1670                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1671                         if (dev->bar)
1672                                 break;
1673                         if (!--nr_io_queues)
1674                                 return -ENOMEM;
1675                         size = db_bar_size(dev, nr_io_queues);
1676                 } while (1);
1677                 dev->dbs = dev->bar + 4096;
1678                 adminq->q_db = dev->dbs;
1679         }
1680
1681         /* Deregister the admin queue's interrupt */
1682         free_irq(dev->entry[0].vector, adminq);
1683
1684         /*
1685          * If we enable msix early due to not intx, disable it again before
1686          * setting up the full range we need.
1687          */
1688         if (!pdev->irq)
1689                 pci_disable_msix(pdev);
1690
1691         for (i = 0; i < nr_io_queues; i++)
1692                 dev->entry[i].entry = i;
1693         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1694         if (vecs < 0) {
1695                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1696                 if (vecs < 0) {
1697                         vecs = 1;
1698                 } else {
1699                         for (i = 0; i < vecs; i++)
1700                                 dev->entry[i].vector = i + pdev->irq;
1701                 }
1702         }
1703
1704         /*
1705          * Should investigate if there's a performance win from allocating
1706          * more queues than interrupt vectors; it might allow the submission
1707          * path to scale better, even if the receive path is limited by the
1708          * number of interrupts.
1709          */
1710         nr_io_queues = vecs;
1711         dev->max_qid = nr_io_queues;
1712
1713         result = queue_request_irq(dev, adminq, adminq->irqname);
1714         if (result) {
1715                 adminq->cq_vector = -1;
1716                 goto free_queues;
1717         }
1718
1719         /* Free previously allocated queues that are no longer usable */
1720         nvme_free_queues(dev, nr_io_queues + 1);
1721         return nvme_create_io_queues(dev);
1722
1723  free_queues:
1724         nvme_free_queues(dev, 1);
1725         return result;
1726 }
1727
1728 static void nvme_set_irq_hints(struct nvme_dev *dev)
1729 {
1730         struct nvme_queue *nvmeq;
1731         int i;
1732
1733         for (i = 0; i < dev->online_queues; i++) {
1734                 nvmeq = dev->queues[i];
1735
1736                 if (!nvmeq->tags || !(*nvmeq->tags))
1737                         continue;
1738
1739                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1740                                         blk_mq_tags_cpumask(*nvmeq->tags));
1741         }
1742 }
1743
1744 static void nvme_dev_scan(struct work_struct *work)
1745 {
1746         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1747
1748         if (!dev->tagset.tags)
1749                 return;
1750         nvme_scan_namespaces(&dev->ctrl);
1751         nvme_set_irq_hints(dev);
1752 }
1753
1754 /*
1755  * Return: error value if an error occurred setting up the queues or calling
1756  * Identify Device.  0 if these succeeded, even if adding some of the
1757  * namespaces failed.  At the moment, these failures are silent.  TBD which
1758  * failures should be reported.
1759  */
1760 static int nvme_dev_add(struct nvme_dev *dev)
1761 {
1762         if (!dev->ctrl.tagset) {
1763                 dev->tagset.ops = &nvme_mq_ops;
1764                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1765                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1766                 dev->tagset.numa_node = dev_to_node(dev->dev);
1767                 dev->tagset.queue_depth =
1768                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1769                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1770                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1771                 dev->tagset.driver_data = dev;
1772
1773                 if (blk_mq_alloc_tag_set(&dev->tagset))
1774                         return 0;
1775                 dev->ctrl.tagset = &dev->tagset;
1776         }
1777         queue_work(nvme_workq, &dev->scan_work);
1778         return 0;
1779 }
1780
1781 static int nvme_dev_map(struct nvme_dev *dev)
1782 {
1783         u64 cap;
1784         int bars, result = -ENOMEM;
1785         struct pci_dev *pdev = to_pci_dev(dev->dev);
1786
1787         if (pci_enable_device_mem(pdev))
1788                 return result;
1789
1790         dev->entry[0].vector = pdev->irq;
1791         pci_set_master(pdev);
1792         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1793         if (!bars)
1794                 goto disable_pci;
1795
1796         if (pci_request_selected_regions(pdev, bars, "nvme"))
1797                 goto disable_pci;
1798
1799         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1800             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1801                 goto disable;
1802
1803         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1804         if (!dev->bar)
1805                 goto disable;
1806
1807         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1808                 result = -ENODEV;
1809                 goto unmap;
1810         }
1811
1812         /*
1813          * Some devices don't advertse INTx interrupts, pre-enable a single
1814          * MSIX vec for setup. We'll adjust this later.
1815          */
1816         if (!pdev->irq) {
1817                 result = pci_enable_msix(pdev, dev->entry, 1);
1818                 if (result < 0)
1819                         goto unmap;
1820         }
1821
1822         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1823
1824         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1825         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1826         dev->dbs = dev->bar + 4096;
1827         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1828                 dev->cmb = nvme_map_cmb(dev);
1829
1830         return 0;
1831
1832  unmap:
1833         iounmap(dev->bar);
1834         dev->bar = NULL;
1835  disable:
1836         pci_release_regions(pdev);
1837  disable_pci:
1838         pci_disable_device(pdev);
1839         return result;
1840 }
1841
1842 static void nvme_dev_unmap(struct nvme_dev *dev)
1843 {
1844         struct pci_dev *pdev = to_pci_dev(dev->dev);
1845
1846         if (pdev->msi_enabled)
1847                 pci_disable_msi(pdev);
1848         else if (pdev->msix_enabled)
1849                 pci_disable_msix(pdev);
1850
1851         if (dev->bar) {
1852                 iounmap(dev->bar);
1853                 dev->bar = NULL;
1854                 pci_release_regions(pdev);
1855         }
1856
1857         if (pci_is_enabled(pdev))
1858                 pci_disable_device(pdev);
1859 }
1860
1861 struct nvme_delq_ctx {
1862         struct task_struct *waiter;
1863         struct kthread_worker *worker;
1864         atomic_t refcount;
1865 };
1866
1867 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
1868 {
1869         dq->waiter = current;
1870         mb();
1871
1872         for (;;) {
1873                 set_current_state(TASK_KILLABLE);
1874                 if (!atomic_read(&dq->refcount))
1875                         break;
1876                 if (!schedule_timeout(ADMIN_TIMEOUT) ||
1877                                         fatal_signal_pending(current)) {
1878                         /*
1879                          * Disable the controller first since we can't trust it
1880                          * at this point, but leave the admin queue enabled
1881                          * until all queue deletion requests are flushed.
1882                          * FIXME: This may take a while if there are more h/w
1883                          * queues than admin tags.
1884                          */
1885                         set_current_state(TASK_RUNNING);
1886                         nvme_disable_ctrl(&dev->ctrl,
1887                                 lo_hi_readq(dev->bar + NVME_REG_CAP));
1888                         nvme_clear_queue(dev->queues[0]);
1889                         flush_kthread_worker(dq->worker);
1890                         nvme_disable_queue(dev, 0);
1891                         return;
1892                 }
1893         }
1894         set_current_state(TASK_RUNNING);
1895 }
1896
1897 static void nvme_put_dq(struct nvme_delq_ctx *dq)
1898 {
1899         atomic_dec(&dq->refcount);
1900         if (dq->waiter)
1901                 wake_up_process(dq->waiter);
1902 }
1903
1904 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
1905 {
1906         atomic_inc(&dq->refcount);
1907         return dq;
1908 }
1909
1910 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
1911 {
1912         struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
1913         nvme_put_dq(dq);
1914
1915         spin_lock_irq(&nvmeq->q_lock);
1916         nvme_process_cq(nvmeq);
1917         spin_unlock_irq(&nvmeq->q_lock);
1918 }
1919
1920 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
1921                                                 kthread_work_func_t fn)
1922 {
1923         struct nvme_command c;
1924
1925         memset(&c, 0, sizeof(c));
1926         c.delete_queue.opcode = opcode;
1927         c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1928
1929         init_kthread_work(&nvmeq->cmdinfo.work, fn);
1930         return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
1931                                                                 ADMIN_TIMEOUT);
1932 }
1933
1934 static void nvme_del_cq_work_handler(struct kthread_work *work)
1935 {
1936         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1937                                                         cmdinfo.work);
1938         nvme_del_queue_end(nvmeq);
1939 }
1940
1941 static int nvme_delete_cq(struct nvme_queue *nvmeq)
1942 {
1943         return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
1944                                                 nvme_del_cq_work_handler);
1945 }
1946
1947 static void nvme_del_sq_work_handler(struct kthread_work *work)
1948 {
1949         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1950                                                         cmdinfo.work);
1951         int status = nvmeq->cmdinfo.status;
1952
1953         if (!status)
1954                 status = nvme_delete_cq(nvmeq);
1955         if (status)
1956                 nvme_del_queue_end(nvmeq);
1957 }
1958
1959 static int nvme_delete_sq(struct nvme_queue *nvmeq)
1960 {
1961         return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
1962                                                 nvme_del_sq_work_handler);
1963 }
1964
1965 static void nvme_del_queue_start(struct kthread_work *work)
1966 {
1967         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1968                                                         cmdinfo.work);
1969         if (nvme_delete_sq(nvmeq))
1970                 nvme_del_queue_end(nvmeq);
1971 }
1972
1973 static void nvme_disable_io_queues(struct nvme_dev *dev)
1974 {
1975         int i;
1976         DEFINE_KTHREAD_WORKER_ONSTACK(worker);
1977         struct nvme_delq_ctx dq;
1978         struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
1979                                         &worker, "nvme%d", dev->ctrl.instance);
1980
1981         if (IS_ERR(kworker_task)) {
1982                 dev_err(dev->dev,
1983                         "Failed to create queue del task\n");
1984                 for (i = dev->queue_count - 1; i > 0; i--)
1985                         nvme_disable_queue(dev, i);
1986                 return;
1987         }
1988
1989         dq.waiter = NULL;
1990         atomic_set(&dq.refcount, 0);
1991         dq.worker = &worker;
1992         for (i = dev->queue_count - 1; i > 0; i--) {
1993                 struct nvme_queue *nvmeq = dev->queues[i];
1994
1995                 if (nvme_suspend_queue(nvmeq))
1996                         continue;
1997                 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
1998                 nvmeq->cmdinfo.worker = dq.worker;
1999                 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2000                 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2001         }
2002         nvme_wait_dq(&dq, dev);
2003         kthread_stop(kworker_task);
2004 }
2005
2006 static int nvme_dev_list_add(struct nvme_dev *dev)
2007 {
2008         bool start_thread = false;
2009
2010         spin_lock(&dev_list_lock);
2011         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2012                 start_thread = true;
2013                 nvme_thread = NULL;
2014         }
2015         list_add(&dev->node, &dev_list);
2016         spin_unlock(&dev_list_lock);
2017
2018         if (start_thread) {
2019                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2020                 wake_up_all(&nvme_kthread_wait);
2021         } else
2022                 wait_event_killable(nvme_kthread_wait, nvme_thread);
2023
2024         if (IS_ERR_OR_NULL(nvme_thread))
2025                 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2026
2027         return 0;
2028 }
2029
2030 /*
2031 * Remove the node from the device list and check
2032 * for whether or not we need to stop the nvme_thread.
2033 */
2034 static void nvme_dev_list_remove(struct nvme_dev *dev)
2035 {
2036         struct task_struct *tmp = NULL;
2037
2038         spin_lock(&dev_list_lock);
2039         list_del_init(&dev->node);
2040         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2041                 tmp = nvme_thread;
2042                 nvme_thread = NULL;
2043         }
2044         spin_unlock(&dev_list_lock);
2045
2046         if (tmp)
2047                 kthread_stop(tmp);
2048 }
2049
2050 static void nvme_freeze_queues(struct nvme_dev *dev)
2051 {
2052         struct nvme_ns *ns;
2053
2054         list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
2055                 blk_mq_freeze_queue_start(ns->queue);
2056
2057                 spin_lock_irq(ns->queue->queue_lock);
2058                 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2059                 spin_unlock_irq(ns->queue->queue_lock);
2060
2061                 blk_mq_cancel_requeue_work(ns->queue);
2062                 blk_mq_stop_hw_queues(ns->queue);
2063         }
2064 }
2065
2066 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2067 {
2068         struct nvme_ns *ns;
2069
2070         list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
2071                 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2072                 blk_mq_unfreeze_queue(ns->queue);
2073                 blk_mq_start_stopped_hw_queues(ns->queue, true);
2074                 blk_mq_kick_requeue_list(ns->queue);
2075         }
2076 }
2077
2078 static void nvme_dev_shutdown(struct nvme_dev *dev)
2079 {
2080         int i;
2081         u32 csts = -1;
2082
2083         nvme_dev_list_remove(dev);
2084
2085         mutex_lock(&dev->shutdown_lock);
2086         if (dev->bar) {
2087                 nvme_freeze_queues(dev);
2088                 csts = readl(dev->bar + NVME_REG_CSTS);
2089         }
2090         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2091                 for (i = dev->queue_count - 1; i >= 0; i--) {
2092                         struct nvme_queue *nvmeq = dev->queues[i];
2093                         nvme_suspend_queue(nvmeq);
2094                 }
2095         } else {
2096                 nvme_disable_io_queues(dev);
2097                 nvme_shutdown_ctrl(&dev->ctrl);
2098                 nvme_disable_queue(dev, 0);
2099         }
2100         nvme_dev_unmap(dev);
2101
2102         for (i = dev->queue_count - 1; i >= 0; i--)
2103                 nvme_clear_queue(dev->queues[i]);
2104         mutex_unlock(&dev->shutdown_lock);
2105 }
2106
2107 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2108 {
2109         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2110                                                 PAGE_SIZE, PAGE_SIZE, 0);
2111         if (!dev->prp_page_pool)
2112                 return -ENOMEM;
2113
2114         /* Optimisation for I/Os between 4k and 128k */
2115         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2116                                                 256, 256, 0);
2117         if (!dev->prp_small_pool) {
2118                 dma_pool_destroy(dev->prp_page_pool);
2119                 return -ENOMEM;
2120         }
2121         return 0;
2122 }
2123
2124 static void nvme_release_prp_pools(struct nvme_dev *dev)
2125 {
2126         dma_pool_destroy(dev->prp_page_pool);
2127         dma_pool_destroy(dev->prp_small_pool);
2128 }
2129
2130 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2131 {
2132         struct nvme_dev *dev = to_nvme_dev(ctrl);
2133
2134         put_device(dev->dev);
2135         if (dev->tagset.tags)
2136                 blk_mq_free_tag_set(&dev->tagset);
2137         if (dev->ctrl.admin_q)
2138                 blk_put_queue(dev->ctrl.admin_q);
2139         kfree(dev->queues);
2140         kfree(dev->entry);
2141         kfree(dev);
2142 }
2143
2144 static void nvme_reset_work(struct work_struct *work)
2145 {
2146         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2147         int result;
2148
2149         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
2150                 goto out;
2151
2152         /*
2153          * If we're called to reset a live controller first shut it down before
2154          * moving on.
2155          */
2156         if (dev->bar)
2157                 nvme_dev_shutdown(dev);
2158
2159         set_bit(NVME_CTRL_RESETTING, &dev->flags);
2160
2161         result = nvme_dev_map(dev);
2162         if (result)
2163                 goto out;
2164
2165         result = nvme_configure_admin_queue(dev);
2166         if (result)
2167                 goto unmap;
2168
2169         nvme_init_queue(dev->queues[0], 0);
2170         result = nvme_alloc_admin_tags(dev);
2171         if (result)
2172                 goto disable;
2173
2174         result = nvme_init_identify(&dev->ctrl);
2175         if (result)
2176                 goto free_tags;
2177
2178         result = nvme_setup_io_queues(dev);
2179         if (result)
2180                 goto free_tags;
2181
2182         dev->ctrl.event_limit = 1;
2183
2184         result = nvme_dev_list_add(dev);
2185         if (result)
2186                 goto remove;
2187
2188         /*
2189          * Keep the controller around but remove all namespaces if we don't have
2190          * any working I/O queue.
2191          */
2192         if (dev->online_queues < 2) {
2193                 dev_warn(dev->dev, "IO queues not created\n");
2194                 nvme_remove_namespaces(&dev->ctrl);
2195         } else {
2196                 nvme_unfreeze_queues(dev);
2197                 nvme_dev_add(dev);
2198         }
2199
2200         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
2201         return;
2202
2203  remove:
2204         nvme_dev_list_remove(dev);
2205  free_tags:
2206         nvme_dev_remove_admin(dev);
2207         blk_put_queue(dev->ctrl.admin_q);
2208         dev->ctrl.admin_q = NULL;
2209         dev->queues[0]->tags = NULL;
2210  disable:
2211         nvme_disable_queue(dev, 0);
2212  unmap:
2213         nvme_dev_unmap(dev);
2214  out:
2215         nvme_remove_dead_ctrl(dev);
2216 }
2217
2218 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2219 {
2220         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2221         struct pci_dev *pdev = to_pci_dev(dev->dev);
2222
2223         if (pci_get_drvdata(pdev))
2224                 pci_stop_and_remove_bus_device_locked(pdev);
2225         nvme_put_ctrl(&dev->ctrl);
2226 }
2227
2228 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2229 {
2230         dev_warn(dev->dev, "Removing after probe failure\n");
2231         kref_get(&dev->ctrl.kref);
2232         if (!schedule_work(&dev->remove_work))
2233                 nvme_put_ctrl(&dev->ctrl);
2234 }
2235
2236 static int nvme_reset(struct nvme_dev *dev)
2237 {
2238         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2239                 return -ENODEV;
2240
2241         if (!queue_work(nvme_workq, &dev->reset_work))
2242                 return -EBUSY;
2243
2244         flush_work(&dev->reset_work);
2245         return 0;
2246 }
2247
2248 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2249 {
2250         *val = readl(to_nvme_dev(ctrl)->bar + off);
2251         return 0;
2252 }
2253
2254 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2255 {
2256         writel(val, to_nvme_dev(ctrl)->bar + off);
2257         return 0;
2258 }
2259
2260 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2261 {
2262         *val = readq(to_nvme_dev(ctrl)->bar + off);
2263         return 0;
2264 }
2265
2266 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2267 {
2268         struct nvme_dev *dev = to_nvme_dev(ctrl);
2269
2270         return !dev->bar || dev->online_queues < 2;
2271 }
2272
2273 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2274 {
2275         return nvme_reset(to_nvme_dev(ctrl));
2276 }
2277
2278 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2279         .reg_read32             = nvme_pci_reg_read32,
2280         .reg_write32            = nvme_pci_reg_write32,
2281         .reg_read64             = nvme_pci_reg_read64,
2282         .io_incapable           = nvme_pci_io_incapable,
2283         .reset_ctrl             = nvme_pci_reset_ctrl,
2284         .free_ctrl              = nvme_pci_free_ctrl,
2285 };
2286
2287 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2288 {
2289         int node, result = -ENOMEM;
2290         struct nvme_dev *dev;
2291
2292         node = dev_to_node(&pdev->dev);
2293         if (node == NUMA_NO_NODE)
2294                 set_dev_node(&pdev->dev, 0);
2295
2296         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2297         if (!dev)
2298                 return -ENOMEM;
2299         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2300                                                         GFP_KERNEL, node);
2301         if (!dev->entry)
2302                 goto free;
2303         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2304                                                         GFP_KERNEL, node);
2305         if (!dev->queues)
2306                 goto free;
2307
2308         dev->dev = get_device(&pdev->dev);
2309         pci_set_drvdata(pdev, dev);
2310
2311         INIT_LIST_HEAD(&dev->node);
2312         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2313         INIT_WORK(&dev->reset_work, nvme_reset_work);
2314         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2315         mutex_init(&dev->shutdown_lock);
2316
2317         result = nvme_setup_prp_pools(dev);
2318         if (result)
2319                 goto put_pci;
2320
2321         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2322                         id->driver_data);
2323         if (result)
2324                 goto release_pools;
2325
2326         queue_work(nvme_workq, &dev->reset_work);
2327         return 0;
2328
2329  release_pools:
2330         nvme_release_prp_pools(dev);
2331  put_pci:
2332         put_device(dev->dev);
2333  free:
2334         kfree(dev->queues);
2335         kfree(dev->entry);
2336         kfree(dev);
2337         return result;
2338 }
2339
2340 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2341 {
2342         struct nvme_dev *dev = pci_get_drvdata(pdev);
2343
2344         if (prepare)
2345                 nvme_dev_shutdown(dev);
2346         else
2347                 queue_work(nvme_workq, &dev->reset_work);
2348 }
2349
2350 static void nvme_shutdown(struct pci_dev *pdev)
2351 {
2352         struct nvme_dev *dev = pci_get_drvdata(pdev);
2353         nvme_dev_shutdown(dev);
2354 }
2355
2356 static void nvme_remove(struct pci_dev *pdev)
2357 {
2358         struct nvme_dev *dev = pci_get_drvdata(pdev);
2359
2360         spin_lock(&dev_list_lock);
2361         list_del_init(&dev->node);
2362         spin_unlock(&dev_list_lock);
2363
2364         pci_set_drvdata(pdev, NULL);
2365         flush_work(&dev->reset_work);
2366         flush_work(&dev->scan_work);
2367         nvme_remove_namespaces(&dev->ctrl);
2368         nvme_uninit_ctrl(&dev->ctrl);
2369         nvme_dev_shutdown(dev);
2370         nvme_dev_remove_admin(dev);
2371         nvme_free_queues(dev, 0);
2372         nvme_release_cmb(dev);
2373         nvme_release_prp_pools(dev);
2374         nvme_put_ctrl(&dev->ctrl);
2375 }
2376
2377 /* These functions are yet to be implemented */
2378 #define nvme_error_detected NULL
2379 #define nvme_dump_registers NULL
2380 #define nvme_link_reset NULL
2381 #define nvme_slot_reset NULL
2382 #define nvme_error_resume NULL
2383
2384 #ifdef CONFIG_PM_SLEEP
2385 static int nvme_suspend(struct device *dev)
2386 {
2387         struct pci_dev *pdev = to_pci_dev(dev);
2388         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2389
2390         nvme_dev_shutdown(ndev);
2391         return 0;
2392 }
2393
2394 static int nvme_resume(struct device *dev)
2395 {
2396         struct pci_dev *pdev = to_pci_dev(dev);
2397         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2398
2399         queue_work(nvme_workq, &ndev->reset_work);
2400         return 0;
2401 }
2402 #endif
2403
2404 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2405
2406 static const struct pci_error_handlers nvme_err_handler = {
2407         .error_detected = nvme_error_detected,
2408         .mmio_enabled   = nvme_dump_registers,
2409         .link_reset     = nvme_link_reset,
2410         .slot_reset     = nvme_slot_reset,
2411         .resume         = nvme_error_resume,
2412         .reset_notify   = nvme_reset_notify,
2413 };
2414
2415 /* Move to pci_ids.h later */
2416 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2417
2418 static const struct pci_device_id nvme_id_table[] = {
2419         { PCI_VDEVICE(INTEL, 0x0953),
2420                 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2421         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2422                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2423         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2424         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2425         { 0, }
2426 };
2427 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2428
2429 static struct pci_driver nvme_driver = {
2430         .name           = "nvme",
2431         .id_table       = nvme_id_table,
2432         .probe          = nvme_probe,
2433         .remove         = nvme_remove,
2434         .shutdown       = nvme_shutdown,
2435         .driver         = {
2436                 .pm     = &nvme_dev_pm_ops,
2437         },
2438         .err_handler    = &nvme_err_handler,
2439 };
2440
2441 static int __init nvme_init(void)
2442 {
2443         int result;
2444
2445         init_waitqueue_head(&nvme_kthread_wait);
2446
2447         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2448         if (!nvme_workq)
2449                 return -ENOMEM;
2450
2451         result = nvme_core_init();
2452         if (result < 0)
2453                 goto kill_workq;
2454
2455         result = pci_register_driver(&nvme_driver);
2456         if (result)
2457                 goto core_exit;
2458         return 0;
2459
2460  core_exit:
2461         nvme_core_exit();
2462  kill_workq:
2463         destroy_workqueue(nvme_workq);
2464         return result;
2465 }
2466
2467 static void __exit nvme_exit(void)
2468 {
2469         pci_unregister_driver(&nvme_driver);
2470         nvme_core_exit();
2471         destroy_workqueue(nvme_workq);
2472         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2473         _nvme_check_size();
2474 }
2475
2476 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2477 MODULE_LICENSE("GPL");
2478 MODULE_VERSION("1.0");
2479 module_init(nvme_init);
2480 module_exit(nvme_exit);