2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/async.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
36 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
37 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
39 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
41 static int use_threaded_interrupts;
42 module_param(use_threaded_interrupts, int, 0);
44 static bool use_cmb_sqes = true;
45 module_param(use_cmb_sqes, bool, 0644);
46 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
48 static unsigned int max_host_mem_size_mb = 128;
49 module_param(max_host_mem_size_mb, uint, 0444);
50 MODULE_PARM_DESC(max_host_mem_size_mb,
51 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
53 static unsigned int sgl_threshold = SZ_32K;
54 module_param(sgl_threshold, uint, 0644);
55 MODULE_PARM_DESC(sgl_threshold,
56 "Use SGLs when average request segment size is larger or equal to "
57 "this size. Use 0 to disable SGLs.");
59 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
60 static const struct kernel_param_ops io_queue_depth_ops = {
61 .set = io_queue_depth_set,
65 static int io_queue_depth = 1024;
66 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
67 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
75 * Represents an NVM Express device. Each nvme_dev is a PCI function.
78 struct nvme_queue *queues;
79 struct blk_mq_tag_set tagset;
80 struct blk_mq_tag_set admin_tagset;
83 struct dma_pool *prp_page_pool;
84 struct dma_pool *prp_small_pool;
85 unsigned online_queues;
87 unsigned int num_vecs;
91 unsigned long bar_mapped_size;
92 struct work_struct remove_work;
93 struct mutex shutdown_lock;
96 pci_bus_addr_t cmb_bus_addr;
100 struct nvme_ctrl ctrl;
101 struct completion ioq_wait;
103 /* shadow doorbell buffer support: */
105 dma_addr_t dbbuf_dbs_dma_addr;
107 dma_addr_t dbbuf_eis_dma_addr;
109 /* host memory buffer support: */
111 u32 nr_host_mem_descs;
112 dma_addr_t host_mem_descs_dma;
113 struct nvme_host_mem_buf_desc *host_mem_descs;
114 void **host_mem_desc_bufs;
117 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
121 ret = kstrtoint(val, 10, &n);
122 if (ret != 0 || n < 2)
125 return param_set_int(val, kp);
128 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
130 return qid * 2 * stride;
133 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
135 return (qid * 2 + 1) * stride;
138 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
140 return container_of(ctrl, struct nvme_dev, ctrl);
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
148 struct device *q_dmadev;
149 struct nvme_dev *dev;
151 struct nvme_command *sq_cmds;
152 struct nvme_command __iomem *sq_cmds_io;
153 spinlock_t cq_lock ____cacheline_aligned_in_smp;
154 volatile struct nvme_completion *cqes;
155 struct blk_mq_tags **tags;
156 dma_addr_t sq_dma_addr;
157 dma_addr_t cq_dma_addr;
173 * The nvme_iod describes the data in an I/O, including the list of PRP
174 * entries. You can't see it in this data structure because C doesn't let
175 * me express that. Use nvme_init_iod to ensure there's enough space
176 * allocated to store the PRP list.
179 struct nvme_request req;
180 struct nvme_queue *nvmeq;
183 int npages; /* In the PRP list. 0 means small pool in use */
184 int nents; /* Used in scatterlist */
185 int length; /* Of data, in bytes */
186 dma_addr_t first_dma;
187 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
188 struct scatterlist *sg;
189 struct scatterlist inline_sg[0];
193 * Check we didin't inadvertently grow the command struct
195 static inline void _nvme_check_size(void)
197 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
205 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
206 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
207 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
208 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
209 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
212 static inline unsigned int nvme_dbbuf_size(u32 stride)
214 return ((num_possible_cpus() + 1) * 8 * stride);
217 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
219 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
224 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
225 &dev->dbbuf_dbs_dma_addr,
229 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
230 &dev->dbbuf_eis_dma_addr,
232 if (!dev->dbbuf_eis) {
233 dma_free_coherent(dev->dev, mem_size,
234 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
235 dev->dbbuf_dbs = NULL;
242 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
244 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
246 if (dev->dbbuf_dbs) {
247 dma_free_coherent(dev->dev, mem_size,
248 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
249 dev->dbbuf_dbs = NULL;
251 if (dev->dbbuf_eis) {
252 dma_free_coherent(dev->dev, mem_size,
253 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
254 dev->dbbuf_eis = NULL;
258 static void nvme_dbbuf_init(struct nvme_dev *dev,
259 struct nvme_queue *nvmeq, int qid)
261 if (!dev->dbbuf_dbs || !qid)
264 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
266 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
267 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
270 static void nvme_dbbuf_set(struct nvme_dev *dev)
272 struct nvme_command c;
277 memset(&c, 0, sizeof(c));
278 c.dbbuf.opcode = nvme_admin_dbbuf;
279 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
280 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
282 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
283 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
284 /* Free memory and continue on */
285 nvme_dbbuf_dma_free(dev);
289 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
291 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
294 /* Update dbbuf and return true if an MMIO is required */
295 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
296 volatile u32 *dbbuf_ei)
302 * Ensure that the queue is written before updating
303 * the doorbell in memory
307 old_value = *dbbuf_db;
310 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
318 * Max size of iod being embedded in the request payload
320 #define NVME_INT_PAGES 2
321 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
324 * Will slightly overestimate the number of pages needed. This is OK
325 * as it only leads to a small amount of wasted memory for the lifetime of
328 static int nvme_npages(unsigned size, struct nvme_dev *dev)
330 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
331 dev->ctrl.page_size);
332 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
336 * Calculates the number of pages needed for the SGL segments. For example a 4k
337 * page can accommodate 256 SGL descriptors.
339 static int nvme_pci_npages_sgl(unsigned int num_seg)
341 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
344 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
345 unsigned int size, unsigned int nseg, bool use_sgl)
350 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
352 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
354 return alloc_size + sizeof(struct scatterlist) * nseg;
357 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
359 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
360 NVME_INT_BYTES(dev), NVME_INT_PAGES,
363 return sizeof(struct nvme_iod) + alloc_size;
366 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
367 unsigned int hctx_idx)
369 struct nvme_dev *dev = data;
370 struct nvme_queue *nvmeq = &dev->queues[0];
372 WARN_ON(hctx_idx != 0);
373 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
374 WARN_ON(nvmeq->tags);
376 hctx->driver_data = nvmeq;
377 nvmeq->tags = &dev->admin_tagset.tags[0];
381 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
383 struct nvme_queue *nvmeq = hctx->driver_data;
388 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
389 unsigned int hctx_idx)
391 struct nvme_dev *dev = data;
392 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
395 nvmeq->tags = &dev->tagset.tags[hctx_idx];
397 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
398 hctx->driver_data = nvmeq;
402 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
403 unsigned int hctx_idx, unsigned int numa_node)
405 struct nvme_dev *dev = set->driver_data;
406 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
407 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
408 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
415 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
417 struct nvme_dev *dev = set->driver_data;
419 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
420 dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
424 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
425 * @nvmeq: The queue to use
426 * @cmd: The command to send
428 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
430 spin_lock(&nvmeq->sq_lock);
431 if (nvmeq->sq_cmds_io)
432 memcpy_toio(&nvmeq->sq_cmds_io[nvmeq->sq_tail], cmd,
435 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
437 if (++nvmeq->sq_tail == nvmeq->q_depth)
439 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
440 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
441 writel(nvmeq->sq_tail, nvmeq->q_db);
442 spin_unlock(&nvmeq->sq_lock);
445 static void **nvme_pci_iod_list(struct request *req)
447 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
448 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
451 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
453 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
454 int nseg = blk_rq_nr_phys_segments(req);
455 unsigned int avg_seg_size;
460 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
462 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
464 if (!iod->nvmeq->qid)
466 if (!sgl_threshold || avg_seg_size < sgl_threshold)
471 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
473 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
474 int nseg = blk_rq_nr_phys_segments(rq);
475 unsigned int size = blk_rq_payload_bytes(rq);
477 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
479 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
480 size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg,
483 iod->sg = kmalloc(alloc_size, GFP_ATOMIC);
485 return BLK_STS_RESOURCE;
487 iod->sg = iod->inline_sg;
498 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
500 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
501 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
502 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
506 if (iod->npages == 0)
507 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
510 for (i = 0; i < iod->npages; i++) {
511 void *addr = nvme_pci_iod_list(req)[i];
514 struct nvme_sgl_desc *sg_list = addr;
517 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
519 __le64 *prp_list = addr;
521 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
524 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
525 dma_addr = next_dma_addr;
528 if (iod->sg != iod->inline_sg)
532 #ifdef CONFIG_BLK_DEV_INTEGRITY
533 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
535 if (be32_to_cpu(pi->ref_tag) == v)
536 pi->ref_tag = cpu_to_be32(p);
539 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
541 if (be32_to_cpu(pi->ref_tag) == p)
542 pi->ref_tag = cpu_to_be32(v);
546 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
548 * The virtual start sector is the one that was originally submitted by the
549 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
550 * start sector may be different. Remap protection information to match the
551 * physical LBA on writes, and back to the original seed on reads.
553 * Type 0 and 3 do not have a ref tag, so no remapping required.
555 static void nvme_dif_remap(struct request *req,
556 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
558 struct nvme_ns *ns = req->rq_disk->private_data;
559 struct bio_integrity_payload *bip;
560 struct t10_pi_tuple *pi;
562 u32 i, nlb, ts, phys, virt;
564 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
567 bip = bio_integrity(req->bio);
571 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
574 virt = bip_get_seed(bip);
575 phys = nvme_block_nr(ns, blk_rq_pos(req));
576 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
577 ts = ns->disk->queue->integrity.tuple_size;
579 for (i = 0; i < nlb; i++, virt++, phys++) {
580 pi = (struct t10_pi_tuple *)p;
581 dif_swap(phys, virt, pi);
586 #else /* CONFIG_BLK_DEV_INTEGRITY */
587 static void nvme_dif_remap(struct request *req,
588 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
591 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
594 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
599 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
602 struct scatterlist *sg;
604 for_each_sg(sgl, sg, nents, i) {
605 dma_addr_t phys = sg_phys(sg);
606 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
607 "dma_address:%pad dma_length:%d\n",
608 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
613 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
614 struct request *req, struct nvme_rw_command *cmnd)
616 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
617 struct dma_pool *pool;
618 int length = blk_rq_payload_bytes(req);
619 struct scatterlist *sg = iod->sg;
620 int dma_len = sg_dma_len(sg);
621 u64 dma_addr = sg_dma_address(sg);
622 u32 page_size = dev->ctrl.page_size;
623 int offset = dma_addr & (page_size - 1);
625 void **list = nvme_pci_iod_list(req);
629 length -= (page_size - offset);
635 dma_len -= (page_size - offset);
637 dma_addr += (page_size - offset);
640 dma_addr = sg_dma_address(sg);
641 dma_len = sg_dma_len(sg);
644 if (length <= page_size) {
645 iod->first_dma = dma_addr;
649 nprps = DIV_ROUND_UP(length, page_size);
650 if (nprps <= (256 / 8)) {
651 pool = dev->prp_small_pool;
654 pool = dev->prp_page_pool;
658 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
660 iod->first_dma = dma_addr;
662 return BLK_STS_RESOURCE;
665 iod->first_dma = prp_dma;
668 if (i == page_size >> 3) {
669 __le64 *old_prp_list = prp_list;
670 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
672 return BLK_STS_RESOURCE;
673 list[iod->npages++] = prp_list;
674 prp_list[0] = old_prp_list[i - 1];
675 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
678 prp_list[i++] = cpu_to_le64(dma_addr);
679 dma_len -= page_size;
680 dma_addr += page_size;
686 if (unlikely(dma_len < 0))
689 dma_addr = sg_dma_address(sg);
690 dma_len = sg_dma_len(sg);
694 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
695 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
700 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
701 "Invalid SGL for payload:%d nents:%d\n",
702 blk_rq_payload_bytes(req), iod->nents);
703 return BLK_STS_IOERR;
706 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
707 struct scatterlist *sg)
709 sge->addr = cpu_to_le64(sg_dma_address(sg));
710 sge->length = cpu_to_le32(sg_dma_len(sg));
711 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
714 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
715 dma_addr_t dma_addr, int entries)
717 sge->addr = cpu_to_le64(dma_addr);
718 if (entries < SGES_PER_PAGE) {
719 sge->length = cpu_to_le32(entries * sizeof(*sge));
720 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
722 sge->length = cpu_to_le32(PAGE_SIZE);
723 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
727 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
728 struct request *req, struct nvme_rw_command *cmd, int entries)
730 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
731 struct dma_pool *pool;
732 struct nvme_sgl_desc *sg_list;
733 struct scatterlist *sg = iod->sg;
737 /* setting the transfer type as SGL */
738 cmd->flags = NVME_CMD_SGL_METABUF;
741 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
745 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
746 pool = dev->prp_small_pool;
749 pool = dev->prp_page_pool;
753 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
756 return BLK_STS_RESOURCE;
759 nvme_pci_iod_list(req)[0] = sg_list;
760 iod->first_dma = sgl_dma;
762 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
765 if (i == SGES_PER_PAGE) {
766 struct nvme_sgl_desc *old_sg_desc = sg_list;
767 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
769 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
771 return BLK_STS_RESOURCE;
774 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
775 sg_list[i++] = *link;
776 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
779 nvme_pci_sgl_set_data(&sg_list[i++], sg);
781 } while (--entries > 0);
786 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
787 struct nvme_command *cmnd)
789 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
790 struct request_queue *q = req->q;
791 enum dma_data_direction dma_dir = rq_data_dir(req) ?
792 DMA_TO_DEVICE : DMA_FROM_DEVICE;
793 blk_status_t ret = BLK_STS_IOERR;
796 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
797 iod->nents = blk_rq_map_sg(q, req, iod->sg);
801 ret = BLK_STS_RESOURCE;
802 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
808 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
810 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
812 if (ret != BLK_STS_OK)
816 if (blk_integrity_rq(req)) {
817 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
820 sg_init_table(&iod->meta_sg, 1);
821 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
824 if (req_op(req) == REQ_OP_WRITE)
825 nvme_dif_remap(req, nvme_dif_prep);
827 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
831 if (blk_integrity_rq(req))
832 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
836 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
841 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
844 enum dma_data_direction dma_dir = rq_data_dir(req) ?
845 DMA_TO_DEVICE : DMA_FROM_DEVICE;
848 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
849 if (blk_integrity_rq(req)) {
850 if (req_op(req) == REQ_OP_READ)
851 nvme_dif_remap(req, nvme_dif_complete);
852 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
856 nvme_cleanup_cmd(req);
857 nvme_free_iod(dev, req);
861 * NOTE: ns is NULL when called on the admin queue.
863 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
864 const struct blk_mq_queue_data *bd)
866 struct nvme_ns *ns = hctx->queue->queuedata;
867 struct nvme_queue *nvmeq = hctx->driver_data;
868 struct nvme_dev *dev = nvmeq->dev;
869 struct request *req = bd->rq;
870 struct nvme_command cmnd;
874 * We should not need to do this, but we're still using this to
875 * ensure we can drain requests on a dying queue.
877 if (unlikely(nvmeq->cq_vector < 0))
878 return BLK_STS_IOERR;
880 ret = nvme_setup_cmd(ns, req, &cmnd);
884 ret = nvme_init_iod(req, dev);
888 if (blk_rq_nr_phys_segments(req)) {
889 ret = nvme_map_data(dev, req, &cmnd);
891 goto out_cleanup_iod;
894 blk_mq_start_request(req);
895 nvme_submit_cmd(nvmeq, &cmnd);
898 nvme_free_iod(dev, req);
900 nvme_cleanup_cmd(req);
904 static void nvme_pci_complete_rq(struct request *req)
906 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
908 nvme_unmap_data(iod->nvmeq->dev, req);
909 nvme_complete_rq(req);
912 /* We read the CQE phase first to check if the rest of the entry is valid */
913 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
915 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
919 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
921 u16 head = nvmeq->cq_head;
923 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
925 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
928 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
930 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
933 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
934 dev_warn(nvmeq->dev->ctrl.device,
935 "invalid id %d completed on queue %d\n",
936 cqe->command_id, le16_to_cpu(cqe->sq_id));
941 * AEN requests are special as they don't time out and can
942 * survive any kind of queue freeze and often don't respond to
943 * aborts. We don't even bother to allocate a struct request
944 * for them but rather special case them here.
946 if (unlikely(nvmeq->qid == 0 &&
947 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
948 nvme_complete_async_event(&nvmeq->dev->ctrl,
949 cqe->status, &cqe->result);
953 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
954 nvme_end_request(req, cqe->status, cqe->result);
957 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
959 while (start != end) {
960 nvme_handle_cqe(nvmeq, start);
961 if (++start == nvmeq->q_depth)
966 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
968 if (++nvmeq->cq_head == nvmeq->q_depth) {
970 nvmeq->cq_phase = !nvmeq->cq_phase;
974 static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
979 *start = nvmeq->cq_head;
980 while (!found && nvme_cqe_pending(nvmeq)) {
981 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
983 nvme_update_cq_head(nvmeq);
985 *end = nvmeq->cq_head;
988 nvme_ring_cq_doorbell(nvmeq);
992 static irqreturn_t nvme_irq(int irq, void *data)
994 struct nvme_queue *nvmeq = data;
995 irqreturn_t ret = IRQ_NONE;
998 spin_lock(&nvmeq->cq_lock);
999 if (nvmeq->cq_head != nvmeq->last_cq_head)
1001 nvme_process_cq(nvmeq, &start, &end, -1);
1002 nvmeq->last_cq_head = nvmeq->cq_head;
1003 spin_unlock(&nvmeq->cq_lock);
1006 nvme_complete_cqes(nvmeq, start, end);
1013 static irqreturn_t nvme_irq_check(int irq, void *data)
1015 struct nvme_queue *nvmeq = data;
1016 if (nvme_cqe_pending(nvmeq))
1017 return IRQ_WAKE_THREAD;
1021 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
1026 if (!nvme_cqe_pending(nvmeq))
1029 spin_lock_irq(&nvmeq->cq_lock);
1030 found = nvme_process_cq(nvmeq, &start, &end, tag);
1031 spin_unlock_irq(&nvmeq->cq_lock);
1033 nvme_complete_cqes(nvmeq, start, end);
1037 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1039 struct nvme_queue *nvmeq = hctx->driver_data;
1041 return __nvme_poll(nvmeq, tag);
1044 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1046 struct nvme_dev *dev = to_nvme_dev(ctrl);
1047 struct nvme_queue *nvmeq = &dev->queues[0];
1048 struct nvme_command c;
1050 memset(&c, 0, sizeof(c));
1051 c.common.opcode = nvme_admin_async_event;
1052 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1053 nvme_submit_cmd(nvmeq, &c);
1056 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1058 struct nvme_command c;
1060 memset(&c, 0, sizeof(c));
1061 c.delete_queue.opcode = opcode;
1062 c.delete_queue.qid = cpu_to_le16(id);
1064 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1067 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1068 struct nvme_queue *nvmeq, s16 vector)
1070 struct nvme_command c;
1071 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1074 * Note: we (ab)use the fact that the prp fields survive if no data
1075 * is attached to the request.
1077 memset(&c, 0, sizeof(c));
1078 c.create_cq.opcode = nvme_admin_create_cq;
1079 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1080 c.create_cq.cqid = cpu_to_le16(qid);
1081 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1082 c.create_cq.cq_flags = cpu_to_le16(flags);
1083 c.create_cq.irq_vector = cpu_to_le16(vector);
1085 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1088 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1089 struct nvme_queue *nvmeq)
1091 struct nvme_ctrl *ctrl = &dev->ctrl;
1092 struct nvme_command c;
1093 int flags = NVME_QUEUE_PHYS_CONTIG;
1096 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1097 * set. Since URGENT priority is zeroes, it makes all queues
1100 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1101 flags |= NVME_SQ_PRIO_MEDIUM;
1104 * Note: we (ab)use the fact that the prp fields survive if no data
1105 * is attached to the request.
1107 memset(&c, 0, sizeof(c));
1108 c.create_sq.opcode = nvme_admin_create_sq;
1109 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1110 c.create_sq.sqid = cpu_to_le16(qid);
1111 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1112 c.create_sq.sq_flags = cpu_to_le16(flags);
1113 c.create_sq.cqid = cpu_to_le16(qid);
1115 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1118 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1120 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1123 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1125 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1128 static void abort_endio(struct request *req, blk_status_t error)
1130 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1131 struct nvme_queue *nvmeq = iod->nvmeq;
1133 dev_warn(nvmeq->dev->ctrl.device,
1134 "Abort status: 0x%x", nvme_req(req)->status);
1135 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1136 blk_mq_free_request(req);
1139 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1142 /* If true, indicates loss of adapter communication, possibly by a
1143 * NVMe Subsystem reset.
1145 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1147 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1148 switch (dev->ctrl.state) {
1149 case NVME_CTRL_RESETTING:
1150 case NVME_CTRL_CONNECTING:
1156 /* We shouldn't reset unless the controller is on fatal error state
1157 * _or_ if we lost the communication with it.
1159 if (!(csts & NVME_CSTS_CFS) && !nssro)
1165 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1167 /* Read a config register to help see what died. */
1171 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1173 if (result == PCIBIOS_SUCCESSFUL)
1174 dev_warn(dev->ctrl.device,
1175 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1178 dev_warn(dev->ctrl.device,
1179 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1183 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1185 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1186 struct nvme_queue *nvmeq = iod->nvmeq;
1187 struct nvme_dev *dev = nvmeq->dev;
1188 struct request *abort_req;
1189 struct nvme_command cmd;
1190 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1192 /* If PCI error recovery process is happening, we cannot reset or
1193 * the recovery mechanism will surely fail.
1196 if (pci_channel_offline(to_pci_dev(dev->dev)))
1197 return BLK_EH_RESET_TIMER;
1200 * Reset immediately if the controller is failed
1202 if (nvme_should_reset(dev, csts)) {
1203 nvme_warn_reset(dev, csts);
1204 nvme_dev_disable(dev, false);
1205 nvme_reset_ctrl(&dev->ctrl);
1210 * Did we miss an interrupt?
1212 if (__nvme_poll(nvmeq, req->tag)) {
1213 dev_warn(dev->ctrl.device,
1214 "I/O %d QID %d timeout, completion polled\n",
1215 req->tag, nvmeq->qid);
1220 * Shutdown immediately if controller times out while starting. The
1221 * reset work will see the pci device disabled when it gets the forced
1222 * cancellation error. All outstanding requests are completed on
1223 * shutdown, so we return BLK_EH_DONE.
1225 switch (dev->ctrl.state) {
1226 case NVME_CTRL_CONNECTING:
1227 case NVME_CTRL_RESETTING:
1228 dev_warn_ratelimited(dev->ctrl.device,
1229 "I/O %d QID %d timeout, disable controller\n",
1230 req->tag, nvmeq->qid);
1231 nvme_dev_disable(dev, false);
1232 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1239 * Shutdown the controller immediately and schedule a reset if the
1240 * command was already aborted once before and still hasn't been
1241 * returned to the driver, or if this is the admin queue.
1243 if (!nvmeq->qid || iod->aborted) {
1244 dev_warn(dev->ctrl.device,
1245 "I/O %d QID %d timeout, reset controller\n",
1246 req->tag, nvmeq->qid);
1247 nvme_dev_disable(dev, false);
1248 nvme_reset_ctrl(&dev->ctrl);
1250 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1254 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1255 atomic_inc(&dev->ctrl.abort_limit);
1256 return BLK_EH_RESET_TIMER;
1260 memset(&cmd, 0, sizeof(cmd));
1261 cmd.abort.opcode = nvme_admin_abort_cmd;
1262 cmd.abort.cid = req->tag;
1263 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1265 dev_warn(nvmeq->dev->ctrl.device,
1266 "I/O %d QID %d timeout, aborting\n",
1267 req->tag, nvmeq->qid);
1269 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1270 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1271 if (IS_ERR(abort_req)) {
1272 atomic_inc(&dev->ctrl.abort_limit);
1273 return BLK_EH_RESET_TIMER;
1276 abort_req->timeout = ADMIN_TIMEOUT;
1277 abort_req->end_io_data = NULL;
1278 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1281 * The aborted req will be completed on receiving the abort req.
1282 * We enable the timer again. If hit twice, it'll cause a device reset,
1283 * as the device then is in a faulty state.
1285 return BLK_EH_RESET_TIMER;
1288 static void nvme_free_queue(struct nvme_queue *nvmeq)
1290 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1291 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1293 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1294 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1297 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1301 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1302 dev->ctrl.queue_count--;
1303 nvme_free_queue(&dev->queues[i]);
1308 * nvme_suspend_queue - put queue into suspended state
1309 * @nvmeq - queue to suspend
1311 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1315 spin_lock_irq(&nvmeq->cq_lock);
1316 if (nvmeq->cq_vector == -1) {
1317 spin_unlock_irq(&nvmeq->cq_lock);
1320 vector = nvmeq->cq_vector;
1321 nvmeq->dev->online_queues--;
1322 nvmeq->cq_vector = -1;
1323 spin_unlock_irq(&nvmeq->cq_lock);
1326 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1327 * having to grab the lock.
1331 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1332 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1334 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1339 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1341 struct nvme_queue *nvmeq = &dev->queues[0];
1345 nvme_shutdown_ctrl(&dev->ctrl);
1347 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1349 spin_lock_irq(&nvmeq->cq_lock);
1350 nvme_process_cq(nvmeq, &start, &end, -1);
1351 spin_unlock_irq(&nvmeq->cq_lock);
1353 nvme_complete_cqes(nvmeq, start, end);
1356 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1359 int q_depth = dev->q_depth;
1360 unsigned q_size_aligned = roundup(q_depth * entry_size,
1361 dev->ctrl.page_size);
1363 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1364 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1365 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1366 q_depth = div_u64(mem_per_q, entry_size);
1369 * Ensure the reduced q_depth is above some threshold where it
1370 * would be better to map queues in system memory with the
1380 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1383 /* CMB SQEs will be mapped before creation */
1384 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1387 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1388 &nvmeq->sq_dma_addr, GFP_KERNEL);
1389 if (!nvmeq->sq_cmds)
1394 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1396 struct nvme_queue *nvmeq = &dev->queues[qid];
1398 if (dev->ctrl.queue_count > qid)
1401 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1402 &nvmeq->cq_dma_addr, GFP_KERNEL);
1406 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1409 nvmeq->q_dmadev = dev->dev;
1411 spin_lock_init(&nvmeq->sq_lock);
1412 spin_lock_init(&nvmeq->cq_lock);
1414 nvmeq->cq_phase = 1;
1415 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1416 nvmeq->q_depth = depth;
1418 nvmeq->cq_vector = -1;
1419 dev->ctrl.queue_count++;
1424 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1425 nvmeq->cq_dma_addr);
1430 static int queue_request_irq(struct nvme_queue *nvmeq)
1432 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1433 int nr = nvmeq->dev->ctrl.instance;
1435 if (use_threaded_interrupts) {
1436 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1437 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1439 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1440 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1444 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1446 struct nvme_dev *dev = nvmeq->dev;
1448 spin_lock_irq(&nvmeq->cq_lock);
1451 nvmeq->cq_phase = 1;
1452 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1453 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1454 nvme_dbbuf_init(dev, nvmeq, qid);
1455 dev->online_queues++;
1456 spin_unlock_irq(&nvmeq->cq_lock);
1459 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1461 struct nvme_dev *dev = nvmeq->dev;
1465 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1466 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1467 dev->ctrl.page_size);
1468 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1469 nvmeq->sq_cmds_io = dev->cmb + offset;
1473 * A queue's vector matches the queue identifier unless the controller
1474 * has only one vector available.
1476 vector = dev->num_vecs == 1 ? 0 : qid;
1477 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1481 result = adapter_alloc_sq(dev, qid, nvmeq);
1488 * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
1489 * invoke free_irq for it and cause a 'Trying to free already-free IRQ
1490 * xxx' warning if the create CQ/SQ command times out.
1492 nvmeq->cq_vector = vector;
1493 nvme_init_queue(nvmeq, qid);
1494 result = queue_request_irq(nvmeq);
1501 nvmeq->cq_vector = -1;
1502 dev->online_queues--;
1503 adapter_delete_sq(dev, qid);
1505 adapter_delete_cq(dev, qid);
1509 static const struct blk_mq_ops nvme_mq_admin_ops = {
1510 .queue_rq = nvme_queue_rq,
1511 .complete = nvme_pci_complete_rq,
1512 .init_hctx = nvme_admin_init_hctx,
1513 .exit_hctx = nvme_admin_exit_hctx,
1514 .init_request = nvme_init_request,
1515 .timeout = nvme_timeout,
1518 static const struct blk_mq_ops nvme_mq_ops = {
1519 .queue_rq = nvme_queue_rq,
1520 .complete = nvme_pci_complete_rq,
1521 .init_hctx = nvme_init_hctx,
1522 .init_request = nvme_init_request,
1523 .map_queues = nvme_pci_map_queues,
1524 .timeout = nvme_timeout,
1528 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1530 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1532 * If the controller was reset during removal, it's possible
1533 * user requests may be waiting on a stopped queue. Start the
1534 * queue to flush these to completion.
1536 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1537 blk_cleanup_queue(dev->ctrl.admin_q);
1538 blk_mq_free_tag_set(&dev->admin_tagset);
1542 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1544 if (!dev->ctrl.admin_q) {
1545 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1546 dev->admin_tagset.nr_hw_queues = 1;
1548 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1549 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1550 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1551 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1552 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1553 dev->admin_tagset.driver_data = dev;
1555 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1557 dev->ctrl.admin_tagset = &dev->admin_tagset;
1559 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1560 if (IS_ERR(dev->ctrl.admin_q)) {
1561 blk_mq_free_tag_set(&dev->admin_tagset);
1564 if (!blk_get_queue(dev->ctrl.admin_q)) {
1565 nvme_dev_remove_admin(dev);
1566 dev->ctrl.admin_q = NULL;
1570 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1575 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1577 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1580 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1582 struct pci_dev *pdev = to_pci_dev(dev->dev);
1584 if (size <= dev->bar_mapped_size)
1586 if (size > pci_resource_len(pdev, 0))
1590 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1592 dev->bar_mapped_size = 0;
1595 dev->bar_mapped_size = size;
1596 dev->dbs = dev->bar + NVME_REG_DBS;
1601 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1605 struct nvme_queue *nvmeq;
1607 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1611 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1612 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1614 if (dev->subsystem &&
1615 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1616 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1618 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1622 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1626 nvmeq = &dev->queues[0];
1627 aqa = nvmeq->q_depth - 1;
1630 writel(aqa, dev->bar + NVME_REG_AQA);
1631 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1632 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1634 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1638 nvmeq->cq_vector = 0;
1639 nvme_init_queue(nvmeq, 0);
1640 result = queue_request_irq(nvmeq);
1642 nvmeq->cq_vector = -1;
1649 static int nvme_create_io_queues(struct nvme_dev *dev)
1654 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1655 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1661 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1662 for (i = dev->online_queues; i <= max; i++) {
1663 ret = nvme_create_queue(&dev->queues[i], i);
1669 * Ignore failing Create SQ/CQ commands, we can continue with less
1670 * than the desired amount of queues, and even a controller without
1671 * I/O queues can still be used to issue admin commands. This might
1672 * be useful to upgrade a buggy firmware for example.
1674 return ret >= 0 ? 0 : ret;
1677 static ssize_t nvme_cmb_show(struct device *dev,
1678 struct device_attribute *attr,
1681 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1683 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1684 ndev->cmbloc, ndev->cmbsz);
1686 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1688 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1690 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1692 return 1ULL << (12 + 4 * szu);
1695 static u32 nvme_cmb_size(struct nvme_dev *dev)
1697 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1700 static void nvme_map_cmb(struct nvme_dev *dev)
1703 resource_size_t bar_size;
1704 struct pci_dev *pdev = to_pci_dev(dev->dev);
1707 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1710 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1715 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1716 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1717 bar = NVME_CMB_BIR(dev->cmbloc);
1718 bar_size = pci_resource_len(pdev, bar);
1720 if (offset > bar_size)
1724 * Controllers may support a CMB size larger than their BAR,
1725 * for example, due to being behind a bridge. Reduce the CMB to
1726 * the reported size of the BAR
1728 if (size > bar_size - offset)
1729 size = bar_size - offset;
1731 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1734 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1735 dev->cmb_size = size;
1737 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1738 &dev_attr_cmb.attr, NULL))
1739 dev_warn(dev->ctrl.device,
1740 "failed to add sysfs attribute for CMB\n");
1743 static inline void nvme_release_cmb(struct nvme_dev *dev)
1748 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1749 &dev_attr_cmb.attr, NULL);
1754 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1756 u64 dma_addr = dev->host_mem_descs_dma;
1757 struct nvme_command c;
1760 memset(&c, 0, sizeof(c));
1761 c.features.opcode = nvme_admin_set_features;
1762 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1763 c.features.dword11 = cpu_to_le32(bits);
1764 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1765 ilog2(dev->ctrl.page_size));
1766 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1767 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1768 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1770 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1772 dev_warn(dev->ctrl.device,
1773 "failed to set host mem (err %d, flags %#x).\n",
1779 static void nvme_free_host_mem(struct nvme_dev *dev)
1783 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1784 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1785 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1787 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1788 le64_to_cpu(desc->addr));
1791 kfree(dev->host_mem_desc_bufs);
1792 dev->host_mem_desc_bufs = NULL;
1793 dma_free_coherent(dev->dev,
1794 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1795 dev->host_mem_descs, dev->host_mem_descs_dma);
1796 dev->host_mem_descs = NULL;
1797 dev->nr_host_mem_descs = 0;
1800 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1803 struct nvme_host_mem_buf_desc *descs;
1804 u32 max_entries, len;
1805 dma_addr_t descs_dma;
1810 tmp = (preferred + chunk_size - 1);
1811 do_div(tmp, chunk_size);
1814 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1815 max_entries = dev->ctrl.hmmaxd;
1817 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1818 &descs_dma, GFP_KERNEL);
1822 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1824 goto out_free_descs;
1826 for (size = 0; size < preferred && i < max_entries; size += len) {
1827 dma_addr_t dma_addr;
1829 len = min_t(u64, chunk_size, preferred - size);
1830 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1831 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1835 descs[i].addr = cpu_to_le64(dma_addr);
1836 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1843 dev->nr_host_mem_descs = i;
1844 dev->host_mem_size = size;
1845 dev->host_mem_descs = descs;
1846 dev->host_mem_descs_dma = descs_dma;
1847 dev->host_mem_desc_bufs = bufs;
1852 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1854 dma_free_coherent(dev->dev, size, bufs[i],
1855 le64_to_cpu(descs[i].addr));
1860 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1863 dev->host_mem_descs = NULL;
1867 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1871 /* start big and work our way down */
1872 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1873 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1875 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1876 if (!min || dev->host_mem_size >= min)
1878 nvme_free_host_mem(dev);
1885 static int nvme_setup_host_mem(struct nvme_dev *dev)
1887 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1888 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1889 u64 min = (u64)dev->ctrl.hmmin * 4096;
1890 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1893 preferred = min(preferred, max);
1895 dev_warn(dev->ctrl.device,
1896 "min host memory (%lld MiB) above limit (%d MiB).\n",
1897 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1898 nvme_free_host_mem(dev);
1903 * If we already have a buffer allocated check if we can reuse it.
1905 if (dev->host_mem_descs) {
1906 if (dev->host_mem_size >= min)
1907 enable_bits |= NVME_HOST_MEM_RETURN;
1909 nvme_free_host_mem(dev);
1912 if (!dev->host_mem_descs) {
1913 if (nvme_alloc_host_mem(dev, min, preferred)) {
1914 dev_warn(dev->ctrl.device,
1915 "failed to allocate host memory buffer.\n");
1916 return 0; /* controller must work without HMB */
1919 dev_info(dev->ctrl.device,
1920 "allocated %lld MiB host memory buffer.\n",
1921 dev->host_mem_size >> ilog2(SZ_1M));
1924 ret = nvme_set_host_mem(dev, enable_bits);
1926 nvme_free_host_mem(dev);
1930 static int nvme_setup_io_queues(struct nvme_dev *dev)
1932 struct nvme_queue *adminq = &dev->queues[0];
1933 struct pci_dev *pdev = to_pci_dev(dev->dev);
1934 int result, nr_io_queues;
1937 struct irq_affinity affd = {
1941 nr_io_queues = num_possible_cpus();
1942 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1946 if (nr_io_queues == 0)
1949 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1950 result = nvme_cmb_qdepth(dev, nr_io_queues,
1951 sizeof(struct nvme_command));
1953 dev->q_depth = result;
1955 nvme_release_cmb(dev);
1959 size = db_bar_size(dev, nr_io_queues);
1960 result = nvme_remap_bar(dev, size);
1963 if (!--nr_io_queues)
1966 adminq->q_db = dev->dbs;
1968 /* Deregister the admin queue's interrupt */
1969 pci_free_irq(pdev, 0, adminq);
1972 * If we enable msix early due to not intx, disable it again before
1973 * setting up the full range we need.
1975 pci_free_irq_vectors(pdev);
1976 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1977 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1980 dev->num_vecs = result;
1981 dev->max_qid = max(result - 1, 1);
1984 * Should investigate if there's a performance win from allocating
1985 * more queues than interrupt vectors; it might allow the submission
1986 * path to scale better, even if the receive path is limited by the
1987 * number of interrupts.
1990 result = queue_request_irq(adminq);
1992 adminq->cq_vector = -1;
1995 return nvme_create_io_queues(dev);
1998 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2000 struct nvme_queue *nvmeq = req->end_io_data;
2002 blk_mq_free_request(req);
2003 complete(&nvmeq->dev->ioq_wait);
2006 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2008 struct nvme_queue *nvmeq = req->end_io_data;
2012 unsigned long flags;
2014 spin_lock_irqsave(&nvmeq->cq_lock, flags);
2015 nvme_process_cq(nvmeq, &start, &end, -1);
2016 spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
2018 nvme_complete_cqes(nvmeq, start, end);
2021 nvme_del_queue_end(req, error);
2024 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2026 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2027 struct request *req;
2028 struct nvme_command cmd;
2030 memset(&cmd, 0, sizeof(cmd));
2031 cmd.delete_queue.opcode = opcode;
2032 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2034 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2036 return PTR_ERR(req);
2038 req->timeout = ADMIN_TIMEOUT;
2039 req->end_io_data = nvmeq;
2041 blk_execute_rq_nowait(q, NULL, req, false,
2042 opcode == nvme_admin_delete_cq ?
2043 nvme_del_cq_end : nvme_del_queue_end);
2047 static void nvme_disable_io_queues(struct nvme_dev *dev)
2049 int pass, queues = dev->online_queues - 1;
2050 unsigned long timeout;
2051 u8 opcode = nvme_admin_delete_sq;
2053 for (pass = 0; pass < 2; pass++) {
2054 int sent = 0, i = queues;
2056 reinit_completion(&dev->ioq_wait);
2058 timeout = ADMIN_TIMEOUT;
2059 for (; i > 0; i--, sent++)
2060 if (nvme_delete_queue(&dev->queues[i], opcode))
2064 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2070 opcode = nvme_admin_delete_cq;
2075 * return error value only when tagset allocation failed
2077 static int nvme_dev_add(struct nvme_dev *dev)
2081 if (!dev->ctrl.tagset) {
2082 dev->tagset.ops = &nvme_mq_ops;
2083 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2084 dev->tagset.timeout = NVME_IO_TIMEOUT;
2085 dev->tagset.numa_node = dev_to_node(dev->dev);
2086 dev->tagset.queue_depth =
2087 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2088 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2089 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2090 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2091 nvme_pci_cmd_size(dev, true));
2093 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2094 dev->tagset.driver_data = dev;
2096 ret = blk_mq_alloc_tag_set(&dev->tagset);
2098 dev_warn(dev->ctrl.device,
2099 "IO queues tagset allocation failed %d\n", ret);
2102 dev->ctrl.tagset = &dev->tagset;
2104 nvme_dbbuf_set(dev);
2106 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2108 /* Free previously allocated queues that are no longer usable */
2109 nvme_free_queues(dev, dev->online_queues);
2115 static int nvme_pci_enable(struct nvme_dev *dev)
2117 int result = -ENOMEM;
2118 struct pci_dev *pdev = to_pci_dev(dev->dev);
2120 if (pci_enable_device_mem(pdev))
2123 pci_set_master(pdev);
2125 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2126 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2129 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2135 * Some devices and/or platforms don't advertise or work with INTx
2136 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2137 * adjust this later.
2139 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2143 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2145 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2147 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2148 dev->dbs = dev->bar + 4096;
2151 * Temporary fix for the Apple controller found in the MacBook8,1 and
2152 * some MacBook7,1 to avoid controller resets and data loss.
2154 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2156 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2157 "set queue depth=%u to work around controller resets\n",
2159 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2160 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2161 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2163 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2164 "set queue depth=%u\n", dev->q_depth);
2169 pci_enable_pcie_error_reporting(pdev);
2170 pci_save_state(pdev);
2174 pci_disable_device(pdev);
2178 static void nvme_dev_unmap(struct nvme_dev *dev)
2182 pci_release_mem_regions(to_pci_dev(dev->dev));
2185 static void nvme_pci_disable(struct nvme_dev *dev)
2187 struct pci_dev *pdev = to_pci_dev(dev->dev);
2189 nvme_release_cmb(dev);
2190 pci_free_irq_vectors(pdev);
2192 if (pci_is_enabled(pdev)) {
2193 pci_disable_pcie_error_reporting(pdev);
2194 pci_disable_device(pdev);
2198 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2202 struct pci_dev *pdev = to_pci_dev(dev->dev);
2204 mutex_lock(&dev->shutdown_lock);
2205 if (pci_is_enabled(pdev)) {
2206 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2208 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2209 dev->ctrl.state == NVME_CTRL_RESETTING)
2210 nvme_start_freeze(&dev->ctrl);
2211 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2212 pdev->error_state != pci_channel_io_normal);
2216 * Give the controller a chance to complete all entered requests if
2217 * doing a safe shutdown.
2221 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2224 nvme_stop_queues(&dev->ctrl);
2226 if (!dead && dev->ctrl.queue_count > 0) {
2228 * If the controller is still alive tell it to stop using the
2229 * host memory buffer. In theory the shutdown / reset should
2230 * make sure that it doesn't access the host memoery anymore,
2231 * but I'd rather be safe than sorry..
2233 if (dev->host_mem_descs)
2234 nvme_set_host_mem(dev, 0);
2235 nvme_disable_io_queues(dev);
2236 nvme_disable_admin_queue(dev, shutdown);
2238 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2239 nvme_suspend_queue(&dev->queues[i]);
2241 nvme_pci_disable(dev);
2243 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2244 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2247 * The driver will not be starting up queues again if shutting down so
2248 * must flush all entered requests to their failed completion to avoid
2249 * deadlocking blk-mq hot-cpu notifier.
2252 nvme_start_queues(&dev->ctrl);
2253 mutex_unlock(&dev->shutdown_lock);
2256 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2258 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2259 PAGE_SIZE, PAGE_SIZE, 0);
2260 if (!dev->prp_page_pool)
2263 /* Optimisation for I/Os between 4k and 128k */
2264 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2266 if (!dev->prp_small_pool) {
2267 dma_pool_destroy(dev->prp_page_pool);
2273 static void nvme_release_prp_pools(struct nvme_dev *dev)
2275 dma_pool_destroy(dev->prp_page_pool);
2276 dma_pool_destroy(dev->prp_small_pool);
2279 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2281 struct nvme_dev *dev = to_nvme_dev(ctrl);
2283 nvme_dbbuf_dma_free(dev);
2284 put_device(dev->dev);
2285 if (dev->tagset.tags)
2286 blk_mq_free_tag_set(&dev->tagset);
2287 if (dev->ctrl.admin_q)
2288 blk_put_queue(dev->ctrl.admin_q);
2290 free_opal_dev(dev->ctrl.opal_dev);
2294 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2296 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2298 nvme_get_ctrl(&dev->ctrl);
2299 nvme_dev_disable(dev, false);
2300 if (!queue_work(nvme_wq, &dev->remove_work))
2301 nvme_put_ctrl(&dev->ctrl);
2304 static void nvme_reset_work(struct work_struct *work)
2306 struct nvme_dev *dev =
2307 container_of(work, struct nvme_dev, ctrl.reset_work);
2308 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2309 int result = -ENODEV;
2310 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2312 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2316 * If we're called to reset a live controller first shut it down before
2319 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2320 nvme_dev_disable(dev, false);
2323 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2324 * initializing procedure here.
2326 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2327 dev_warn(dev->ctrl.device,
2328 "failed to mark controller CONNECTING\n");
2332 result = nvme_pci_enable(dev);
2336 result = nvme_pci_configure_admin_queue(dev);
2340 result = nvme_alloc_admin_tags(dev);
2344 result = nvme_init_identify(&dev->ctrl);
2348 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2349 if (!dev->ctrl.opal_dev)
2350 dev->ctrl.opal_dev =
2351 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2352 else if (was_suspend)
2353 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2355 free_opal_dev(dev->ctrl.opal_dev);
2356 dev->ctrl.opal_dev = NULL;
2359 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2360 result = nvme_dbbuf_dma_alloc(dev);
2363 "unable to allocate dma for dbbuf\n");
2366 if (dev->ctrl.hmpre) {
2367 result = nvme_setup_host_mem(dev);
2372 result = nvme_setup_io_queues(dev);
2377 * Keep the controller around but remove all namespaces if we don't have
2378 * any working I/O queue.
2380 if (dev->online_queues < 2) {
2381 dev_warn(dev->ctrl.device, "IO queues not created\n");
2382 nvme_kill_queues(&dev->ctrl);
2383 nvme_remove_namespaces(&dev->ctrl);
2384 new_state = NVME_CTRL_ADMIN_ONLY;
2386 nvme_start_queues(&dev->ctrl);
2387 nvme_wait_freeze(&dev->ctrl);
2388 /* hit this only when allocate tagset fails */
2389 if (nvme_dev_add(dev))
2390 new_state = NVME_CTRL_ADMIN_ONLY;
2391 nvme_unfreeze(&dev->ctrl);
2395 * If only admin queue live, keep it to do further investigation or
2398 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2399 dev_warn(dev->ctrl.device,
2400 "failed to mark controller state %d\n", new_state);
2404 nvme_start_ctrl(&dev->ctrl);
2408 nvme_remove_dead_ctrl(dev, result);
2411 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2413 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2414 struct pci_dev *pdev = to_pci_dev(dev->dev);
2416 nvme_kill_queues(&dev->ctrl);
2417 if (pci_get_drvdata(pdev))
2418 device_release_driver(&pdev->dev);
2419 nvme_put_ctrl(&dev->ctrl);
2422 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2424 *val = readl(to_nvme_dev(ctrl)->bar + off);
2428 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2430 writel(val, to_nvme_dev(ctrl)->bar + off);
2434 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2436 *val = readq(to_nvme_dev(ctrl)->bar + off);
2440 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2442 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2444 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2447 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2449 .module = THIS_MODULE,
2450 .flags = NVME_F_METADATA_SUPPORTED,
2451 .reg_read32 = nvme_pci_reg_read32,
2452 .reg_write32 = nvme_pci_reg_write32,
2453 .reg_read64 = nvme_pci_reg_read64,
2454 .free_ctrl = nvme_pci_free_ctrl,
2455 .submit_async_event = nvme_pci_submit_async_event,
2456 .get_address = nvme_pci_get_address,
2459 static int nvme_dev_map(struct nvme_dev *dev)
2461 struct pci_dev *pdev = to_pci_dev(dev->dev);
2463 if (pci_request_mem_regions(pdev, "nvme"))
2466 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2471 pci_release_mem_regions(pdev);
2475 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2477 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2479 * Several Samsung devices seem to drop off the PCIe bus
2480 * randomly when APST is on and uses the deepest sleep state.
2481 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2482 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2483 * 950 PRO 256GB", but it seems to be restricted to two Dell
2486 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2487 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2488 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2489 return NVME_QUIRK_NO_DEEPEST_PS;
2490 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2492 * Samsung SSD 960 EVO drops off the PCIe bus after system
2493 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2494 * within few minutes after bootup on a Coffee Lake board -
2497 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2498 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2499 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2500 return NVME_QUIRK_NO_APST;
2506 static void nvme_async_probe(void *data, async_cookie_t cookie)
2508 struct nvme_dev *dev = data;
2510 nvme_reset_ctrl_sync(&dev->ctrl);
2511 flush_work(&dev->ctrl.scan_work);
2512 nvme_put_ctrl(&dev->ctrl);
2515 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2517 int node, result = -ENOMEM;
2518 struct nvme_dev *dev;
2519 unsigned long quirks = id->driver_data;
2521 node = dev_to_node(&pdev->dev);
2522 if (node == NUMA_NO_NODE)
2523 set_dev_node(&pdev->dev, first_memory_node);
2525 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2529 dev->queues = kcalloc_node(num_possible_cpus() + 1,
2530 sizeof(struct nvme_queue), GFP_KERNEL, node);
2534 dev->dev = get_device(&pdev->dev);
2535 pci_set_drvdata(pdev, dev);
2537 result = nvme_dev_map(dev);
2541 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2542 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2543 mutex_init(&dev->shutdown_lock);
2544 init_completion(&dev->ioq_wait);
2546 result = nvme_setup_prp_pools(dev);
2550 quirks |= check_vendor_combination_bug(pdev);
2552 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2557 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2559 nvme_get_ctrl(&dev->ctrl);
2560 async_schedule(nvme_async_probe, dev);
2565 nvme_release_prp_pools(dev);
2567 nvme_dev_unmap(dev);
2569 put_device(dev->dev);
2576 static void nvme_reset_prepare(struct pci_dev *pdev)
2578 struct nvme_dev *dev = pci_get_drvdata(pdev);
2579 nvme_dev_disable(dev, false);
2582 static void nvme_reset_done(struct pci_dev *pdev)
2584 struct nvme_dev *dev = pci_get_drvdata(pdev);
2585 nvme_reset_ctrl_sync(&dev->ctrl);
2588 static void nvme_shutdown(struct pci_dev *pdev)
2590 struct nvme_dev *dev = pci_get_drvdata(pdev);
2591 nvme_dev_disable(dev, true);
2595 * The driver's remove may be called on a device in a partially initialized
2596 * state. This function must not have any dependencies on the device state in
2599 static void nvme_remove(struct pci_dev *pdev)
2601 struct nvme_dev *dev = pci_get_drvdata(pdev);
2603 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2605 cancel_work_sync(&dev->ctrl.reset_work);
2606 pci_set_drvdata(pdev, NULL);
2608 if (!pci_device_is_present(pdev)) {
2609 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2610 nvme_dev_disable(dev, false);
2613 flush_work(&dev->ctrl.reset_work);
2614 nvme_stop_ctrl(&dev->ctrl);
2615 nvme_remove_namespaces(&dev->ctrl);
2616 nvme_dev_disable(dev, true);
2617 nvme_free_host_mem(dev);
2618 nvme_dev_remove_admin(dev);
2619 nvme_free_queues(dev, 0);
2620 nvme_uninit_ctrl(&dev->ctrl);
2621 nvme_release_prp_pools(dev);
2622 nvme_dev_unmap(dev);
2623 nvme_put_ctrl(&dev->ctrl);
2626 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2631 if (pci_vfs_assigned(pdev)) {
2632 dev_warn(&pdev->dev,
2633 "Cannot disable SR-IOV VFs while assigned\n");
2636 pci_disable_sriov(pdev);
2640 ret = pci_enable_sriov(pdev, numvfs);
2641 return ret ? ret : numvfs;
2644 #ifdef CONFIG_PM_SLEEP
2645 static int nvme_suspend(struct device *dev)
2647 struct pci_dev *pdev = to_pci_dev(dev);
2648 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2650 nvme_dev_disable(ndev, true);
2654 static int nvme_resume(struct device *dev)
2656 struct pci_dev *pdev = to_pci_dev(dev);
2657 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2659 nvme_reset_ctrl(&ndev->ctrl);
2664 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2666 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2667 pci_channel_state_t state)
2669 struct nvme_dev *dev = pci_get_drvdata(pdev);
2672 * A frozen channel requires a reset. When detected, this method will
2673 * shutdown the controller to quiesce. The controller will be restarted
2674 * after the slot reset through driver's slot_reset callback.
2677 case pci_channel_io_normal:
2678 return PCI_ERS_RESULT_CAN_RECOVER;
2679 case pci_channel_io_frozen:
2680 dev_warn(dev->ctrl.device,
2681 "frozen state error detected, reset controller\n");
2682 nvme_dev_disable(dev, false);
2683 return PCI_ERS_RESULT_NEED_RESET;
2684 case pci_channel_io_perm_failure:
2685 dev_warn(dev->ctrl.device,
2686 "failure state error detected, request disconnect\n");
2687 return PCI_ERS_RESULT_DISCONNECT;
2689 return PCI_ERS_RESULT_NEED_RESET;
2692 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2694 struct nvme_dev *dev = pci_get_drvdata(pdev);
2696 dev_info(dev->ctrl.device, "restart after slot reset\n");
2697 pci_restore_state(pdev);
2698 nvme_reset_ctrl(&dev->ctrl);
2699 return PCI_ERS_RESULT_RECOVERED;
2702 static void nvme_error_resume(struct pci_dev *pdev)
2704 struct nvme_dev *dev = pci_get_drvdata(pdev);
2706 flush_work(&dev->ctrl.reset_work);
2707 pci_cleanup_aer_uncorrect_error_status(pdev);
2710 static const struct pci_error_handlers nvme_err_handler = {
2711 .error_detected = nvme_error_detected,
2712 .slot_reset = nvme_slot_reset,
2713 .resume = nvme_error_resume,
2714 .reset_prepare = nvme_reset_prepare,
2715 .reset_done = nvme_reset_done,
2718 static const struct pci_device_id nvme_id_table[] = {
2719 { PCI_VDEVICE(INTEL, 0x0953),
2720 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2721 NVME_QUIRK_DEALLOCATE_ZEROES, },
2722 { PCI_VDEVICE(INTEL, 0x0a53),
2723 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2724 NVME_QUIRK_DEALLOCATE_ZEROES, },
2725 { PCI_VDEVICE(INTEL, 0x0a54),
2726 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2727 NVME_QUIRK_DEALLOCATE_ZEROES, },
2728 { PCI_VDEVICE(INTEL, 0x0a55),
2729 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2730 NVME_QUIRK_DEALLOCATE_ZEROES, },
2731 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2732 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2733 NVME_QUIRK_MEDIUM_PRIO_SQ },
2734 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2735 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2736 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2737 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2738 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2739 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2740 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2741 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2742 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2743 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2744 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2745 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2746 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2747 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2748 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2749 .driver_data = NVME_QUIRK_LIGHTNVM, },
2750 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2751 .driver_data = NVME_QUIRK_LIGHTNVM, },
2752 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2753 .driver_data = NVME_QUIRK_LIGHTNVM, },
2754 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2755 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2756 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2759 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2761 static struct pci_driver nvme_driver = {
2763 .id_table = nvme_id_table,
2764 .probe = nvme_probe,
2765 .remove = nvme_remove,
2766 .shutdown = nvme_shutdown,
2768 .pm = &nvme_dev_pm_ops,
2770 .sriov_configure = nvme_pci_sriov_configure,
2771 .err_handler = &nvme_err_handler,
2774 static int __init nvme_init(void)
2776 return pci_register_driver(&nvme_driver);
2779 static void __exit nvme_exit(void)
2781 pci_unregister_driver(&nvme_driver);
2782 flush_workqueue(nvme_wq);
2786 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2787 MODULE_LICENSE("GPL");
2788 MODULE_VERSION("1.0");
2789 module_init(nvme_init);
2790 module_exit(nvme_exit);