drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/bitops.h>
  16 #include <linux/blkdev.h>
  17 #include <linux/blk-mq.h>
  18 #include <linux/cpu.h>
  19 #include <linux/delay.h>
  20 #include <linux/errno.h>
  21 #include <linux/fs.h>
  22 #include <linux/genhd.h>
  23 #include <linux/hdreg.h>
  24 #include <linux/idr.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kthread.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/types.h>
  42 #include <linux/io-64-nonatomic-lo-hi.h>
  43 #include <asm/unaligned.h>
  44
  45 #include "nvme.h"
  46
  47 #define NVME_Q_DEPTH            1024
  48 #define NVME_AQ_DEPTH           256
  49 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  50 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  51
  52 unsigned char admin_timeout = 60;
  53 module_param(admin_timeout, byte, 0644);
  54 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  55
  56 unsigned char nvme_io_timeout = 30;
  57 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  58 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  59
  60 unsigned char shutdown_timeout = 5;
  61 module_param(shutdown_timeout, byte, 0644);
  62 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  63
  64 static int use_threaded_interrupts;
  65 module_param(use_threaded_interrupts, int, 0);
  66
  67 static bool use_cmb_sqes = true;
  68 module_param(use_cmb_sqes, bool, 0644);
  69 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  70
  71 static LIST_HEAD(dev_list);
  72 static struct task_struct *nvme_thread;
  73 static struct workqueue_struct *nvme_workq;
  74 static wait_queue_head_t nvme_kthread_wait;
  75
  76 struct nvme_dev;
  77 struct nvme_queue;
  78 struct nvme_iod;
  79
  80 static int nvme_reset(struct nvme_dev *dev);
  81 static void nvme_process_cq(struct nvme_queue *nvmeq);
  82 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod);
  83 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
  84 static void nvme_dev_shutdown(struct nvme_dev *dev);
  85
  86 struct async_cmd_info {
  87         struct kthread_work work;
  88         struct kthread_worker *worker;
  89         int status;
  90         void *ctx;
  91 };
  92
  93 /*
  94  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  95  */
  96 struct nvme_dev {
  97         struct list_head node;
  98         struct nvme_queue **queues;
  99         struct blk_mq_tag_set tagset;
 100         struct blk_mq_tag_set admin_tagset;
 101         u32 __iomem *dbs;
 102         struct device *dev;
 103         struct dma_pool *prp_page_pool;
 104         struct dma_pool *prp_small_pool;
 105         unsigned queue_count;
 106         unsigned online_queues;
 107         unsigned max_qid;
 108         int q_depth;
 109         u32 db_stride;
 110         struct msix_entry *entry;
 111         void __iomem *bar;
 112         struct work_struct reset_work;
 113         struct work_struct scan_work;
 114         struct work_struct remove_work;
 115         struct mutex shutdown_lock;
 116         bool subsystem;
 117         void __iomem *cmb;
 118         dma_addr_t cmb_dma_addr;
 119         u64 cmb_size;
 120         u32 cmbsz;
 121         unsigned long flags;
 122 #define NVME_CTRL_RESETTING    0
 123
 124         struct nvme_ctrl ctrl;
 125 };
 126
 127 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 128 {
 129         return container_of(ctrl, struct nvme_dev, ctrl);
 130 }
 131
 132 /*
 133  * An NVM Express queue.  Each device has at least two (one for admin
 134  * commands and one for I/O commands).
 135  */
 136 struct nvme_queue {
 137         struct device *q_dmadev;
 138         struct nvme_dev *dev;
 139         char irqname[24];       /* nvme4294967295-65535\0 */
 140         spinlock_t q_lock;
 141         struct nvme_command *sq_cmds;
 142         struct nvme_command __iomem *sq_cmds_io;
 143         volatile struct nvme_completion *cqes;
 144         struct blk_mq_tags **tags;
 145         dma_addr_t sq_dma_addr;
 146         dma_addr_t cq_dma_addr;
 147         u32 __iomem *q_db;
 148         u16 q_depth;
 149         s16 cq_vector;
 150         u16 sq_head;
 151         u16 sq_tail;
 152         u16 cq_head;
 153         u16 qid;
 154         u8 cq_phase;
 155         u8 cqe_seen;
 156         struct async_cmd_info cmdinfo;
 157 };
 158
 159 /*
 160  * The nvme_iod describes the data in an I/O, including the list of PRP
 161  * entries.  You can't see it in this data structure because C doesn't let
 162  * me express that.  Use nvme_alloc_iod to ensure there's enough space
 163  * allocated to store the PRP list.
 164  */
 165 struct nvme_iod {
 166         unsigned long private;  /* For the use of the submitter of the I/O */
 167         int npages;             /* In the PRP list. 0 means small pool in use */
 168         int offset;             /* Of PRP list */
 169         int nents;              /* Used in scatterlist */
 170         int length;             /* Of data, in bytes */
 171         dma_addr_t first_dma;
 172         struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
 173         struct scatterlist sg[0];
 174 };
 175
 176 /*
 177  * Check we didin't inadvertently grow the command struct
 178  */
 179 static inline void _nvme_check_size(void)
 180 {
 181         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 182         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 183         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 184         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 185         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 186         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 187         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 188         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 189         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 190         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 191         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 192         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 193 }
 194
 195 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
 196                                                 struct nvme_completion *);
 197
 198 struct nvme_cmd_info {
 199         nvme_completion_fn fn;
 200         void *ctx;
 201         int aborted;
 202         struct nvme_queue *nvmeq;
 203         struct nvme_iod iod[0];
 204 };
 205
 206 /*
 207  * Max size of iod being embedded in the request payload
 208  */
 209 #define NVME_INT_PAGES          2
 210 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 211 #define NVME_INT_MASK           0x01
 212
 213 /*
 214  * Will slightly overestimate the number of pages needed.  This is OK
 215  * as it only leads to a small amount of wasted memory for the lifetime of
 216  * the I/O.
 217  */
 218 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 219 {
 220         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 221                                       dev->ctrl.page_size);
 222         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 223 }
 224
 225 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 226 {
 227         unsigned int ret = sizeof(struct nvme_cmd_info);
 228
 229         ret += sizeof(struct nvme_iod);
 230         ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
 231         ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
 232
 233         return ret;
 234 }
 235
 236 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 237                                 unsigned int hctx_idx)
 238 {
 239         struct nvme_dev *dev = data;
 240         struct nvme_queue *nvmeq = dev->queues[0];
 241
 242         WARN_ON(hctx_idx != 0);
 243         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 244         WARN_ON(nvmeq->tags);
 245
 246         hctx->driver_data = nvmeq;
 247         nvmeq->tags = &dev->admin_tagset.tags[0];
 248         return 0;
 249 }
 250
 251 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 252 {
 253         struct nvme_queue *nvmeq = hctx->driver_data;
 254
 255         nvmeq->tags = NULL;
 256 }
 257
 258 static int nvme_admin_init_request(void *data, struct request *req,
 259                                 unsigned int hctx_idx, unsigned int rq_idx,
 260                                 unsigned int numa_node)
 261 {
 262         struct nvme_dev *dev = data;
 263         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 264         struct nvme_queue *nvmeq = dev->queues[0];
 265
 266         BUG_ON(!nvmeq);
 267         cmd->nvmeq = nvmeq;
 268         return 0;
 269 }
 270
 271 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 272                           unsigned int hctx_idx)
 273 {
 274         struct nvme_dev *dev = data;
 275         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 276
 277         if (!nvmeq->tags)
 278                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 279
 280         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 281         hctx->driver_data = nvmeq;
 282         return 0;
 283 }
 284
 285 static int nvme_init_request(void *data, struct request *req,
 286                                 unsigned int hctx_idx, unsigned int rq_idx,
 287                                 unsigned int numa_node)
 288 {
 289         struct nvme_dev *dev = data;
 290         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 291         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 292
 293         BUG_ON(!nvmeq);
 294         cmd->nvmeq = nvmeq;
 295         return 0;
 296 }
 297
 298 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
 299                                 nvme_completion_fn handler)
 300 {
 301         cmd->fn = handler;
 302         cmd->ctx = ctx;
 303         cmd->aborted = 0;
 304         blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
 305 }
 306
 307 static void *iod_get_private(struct nvme_iod *iod)
 308 {
 309         return (void *) (iod->private & ~0x1UL);
 310 }
 311
 312 /*
 313  * If bit 0 is set, the iod is embedded in the request payload.
 314  */
 315 static bool iod_should_kfree(struct nvme_iod *iod)
 316 {
 317         return (iod->private & NVME_INT_MASK) == 0;
 318 }
 319
 320 /* Special values must be less than 0x1000 */
 321 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
 322 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 323 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 324 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 325
 326 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
 327                                                 struct nvme_completion *cqe)
 328 {
 329         if (ctx == CMD_CTX_CANCELLED)
 330                 return;
 331         if (ctx == CMD_CTX_COMPLETED) {
 332                 dev_warn(nvmeq->q_dmadev,
 333                                 "completed id %d twice on queue %d\n",
 334                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 335                 return;
 336         }
 337         if (ctx == CMD_CTX_INVALID) {
 338                 dev_warn(nvmeq->q_dmadev,
 339                                 "invalid id %d completed on queue %d\n",
 340                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 341                 return;
 342         }
 343         dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
 344 }
 345
 346 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
 347 {
 348         void *ctx;
 349
 350         if (fn)
 351                 *fn = cmd->fn;
 352         ctx = cmd->ctx;
 353         cmd->fn = special_completion;
 354         cmd->ctx = CMD_CTX_CANCELLED;
 355         return ctx;
 356 }
 357
 358 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
 359                                                 struct nvme_completion *cqe)
 360 {
 361         u32 result = le32_to_cpup(&cqe->result);
 362         u16 status = le16_to_cpup(&cqe->status) >> 1;
 363
 364         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 365                 ++nvmeq->dev->ctrl.event_limit;
 366         if (status != NVME_SC_SUCCESS)
 367                 return;
 368
 369         switch (result & 0xff07) {
 370         case NVME_AER_NOTICE_NS_CHANGED:
 371                 dev_info(nvmeq->q_dmadev, "rescanning\n");
 372                 queue_work(nvme_workq, &nvmeq->dev->scan_work);
 373         default:
 374                 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
 375         }
 376 }
 377
 378 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
 379                                   unsigned int tag)
 380 {
 381         struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
 382
 383         return blk_mq_rq_to_pdu(req);
 384 }
 385
 386 /*
 387  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 388  */
 389 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
 390                                                 nvme_completion_fn *fn)
 391 {
 392         struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
 393         void *ctx;
 394         if (tag >= nvmeq->q_depth) {
 395                 *fn = special_completion;
 396                 return CMD_CTX_INVALID;
 397         }
 398         if (fn)
 399                 *fn = cmd->fn;
 400         ctx = cmd->ctx;
 401         cmd->fn = special_completion;
 402         cmd->ctx = CMD_CTX_COMPLETED;
 403         return ctx;
 404 }
 405
 406 /**
 407  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 408  * @nvmeq: The queue to use
 409  * @cmd: The command to send
 410  *
 411  * Safe to use from interrupt context
 412  */
 413 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 414                                                 struct nvme_command *cmd)
 415 {
 416         u16 tail = nvmeq->sq_tail;
 417
 418         if (nvmeq->sq_cmds_io)
 419                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 420         else
 421                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 422
 423         if (++tail == nvmeq->q_depth)
 424                 tail = 0;
 425         writel(tail, nvmeq->q_db);
 426         nvmeq->sq_tail = tail;
 427 }
 428
 429 static __le64 **iod_list(struct nvme_iod *iod)
 430 {
 431         return ((void *)iod) + iod->offset;
 432 }
 433
 434 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
 435                             unsigned nseg, unsigned long private)
 436 {
 437         iod->private = private;
 438         iod->offset = offsetof(struct nvme_iod, sg[nseg]);
 439         iod->npages = -1;
 440         iod->length = nbytes;
 441         iod->nents = 0;
 442 }
 443
 444 static struct nvme_iod *
 445 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
 446                  unsigned long priv, gfp_t gfp)
 447 {
 448         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
 449                                 sizeof(__le64 *) * nvme_npages(bytes, dev) +
 450                                 sizeof(struct scatterlist) * nseg, gfp);
 451
 452         if (iod)
 453                 iod_init(iod, bytes, nseg, priv);
 454
 455         return iod;
 456 }
 457
 458 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
 459                                        gfp_t gfp)
 460 {
 461         unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
 462                                                 sizeof(struct nvme_dsm_range);
 463         struct nvme_iod *iod;
 464
 465         if (rq->nr_phys_segments <= NVME_INT_PAGES &&
 466             size <= NVME_INT_BYTES(dev)) {
 467                 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
 468
 469                 iod = cmd->iod;
 470                 iod_init(iod, size, rq->nr_phys_segments,
 471                                 (unsigned long) rq | NVME_INT_MASK);
 472                 return iod;
 473         }
 474
 475         return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
 476                                 (unsigned long) rq, gfp);
 477 }
 478
 479 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
 480 {
 481         const int last_prp = dev->ctrl.page_size / 8 - 1;
 482         int i;
 483         __le64 **list = iod_list(iod);
 484         dma_addr_t prp_dma = iod->first_dma;
 485
 486         if (iod->npages == 0)
 487                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 488         for (i = 0; i < iod->npages; i++) {
 489                 __le64 *prp_list = list[i];
 490                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 491                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 492                 prp_dma = next_prp_dma;
 493         }
 494
 495         if (iod_should_kfree(iod))
 496                 kfree(iod);
 497 }
 498
 499 #ifdef CONFIG_BLK_DEV_INTEGRITY
 500 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 501 {
 502         if (be32_to_cpu(pi->ref_tag) == v)
 503                 pi->ref_tag = cpu_to_be32(p);
 504 }
 505
 506 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 507 {
 508         if (be32_to_cpu(pi->ref_tag) == p)
 509                 pi->ref_tag = cpu_to_be32(v);
 510 }
 511
 512 /**
 513  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 514  *
 515  * The virtual start sector is the one that was originally submitted by the
 516  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 517  * start sector may be different. Remap protection information to match the
 518  * physical LBA on writes, and back to the original seed on reads.
 519  *
 520  * Type 0 and 3 do not have a ref tag, so no remapping required.
 521  */
 522 static void nvme_dif_remap(struct request *req,
 523                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 524 {
 525         struct nvme_ns *ns = req->rq_disk->private_data;
 526         struct bio_integrity_payload *bip;
 527         struct t10_pi_tuple *pi;
 528         void *p, *pmap;
 529         u32 i, nlb, ts, phys, virt;
 530
 531         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 532                 return;
 533
 534         bip = bio_integrity(req->bio);
 535         if (!bip)
 536                 return;
 537
 538         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 539
 540         p = pmap;
 541         virt = bip_get_seed(bip);
 542         phys = nvme_block_nr(ns, blk_rq_pos(req));
 543         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 544         ts = ns->disk->queue->integrity.tuple_size;
 545
 546         for (i = 0; i < nlb; i++, virt++, phys++) {
 547                 pi = (struct t10_pi_tuple *)p;
 548                 dif_swap(phys, virt, pi);
 549                 p += ts;
 550         }
 551         kunmap_atomic(pmap);
 552 }
 553 #else /* CONFIG_BLK_DEV_INTEGRITY */
 554 static void nvme_dif_remap(struct request *req,
 555                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 556 {
 557 }
 558 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 559 {
 560 }
 561 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 562 {
 563 }
 564 #endif
 565
 566 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
 567                                                 struct nvme_completion *cqe)
 568 {
 569         struct nvme_iod *iod = ctx;
 570         struct request *req = iod_get_private(iod);
 571         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
 572         u16 status = le16_to_cpup(&cqe->status) >> 1;
 573         int error = 0;
 574
 575         if (unlikely(status)) {
 576                 if (nvme_req_needs_retry(req, status)) {
 577                         nvme_unmap_data(nvmeq->dev, iod);
 578                         nvme_requeue_req(req);
 579                         return;
 580                 }
 581
 582                 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 583                         if (cmd_rq->ctx == CMD_CTX_CANCELLED)
 584                                 error = NVME_SC_CANCELLED;
 585                         else
 586                                 error = status;
 587                 } else {
 588                         error = nvme_error_status(status);
 589                 }
 590         }
 591
 592         if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 593                 u32 result = le32_to_cpup(&cqe->result);
 594                 req->special = (void *)(uintptr_t)result;
 595         }
 596
 597         if (cmd_rq->aborted)
 598                 dev_warn(nvmeq->dev->dev,
 599                         "completing aborted command with status:%04x\n",
 600                         error);
 601
 602         nvme_unmap_data(nvmeq->dev, iod);
 603         blk_mq_complete_request(req, error);
 604 }
 605
 606 static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
 607                 int total_len)
 608 {
 609         struct dma_pool *pool;
 610         int length = total_len;
 611         struct scatterlist *sg = iod->sg;
 612         int dma_len = sg_dma_len(sg);
 613         u64 dma_addr = sg_dma_address(sg);
 614         u32 page_size = dev->ctrl.page_size;
 615         int offset = dma_addr & (page_size - 1);
 616         __le64 *prp_list;
 617         __le64 **list = iod_list(iod);
 618         dma_addr_t prp_dma;
 619         int nprps, i;
 620
 621         length -= (page_size - offset);
 622         if (length <= 0)
 623                 return true;
 624
 625         dma_len -= (page_size - offset);
 626         if (dma_len) {
 627                 dma_addr += (page_size - offset);
 628         } else {
 629                 sg = sg_next(sg);
 630                 dma_addr = sg_dma_address(sg);
 631                 dma_len = sg_dma_len(sg);
 632         }
 633
 634         if (length <= page_size) {
 635                 iod->first_dma = dma_addr;
 636                 return true;
 637         }
 638
 639         nprps = DIV_ROUND_UP(length, page_size);
 640         if (nprps <= (256 / 8)) {
 641                 pool = dev->prp_small_pool;
 642                 iod->npages = 0;
 643         } else {
 644                 pool = dev->prp_page_pool;
 645                 iod->npages = 1;
 646         }
 647
 648         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 649         if (!prp_list) {
 650                 iod->first_dma = dma_addr;
 651                 iod->npages = -1;
 652                 return false;
 653         }
 654         list[0] = prp_list;
 655         iod->first_dma = prp_dma;
 656         i = 0;
 657         for (;;) {
 658                 if (i == page_size >> 3) {
 659                         __le64 *old_prp_list = prp_list;
 660                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 661                         if (!prp_list)
 662                                 return false;
 663                         list[iod->npages++] = prp_list;
 664                         prp_list[0] = old_prp_list[i - 1];
 665                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 666                         i = 1;
 667                 }
 668                 prp_list[i++] = cpu_to_le64(dma_addr);
 669                 dma_len -= page_size;
 670                 dma_addr += page_size;
 671                 length -= page_size;
 672                 if (length <= 0)
 673                         break;
 674                 if (dma_len > 0)
 675                         continue;
 676                 BUG_ON(dma_len < 0);
 677                 sg = sg_next(sg);
 678                 dma_addr = sg_dma_address(sg);
 679                 dma_len = sg_dma_len(sg);
 680         }
 681
 682         return true;
 683 }
 684
 685 static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod,
 686                 struct nvme_command *cmnd)
 687 {
 688         struct request *req = iod_get_private(iod);
 689         struct request_queue *q = req->q;
 690         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 691                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 692         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 693
 694         sg_init_table(iod->sg, req->nr_phys_segments);
 695         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 696         if (!iod->nents)
 697                 goto out;
 698
 699         ret = BLK_MQ_RQ_QUEUE_BUSY;
 700         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 701                 goto out;
 702
 703         if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req)))
 704                 goto out_unmap;
 705
 706         ret = BLK_MQ_RQ_QUEUE_ERROR;
 707         if (blk_integrity_rq(req)) {
 708                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 709                         goto out_unmap;
 710
 711                 sg_init_table(iod->meta_sg, 1);
 712                 if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1)
 713                         goto out_unmap;
 714
 715                 if (rq_data_dir(req))
 716                         nvme_dif_remap(req, nvme_dif_prep);
 717
 718                 if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir))
 719                         goto out_unmap;
 720         }
 721
 722         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 723         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 724         if (blk_integrity_rq(req))
 725                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
 726         return BLK_MQ_RQ_QUEUE_OK;
 727
 728 out_unmap:
 729         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 730 out:
 731         return ret;
 732 }
 733
 734 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod)
 735 {
 736         struct request *req = iod_get_private(iod);
 737         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 738                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 739
 740         if (iod->nents) {
 741                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 742                 if (blk_integrity_rq(req)) {
 743                         if (!rq_data_dir(req))
 744                                 nvme_dif_remap(req, nvme_dif_complete);
 745                         dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir);
 746                 }
 747         }
 748
 749         nvme_free_iod(dev, iod);
 750 }
 751
 752 /*
 753  * We reuse the small pool to allocate the 16-byte range here as it is not
 754  * worth having a special pool for these or additional cases to handle freeing
 755  * the iod.
 756  */
 757 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 758                 struct nvme_iod *iod, struct nvme_command *cmnd)
 759 {
 760         struct request *req = iod_get_private(iod);
 761         struct nvme_dsm_range *range;
 762
 763         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 764                                                 &iod->first_dma);
 765         if (!range)
 766                 return BLK_MQ_RQ_QUEUE_BUSY;
 767         iod_list(iod)[0] = (__le64 *)range;
 768         iod->npages = 0;
 769
 770         range->cattr = cpu_to_le32(0);
 771         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 772         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 773
 774         memset(cmnd, 0, sizeof(*cmnd));
 775         cmnd->dsm.opcode = nvme_cmd_dsm;
 776         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 777         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 778         cmnd->dsm.nr = 0;
 779         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 780         return BLK_MQ_RQ_QUEUE_OK;
 781 }
 782
 783 /*
 784  * NOTE: ns is NULL when called on the admin queue.
 785  */
 786 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 787                          const struct blk_mq_queue_data *bd)
 788 {
 789         struct nvme_ns *ns = hctx->queue->queuedata;
 790         struct nvme_queue *nvmeq = hctx->driver_data;
 791         struct nvme_dev *dev = nvmeq->dev;
 792         struct request *req = bd->rq;
 793         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
 794         struct nvme_iod *iod;
 795         struct nvme_command cmnd;
 796         int ret = BLK_MQ_RQ_QUEUE_OK;
 797
 798         /*
 799          * If formated with metadata, require the block layer provide a buffer
 800          * unless this namespace is formated such that the metadata can be
 801          * stripped/generated by the controller with PRACT=1.
 802          */
 803         if (ns && ns->ms && !blk_integrity_rq(req)) {
 804                 if (!(ns->pi_type && ns->ms == 8) &&
 805                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 806                         blk_mq_complete_request(req, -EFAULT);
 807                         return BLK_MQ_RQ_QUEUE_OK;
 808                 }
 809         }
 810
 811         iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
 812         if (!iod)
 813                 return BLK_MQ_RQ_QUEUE_BUSY;
 814
 815         if (req->cmd_flags & REQ_DISCARD) {
 816                 ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd);
 817         } else {
 818                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 819                         memcpy(&cmnd, req->cmd, sizeof(cmnd));
 820                 else if (req->cmd_flags & REQ_FLUSH)
 821                         nvme_setup_flush(ns, &cmnd);
 822                 else
 823                         nvme_setup_rw(ns, req, &cmnd);
 824
 825                 if (req->nr_phys_segments)
 826                         ret = nvme_map_data(dev, iod, &cmnd);
 827         }
 828
 829         if (ret)
 830                 goto out;
 831
 832         cmnd.common.command_id = req->tag;
 833         nvme_set_info(cmd, iod, req_completion);
 834
 835         spin_lock_irq(&nvmeq->q_lock);
 836         __nvme_submit_cmd(nvmeq, &cmnd);
 837         nvme_process_cq(nvmeq);
 838         spin_unlock_irq(&nvmeq->q_lock);
 839         return BLK_MQ_RQ_QUEUE_OK;
 840 out:
 841         nvme_free_iod(dev, iod);
 842         return ret;
 843 }
 844
 845 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 846 {
 847         u16 head, phase;
 848
 849         head = nvmeq->cq_head;
 850         phase = nvmeq->cq_phase;
 851
 852         for (;;) {
 853                 void *ctx;
 854                 nvme_completion_fn fn;
 855                 struct nvme_completion cqe = nvmeq->cqes[head];
 856                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 857                         break;
 858                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 859                 if (++head == nvmeq->q_depth) {
 860                         head = 0;
 861                         phase = !phase;
 862                 }
 863                 if (tag && *tag == cqe.command_id)
 864                         *tag = -1;
 865                 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
 866                 fn(nvmeq, ctx, &cqe);
 867         }
 868
 869         /* If the controller ignores the cq head doorbell and continuously
 870          * writes to the queue, it is theoretically possible to wrap around
 871          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 872          * requires that 0.1% of your interrupts are handled, so this isn't
 873          * a big problem.
 874          */
 875         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 876                 return;
 877
 878         if (likely(nvmeq->cq_vector >= 0))
 879                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 880         nvmeq->cq_head = head;
 881         nvmeq->cq_phase = phase;
 882
 883         nvmeq->cqe_seen = 1;
 884 }
 885
 886 static void nvme_process_cq(struct nvme_queue *nvmeq)
 887 {
 888         __nvme_process_cq(nvmeq, NULL);
 889 }
 890
 891 static irqreturn_t nvme_irq(int irq, void *data)
 892 {
 893         irqreturn_t result;
 894         struct nvme_queue *nvmeq = data;
 895         spin_lock(&nvmeq->q_lock);
 896         nvme_process_cq(nvmeq);
 897         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 898         nvmeq->cqe_seen = 0;
 899         spin_unlock(&nvmeq->q_lock);
 900         return result;
 901 }
 902
 903 static irqreturn_t nvme_irq_check(int irq, void *data)
 904 {
 905         struct nvme_queue *nvmeq = data;
 906         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 907         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 908                 return IRQ_NONE;
 909         return IRQ_WAKE_THREAD;
 910 }
 911
 912 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 913 {
 914         struct nvme_queue *nvmeq = hctx->driver_data;
 915
 916         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 917             nvmeq->cq_phase) {
 918                 spin_lock_irq(&nvmeq->q_lock);
 919                 __nvme_process_cq(nvmeq, &tag);
 920                 spin_unlock_irq(&nvmeq->q_lock);
 921
 922                 if (tag == -1)
 923                         return 1;
 924         }
 925
 926         return 0;
 927 }
 928
 929 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
 930 {
 931         struct nvme_queue *nvmeq = dev->queues[0];
 932         struct nvme_command c;
 933         struct nvme_cmd_info *cmd_info;
 934         struct request *req;
 935
 936         req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE,
 937                         BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED);
 938         if (IS_ERR(req))
 939                 return PTR_ERR(req);
 940
 941         req->cmd_flags |= REQ_NO_TIMEOUT;
 942         cmd_info = blk_mq_rq_to_pdu(req);
 943         nvme_set_info(cmd_info, NULL, async_req_completion);
 944
 945         memset(&c, 0, sizeof(c));
 946         c.common.opcode = nvme_admin_async_event;
 947         c.common.command_id = req->tag;
 948
 949         blk_mq_free_request(req);
 950         __nvme_submit_cmd(nvmeq, &c);
 951         return 0;
 952 }
 953
 954 static void async_cmd_info_endio(struct request *req, int error)
 955 {
 956         struct async_cmd_info *cmdinfo = req->end_io_data;
 957
 958         cmdinfo->status = req->errors;
 959         queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
 960         blk_mq_free_request(req);
 961 }
 962
 963 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 964 {
 965         struct nvme_command c;
 966
 967         memset(&c, 0, sizeof(c));
 968         c.delete_queue.opcode = opcode;
 969         c.delete_queue.qid = cpu_to_le16(id);
 970
 971         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 972 }
 973
 974 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 975                                                 struct nvme_queue *nvmeq)
 976 {
 977         struct nvme_command c;
 978         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 979
 980         /*
 981          * Note: we (ab)use the fact the the prp fields survive if no data
 982          * is attached to the request.
 983          */
 984         memset(&c, 0, sizeof(c));
 985         c.create_cq.opcode = nvme_admin_create_cq;
 986         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 987         c.create_cq.cqid = cpu_to_le16(qid);
 988         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 989         c.create_cq.cq_flags = cpu_to_le16(flags);
 990         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 991
 992         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 993 }
 994
 995 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 996                                                 struct nvme_queue *nvmeq)
 997 {
 998         struct nvme_command c;
 999         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1000
1001         /*
1002          * Note: we (ab)use the fact the the prp fields survive if no data
1003          * is attached to the request.
1004          */
1005         memset(&c, 0, sizeof(c));
1006         c.create_sq.opcode = nvme_admin_create_sq;
1007         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1008         c.create_sq.sqid = cpu_to_le16(qid);
1009         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1010         c.create_sq.sq_flags = cpu_to_le16(flags);
1011         c.create_sq.cqid = cpu_to_le16(qid);
1012
1013         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1014 }
1015
1016 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1017 {
1018         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1019 }
1020
1021 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1022 {
1023         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1024 }
1025
1026 static void abort_endio(struct request *req, int error)
1027 {
1028         struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1029         struct nvme_queue *nvmeq = cmd->nvmeq;
1030         u32 result = (u32)(uintptr_t)req->special;
1031         u16 status = req->errors;
1032
1033         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
1034         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1035
1036         blk_mq_free_request(req);
1037 }
1038
1039 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1040 {
1041         struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1042         struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1043         struct nvme_dev *dev = nvmeq->dev;
1044         struct request *abort_req;
1045         struct nvme_command cmd;
1046
1047         /*
1048          * Shutdown immediately if controller times out while starting. The
1049          * reset work will see the pci device disabled when it gets the forced
1050          * cancellation error. All outstanding requests are completed on
1051          * shutdown, so we return BLK_EH_HANDLED.
1052          */
1053         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
1054                 dev_warn(dev->dev,
1055                          "I/O %d QID %d timeout, disable controller\n",
1056                          req->tag, nvmeq->qid);
1057                 nvme_dev_shutdown(dev);
1058                 req->errors = NVME_SC_CANCELLED;
1059                 return BLK_EH_HANDLED;
1060         }
1061
1062         /*
1063          * Shutdown the controller immediately and schedule a reset if the
1064          * command was already aborted once before and still hasn't been
1065          * returned to the driver, or if this is the admin queue.
1066          */
1067         if (!nvmeq->qid || cmd_rq->aborted) {
1068                 dev_warn(dev->dev,
1069                          "I/O %d QID %d timeout, reset controller\n",
1070                          req->tag, nvmeq->qid);
1071                 nvme_dev_shutdown(dev);
1072                 queue_work(nvme_workq, &dev->reset_work);
1073
1074                 /*
1075                  * Mark the request as handled, since the inline shutdown
1076                  * forces all outstanding requests to complete.
1077                  */
1078                 req->errors = NVME_SC_CANCELLED;
1079                 return BLK_EH_HANDLED;
1080         }
1081
1082         cmd_rq->aborted = 1;
1083
1084         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1085                 atomic_inc(&dev->ctrl.abort_limit);
1086                 return BLK_EH_RESET_TIMER;
1087         }
1088
1089         memset(&cmd, 0, sizeof(cmd));
1090         cmd.abort.opcode = nvme_admin_abort_cmd;
1091         cmd.abort.cid = req->tag;
1092         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1093
1094         dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n",
1095                                  req->tag, nvmeq->qid);
1096
1097         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1098                         BLK_MQ_REQ_NOWAIT);
1099         if (IS_ERR(abort_req)) {
1100                 atomic_inc(&dev->ctrl.abort_limit);
1101                 return BLK_EH_RESET_TIMER;
1102         }
1103
1104         abort_req->timeout = ADMIN_TIMEOUT;
1105         abort_req->end_io_data = NULL;
1106         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1107
1108         /*
1109          * The aborted req will be completed on receiving the abort req.
1110          * We enable the timer again. If hit twice, it'll cause a device reset,
1111          * as the device then is in a faulty state.
1112          */
1113         return BLK_EH_RESET_TIMER;
1114 }
1115
1116 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1117 {
1118         struct nvme_queue *nvmeq = data;
1119         void *ctx;
1120         nvme_completion_fn fn;
1121         struct nvme_cmd_info *cmd;
1122         struct nvme_completion cqe;
1123
1124         if (!blk_mq_request_started(req))
1125                 return;
1126
1127         cmd = blk_mq_rq_to_pdu(req);
1128
1129         if (cmd->ctx == CMD_CTX_CANCELLED)
1130                 return;
1131
1132         if (blk_queue_dying(req->q))
1133                 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1134         else
1135                 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1136
1137
1138         dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1139                                                 req->tag, nvmeq->qid);
1140         ctx = cancel_cmd_info(cmd, &fn);
1141         fn(nvmeq, ctx, &cqe);
1142 }
1143
1144 static void nvme_free_queue(struct nvme_queue *nvmeq)
1145 {
1146         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1147                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1148         if (nvmeq->sq_cmds)
1149                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1150                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1151         kfree(nvmeq);
1152 }
1153
1154 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1155 {
1156         int i;
1157
1158         for (i = dev->queue_count - 1; i >= lowest; i--) {
1159                 struct nvme_queue *nvmeq = dev->queues[i];
1160                 dev->queue_count--;
1161                 dev->queues[i] = NULL;
1162                 nvme_free_queue(nvmeq);
1163         }
1164 }
1165
1166 /**
1167  * nvme_suspend_queue - put queue into suspended state
1168  * @nvmeq - queue to suspend
1169  */
1170 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1171 {
1172         int vector;
1173
1174         spin_lock_irq(&nvmeq->q_lock);
1175         if (nvmeq->cq_vector == -1) {
1176                 spin_unlock_irq(&nvmeq->q_lock);
1177                 return 1;
1178         }
1179         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1180         nvmeq->dev->online_queues--;
1181         nvmeq->cq_vector = -1;
1182         spin_unlock_irq(&nvmeq->q_lock);
1183
1184         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1185                 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q);
1186
1187         irq_set_affinity_hint(vector, NULL);
1188         free_irq(vector, nvmeq);
1189
1190         return 0;
1191 }
1192
1193 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1194 {
1195         spin_lock_irq(&nvmeq->q_lock);
1196         if (nvmeq->tags && *nvmeq->tags)
1197                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1198         spin_unlock_irq(&nvmeq->q_lock);
1199 }
1200
1201 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1202 {
1203         struct nvme_queue *nvmeq = dev->queues[qid];
1204
1205         if (!nvmeq)
1206                 return;
1207         if (nvme_suspend_queue(nvmeq))
1208                 return;
1209
1210         /* Don't tell the adapter to delete the admin queue.
1211          * Don't tell a removed adapter to delete IO queues. */
1212         if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) {
1213                 adapter_delete_sq(dev, qid);
1214                 adapter_delete_cq(dev, qid);
1215         }
1216
1217         spin_lock_irq(&nvmeq->q_lock);
1218         nvme_process_cq(nvmeq);
1219         spin_unlock_irq(&nvmeq->q_lock);
1220 }
1221
1222 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1223                                 int entry_size)
1224 {
1225         int q_depth = dev->q_depth;
1226         unsigned q_size_aligned = roundup(q_depth * entry_size,
1227                                           dev->ctrl.page_size);
1228
1229         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1230                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1231                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1232                 q_depth = div_u64(mem_per_q, entry_size);
1233
1234                 /*
1235                  * Ensure the reduced q_depth is above some threshold where it
1236                  * would be better to map queues in system memory with the
1237                  * original depth
1238                  */
1239                 if (q_depth < 64)
1240                         return -ENOMEM;
1241         }
1242
1243         return q_depth;
1244 }
1245
1246 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1247                                 int qid, int depth)
1248 {
1249         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1250                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1251                                                       dev->ctrl.page_size);
1252                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1253                 nvmeq->sq_cmds_io = dev->cmb + offset;
1254         } else {
1255                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1256                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1257                 if (!nvmeq->sq_cmds)
1258                         return -ENOMEM;
1259         }
1260
1261         return 0;
1262 }
1263
1264 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1265                                                         int depth)
1266 {
1267         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1268         if (!nvmeq)
1269                 return NULL;
1270
1271         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1272                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1273         if (!nvmeq->cqes)
1274                 goto free_nvmeq;
1275
1276         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1277                 goto free_cqdma;
1278
1279         nvmeq->q_dmadev = dev->dev;
1280         nvmeq->dev = dev;
1281         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1282                         dev->ctrl.instance, qid);
1283         spin_lock_init(&nvmeq->q_lock);
1284         nvmeq->cq_head = 0;
1285         nvmeq->cq_phase = 1;
1286         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1287         nvmeq->q_depth = depth;
1288         nvmeq->qid = qid;
1289         nvmeq->cq_vector = -1;
1290         dev->queues[qid] = nvmeq;
1291
1292         /* make sure queue descriptor is set before queue count, for kthread */
1293         mb();
1294         dev->queue_count++;
1295
1296         return nvmeq;
1297
1298  free_cqdma:
1299         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1300                                                         nvmeq->cq_dma_addr);
1301  free_nvmeq:
1302         kfree(nvmeq);
1303         return NULL;
1304 }
1305
1306 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1307                                                         const char *name)
1308 {
1309         if (use_threaded_interrupts)
1310                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1311                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1312                                         name, nvmeq);
1313         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1314                                 IRQF_SHARED, name, nvmeq);
1315 }
1316
1317 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1318 {
1319         struct nvme_dev *dev = nvmeq->dev;
1320
1321         spin_lock_irq(&nvmeq->q_lock);
1322         nvmeq->sq_tail = 0;
1323         nvmeq->cq_head = 0;
1324         nvmeq->cq_phase = 1;
1325         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1326         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1327         dev->online_queues++;
1328         spin_unlock_irq(&nvmeq->q_lock);
1329 }
1330
1331 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1332 {
1333         struct nvme_dev *dev = nvmeq->dev;
1334         int result;
1335
1336         nvmeq->cq_vector = qid - 1;
1337         result = adapter_alloc_cq(dev, qid, nvmeq);
1338         if (result < 0)
1339                 return result;
1340
1341         result = adapter_alloc_sq(dev, qid, nvmeq);
1342         if (result < 0)
1343                 goto release_cq;
1344
1345         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1346         if (result < 0)
1347                 goto release_sq;
1348
1349         nvme_init_queue(nvmeq, qid);
1350         return result;
1351
1352  release_sq:
1353         adapter_delete_sq(dev, qid);
1354  release_cq:
1355         adapter_delete_cq(dev, qid);
1356         return result;
1357 }
1358
1359 static struct blk_mq_ops nvme_mq_admin_ops = {
1360         .queue_rq       = nvme_queue_rq,
1361         .map_queue      = blk_mq_map_queue,
1362         .init_hctx      = nvme_admin_init_hctx,
1363         .exit_hctx      = nvme_admin_exit_hctx,
1364         .init_request   = nvme_admin_init_request,
1365         .timeout        = nvme_timeout,
1366 };
1367
1368 static struct blk_mq_ops nvme_mq_ops = {
1369         .queue_rq       = nvme_queue_rq,
1370         .map_queue      = blk_mq_map_queue,
1371         .init_hctx      = nvme_init_hctx,
1372         .init_request   = nvme_init_request,
1373         .timeout        = nvme_timeout,
1374         .poll           = nvme_poll,
1375 };
1376
1377 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1378 {
1379         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1380                 blk_cleanup_queue(dev->ctrl.admin_q);
1381                 blk_mq_free_tag_set(&dev->admin_tagset);
1382         }
1383 }
1384
1385 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1386 {
1387         if (!dev->ctrl.admin_q) {
1388                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1389                 dev->admin_tagset.nr_hw_queues = 1;
1390                 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH;
1391                 dev->admin_tagset.reserved_tags = 1;
1392                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1393                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1394                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1395                 dev->admin_tagset.driver_data = dev;
1396
1397                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1398                         return -ENOMEM;
1399
1400                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1401                 if (IS_ERR(dev->ctrl.admin_q)) {
1402                         blk_mq_free_tag_set(&dev->admin_tagset);
1403                         return -ENOMEM;
1404                 }
1405                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1406                         nvme_dev_remove_admin(dev);
1407                         dev->ctrl.admin_q = NULL;
1408                         return -ENODEV;
1409                 }
1410         } else
1411                 blk_mq_unfreeze_queue(dev->ctrl.admin_q);
1412
1413         return 0;
1414 }
1415
1416 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1417 {
1418         int result;
1419         u32 aqa;
1420         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1421         struct nvme_queue *nvmeq;
1422
1423         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1424                                                 NVME_CAP_NSSRC(cap) : 0;
1425
1426         if (dev->subsystem &&
1427             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1428                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1429
1430         result = nvme_disable_ctrl(&dev->ctrl, cap);
1431         if (result < 0)
1432                 return result;
1433
1434         nvmeq = dev->queues[0];
1435         if (!nvmeq) {
1436                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1437                 if (!nvmeq)
1438                         return -ENOMEM;
1439         }
1440
1441         aqa = nvmeq->q_depth - 1;
1442         aqa |= aqa << 16;
1443
1444         writel(aqa, dev->bar + NVME_REG_AQA);
1445         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1446         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1447
1448         result = nvme_enable_ctrl(&dev->ctrl, cap);
1449         if (result)
1450                 goto free_nvmeq;
1451
1452         nvmeq->cq_vector = 0;
1453         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1454         if (result) {
1455                 nvmeq->cq_vector = -1;
1456                 goto free_nvmeq;
1457         }
1458
1459         return result;
1460
1461  free_nvmeq:
1462         nvme_free_queues(dev, 0);
1463         return result;
1464 }
1465
1466 static int nvme_kthread(void *data)
1467 {
1468         struct nvme_dev *dev, *next;
1469
1470         while (!kthread_should_stop()) {
1471                 set_current_state(TASK_INTERRUPTIBLE);
1472                 spin_lock(&dev_list_lock);
1473                 list_for_each_entry_safe(dev, next, &dev_list, node) {
1474                         int i;
1475                         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1476
1477                         /*
1478                          * Skip controllers currently under reset.
1479                          */
1480                         if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1481                                 continue;
1482
1483                         if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1484                                                         csts & NVME_CSTS_CFS) {
1485                                 if (queue_work(nvme_workq, &dev->reset_work)) {
1486                                         dev_warn(dev->dev,
1487                                                 "Failed status: %x, reset controller\n",
1488                                                 readl(dev->bar + NVME_REG_CSTS));
1489                                 }
1490                                 continue;
1491                         }
1492                         for (i = 0; i < dev->queue_count; i++) {
1493                                 struct nvme_queue *nvmeq = dev->queues[i];
1494                                 if (!nvmeq)
1495                                         continue;
1496                                 spin_lock_irq(&nvmeq->q_lock);
1497                                 nvme_process_cq(nvmeq);
1498
1499                                 while (i == 0 && dev->ctrl.event_limit > 0) {
1500                                         if (nvme_submit_async_admin_req(dev))
1501                                                 break;
1502                                         dev->ctrl.event_limit--;
1503                                 }
1504                                 spin_unlock_irq(&nvmeq->q_lock);
1505                         }
1506                 }
1507                 spin_unlock(&dev_list_lock);
1508                 schedule_timeout(round_jiffies_relative(HZ));
1509         }
1510         return 0;
1511 }
1512
1513 static int nvme_create_io_queues(struct nvme_dev *dev)
1514 {
1515         unsigned i;
1516         int ret = 0;
1517
1518         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1519                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1520                         ret = -ENOMEM;
1521                         break;
1522                 }
1523         }
1524
1525         for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
1526                 ret = nvme_create_queue(dev->queues[i], i);
1527                 if (ret) {
1528                         nvme_free_queues(dev, i);
1529                         break;
1530                 }
1531         }
1532
1533         /*
1534          * Ignore failing Create SQ/CQ commands, we can continue with less
1535          * than the desired aount of queues, and even a controller without
1536          * I/O queues an still be used to issue admin commands.  This might
1537          * be useful to upgrade a buggy firmware for example.
1538          */
1539         return ret >= 0 ? 0 : ret;
1540 }
1541
1542 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1543 {
1544         u64 szu, size, offset;
1545         u32 cmbloc;
1546         resource_size_t bar_size;
1547         struct pci_dev *pdev = to_pci_dev(dev->dev);
1548         void __iomem *cmb;
1549         dma_addr_t dma_addr;
1550
1551         if (!use_cmb_sqes)
1552                 return NULL;
1553
1554         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1555         if (!(NVME_CMB_SZ(dev->cmbsz)))
1556                 return NULL;
1557
1558         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1559
1560         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1561         size = szu * NVME_CMB_SZ(dev->cmbsz);
1562         offset = szu * NVME_CMB_OFST(cmbloc);
1563         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1564
1565         if (offset > bar_size)
1566                 return NULL;
1567
1568         /*
1569          * Controllers may support a CMB size larger than their BAR,
1570          * for example, due to being behind a bridge. Reduce the CMB to
1571          * the reported size of the BAR
1572          */
1573         if (size > bar_size - offset)
1574                 size = bar_size - offset;
1575
1576         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1577         cmb = ioremap_wc(dma_addr, size);
1578         if (!cmb)
1579                 return NULL;
1580
1581         dev->cmb_dma_addr = dma_addr;
1582         dev->cmb_size = size;
1583         return cmb;
1584 }
1585
1586 static inline void nvme_release_cmb(struct nvme_dev *dev)
1587 {
1588         if (dev->cmb) {
1589                 iounmap(dev->cmb);
1590                 dev->cmb = NULL;
1591         }
1592 }
1593
1594 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1595 {
1596         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1597 }
1598
1599 static int nvme_setup_io_queues(struct nvme_dev *dev)
1600 {
1601         struct nvme_queue *adminq = dev->queues[0];
1602         struct pci_dev *pdev = to_pci_dev(dev->dev);
1603         int result, i, vecs, nr_io_queues, size;
1604
1605         nr_io_queues = num_possible_cpus();
1606         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1607         if (result < 0)
1608                 return result;
1609
1610         /*
1611          * Degraded controllers might return an error when setting the queue
1612          * count.  We still want to be able to bring them online and offer
1613          * access to the admin queue, as that might be only way to fix them up.
1614          */
1615         if (result > 0) {
1616                 dev_err(dev->dev, "Could not set queue count (%d)\n", result);
1617                 nr_io_queues = 0;
1618                 result = 0;
1619         }
1620
1621         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1622                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1623                                 sizeof(struct nvme_command));
1624                 if (result > 0)
1625                         dev->q_depth = result;
1626                 else
1627                         nvme_release_cmb(dev);
1628         }
1629
1630         size = db_bar_size(dev, nr_io_queues);
1631         if (size > 8192) {
1632                 iounmap(dev->bar);
1633                 do {
1634                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1635                         if (dev->bar)
1636                                 break;
1637                         if (!--nr_io_queues)
1638                                 return -ENOMEM;
1639                         size = db_bar_size(dev, nr_io_queues);
1640                 } while (1);
1641                 dev->dbs = dev->bar + 4096;
1642                 adminq->q_db = dev->dbs;
1643         }
1644
1645         /* Deregister the admin queue's interrupt */
1646         free_irq(dev->entry[0].vector, adminq);
1647
1648         /*
1649          * If we enable msix early due to not intx, disable it again before
1650          * setting up the full range we need.
1651          */
1652         if (!pdev->irq)
1653                 pci_disable_msix(pdev);
1654
1655         for (i = 0; i < nr_io_queues; i++)
1656                 dev->entry[i].entry = i;
1657         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1658         if (vecs < 0) {
1659                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1660                 if (vecs < 0) {
1661                         vecs = 1;
1662                 } else {
1663                         for (i = 0; i < vecs; i++)
1664                                 dev->entry[i].vector = i + pdev->irq;
1665                 }
1666         }
1667
1668         /*
1669          * Should investigate if there's a performance win from allocating
1670          * more queues than interrupt vectors; it might allow the submission
1671          * path to scale better, even if the receive path is limited by the
1672          * number of interrupts.
1673          */
1674         nr_io_queues = vecs;
1675         dev->max_qid = nr_io_queues;
1676
1677         result = queue_request_irq(dev, adminq, adminq->irqname);
1678         if (result) {
1679                 adminq->cq_vector = -1;
1680                 goto free_queues;
1681         }
1682
1683         /* Free previously allocated queues that are no longer usable */
1684         nvme_free_queues(dev, nr_io_queues + 1);
1685         return nvme_create_io_queues(dev);
1686
1687  free_queues:
1688         nvme_free_queues(dev, 1);
1689         return result;
1690 }
1691
1692 static void nvme_set_irq_hints(struct nvme_dev *dev)
1693 {
1694         struct nvme_queue *nvmeq;
1695         int i;
1696
1697         for (i = 0; i < dev->online_queues; i++) {
1698                 nvmeq = dev->queues[i];
1699
1700                 if (!nvmeq->tags || !(*nvmeq->tags))
1701                         continue;
1702
1703                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1704                                         blk_mq_tags_cpumask(*nvmeq->tags));
1705         }
1706 }
1707
1708 static void nvme_dev_scan(struct work_struct *work)
1709 {
1710         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1711
1712         if (!dev->tagset.tags)
1713                 return;
1714         nvme_scan_namespaces(&dev->ctrl);
1715         nvme_set_irq_hints(dev);
1716 }
1717
1718 /*
1719  * Return: error value if an error occurred setting up the queues or calling
1720  * Identify Device.  0 if these succeeded, even if adding some of the
1721  * namespaces failed.  At the moment, these failures are silent.  TBD which
1722  * failures should be reported.
1723  */
1724 static int nvme_dev_add(struct nvme_dev *dev)
1725 {
1726         if (!dev->ctrl.tagset) {
1727                 dev->tagset.ops = &nvme_mq_ops;
1728                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1729                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1730                 dev->tagset.numa_node = dev_to_node(dev->dev);
1731                 dev->tagset.queue_depth =
1732                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1733                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1734                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1735                 dev->tagset.driver_data = dev;
1736
1737                 if (blk_mq_alloc_tag_set(&dev->tagset))
1738                         return 0;
1739                 dev->ctrl.tagset = &dev->tagset;
1740         }
1741         queue_work(nvme_workq, &dev->scan_work);
1742         return 0;
1743 }
1744
1745 static int nvme_dev_map(struct nvme_dev *dev)
1746 {
1747         u64 cap;
1748         int bars, result = -ENOMEM;
1749         struct pci_dev *pdev = to_pci_dev(dev->dev);
1750
1751         if (pci_enable_device_mem(pdev))
1752                 return result;
1753
1754         dev->entry[0].vector = pdev->irq;
1755         pci_set_master(pdev);
1756         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1757         if (!bars)
1758                 goto disable_pci;
1759
1760         if (pci_request_selected_regions(pdev, bars, "nvme"))
1761                 goto disable_pci;
1762
1763         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1764             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1765                 goto disable;
1766
1767         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1768         if (!dev->bar)
1769                 goto disable;
1770
1771         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1772                 result = -ENODEV;
1773                 goto unmap;
1774         }
1775
1776         /*
1777          * Some devices don't advertse INTx interrupts, pre-enable a single
1778          * MSIX vec for setup. We'll adjust this later.
1779          */
1780         if (!pdev->irq) {
1781                 result = pci_enable_msix(pdev, dev->entry, 1);
1782                 if (result < 0)
1783                         goto unmap;
1784         }
1785
1786         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1787
1788         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1789         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1790         dev->dbs = dev->bar + 4096;
1791         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1792                 dev->cmb = nvme_map_cmb(dev);
1793
1794         return 0;
1795
1796  unmap:
1797         iounmap(dev->bar);
1798         dev->bar = NULL;
1799  disable:
1800         pci_release_regions(pdev);
1801  disable_pci:
1802         pci_disable_device(pdev);
1803         return result;
1804 }
1805
1806 static void nvme_dev_unmap(struct nvme_dev *dev)
1807 {
1808         struct pci_dev *pdev = to_pci_dev(dev->dev);
1809
1810         if (pdev->msi_enabled)
1811                 pci_disable_msi(pdev);
1812         else if (pdev->msix_enabled)
1813                 pci_disable_msix(pdev);
1814
1815         if (dev->bar) {
1816                 iounmap(dev->bar);
1817                 dev->bar = NULL;
1818                 pci_release_regions(pdev);
1819         }
1820
1821         if (pci_is_enabled(pdev))
1822                 pci_disable_device(pdev);
1823 }
1824
1825 struct nvme_delq_ctx {
1826         struct task_struct *waiter;
1827         struct kthread_worker *worker;
1828         atomic_t refcount;
1829 };
1830
1831 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
1832 {
1833         dq->waiter = current;
1834         mb();
1835
1836         for (;;) {
1837                 set_current_state(TASK_KILLABLE);
1838                 if (!atomic_read(&dq->refcount))
1839                         break;
1840                 if (!schedule_timeout(ADMIN_TIMEOUT) ||
1841                                         fatal_signal_pending(current)) {
1842                         /*
1843                          * Disable the controller first since we can't trust it
1844                          * at this point, but leave the admin queue enabled
1845                          * until all queue deletion requests are flushed.
1846                          * FIXME: This may take a while if there are more h/w
1847                          * queues than admin tags.
1848                          */
1849                         set_current_state(TASK_RUNNING);
1850                         nvme_disable_ctrl(&dev->ctrl,
1851                                 lo_hi_readq(dev->bar + NVME_REG_CAP));
1852                         nvme_clear_queue(dev->queues[0]);
1853                         flush_kthread_worker(dq->worker);
1854                         nvme_disable_queue(dev, 0);
1855                         return;
1856                 }
1857         }
1858         set_current_state(TASK_RUNNING);
1859 }
1860
1861 static void nvme_put_dq(struct nvme_delq_ctx *dq)
1862 {
1863         atomic_dec(&dq->refcount);
1864         if (dq->waiter)
1865                 wake_up_process(dq->waiter);
1866 }
1867
1868 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
1869 {
1870         atomic_inc(&dq->refcount);
1871         return dq;
1872 }
1873
1874 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
1875 {
1876         struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
1877         nvme_put_dq(dq);
1878
1879         spin_lock_irq(&nvmeq->q_lock);
1880         nvme_process_cq(nvmeq);
1881         spin_unlock_irq(&nvmeq->q_lock);
1882 }
1883
1884 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
1885                                                 kthread_work_func_t fn)
1886 {
1887         struct request *req;
1888         struct nvme_command c;
1889
1890         memset(&c, 0, sizeof(c));
1891         c.delete_queue.opcode = opcode;
1892         c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1893
1894         init_kthread_work(&nvmeq->cmdinfo.work, fn);
1895
1896         req = nvme_alloc_request(nvmeq->dev->ctrl.admin_q, &c, 0);
1897         if (IS_ERR(req))
1898                 return PTR_ERR(req);
1899
1900         req->timeout = ADMIN_TIMEOUT;
1901         req->end_io_data = &nvmeq->cmdinfo;
1902         blk_execute_rq_nowait(req->q, NULL, req, 0, async_cmd_info_endio);
1903         return 0;
1904 }
1905
1906 static void nvme_del_cq_work_handler(struct kthread_work *work)
1907 {
1908         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1909                                                         cmdinfo.work);
1910         nvme_del_queue_end(nvmeq);
1911 }
1912
1913 static int nvme_delete_cq(struct nvme_queue *nvmeq)
1914 {
1915         return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
1916                                                 nvme_del_cq_work_handler);
1917 }
1918
1919 static void nvme_del_sq_work_handler(struct kthread_work *work)
1920 {
1921         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1922                                                         cmdinfo.work);
1923         int status = nvmeq->cmdinfo.status;
1924
1925         if (!status)
1926                 status = nvme_delete_cq(nvmeq);
1927         if (status)
1928                 nvme_del_queue_end(nvmeq);
1929 }
1930
1931 static int nvme_delete_sq(struct nvme_queue *nvmeq)
1932 {
1933         return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
1934                                                 nvme_del_sq_work_handler);
1935 }
1936
1937 static void nvme_del_queue_start(struct kthread_work *work)
1938 {
1939         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1940                                                         cmdinfo.work);
1941         if (nvme_delete_sq(nvmeq))
1942                 nvme_del_queue_end(nvmeq);
1943 }
1944
1945 static void nvme_disable_io_queues(struct nvme_dev *dev)
1946 {
1947         int i;
1948         DEFINE_KTHREAD_WORKER_ONSTACK(worker);
1949         struct nvme_delq_ctx dq;
1950         struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
1951                                         &worker, "nvme%d", dev->ctrl.instance);
1952
1953         if (IS_ERR(kworker_task)) {
1954                 dev_err(dev->dev,
1955                         "Failed to create queue del task\n");
1956                 for (i = dev->queue_count - 1; i > 0; i--)
1957                         nvme_disable_queue(dev, i);
1958                 return;
1959         }
1960
1961         dq.waiter = NULL;
1962         atomic_set(&dq.refcount, 0);
1963         dq.worker = &worker;
1964         for (i = dev->queue_count - 1; i > 0; i--) {
1965                 struct nvme_queue *nvmeq = dev->queues[i];
1966
1967                 if (nvme_suspend_queue(nvmeq))
1968                         continue;
1969                 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
1970                 nvmeq->cmdinfo.worker = dq.worker;
1971                 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
1972                 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
1973         }
1974         nvme_wait_dq(&dq, dev);
1975         kthread_stop(kworker_task);
1976 }
1977
1978 static int nvme_dev_list_add(struct nvme_dev *dev)
1979 {
1980         bool start_thread = false;
1981
1982         spin_lock(&dev_list_lock);
1983         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
1984                 start_thread = true;
1985                 nvme_thread = NULL;
1986         }
1987         list_add(&dev->node, &dev_list);
1988         spin_unlock(&dev_list_lock);
1989
1990         if (start_thread) {
1991                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1992                 wake_up_all(&nvme_kthread_wait);
1993         } else
1994                 wait_event_killable(nvme_kthread_wait, nvme_thread);
1995
1996         if (IS_ERR_OR_NULL(nvme_thread))
1997                 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
1998
1999         return 0;
2000 }
2001
2002 /*
2003 * Remove the node from the device list and check
2004 * for whether or not we need to stop the nvme_thread.
2005 */
2006 static void nvme_dev_list_remove(struct nvme_dev *dev)
2007 {
2008         struct task_struct *tmp = NULL;
2009
2010         spin_lock(&dev_list_lock);
2011         list_del_init(&dev->node);
2012         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2013                 tmp = nvme_thread;
2014                 nvme_thread = NULL;
2015         }
2016         spin_unlock(&dev_list_lock);
2017
2018         if (tmp)
2019                 kthread_stop(tmp);
2020 }
2021
2022 static void nvme_freeze_queues(struct nvme_dev *dev)
2023 {
2024         struct nvme_ns *ns;
2025
2026         list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
2027                 blk_mq_freeze_queue_start(ns->queue);
2028
2029                 spin_lock_irq(ns->queue->queue_lock);
2030                 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2031                 spin_unlock_irq(ns->queue->queue_lock);
2032
2033                 blk_mq_cancel_requeue_work(ns->queue);
2034                 blk_mq_stop_hw_queues(ns->queue);
2035         }
2036 }
2037
2038 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2039 {
2040         struct nvme_ns *ns;
2041
2042         list_for_each_entry(ns, &dev->ctrl.namespaces, list) {
2043                 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2044                 blk_mq_unfreeze_queue(ns->queue);
2045                 blk_mq_start_stopped_hw_queues(ns->queue, true);
2046                 blk_mq_kick_requeue_list(ns->queue);
2047         }
2048 }
2049
2050 static void nvme_dev_shutdown(struct nvme_dev *dev)
2051 {
2052         int i;
2053         u32 csts = -1;
2054
2055         nvme_dev_list_remove(dev);
2056
2057         mutex_lock(&dev->shutdown_lock);
2058         if (dev->bar) {
2059                 nvme_freeze_queues(dev);
2060                 csts = readl(dev->bar + NVME_REG_CSTS);
2061         }
2062         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2063                 for (i = dev->queue_count - 1; i >= 0; i--) {
2064                         struct nvme_queue *nvmeq = dev->queues[i];
2065                         nvme_suspend_queue(nvmeq);
2066                 }
2067         } else {
2068                 nvme_disable_io_queues(dev);
2069                 nvme_shutdown_ctrl(&dev->ctrl);
2070                 nvme_disable_queue(dev, 0);
2071         }
2072         nvme_dev_unmap(dev);
2073
2074         for (i = dev->queue_count - 1; i >= 0; i--)
2075                 nvme_clear_queue(dev->queues[i]);
2076         mutex_unlock(&dev->shutdown_lock);
2077 }
2078
2079 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2080 {
2081         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2082                                                 PAGE_SIZE, PAGE_SIZE, 0);
2083         if (!dev->prp_page_pool)
2084                 return -ENOMEM;
2085
2086         /* Optimisation for I/Os between 4k and 128k */
2087         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2088                                                 256, 256, 0);
2089         if (!dev->prp_small_pool) {
2090                 dma_pool_destroy(dev->prp_page_pool);
2091                 return -ENOMEM;
2092         }
2093         return 0;
2094 }
2095
2096 static void nvme_release_prp_pools(struct nvme_dev *dev)
2097 {
2098         dma_pool_destroy(dev->prp_page_pool);
2099         dma_pool_destroy(dev->prp_small_pool);
2100 }
2101
2102 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2103 {
2104         struct nvme_dev *dev = to_nvme_dev(ctrl);
2105
2106         put_device(dev->dev);
2107         if (dev->tagset.tags)
2108                 blk_mq_free_tag_set(&dev->tagset);
2109         if (dev->ctrl.admin_q)
2110                 blk_put_queue(dev->ctrl.admin_q);
2111         kfree(dev->queues);
2112         kfree(dev->entry);
2113         kfree(dev);
2114 }
2115
2116 static void nvme_reset_work(struct work_struct *work)
2117 {
2118         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2119         int result;
2120
2121         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
2122                 goto out;
2123
2124         /*
2125          * If we're called to reset a live controller first shut it down before
2126          * moving on.
2127          */
2128         if (dev->bar)
2129                 nvme_dev_shutdown(dev);
2130
2131         set_bit(NVME_CTRL_RESETTING, &dev->flags);
2132
2133         result = nvme_dev_map(dev);
2134         if (result)
2135                 goto out;
2136
2137         result = nvme_configure_admin_queue(dev);
2138         if (result)
2139                 goto unmap;
2140
2141         nvme_init_queue(dev->queues[0], 0);
2142         result = nvme_alloc_admin_tags(dev);
2143         if (result)
2144                 goto disable;
2145
2146         result = nvme_init_identify(&dev->ctrl);
2147         if (result)
2148                 goto free_tags;
2149
2150         result = nvme_setup_io_queues(dev);
2151         if (result)
2152                 goto free_tags;
2153
2154         dev->ctrl.event_limit = 1;
2155
2156         result = nvme_dev_list_add(dev);
2157         if (result)
2158                 goto remove;
2159
2160         /*
2161          * Keep the controller around but remove all namespaces if we don't have
2162          * any working I/O queue.
2163          */
2164         if (dev->online_queues < 2) {
2165                 dev_warn(dev->dev, "IO queues not created\n");
2166                 nvme_remove_namespaces(&dev->ctrl);
2167         } else {
2168                 nvme_unfreeze_queues(dev);
2169                 nvme_dev_add(dev);
2170         }
2171
2172         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
2173         return;
2174
2175  remove:
2176         nvme_dev_list_remove(dev);
2177  free_tags:
2178         nvme_dev_remove_admin(dev);
2179         blk_put_queue(dev->ctrl.admin_q);
2180         dev->ctrl.admin_q = NULL;
2181         dev->queues[0]->tags = NULL;
2182  disable:
2183         nvme_disable_queue(dev, 0);
2184  unmap:
2185         nvme_dev_unmap(dev);
2186  out:
2187         nvme_remove_dead_ctrl(dev);
2188 }
2189
2190 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2191 {
2192         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2193         struct pci_dev *pdev = to_pci_dev(dev->dev);
2194
2195         if (pci_get_drvdata(pdev))
2196                 pci_stop_and_remove_bus_device_locked(pdev);
2197         nvme_put_ctrl(&dev->ctrl);
2198 }
2199
2200 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2201 {
2202         dev_warn(dev->dev, "Removing after probe failure\n");
2203         kref_get(&dev->ctrl.kref);
2204         if (!schedule_work(&dev->remove_work))
2205                 nvme_put_ctrl(&dev->ctrl);
2206 }
2207
2208 static int nvme_reset(struct nvme_dev *dev)
2209 {
2210         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2211                 return -ENODEV;
2212
2213         if (!queue_work(nvme_workq, &dev->reset_work))
2214                 return -EBUSY;
2215
2216         flush_work(&dev->reset_work);
2217         return 0;
2218 }
2219
2220 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2221 {
2222         *val = readl(to_nvme_dev(ctrl)->bar + off);
2223         return 0;
2224 }
2225
2226 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2227 {
2228         writel(val, to_nvme_dev(ctrl)->bar + off);
2229         return 0;
2230 }
2231
2232 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2233 {
2234         *val = readq(to_nvme_dev(ctrl)->bar + off);
2235         return 0;
2236 }
2237
2238 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2239 {
2240         struct nvme_dev *dev = to_nvme_dev(ctrl);
2241
2242         return !dev->bar || dev->online_queues < 2;
2243 }
2244
2245 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2246 {
2247         return nvme_reset(to_nvme_dev(ctrl));
2248 }
2249
2250 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2251         .reg_read32             = nvme_pci_reg_read32,
2252         .reg_write32            = nvme_pci_reg_write32,
2253         .reg_read64             = nvme_pci_reg_read64,
2254         .io_incapable           = nvme_pci_io_incapable,
2255         .reset_ctrl             = nvme_pci_reset_ctrl,
2256         .free_ctrl              = nvme_pci_free_ctrl,
2257 };
2258
2259 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2260 {
2261         int node, result = -ENOMEM;
2262         struct nvme_dev *dev;
2263
2264         node = dev_to_node(&pdev->dev);
2265         if (node == NUMA_NO_NODE)
2266                 set_dev_node(&pdev->dev, 0);
2267
2268         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2269         if (!dev)
2270                 return -ENOMEM;
2271         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2272                                                         GFP_KERNEL, node);
2273         if (!dev->entry)
2274                 goto free;
2275         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2276                                                         GFP_KERNEL, node);
2277         if (!dev->queues)
2278                 goto free;
2279
2280         dev->dev = get_device(&pdev->dev);
2281         pci_set_drvdata(pdev, dev);
2282
2283         INIT_LIST_HEAD(&dev->node);
2284         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2285         INIT_WORK(&dev->reset_work, nvme_reset_work);
2286         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2287         mutex_init(&dev->shutdown_lock);
2288
2289         result = nvme_setup_prp_pools(dev);
2290         if (result)
2291                 goto put_pci;
2292
2293         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2294                         id->driver_data);
2295         if (result)
2296                 goto release_pools;
2297
2298         queue_work(nvme_workq, &dev->reset_work);
2299         return 0;
2300
2301  release_pools:
2302         nvme_release_prp_pools(dev);
2303  put_pci:
2304         put_device(dev->dev);
2305  free:
2306         kfree(dev->queues);
2307         kfree(dev->entry);
2308         kfree(dev);
2309         return result;
2310 }
2311
2312 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2313 {
2314         struct nvme_dev *dev = pci_get_drvdata(pdev);
2315
2316         if (prepare)
2317                 nvme_dev_shutdown(dev);
2318         else
2319                 queue_work(nvme_workq, &dev->reset_work);
2320 }
2321
2322 static void nvme_shutdown(struct pci_dev *pdev)
2323 {
2324         struct nvme_dev *dev = pci_get_drvdata(pdev);
2325         nvme_dev_shutdown(dev);
2326 }
2327
2328 static void nvme_remove(struct pci_dev *pdev)
2329 {
2330         struct nvme_dev *dev = pci_get_drvdata(pdev);
2331
2332         spin_lock(&dev_list_lock);
2333         list_del_init(&dev->node);
2334         spin_unlock(&dev_list_lock);
2335
2336         pci_set_drvdata(pdev, NULL);
2337         flush_work(&dev->reset_work);
2338         flush_work(&dev->scan_work);
2339         nvme_remove_namespaces(&dev->ctrl);
2340         nvme_uninit_ctrl(&dev->ctrl);
2341         nvme_dev_shutdown(dev);
2342         nvme_dev_remove_admin(dev);
2343         nvme_free_queues(dev, 0);
2344         nvme_release_cmb(dev);
2345         nvme_release_prp_pools(dev);
2346         nvme_put_ctrl(&dev->ctrl);
2347 }
2348
2349 /* These functions are yet to be implemented */
2350 #define nvme_error_detected NULL
2351 #define nvme_dump_registers NULL
2352 #define nvme_link_reset NULL
2353 #define nvme_slot_reset NULL
2354 #define nvme_error_resume NULL
2355
2356 #ifdef CONFIG_PM_SLEEP
2357 static int nvme_suspend(struct device *dev)
2358 {
2359         struct pci_dev *pdev = to_pci_dev(dev);
2360         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2361
2362         nvme_dev_shutdown(ndev);
2363         return 0;
2364 }
2365
2366 static int nvme_resume(struct device *dev)
2367 {
2368         struct pci_dev *pdev = to_pci_dev(dev);
2369         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2370
2371         queue_work(nvme_workq, &ndev->reset_work);
2372         return 0;
2373 }
2374 #endif
2375
2376 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2377
2378 static const struct pci_error_handlers nvme_err_handler = {
2379         .error_detected = nvme_error_detected,
2380         .mmio_enabled   = nvme_dump_registers,
2381         .link_reset     = nvme_link_reset,
2382         .slot_reset     = nvme_slot_reset,
2383         .resume         = nvme_error_resume,
2384         .reset_notify   = nvme_reset_notify,
2385 };
2386
2387 /* Move to pci_ids.h later */
2388 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2389
2390 static const struct pci_device_id nvme_id_table[] = {
2391         { PCI_VDEVICE(INTEL, 0x0953),
2392                 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2393         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2394                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2395         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2396         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2397         { 0, }
2398 };
2399 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2400
2401 static struct pci_driver nvme_driver = {
2402         .name           = "nvme",
2403         .id_table       = nvme_id_table,
2404         .probe          = nvme_probe,
2405         .remove         = nvme_remove,
2406         .shutdown       = nvme_shutdown,
2407         .driver         = {
2408                 .pm     = &nvme_dev_pm_ops,
2409         },
2410         .err_handler    = &nvme_err_handler,
2411 };
2412
2413 static int __init nvme_init(void)
2414 {
2415         int result;
2416
2417         init_waitqueue_head(&nvme_kthread_wait);
2418
2419         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2420         if (!nvme_workq)
2421                 return -ENOMEM;
2422
2423         result = nvme_core_init();
2424         if (result < 0)
2425                 goto kill_workq;
2426
2427         result = pci_register_driver(&nvme_driver);
2428         if (result)
2429                 goto core_exit;
2430         return 0;
2431
2432  core_exit:
2433         nvme_core_exit();
2434  kill_workq:
2435         destroy_workqueue(nvme_workq);
2436         return result;
2437 }
2438
2439 static void __exit nvme_exit(void)
2440 {
2441         pci_unregister_driver(&nvme_driver);
2442         nvme_core_exit();
2443         destroy_workqueue(nvme_workq);
2444         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2445         _nvme_check_size();
2446 }
2447
2448 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2449 MODULE_LICENSE("GPL");
2450 MODULE_VERSION("1.0");
2451 module_init(nvme_init);
2452 module_exit(nvme_exit);