1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
7 #include <linux/acpi.h>
9 #include <linux/async.h>
10 #include <linux/blkdev.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/once.h>
21 #include <linux/pci.h>
22 #include <linux/suspend.h>
23 #include <linux/t10-pi.h>
24 #include <linux/types.h>
25 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <linux/io-64-nonatomic-hi-lo.h>
27 #include <linux/sed-opal.h>
28 #include <linux/pci-p2pdma.h>
33 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
34 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
36 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
42 #define NVME_MAX_KB_SZ 4096
43 #define NVME_MAX_SEGS 127
45 static int use_threaded_interrupts;
46 module_param(use_threaded_interrupts, int, 0);
48 static bool use_cmb_sqes = true;
49 module_param(use_cmb_sqes, bool, 0444);
50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
52 static unsigned int max_host_mem_size_mb = 128;
53 module_param(max_host_mem_size_mb, uint, 0444);
54 MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
57 static unsigned int sgl_threshold = SZ_32K;
58 module_param(sgl_threshold, uint, 0644);
59 MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
63 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
64 static const struct kernel_param_ops io_queue_depth_ops = {
65 .set = io_queue_depth_set,
66 .get = param_get_uint,
69 static unsigned int io_queue_depth = 1024;
70 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
71 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
73 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
78 ret = kstrtouint(val, 10, &n);
79 if (ret != 0 || n > num_possible_cpus())
81 return param_set_uint(val, kp);
84 static const struct kernel_param_ops io_queue_count_ops = {
85 .set = io_queue_count_set,
86 .get = param_get_uint,
89 static unsigned int write_queues;
90 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
91 MODULE_PARM_DESC(write_queues,
92 "Number of queues to use for writes. If not set, reads and writes "
93 "will share a queue set.");
95 static unsigned int poll_queues;
96 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
97 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
100 module_param(noacpi, bool, 0444);
101 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
106 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
107 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
110 * Represents an NVM Express device. Each nvme_dev is a PCI function.
113 struct nvme_queue *queues;
114 struct blk_mq_tag_set tagset;
115 struct blk_mq_tag_set admin_tagset;
118 struct dma_pool *prp_page_pool;
119 struct dma_pool *prp_small_pool;
120 unsigned online_queues;
122 unsigned io_queues[HCTX_MAX_TYPES];
123 unsigned int num_vecs;
128 unsigned long bar_mapped_size;
129 struct work_struct remove_work;
130 struct mutex shutdown_lock;
136 struct nvme_ctrl ctrl;
139 mempool_t *iod_mempool;
141 /* shadow doorbell buffer support: */
143 dma_addr_t dbbuf_dbs_dma_addr;
145 dma_addr_t dbbuf_eis_dma_addr;
147 /* host memory buffer support: */
149 u32 nr_host_mem_descs;
150 dma_addr_t host_mem_descs_dma;
151 struct nvme_host_mem_buf_desc *host_mem_descs;
152 void **host_mem_desc_bufs;
153 unsigned int nr_allocated_queues;
154 unsigned int nr_write_queues;
155 unsigned int nr_poll_queues;
158 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
163 ret = kstrtou32(val, 10, &n);
164 if (ret != 0 || n < 2)
167 return param_set_uint(val, kp);
170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
172 return qid * 2 * stride;
175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
177 return (qid * 2 + 1) * stride;
180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
182 return container_of(ctrl, struct nvme_dev, ctrl);
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
190 struct nvme_dev *dev;
193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
195 struct nvme_completion *cqes;
196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
208 #define NVMEQ_ENABLED 0
209 #define NVMEQ_SQ_CMB 1
210 #define NVMEQ_DELETE_ERROR 2
211 #define NVMEQ_POLLED 3
216 struct completion delete_done;
220 * The nvme_iod describes the data in an I/O.
222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223 * to the actual struct scatterlist.
226 struct nvme_request req;
227 struct nvme_queue *nvmeq;
230 int npages; /* In the PRP list. 0 means small pool in use */
231 int nents; /* Used in scatterlist */
232 dma_addr_t first_dma;
233 unsigned int dma_len; /* length of single DMA segment mapping */
235 struct scatterlist *sg;
238 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
240 return dev->nr_allocated_queues * 8 * dev->db_stride;
243 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245 unsigned int mem_size = nvme_dbbuf_size(dev);
250 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
251 &dev->dbbuf_dbs_dma_addr,
255 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
256 &dev->dbbuf_eis_dma_addr,
258 if (!dev->dbbuf_eis) {
259 dma_free_coherent(dev->dev, mem_size,
260 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
261 dev->dbbuf_dbs = NULL;
268 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
270 unsigned int mem_size = nvme_dbbuf_size(dev);
272 if (dev->dbbuf_dbs) {
273 dma_free_coherent(dev->dev, mem_size,
274 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
275 dev->dbbuf_dbs = NULL;
277 if (dev->dbbuf_eis) {
278 dma_free_coherent(dev->dev, mem_size,
279 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
280 dev->dbbuf_eis = NULL;
284 static void nvme_dbbuf_init(struct nvme_dev *dev,
285 struct nvme_queue *nvmeq, int qid)
287 if (!dev->dbbuf_dbs || !qid)
290 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
291 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
296 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
301 nvmeq->dbbuf_sq_db = NULL;
302 nvmeq->dbbuf_cq_db = NULL;
303 nvmeq->dbbuf_sq_ei = NULL;
304 nvmeq->dbbuf_cq_ei = NULL;
307 static void nvme_dbbuf_set(struct nvme_dev *dev)
309 struct nvme_command c;
315 memset(&c, 0, sizeof(c));
316 c.dbbuf.opcode = nvme_admin_dbbuf;
317 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
318 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
320 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
321 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
322 /* Free memory and continue on */
323 nvme_dbbuf_dma_free(dev);
325 for (i = 1; i <= dev->online_queues; i++)
326 nvme_dbbuf_free(&dev->queues[i]);
330 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
332 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
335 /* Update dbbuf and return true if an MMIO is required */
336 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
337 volatile u32 *dbbuf_ei)
343 * Ensure that the queue is written before updating
344 * the doorbell in memory
348 old_value = *dbbuf_db;
352 * Ensure that the doorbell is updated before reading the event
353 * index from memory. The controller needs to provide similar
354 * ordering to ensure the envent index is updated before reading
359 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
367 * Will slightly overestimate the number of pages needed. This is OK
368 * as it only leads to a small amount of wasted memory for the lifetime of
371 static int nvme_pci_npages_prp(void)
373 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
374 NVME_CTRL_PAGE_SIZE);
375 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
379 * Calculates the number of pages needed for the SGL segments. For example a 4k
380 * page can accommodate 256 SGL descriptors.
382 static int nvme_pci_npages_sgl(void)
384 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
388 static size_t nvme_pci_iod_alloc_size(void)
390 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
392 return sizeof(__le64 *) * npages +
393 sizeof(struct scatterlist) * NVME_MAX_SEGS;
396 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
397 unsigned int hctx_idx)
399 struct nvme_dev *dev = data;
400 struct nvme_queue *nvmeq = &dev->queues[0];
402 WARN_ON(hctx_idx != 0);
403 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
405 hctx->driver_data = nvmeq;
409 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
410 unsigned int hctx_idx)
412 struct nvme_dev *dev = data;
413 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
415 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
416 hctx->driver_data = nvmeq;
420 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
421 unsigned int hctx_idx, unsigned int numa_node)
423 struct nvme_dev *dev = set->driver_data;
424 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
425 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
426 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
431 nvme_req(req)->ctrl = &dev->ctrl;
435 static int queue_irq_offset(struct nvme_dev *dev)
437 /* if we have more than 1 vec, admin queue offsets us by 1 */
438 if (dev->num_vecs > 1)
444 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
446 struct nvme_dev *dev = set->driver_data;
449 offset = queue_irq_offset(dev);
450 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 struct blk_mq_queue_map *map = &set->map[i];
453 map->nr_queues = dev->io_queues[i];
454 if (!map->nr_queues) {
455 BUG_ON(i == HCTX_TYPE_DEFAULT);
460 * The poll queue(s) doesn't have an IRQ (and hence IRQ
461 * affinity), so use the regular blk-mq cpu mapping
463 map->queue_offset = qoff;
464 if (i != HCTX_TYPE_POLL && offset)
465 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
467 blk_mq_map_queues(map);
468 qoff += map->nr_queues;
469 offset += map->nr_queues;
476 * Write sq tail if we are asked to, or if the next command would wrap.
478 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
481 u16 next_tail = nvmeq->sq_tail + 1;
483 if (next_tail == nvmeq->q_depth)
485 if (next_tail != nvmeq->last_sq_tail)
489 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
490 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
491 writel(nvmeq->sq_tail, nvmeq->q_db);
492 nvmeq->last_sq_tail = nvmeq->sq_tail;
496 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
497 * @nvmeq: The queue to use
498 * @cmd: The command to send
499 * @write_sq: whether to write to the SQ doorbell
501 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
504 spin_lock(&nvmeq->sq_lock);
505 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
507 if (++nvmeq->sq_tail == nvmeq->q_depth)
509 nvme_write_sq_db(nvmeq, write_sq);
510 spin_unlock(&nvmeq->sq_lock);
513 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
515 struct nvme_queue *nvmeq = hctx->driver_data;
517 spin_lock(&nvmeq->sq_lock);
518 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
519 nvme_write_sq_db(nvmeq, true);
520 spin_unlock(&nvmeq->sq_lock);
523 static void **nvme_pci_iod_list(struct request *req)
525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
526 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
529 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
531 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
532 int nseg = blk_rq_nr_phys_segments(req);
533 unsigned int avg_seg_size;
535 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
537 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
539 if (!iod->nvmeq->qid)
541 if (!sgl_threshold || avg_seg_size < sgl_threshold)
546 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
548 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
549 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
550 dma_addr_t dma_addr = iod->first_dma;
553 for (i = 0; i < iod->npages; i++) {
554 __le64 *prp_list = nvme_pci_iod_list(req)[i];
555 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
557 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
558 dma_addr = next_dma_addr;
563 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
565 const int last_sg = SGES_PER_PAGE - 1;
566 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
567 dma_addr_t dma_addr = iod->first_dma;
570 for (i = 0; i < iod->npages; i++) {
571 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
572 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
574 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
575 dma_addr = next_dma_addr;
580 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
584 if (is_pci_p2pdma_page(sg_page(iod->sg)))
585 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
588 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
591 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
593 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
596 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
601 WARN_ON_ONCE(!iod->nents);
603 nvme_unmap_sg(dev, req);
604 if (iod->npages == 0)
605 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
607 else if (iod->use_sgl)
608 nvme_free_sgls(dev, req);
610 nvme_free_prps(dev, req);
611 mempool_free(iod->sg, dev->iod_mempool);
614 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
617 struct scatterlist *sg;
619 for_each_sg(sgl, sg, nents, i) {
620 dma_addr_t phys = sg_phys(sg);
621 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
622 "dma_address:%pad dma_length:%d\n",
623 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
628 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
629 struct request *req, struct nvme_rw_command *cmnd)
631 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
632 struct dma_pool *pool;
633 int length = blk_rq_payload_bytes(req);
634 struct scatterlist *sg = iod->sg;
635 int dma_len = sg_dma_len(sg);
636 u64 dma_addr = sg_dma_address(sg);
637 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
639 void **list = nvme_pci_iod_list(req);
643 length -= (NVME_CTRL_PAGE_SIZE - offset);
649 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
651 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
654 dma_addr = sg_dma_address(sg);
655 dma_len = sg_dma_len(sg);
658 if (length <= NVME_CTRL_PAGE_SIZE) {
659 iod->first_dma = dma_addr;
663 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
664 if (nprps <= (256 / 8)) {
665 pool = dev->prp_small_pool;
668 pool = dev->prp_page_pool;
672 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
674 iod->first_dma = dma_addr;
676 return BLK_STS_RESOURCE;
679 iod->first_dma = prp_dma;
682 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
683 __le64 *old_prp_list = prp_list;
684 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
687 list[iod->npages++] = prp_list;
688 prp_list[0] = old_prp_list[i - 1];
689 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
692 prp_list[i++] = cpu_to_le64(dma_addr);
693 dma_len -= NVME_CTRL_PAGE_SIZE;
694 dma_addr += NVME_CTRL_PAGE_SIZE;
695 length -= NVME_CTRL_PAGE_SIZE;
700 if (unlikely(dma_len < 0))
703 dma_addr = sg_dma_address(sg);
704 dma_len = sg_dma_len(sg);
707 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
708 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
711 nvme_free_prps(dev, req);
712 return BLK_STS_RESOURCE;
714 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
715 "Invalid SGL for payload:%d nents:%d\n",
716 blk_rq_payload_bytes(req), iod->nents);
717 return BLK_STS_IOERR;
720 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
721 struct scatterlist *sg)
723 sge->addr = cpu_to_le64(sg_dma_address(sg));
724 sge->length = cpu_to_le32(sg_dma_len(sg));
725 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
728 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
729 dma_addr_t dma_addr, int entries)
731 sge->addr = cpu_to_le64(dma_addr);
732 if (entries < SGES_PER_PAGE) {
733 sge->length = cpu_to_le32(entries * sizeof(*sge));
734 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
736 sge->length = cpu_to_le32(PAGE_SIZE);
737 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
741 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
742 struct request *req, struct nvme_rw_command *cmd, int entries)
744 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
745 struct dma_pool *pool;
746 struct nvme_sgl_desc *sg_list;
747 struct scatterlist *sg = iod->sg;
751 /* setting the transfer type as SGL */
752 cmd->flags = NVME_CMD_SGL_METABUF;
755 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
759 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
760 pool = dev->prp_small_pool;
763 pool = dev->prp_page_pool;
767 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
770 return BLK_STS_RESOURCE;
773 nvme_pci_iod_list(req)[0] = sg_list;
774 iod->first_dma = sgl_dma;
776 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
779 if (i == SGES_PER_PAGE) {
780 struct nvme_sgl_desc *old_sg_desc = sg_list;
781 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
783 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
788 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
789 sg_list[i++] = *link;
790 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
793 nvme_pci_sgl_set_data(&sg_list[i++], sg);
795 } while (--entries > 0);
799 nvme_free_sgls(dev, req);
800 return BLK_STS_RESOURCE;
803 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
804 struct request *req, struct nvme_rw_command *cmnd,
807 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
808 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
809 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
811 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
812 if (dma_mapping_error(dev->dev, iod->first_dma))
813 return BLK_STS_RESOURCE;
814 iod->dma_len = bv->bv_len;
816 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
817 if (bv->bv_len > first_prp_len)
818 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
822 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
823 struct request *req, struct nvme_rw_command *cmnd,
826 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
828 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
829 if (dma_mapping_error(dev->dev, iod->first_dma))
830 return BLK_STS_RESOURCE;
831 iod->dma_len = bv->bv_len;
833 cmnd->flags = NVME_CMD_SGL_METABUF;
834 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
835 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
836 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
840 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
841 struct nvme_command *cmnd)
843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
844 blk_status_t ret = BLK_STS_RESOURCE;
847 if (blk_rq_nr_phys_segments(req) == 1) {
848 struct bio_vec bv = req_bvec(req);
850 if (!is_pci_p2pdma_page(bv.bv_page)) {
851 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
852 return nvme_setup_prp_simple(dev, req,
855 if (iod->nvmeq->qid &&
856 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
857 return nvme_setup_sgl_simple(dev, req,
863 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
865 return BLK_STS_RESOURCE;
866 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
867 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
871 if (is_pci_p2pdma_page(sg_page(iod->sg)))
872 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
873 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
875 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
876 rq_dma_dir(req), DMA_ATTR_NO_WARN);
880 iod->use_sgl = nvme_pci_use_sgls(dev, req);
882 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
884 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
885 if (ret != BLK_STS_OK)
890 nvme_unmap_sg(dev, req);
892 mempool_free(iod->sg, dev->iod_mempool);
896 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
897 struct nvme_command *cmnd)
899 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
901 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
903 if (dma_mapping_error(dev->dev, iod->meta_dma))
904 return BLK_STS_IOERR;
905 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
910 * NOTE: ns is NULL when called on the admin queue.
912 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
913 const struct blk_mq_queue_data *bd)
915 struct nvme_ns *ns = hctx->queue->queuedata;
916 struct nvme_queue *nvmeq = hctx->driver_data;
917 struct nvme_dev *dev = nvmeq->dev;
918 struct request *req = bd->rq;
919 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
920 struct nvme_command cmnd;
928 * We should not need to do this, but we're still using this to
929 * ensure we can drain requests on a dying queue.
931 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
932 return BLK_STS_IOERR;
934 ret = nvme_setup_cmd(ns, req, &cmnd);
938 if (blk_rq_nr_phys_segments(req)) {
939 ret = nvme_map_data(dev, req, &cmnd);
944 if (blk_integrity_rq(req)) {
945 ret = nvme_map_metadata(dev, req, &cmnd);
950 blk_mq_start_request(req);
951 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
954 nvme_unmap_data(dev, req);
956 nvme_cleanup_cmd(req);
960 static void nvme_pci_complete_rq(struct request *req)
962 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
963 struct nvme_dev *dev = iod->nvmeq->dev;
965 if (blk_integrity_rq(req))
966 dma_unmap_page(dev->dev, iod->meta_dma,
967 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
968 if (blk_rq_nr_phys_segments(req))
969 nvme_unmap_data(dev, req);
970 nvme_complete_rq(req);
973 /* We read the CQE phase first to check if the rest of the entry is valid */
974 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
976 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
978 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
981 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
983 u16 head = nvmeq->cq_head;
985 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
987 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
990 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
993 return nvmeq->dev->admin_tagset.tags[0];
994 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
997 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
999 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1000 __u16 command_id = READ_ONCE(cqe->command_id);
1001 struct request *req;
1004 * AEN requests are special as they don't time out and can
1005 * survive any kind of queue freeze and often don't respond to
1006 * aborts. We don't even bother to allocate a struct request
1007 * for them but rather special case them here.
1009 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1010 nvme_complete_async_event(&nvmeq->dev->ctrl,
1011 cqe->status, &cqe->result);
1015 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
1016 if (unlikely(!req)) {
1017 dev_warn(nvmeq->dev->ctrl.device,
1018 "invalid id %d completed on queue %d\n",
1019 command_id, le16_to_cpu(cqe->sq_id));
1023 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1024 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1025 nvme_pci_complete_rq(req);
1028 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1030 u16 tmp = nvmeq->cq_head + 1;
1032 if (tmp == nvmeq->q_depth) {
1034 nvmeq->cq_phase ^= 1;
1036 nvmeq->cq_head = tmp;
1040 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1044 while (nvme_cqe_pending(nvmeq)) {
1047 * load-load control dependency between phase and the rest of
1048 * the cqe requires a full read memory barrier
1051 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1052 nvme_update_cq_head(nvmeq);
1056 nvme_ring_cq_doorbell(nvmeq);
1060 static irqreturn_t nvme_irq(int irq, void *data)
1062 struct nvme_queue *nvmeq = data;
1063 irqreturn_t ret = IRQ_NONE;
1066 * The rmb/wmb pair ensures we see all updates from a previous run of
1067 * the irq handler, even if that was on another CPU.
1070 if (nvme_process_cq(nvmeq))
1077 static irqreturn_t nvme_irq_check(int irq, void *data)
1079 struct nvme_queue *nvmeq = data;
1081 if (nvme_cqe_pending(nvmeq))
1082 return IRQ_WAKE_THREAD;
1087 * Poll for completions for any interrupt driven queue
1088 * Can be called from any context.
1090 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1092 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1094 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1096 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1097 nvme_process_cq(nvmeq);
1098 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1101 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1103 struct nvme_queue *nvmeq = hctx->driver_data;
1106 if (!nvme_cqe_pending(nvmeq))
1109 spin_lock(&nvmeq->cq_poll_lock);
1110 found = nvme_process_cq(nvmeq);
1111 spin_unlock(&nvmeq->cq_poll_lock);
1116 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1118 struct nvme_dev *dev = to_nvme_dev(ctrl);
1119 struct nvme_queue *nvmeq = &dev->queues[0];
1120 struct nvme_command c;
1122 memset(&c, 0, sizeof(c));
1123 c.common.opcode = nvme_admin_async_event;
1124 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1125 nvme_submit_cmd(nvmeq, &c, true);
1128 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1130 struct nvme_command c;
1132 memset(&c, 0, sizeof(c));
1133 c.delete_queue.opcode = opcode;
1134 c.delete_queue.qid = cpu_to_le16(id);
1136 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1139 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1140 struct nvme_queue *nvmeq, s16 vector)
1142 struct nvme_command c;
1143 int flags = NVME_QUEUE_PHYS_CONTIG;
1145 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1146 flags |= NVME_CQ_IRQ_ENABLED;
1149 * Note: we (ab)use the fact that the prp fields survive if no data
1150 * is attached to the request.
1152 memset(&c, 0, sizeof(c));
1153 c.create_cq.opcode = nvme_admin_create_cq;
1154 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1155 c.create_cq.cqid = cpu_to_le16(qid);
1156 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1157 c.create_cq.cq_flags = cpu_to_le16(flags);
1158 c.create_cq.irq_vector = cpu_to_le16(vector);
1160 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1163 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1164 struct nvme_queue *nvmeq)
1166 struct nvme_ctrl *ctrl = &dev->ctrl;
1167 struct nvme_command c;
1168 int flags = NVME_QUEUE_PHYS_CONTIG;
1171 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1172 * set. Since URGENT priority is zeroes, it makes all queues
1175 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1176 flags |= NVME_SQ_PRIO_MEDIUM;
1179 * Note: we (ab)use the fact that the prp fields survive if no data
1180 * is attached to the request.
1182 memset(&c, 0, sizeof(c));
1183 c.create_sq.opcode = nvme_admin_create_sq;
1184 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1185 c.create_sq.sqid = cpu_to_le16(qid);
1186 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1187 c.create_sq.sq_flags = cpu_to_le16(flags);
1188 c.create_sq.cqid = cpu_to_le16(qid);
1190 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1193 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1195 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1198 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1200 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1203 static void abort_endio(struct request *req, blk_status_t error)
1205 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1206 struct nvme_queue *nvmeq = iod->nvmeq;
1208 dev_warn(nvmeq->dev->ctrl.device,
1209 "Abort status: 0x%x", nvme_req(req)->status);
1210 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1211 blk_mq_free_request(req);
1214 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1216 /* If true, indicates loss of adapter communication, possibly by a
1217 * NVMe Subsystem reset.
1219 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1221 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1222 switch (dev->ctrl.state) {
1223 case NVME_CTRL_RESETTING:
1224 case NVME_CTRL_CONNECTING:
1230 /* We shouldn't reset unless the controller is on fatal error state
1231 * _or_ if we lost the communication with it.
1233 if (!(csts & NVME_CSTS_CFS) && !nssro)
1239 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1241 /* Read a config register to help see what died. */
1245 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1247 if (result == PCIBIOS_SUCCESSFUL)
1248 dev_warn(dev->ctrl.device,
1249 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1252 dev_warn(dev->ctrl.device,
1253 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1257 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1259 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1260 struct nvme_queue *nvmeq = iod->nvmeq;
1261 struct nvme_dev *dev = nvmeq->dev;
1262 struct request *abort_req;
1263 struct nvme_command cmd;
1264 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1266 /* If PCI error recovery process is happening, we cannot reset or
1267 * the recovery mechanism will surely fail.
1270 if (pci_channel_offline(to_pci_dev(dev->dev)))
1271 return BLK_EH_RESET_TIMER;
1274 * Reset immediately if the controller is failed
1276 if (nvme_should_reset(dev, csts)) {
1277 nvme_warn_reset(dev, csts);
1278 nvme_dev_disable(dev, false);
1279 nvme_reset_ctrl(&dev->ctrl);
1284 * Did we miss an interrupt?
1286 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1287 nvme_poll(req->mq_hctx);
1289 nvme_poll_irqdisable(nvmeq);
1291 if (blk_mq_request_completed(req)) {
1292 dev_warn(dev->ctrl.device,
1293 "I/O %d QID %d timeout, completion polled\n",
1294 req->tag, nvmeq->qid);
1299 * Shutdown immediately if controller times out while starting. The
1300 * reset work will see the pci device disabled when it gets the forced
1301 * cancellation error. All outstanding requests are completed on
1302 * shutdown, so we return BLK_EH_DONE.
1304 switch (dev->ctrl.state) {
1305 case NVME_CTRL_CONNECTING:
1306 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1308 case NVME_CTRL_DELETING:
1309 dev_warn_ratelimited(dev->ctrl.device,
1310 "I/O %d QID %d timeout, disable controller\n",
1311 req->tag, nvmeq->qid);
1312 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1313 nvme_dev_disable(dev, true);
1315 case NVME_CTRL_RESETTING:
1316 return BLK_EH_RESET_TIMER;
1322 * Shutdown the controller immediately and schedule a reset if the
1323 * command was already aborted once before and still hasn't been
1324 * returned to the driver, or if this is the admin queue.
1326 if (!nvmeq->qid || iod->aborted) {
1327 dev_warn(dev->ctrl.device,
1328 "I/O %d QID %d timeout, reset controller\n",
1329 req->tag, nvmeq->qid);
1330 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1331 nvme_dev_disable(dev, false);
1332 nvme_reset_ctrl(&dev->ctrl);
1337 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1338 atomic_inc(&dev->ctrl.abort_limit);
1339 return BLK_EH_RESET_TIMER;
1343 memset(&cmd, 0, sizeof(cmd));
1344 cmd.abort.opcode = nvme_admin_abort_cmd;
1345 cmd.abort.cid = req->tag;
1346 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1348 dev_warn(nvmeq->dev->ctrl.device,
1349 "I/O %d QID %d timeout, aborting\n",
1350 req->tag, nvmeq->qid);
1352 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1354 if (IS_ERR(abort_req)) {
1355 atomic_inc(&dev->ctrl.abort_limit);
1356 return BLK_EH_RESET_TIMER;
1359 abort_req->end_io_data = NULL;
1360 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
1363 * The aborted req will be completed on receiving the abort req.
1364 * We enable the timer again. If hit twice, it'll cause a device reset,
1365 * as the device then is in a faulty state.
1367 return BLK_EH_RESET_TIMER;
1370 static void nvme_free_queue(struct nvme_queue *nvmeq)
1372 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1373 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1374 if (!nvmeq->sq_cmds)
1377 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1378 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1379 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1381 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1382 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1386 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1390 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1391 dev->ctrl.queue_count--;
1392 nvme_free_queue(&dev->queues[i]);
1397 * nvme_suspend_queue - put queue into suspended state
1398 * @nvmeq: queue to suspend
1400 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1402 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1405 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1408 nvmeq->dev->online_queues--;
1409 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1410 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1411 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1412 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1416 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1420 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1421 nvme_suspend_queue(&dev->queues[i]);
1424 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1426 struct nvme_queue *nvmeq = &dev->queues[0];
1429 nvme_shutdown_ctrl(&dev->ctrl);
1431 nvme_disable_ctrl(&dev->ctrl);
1433 nvme_poll_irqdisable(nvmeq);
1437 * Called only on a device that has been disabled and after all other threads
1438 * that can check this device's completion queues have synced, except
1439 * nvme_poll(). This is the last chance for the driver to see a natural
1440 * completion before nvme_cancel_request() terminates all incomplete requests.
1442 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1446 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1447 spin_lock(&dev->queues[i].cq_poll_lock);
1448 nvme_process_cq(&dev->queues[i]);
1449 spin_unlock(&dev->queues[i].cq_poll_lock);
1453 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1456 int q_depth = dev->q_depth;
1457 unsigned q_size_aligned = roundup(q_depth * entry_size,
1458 NVME_CTRL_PAGE_SIZE);
1460 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1461 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1463 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1464 q_depth = div_u64(mem_per_q, entry_size);
1467 * Ensure the reduced q_depth is above some threshold where it
1468 * would be better to map queues in system memory with the
1478 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1481 struct pci_dev *pdev = to_pci_dev(dev->dev);
1483 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1484 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1485 if (nvmeq->sq_cmds) {
1486 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1488 if (nvmeq->sq_dma_addr) {
1489 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1493 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1497 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1498 &nvmeq->sq_dma_addr, GFP_KERNEL);
1499 if (!nvmeq->sq_cmds)
1504 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1506 struct nvme_queue *nvmeq = &dev->queues[qid];
1508 if (dev->ctrl.queue_count > qid)
1511 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1512 nvmeq->q_depth = depth;
1513 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1514 &nvmeq->cq_dma_addr, GFP_KERNEL);
1518 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1522 spin_lock_init(&nvmeq->sq_lock);
1523 spin_lock_init(&nvmeq->cq_poll_lock);
1525 nvmeq->cq_phase = 1;
1526 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1528 dev->ctrl.queue_count++;
1533 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1534 nvmeq->cq_dma_addr);
1539 static int queue_request_irq(struct nvme_queue *nvmeq)
1541 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1542 int nr = nvmeq->dev->ctrl.instance;
1544 if (use_threaded_interrupts) {
1545 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1546 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1548 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1549 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1553 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1555 struct nvme_dev *dev = nvmeq->dev;
1558 nvmeq->last_sq_tail = 0;
1560 nvmeq->cq_phase = 1;
1561 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1562 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1563 nvme_dbbuf_init(dev, nvmeq, qid);
1564 dev->online_queues++;
1565 wmb(); /* ensure the first interrupt sees the initialization */
1568 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1570 struct nvme_dev *dev = nvmeq->dev;
1574 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1577 * A queue's vector matches the queue identifier unless the controller
1578 * has only one vector available.
1581 vector = dev->num_vecs == 1 ? 0 : qid;
1583 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1585 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1589 result = adapter_alloc_sq(dev, qid, nvmeq);
1595 nvmeq->cq_vector = vector;
1596 nvme_init_queue(nvmeq, qid);
1599 result = queue_request_irq(nvmeq);
1604 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1608 dev->online_queues--;
1609 adapter_delete_sq(dev, qid);
1611 adapter_delete_cq(dev, qid);
1615 static const struct blk_mq_ops nvme_mq_admin_ops = {
1616 .queue_rq = nvme_queue_rq,
1617 .complete = nvme_pci_complete_rq,
1618 .init_hctx = nvme_admin_init_hctx,
1619 .init_request = nvme_init_request,
1620 .timeout = nvme_timeout,
1623 static const struct blk_mq_ops nvme_mq_ops = {
1624 .queue_rq = nvme_queue_rq,
1625 .complete = nvme_pci_complete_rq,
1626 .commit_rqs = nvme_commit_rqs,
1627 .init_hctx = nvme_init_hctx,
1628 .init_request = nvme_init_request,
1629 .map_queues = nvme_pci_map_queues,
1630 .timeout = nvme_timeout,
1634 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1636 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1638 * If the controller was reset during removal, it's possible
1639 * user requests may be waiting on a stopped queue. Start the
1640 * queue to flush these to completion.
1642 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1643 blk_cleanup_queue(dev->ctrl.admin_q);
1644 blk_mq_free_tag_set(&dev->admin_tagset);
1648 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1650 if (!dev->ctrl.admin_q) {
1651 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1652 dev->admin_tagset.nr_hw_queues = 1;
1654 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1655 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1656 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1657 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1658 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1659 dev->admin_tagset.driver_data = dev;
1661 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1663 dev->ctrl.admin_tagset = &dev->admin_tagset;
1665 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1666 if (IS_ERR(dev->ctrl.admin_q)) {
1667 blk_mq_free_tag_set(&dev->admin_tagset);
1670 if (!blk_get_queue(dev->ctrl.admin_q)) {
1671 nvme_dev_remove_admin(dev);
1672 dev->ctrl.admin_q = NULL;
1676 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1681 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1683 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1686 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1688 struct pci_dev *pdev = to_pci_dev(dev->dev);
1690 if (size <= dev->bar_mapped_size)
1692 if (size > pci_resource_len(pdev, 0))
1696 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1698 dev->bar_mapped_size = 0;
1701 dev->bar_mapped_size = size;
1702 dev->dbs = dev->bar + NVME_REG_DBS;
1707 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1711 struct nvme_queue *nvmeq;
1713 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1717 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1718 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1720 if (dev->subsystem &&
1721 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1722 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1724 result = nvme_disable_ctrl(&dev->ctrl);
1728 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1732 dev->ctrl.numa_node = dev_to_node(dev->dev);
1734 nvmeq = &dev->queues[0];
1735 aqa = nvmeq->q_depth - 1;
1738 writel(aqa, dev->bar + NVME_REG_AQA);
1739 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1740 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1742 result = nvme_enable_ctrl(&dev->ctrl);
1746 nvmeq->cq_vector = 0;
1747 nvme_init_queue(nvmeq, 0);
1748 result = queue_request_irq(nvmeq);
1750 dev->online_queues--;
1754 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1758 static int nvme_create_io_queues(struct nvme_dev *dev)
1760 unsigned i, max, rw_queues;
1763 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1764 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1770 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1771 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1772 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1773 dev->io_queues[HCTX_TYPE_READ];
1778 for (i = dev->online_queues; i <= max; i++) {
1779 bool polled = i > rw_queues;
1781 ret = nvme_create_queue(&dev->queues[i], i, polled);
1787 * Ignore failing Create SQ/CQ commands, we can continue with less
1788 * than the desired amount of queues, and even a controller without
1789 * I/O queues can still be used to issue admin commands. This might
1790 * be useful to upgrade a buggy firmware for example.
1792 return ret >= 0 ? 0 : ret;
1795 static ssize_t nvme_cmb_show(struct device *dev,
1796 struct device_attribute *attr,
1799 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1801 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1802 ndev->cmbloc, ndev->cmbsz);
1804 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1806 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1808 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1810 return 1ULL << (12 + 4 * szu);
1813 static u32 nvme_cmb_size(struct nvme_dev *dev)
1815 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1818 static void nvme_map_cmb(struct nvme_dev *dev)
1821 resource_size_t bar_size;
1822 struct pci_dev *pdev = to_pci_dev(dev->dev);
1828 if (NVME_CAP_CMBS(dev->ctrl.cap))
1829 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1831 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1834 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1836 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1837 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1838 bar = NVME_CMB_BIR(dev->cmbloc);
1839 bar_size = pci_resource_len(pdev, bar);
1841 if (offset > bar_size)
1845 * Tell the controller about the host side address mapping the CMB,
1846 * and enable CMB decoding for the NVMe 1.4+ scheme:
1848 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1849 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1850 (pci_bus_address(pdev, bar) + offset),
1851 dev->bar + NVME_REG_CMBMSC);
1855 * Controllers may support a CMB size larger than their BAR,
1856 * for example, due to being behind a bridge. Reduce the CMB to
1857 * the reported size of the BAR
1859 if (size > bar_size - offset)
1860 size = bar_size - offset;
1862 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1863 dev_warn(dev->ctrl.device,
1864 "failed to register the CMB\n");
1868 dev->cmb_size = size;
1869 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1871 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1872 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1873 pci_p2pmem_publish(pdev, true);
1875 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1876 &dev_attr_cmb.attr, NULL))
1877 dev_warn(dev->ctrl.device,
1878 "failed to add sysfs attribute for CMB\n");
1881 static inline void nvme_release_cmb(struct nvme_dev *dev)
1883 if (dev->cmb_size) {
1884 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1885 &dev_attr_cmb.attr, NULL);
1890 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1892 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1893 u64 dma_addr = dev->host_mem_descs_dma;
1894 struct nvme_command c;
1897 memset(&c, 0, sizeof(c));
1898 c.features.opcode = nvme_admin_set_features;
1899 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1900 c.features.dword11 = cpu_to_le32(bits);
1901 c.features.dword12 = cpu_to_le32(host_mem_size);
1902 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1903 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1904 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1906 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1908 dev_warn(dev->ctrl.device,
1909 "failed to set host mem (err %d, flags %#x).\n",
1915 static void nvme_free_host_mem(struct nvme_dev *dev)
1919 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1920 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1921 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1923 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1924 le64_to_cpu(desc->addr),
1925 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1928 kfree(dev->host_mem_desc_bufs);
1929 dev->host_mem_desc_bufs = NULL;
1930 dma_free_coherent(dev->dev,
1931 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1932 dev->host_mem_descs, dev->host_mem_descs_dma);
1933 dev->host_mem_descs = NULL;
1934 dev->nr_host_mem_descs = 0;
1937 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1940 struct nvme_host_mem_buf_desc *descs;
1941 u32 max_entries, len;
1942 dma_addr_t descs_dma;
1947 tmp = (preferred + chunk_size - 1);
1948 do_div(tmp, chunk_size);
1951 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1952 max_entries = dev->ctrl.hmmaxd;
1954 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1955 &descs_dma, GFP_KERNEL);
1959 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1961 goto out_free_descs;
1963 for (size = 0; size < preferred && i < max_entries; size += len) {
1964 dma_addr_t dma_addr;
1966 len = min_t(u64, chunk_size, preferred - size);
1967 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1968 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1972 descs[i].addr = cpu_to_le64(dma_addr);
1973 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1980 dev->nr_host_mem_descs = i;
1981 dev->host_mem_size = size;
1982 dev->host_mem_descs = descs;
1983 dev->host_mem_descs_dma = descs_dma;
1984 dev->host_mem_desc_bufs = bufs;
1989 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1991 dma_free_attrs(dev->dev, size, bufs[i],
1992 le64_to_cpu(descs[i].addr),
1993 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1998 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2001 dev->host_mem_descs = NULL;
2005 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2007 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2008 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2011 /* start big and work our way down */
2012 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2013 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2014 if (!min || dev->host_mem_size >= min)
2016 nvme_free_host_mem(dev);
2023 static int nvme_setup_host_mem(struct nvme_dev *dev)
2025 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2026 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2027 u64 min = (u64)dev->ctrl.hmmin * 4096;
2028 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2031 preferred = min(preferred, max);
2033 dev_warn(dev->ctrl.device,
2034 "min host memory (%lld MiB) above limit (%d MiB).\n",
2035 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2036 nvme_free_host_mem(dev);
2041 * If we already have a buffer allocated check if we can reuse it.
2043 if (dev->host_mem_descs) {
2044 if (dev->host_mem_size >= min)
2045 enable_bits |= NVME_HOST_MEM_RETURN;
2047 nvme_free_host_mem(dev);
2050 if (!dev->host_mem_descs) {
2051 if (nvme_alloc_host_mem(dev, min, preferred)) {
2052 dev_warn(dev->ctrl.device,
2053 "failed to allocate host memory buffer.\n");
2054 return 0; /* controller must work without HMB */
2057 dev_info(dev->ctrl.device,
2058 "allocated %lld MiB host memory buffer.\n",
2059 dev->host_mem_size >> ilog2(SZ_1M));
2062 ret = nvme_set_host_mem(dev, enable_bits);
2064 nvme_free_host_mem(dev);
2069 * nirqs is the number of interrupts available for write and read
2070 * queues. The core already reserved an interrupt for the admin queue.
2072 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2074 struct nvme_dev *dev = affd->priv;
2075 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2078 * If there is no interrupt available for queues, ensure that
2079 * the default queue is set to 1. The affinity set size is
2080 * also set to one, but the irq core ignores it for this case.
2082 * If only one interrupt is available or 'write_queue' == 0, combine
2083 * write and read queues.
2085 * If 'write_queues' > 0, ensure it leaves room for at least one read
2091 } else if (nrirqs == 1 || !nr_write_queues) {
2093 } else if (nr_write_queues >= nrirqs) {
2096 nr_read_queues = nrirqs - nr_write_queues;
2099 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2100 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2101 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2102 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2103 affd->nr_sets = nr_read_queues ? 2 : 1;
2106 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2108 struct pci_dev *pdev = to_pci_dev(dev->dev);
2109 struct irq_affinity affd = {
2111 .calc_sets = nvme_calc_irq_sets,
2114 unsigned int irq_queues, poll_queues;
2117 * Poll queues don't need interrupts, but we need at least one I/O queue
2118 * left over for non-polled I/O.
2120 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2121 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2124 * Initialize for the single interrupt case, will be updated in
2125 * nvme_calc_irq_sets().
2127 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2128 dev->io_queues[HCTX_TYPE_READ] = 0;
2131 * We need interrupts for the admin queue and each non-polled I/O queue,
2132 * but some Apple controllers require all queues to use the first
2136 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2137 irq_queues += (nr_io_queues - poll_queues);
2138 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2139 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2142 static void nvme_disable_io_queues(struct nvme_dev *dev)
2144 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2145 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2148 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2151 * If tags are shared with admin queue (Apple bug), then
2152 * make sure we only use one IO queue.
2154 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2156 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2159 static int nvme_setup_io_queues(struct nvme_dev *dev)
2161 struct nvme_queue *adminq = &dev->queues[0];
2162 struct pci_dev *pdev = to_pci_dev(dev->dev);
2163 unsigned int nr_io_queues;
2168 * Sample the module parameters once at reset time so that we have
2169 * stable values to work with.
2171 dev->nr_write_queues = write_queues;
2172 dev->nr_poll_queues = poll_queues;
2174 nr_io_queues = dev->nr_allocated_queues - 1;
2175 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2179 if (nr_io_queues == 0)
2182 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2184 if (dev->cmb_use_sqes) {
2185 result = nvme_cmb_qdepth(dev, nr_io_queues,
2186 sizeof(struct nvme_command));
2188 dev->q_depth = result;
2190 dev->cmb_use_sqes = false;
2194 size = db_bar_size(dev, nr_io_queues);
2195 result = nvme_remap_bar(dev, size);
2198 if (!--nr_io_queues)
2201 adminq->q_db = dev->dbs;
2204 /* Deregister the admin queue's interrupt */
2205 pci_free_irq(pdev, 0, adminq);
2208 * If we enable msix early due to not intx, disable it again before
2209 * setting up the full range we need.
2211 pci_free_irq_vectors(pdev);
2213 result = nvme_setup_irqs(dev, nr_io_queues);
2217 dev->num_vecs = result;
2218 result = max(result - 1, 1);
2219 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2222 * Should investigate if there's a performance win from allocating
2223 * more queues than interrupt vectors; it might allow the submission
2224 * path to scale better, even if the receive path is limited by the
2225 * number of interrupts.
2227 result = queue_request_irq(adminq);
2230 set_bit(NVMEQ_ENABLED, &adminq->flags);
2232 result = nvme_create_io_queues(dev);
2233 if (result || dev->online_queues < 2)
2236 if (dev->online_queues - 1 < dev->max_qid) {
2237 nr_io_queues = dev->online_queues - 1;
2238 nvme_disable_io_queues(dev);
2239 nvme_suspend_io_queues(dev);
2242 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2243 dev->io_queues[HCTX_TYPE_DEFAULT],
2244 dev->io_queues[HCTX_TYPE_READ],
2245 dev->io_queues[HCTX_TYPE_POLL]);
2249 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2251 struct nvme_queue *nvmeq = req->end_io_data;
2253 blk_mq_free_request(req);
2254 complete(&nvmeq->delete_done);
2257 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2259 struct nvme_queue *nvmeq = req->end_io_data;
2262 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2264 nvme_del_queue_end(req, error);
2267 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2269 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2270 struct request *req;
2271 struct nvme_command cmd;
2273 memset(&cmd, 0, sizeof(cmd));
2274 cmd.delete_queue.opcode = opcode;
2275 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2277 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2279 return PTR_ERR(req);
2281 req->end_io_data = nvmeq;
2283 init_completion(&nvmeq->delete_done);
2284 blk_execute_rq_nowait(NULL, req, false,
2285 opcode == nvme_admin_delete_cq ?
2286 nvme_del_cq_end : nvme_del_queue_end);
2290 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2292 int nr_queues = dev->online_queues - 1, sent = 0;
2293 unsigned long timeout;
2296 timeout = NVME_ADMIN_TIMEOUT;
2297 while (nr_queues > 0) {
2298 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2304 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2306 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2318 static void nvme_dev_add(struct nvme_dev *dev)
2322 if (!dev->ctrl.tagset) {
2323 dev->tagset.ops = &nvme_mq_ops;
2324 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2325 dev->tagset.nr_maps = 2; /* default + read */
2326 if (dev->io_queues[HCTX_TYPE_POLL])
2327 dev->tagset.nr_maps++;
2328 dev->tagset.timeout = NVME_IO_TIMEOUT;
2329 dev->tagset.numa_node = dev->ctrl.numa_node;
2330 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2331 BLK_MQ_MAX_DEPTH) - 1;
2332 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2333 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2334 dev->tagset.driver_data = dev;
2337 * Some Apple controllers requires tags to be unique
2338 * across admin and IO queue, so reserve the first 32
2339 * tags of the IO queue.
2341 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2342 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2344 ret = blk_mq_alloc_tag_set(&dev->tagset);
2346 dev_warn(dev->ctrl.device,
2347 "IO queues tagset allocation failed %d\n", ret);
2350 dev->ctrl.tagset = &dev->tagset;
2352 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2354 /* Free previously allocated queues that are no longer usable */
2355 nvme_free_queues(dev, dev->online_queues);
2358 nvme_dbbuf_set(dev);
2361 static int nvme_pci_enable(struct nvme_dev *dev)
2363 int result = -ENOMEM;
2364 struct pci_dev *pdev = to_pci_dev(dev->dev);
2365 int dma_address_bits = 64;
2367 if (pci_enable_device_mem(pdev))
2370 pci_set_master(pdev);
2372 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2373 dma_address_bits = 48;
2374 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2377 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2383 * Some devices and/or platforms don't advertise or work with INTx
2384 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2385 * adjust this later.
2387 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2391 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2393 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2395 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2396 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2397 dev->dbs = dev->bar + 4096;
2400 * Some Apple controllers require a non-standard SQE size.
2401 * Interestingly they also seem to ignore the CC:IOSQES register
2402 * so we don't bother updating it here.
2404 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2407 dev->io_sqes = NVME_NVM_IOSQES;
2410 * Temporary fix for the Apple controller found in the MacBook8,1 and
2411 * some MacBook7,1 to avoid controller resets and data loss.
2413 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2415 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2416 "set queue depth=%u to work around controller resets\n",
2418 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2419 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2420 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2422 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2423 "set queue depth=%u\n", dev->q_depth);
2427 * Controllers with the shared tags quirk need the IO queue to be
2428 * big enough so that we get 32 tags for the admin queue
2430 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2431 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2432 dev->q_depth = NVME_AQ_DEPTH + 2;
2433 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2440 pci_enable_pcie_error_reporting(pdev);
2441 pci_save_state(pdev);
2445 pci_disable_device(pdev);
2449 static void nvme_dev_unmap(struct nvme_dev *dev)
2453 pci_release_mem_regions(to_pci_dev(dev->dev));
2456 static void nvme_pci_disable(struct nvme_dev *dev)
2458 struct pci_dev *pdev = to_pci_dev(dev->dev);
2460 pci_free_irq_vectors(pdev);
2462 if (pci_is_enabled(pdev)) {
2463 pci_disable_pcie_error_reporting(pdev);
2464 pci_disable_device(pdev);
2468 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2470 bool dead = true, freeze = false;
2471 struct pci_dev *pdev = to_pci_dev(dev->dev);
2473 mutex_lock(&dev->shutdown_lock);
2474 if (pci_is_enabled(pdev)) {
2475 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2477 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2478 dev->ctrl.state == NVME_CTRL_RESETTING) {
2480 nvme_start_freeze(&dev->ctrl);
2482 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2483 pdev->error_state != pci_channel_io_normal);
2487 * Give the controller a chance to complete all entered requests if
2488 * doing a safe shutdown.
2490 if (!dead && shutdown && freeze)
2491 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2493 nvme_stop_queues(&dev->ctrl);
2495 if (!dead && dev->ctrl.queue_count > 0) {
2496 nvme_disable_io_queues(dev);
2497 nvme_disable_admin_queue(dev, shutdown);
2499 nvme_suspend_io_queues(dev);
2500 nvme_suspend_queue(&dev->queues[0]);
2501 nvme_pci_disable(dev);
2502 nvme_reap_pending_cqes(dev);
2504 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2505 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2506 blk_mq_tagset_wait_completed_request(&dev->tagset);
2507 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2510 * The driver will not be starting up queues again if shutting down so
2511 * must flush all entered requests to their failed completion to avoid
2512 * deadlocking blk-mq hot-cpu notifier.
2515 nvme_start_queues(&dev->ctrl);
2516 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2517 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2519 mutex_unlock(&dev->shutdown_lock);
2522 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2524 if (!nvme_wait_reset(&dev->ctrl))
2526 nvme_dev_disable(dev, shutdown);
2530 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2532 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2533 NVME_CTRL_PAGE_SIZE,
2534 NVME_CTRL_PAGE_SIZE, 0);
2535 if (!dev->prp_page_pool)
2538 /* Optimisation for I/Os between 4k and 128k */
2539 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2541 if (!dev->prp_small_pool) {
2542 dma_pool_destroy(dev->prp_page_pool);
2548 static void nvme_release_prp_pools(struct nvme_dev *dev)
2550 dma_pool_destroy(dev->prp_page_pool);
2551 dma_pool_destroy(dev->prp_small_pool);
2554 static void nvme_free_tagset(struct nvme_dev *dev)
2556 if (dev->tagset.tags)
2557 blk_mq_free_tag_set(&dev->tagset);
2558 dev->ctrl.tagset = NULL;
2561 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2563 struct nvme_dev *dev = to_nvme_dev(ctrl);
2565 nvme_dbbuf_dma_free(dev);
2566 nvme_free_tagset(dev);
2567 if (dev->ctrl.admin_q)
2568 blk_put_queue(dev->ctrl.admin_q);
2569 free_opal_dev(dev->ctrl.opal_dev);
2570 mempool_destroy(dev->iod_mempool);
2571 put_device(dev->dev);
2576 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2579 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2580 * may be holding this pci_dev's device lock.
2582 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2583 nvme_get_ctrl(&dev->ctrl);
2584 nvme_dev_disable(dev, false);
2585 nvme_kill_queues(&dev->ctrl);
2586 if (!queue_work(nvme_wq, &dev->remove_work))
2587 nvme_put_ctrl(&dev->ctrl);
2590 static void nvme_reset_work(struct work_struct *work)
2592 struct nvme_dev *dev =
2593 container_of(work, struct nvme_dev, ctrl.reset_work);
2594 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2597 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2603 * If we're called to reset a live controller first shut it down before
2606 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2607 nvme_dev_disable(dev, false);
2608 nvme_sync_queues(&dev->ctrl);
2610 mutex_lock(&dev->shutdown_lock);
2611 result = nvme_pci_enable(dev);
2615 result = nvme_pci_configure_admin_queue(dev);
2619 result = nvme_alloc_admin_tags(dev);
2624 * Limit the max command size to prevent iod->sg allocations going
2625 * over a single page.
2627 dev->ctrl.max_hw_sectors = min_t(u32,
2628 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2629 dev->ctrl.max_segments = NVME_MAX_SEGS;
2632 * Don't limit the IOMMU merged segment size.
2634 dma_set_max_seg_size(dev->dev, 0xffffffff);
2635 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2637 mutex_unlock(&dev->shutdown_lock);
2640 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2641 * initializing procedure here.
2643 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2644 dev_warn(dev->ctrl.device,
2645 "failed to mark controller CONNECTING\n");
2651 * We do not support an SGL for metadata (yet), so we are limited to a
2652 * single integrity segment for the separate metadata pointer.
2654 dev->ctrl.max_integrity_segments = 1;
2656 result = nvme_init_identify(&dev->ctrl);
2660 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2661 if (!dev->ctrl.opal_dev)
2662 dev->ctrl.opal_dev =
2663 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2664 else if (was_suspend)
2665 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2667 free_opal_dev(dev->ctrl.opal_dev);
2668 dev->ctrl.opal_dev = NULL;
2671 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2672 result = nvme_dbbuf_dma_alloc(dev);
2675 "unable to allocate dma for dbbuf\n");
2678 if (dev->ctrl.hmpre) {
2679 result = nvme_setup_host_mem(dev);
2684 result = nvme_setup_io_queues(dev);
2689 * Keep the controller around but remove all namespaces if we don't have
2690 * any working I/O queue.
2692 if (dev->online_queues < 2) {
2693 dev_warn(dev->ctrl.device, "IO queues not created\n");
2694 nvme_kill_queues(&dev->ctrl);
2695 nvme_remove_namespaces(&dev->ctrl);
2696 nvme_free_tagset(dev);
2698 nvme_start_queues(&dev->ctrl);
2699 nvme_wait_freeze(&dev->ctrl);
2701 nvme_unfreeze(&dev->ctrl);
2705 * If only admin queue live, keep it to do further investigation or
2708 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2709 dev_warn(dev->ctrl.device,
2710 "failed to mark controller live state\n");
2715 nvme_start_ctrl(&dev->ctrl);
2719 mutex_unlock(&dev->shutdown_lock);
2722 dev_warn(dev->ctrl.device,
2723 "Removing after probe failure status: %d\n", result);
2724 nvme_remove_dead_ctrl(dev);
2727 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2729 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2730 struct pci_dev *pdev = to_pci_dev(dev->dev);
2732 if (pci_get_drvdata(pdev))
2733 device_release_driver(&pdev->dev);
2734 nvme_put_ctrl(&dev->ctrl);
2737 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2739 *val = readl(to_nvme_dev(ctrl)->bar + off);
2743 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2745 writel(val, to_nvme_dev(ctrl)->bar + off);
2749 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2751 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2755 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2757 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2759 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2762 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2764 .module = THIS_MODULE,
2765 .flags = NVME_F_METADATA_SUPPORTED |
2767 .reg_read32 = nvme_pci_reg_read32,
2768 .reg_write32 = nvme_pci_reg_write32,
2769 .reg_read64 = nvme_pci_reg_read64,
2770 .free_ctrl = nvme_pci_free_ctrl,
2771 .submit_async_event = nvme_pci_submit_async_event,
2772 .get_address = nvme_pci_get_address,
2775 static int nvme_dev_map(struct nvme_dev *dev)
2777 struct pci_dev *pdev = to_pci_dev(dev->dev);
2779 if (pci_request_mem_regions(pdev, "nvme"))
2782 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2787 pci_release_mem_regions(pdev);
2791 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2793 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2795 * Several Samsung devices seem to drop off the PCIe bus
2796 * randomly when APST is on and uses the deepest sleep state.
2797 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2798 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2799 * 950 PRO 256GB", but it seems to be restricted to two Dell
2802 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2803 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2804 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2805 return NVME_QUIRK_NO_DEEPEST_PS;
2806 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2808 * Samsung SSD 960 EVO drops off the PCIe bus after system
2809 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2810 * within few minutes after bootup on a Coffee Lake board -
2813 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2814 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2815 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2816 return NVME_QUIRK_NO_APST;
2817 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2818 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2819 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2821 * Forcing to use host managed nvme power settings for
2822 * lowest idle power with quick resume latency on
2823 * Samsung and Toshiba SSDs based on suspend behavior
2824 * on Coffee Lake board for LENOVO C640
2826 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2827 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2828 return NVME_QUIRK_SIMPLE_SUSPEND;
2835 static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2837 struct acpi_device *adev;
2838 struct pci_dev *root;
2844 * Look for _DSD property specifying that the storage device on the port
2845 * must use D3 to support deep platform power savings during
2848 root = pcie_find_root_port(dev);
2852 adev = ACPI_COMPANION(&root->dev);
2857 * The property is defined in the PXSX device for South complex ports
2858 * and in the PEGP device for North complex ports.
2860 status = acpi_get_handle(adev->handle, "PXSX", &handle);
2861 if (ACPI_FAILURE(status)) {
2862 status = acpi_get_handle(adev->handle, "PEGP", &handle);
2863 if (ACPI_FAILURE(status))
2867 if (acpi_bus_get_device(handle, &adev))
2870 if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2876 static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2880 #endif /* CONFIG_ACPI */
2882 static void nvme_async_probe(void *data, async_cookie_t cookie)
2884 struct nvme_dev *dev = data;
2886 flush_work(&dev->ctrl.reset_work);
2887 flush_work(&dev->ctrl.scan_work);
2888 nvme_put_ctrl(&dev->ctrl);
2891 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2893 int node, result = -ENOMEM;
2894 struct nvme_dev *dev;
2895 unsigned long quirks = id->driver_data;
2898 node = dev_to_node(&pdev->dev);
2899 if (node == NUMA_NO_NODE)
2900 set_dev_node(&pdev->dev, first_memory_node);
2902 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2906 dev->nr_write_queues = write_queues;
2907 dev->nr_poll_queues = poll_queues;
2908 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2909 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2910 sizeof(struct nvme_queue), GFP_KERNEL, node);
2914 dev->dev = get_device(&pdev->dev);
2915 pci_set_drvdata(pdev, dev);
2917 result = nvme_dev_map(dev);
2921 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2922 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2923 mutex_init(&dev->shutdown_lock);
2925 result = nvme_setup_prp_pools(dev);
2929 quirks |= check_vendor_combination_bug(pdev);
2931 if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2933 * Some systems use a bios work around to ask for D3 on
2934 * platforms that support kernel managed suspend.
2936 dev_info(&pdev->dev,
2937 "platform quirk: setting simple suspend\n");
2938 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2942 * Double check that our mempool alloc size will cover the biggest
2943 * command we support.
2945 alloc_size = nvme_pci_iod_alloc_size();
2946 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2948 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2950 (void *) alloc_size,
2952 if (!dev->iod_mempool) {
2957 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2960 goto release_mempool;
2962 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2964 nvme_reset_ctrl(&dev->ctrl);
2965 async_schedule(nvme_async_probe, dev);
2970 mempool_destroy(dev->iod_mempool);
2972 nvme_release_prp_pools(dev);
2974 nvme_dev_unmap(dev);
2976 put_device(dev->dev);
2983 static void nvme_reset_prepare(struct pci_dev *pdev)
2985 struct nvme_dev *dev = pci_get_drvdata(pdev);
2988 * We don't need to check the return value from waiting for the reset
2989 * state as pci_dev device lock is held, making it impossible to race
2992 nvme_disable_prepare_reset(dev, false);
2993 nvme_sync_queues(&dev->ctrl);
2996 static void nvme_reset_done(struct pci_dev *pdev)
2998 struct nvme_dev *dev = pci_get_drvdata(pdev);
3000 if (!nvme_try_sched_reset(&dev->ctrl))
3001 flush_work(&dev->ctrl.reset_work);
3004 static void nvme_shutdown(struct pci_dev *pdev)
3006 struct nvme_dev *dev = pci_get_drvdata(pdev);
3008 nvme_disable_prepare_reset(dev, true);
3012 * The driver's remove may be called on a device in a partially initialized
3013 * state. This function must not have any dependencies on the device state in
3016 static void nvme_remove(struct pci_dev *pdev)
3018 struct nvme_dev *dev = pci_get_drvdata(pdev);
3020 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3021 pci_set_drvdata(pdev, NULL);
3023 if (!pci_device_is_present(pdev)) {
3024 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3025 nvme_dev_disable(dev, true);
3026 nvme_dev_remove_admin(dev);
3029 flush_work(&dev->ctrl.reset_work);
3030 nvme_stop_ctrl(&dev->ctrl);
3031 nvme_remove_namespaces(&dev->ctrl);
3032 nvme_dev_disable(dev, true);
3033 nvme_release_cmb(dev);
3034 nvme_free_host_mem(dev);
3035 nvme_dev_remove_admin(dev);
3036 nvme_free_queues(dev, 0);
3037 nvme_release_prp_pools(dev);
3038 nvme_dev_unmap(dev);
3039 nvme_uninit_ctrl(&dev->ctrl);
3042 #ifdef CONFIG_PM_SLEEP
3043 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3045 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3048 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3050 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3053 static int nvme_resume(struct device *dev)
3055 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3056 struct nvme_ctrl *ctrl = &ndev->ctrl;
3058 if (ndev->last_ps == U32_MAX ||
3059 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3060 return nvme_try_sched_reset(&ndev->ctrl);
3064 static int nvme_suspend(struct device *dev)
3066 struct pci_dev *pdev = to_pci_dev(dev);
3067 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3068 struct nvme_ctrl *ctrl = &ndev->ctrl;
3071 ndev->last_ps = U32_MAX;
3074 * The platform does not remove power for a kernel managed suspend so
3075 * use host managed nvme power settings for lowest idle power if
3076 * possible. This should have quicker resume latency than a full device
3077 * shutdown. But if the firmware is involved after the suspend or the
3078 * device does not support any non-default power states, shut down the
3081 * If ASPM is not enabled for the device, shut down the device and allow
3082 * the PCI bus layer to put it into D3 in order to take the PCIe link
3083 * down, so as to allow the platform to achieve its minimum low-power
3084 * state (which may not be possible if the link is up).
3086 * If a host memory buffer is enabled, shut down the device as the NVMe
3087 * specification allows the device to access the host memory buffer in
3088 * host DRAM from all power states, but hosts will fail access to DRAM
3091 if (pm_suspend_via_firmware() || !ctrl->npss ||
3092 !pcie_aspm_enabled(pdev) ||
3093 ndev->nr_host_mem_descs ||
3094 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3095 return nvme_disable_prepare_reset(ndev, true);
3097 nvme_start_freeze(ctrl);
3098 nvme_wait_freeze(ctrl);
3099 nvme_sync_queues(ctrl);
3101 if (ctrl->state != NVME_CTRL_LIVE)
3104 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3109 * A saved state prevents pci pm from generically controlling the
3110 * device's power. If we're using protocol specific settings, we don't
3111 * want pci interfering.
3113 pci_save_state(pdev);
3115 ret = nvme_set_power_state(ctrl, ctrl->npss);
3120 /* discard the saved state */
3121 pci_load_saved_state(pdev, NULL);
3124 * Clearing npss forces a controller reset on resume. The
3125 * correct value will be rediscovered then.
3127 ret = nvme_disable_prepare_reset(ndev, true);
3131 nvme_unfreeze(ctrl);
3135 static int nvme_simple_suspend(struct device *dev)
3137 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3139 return nvme_disable_prepare_reset(ndev, true);
3142 static int nvme_simple_resume(struct device *dev)
3144 struct pci_dev *pdev = to_pci_dev(dev);
3145 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3147 return nvme_try_sched_reset(&ndev->ctrl);
3150 static const struct dev_pm_ops nvme_dev_pm_ops = {
3151 .suspend = nvme_suspend,
3152 .resume = nvme_resume,
3153 .freeze = nvme_simple_suspend,
3154 .thaw = nvme_simple_resume,
3155 .poweroff = nvme_simple_suspend,
3156 .restore = nvme_simple_resume,
3158 #endif /* CONFIG_PM_SLEEP */
3160 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3161 pci_channel_state_t state)
3163 struct nvme_dev *dev = pci_get_drvdata(pdev);
3166 * A frozen channel requires a reset. When detected, this method will
3167 * shutdown the controller to quiesce. The controller will be restarted
3168 * after the slot reset through driver's slot_reset callback.
3171 case pci_channel_io_normal:
3172 return PCI_ERS_RESULT_CAN_RECOVER;
3173 case pci_channel_io_frozen:
3174 dev_warn(dev->ctrl.device,
3175 "frozen state error detected, reset controller\n");
3176 nvme_dev_disable(dev, false);
3177 return PCI_ERS_RESULT_NEED_RESET;
3178 case pci_channel_io_perm_failure:
3179 dev_warn(dev->ctrl.device,
3180 "failure state error detected, request disconnect\n");
3181 return PCI_ERS_RESULT_DISCONNECT;
3183 return PCI_ERS_RESULT_NEED_RESET;
3186 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3188 struct nvme_dev *dev = pci_get_drvdata(pdev);
3190 dev_info(dev->ctrl.device, "restart after slot reset\n");
3191 pci_restore_state(pdev);
3192 nvme_reset_ctrl(&dev->ctrl);
3193 return PCI_ERS_RESULT_RECOVERED;
3196 static void nvme_error_resume(struct pci_dev *pdev)
3198 struct nvme_dev *dev = pci_get_drvdata(pdev);
3200 flush_work(&dev->ctrl.reset_work);
3203 static const struct pci_error_handlers nvme_err_handler = {
3204 .error_detected = nvme_error_detected,
3205 .slot_reset = nvme_slot_reset,
3206 .resume = nvme_error_resume,
3207 .reset_prepare = nvme_reset_prepare,
3208 .reset_done = nvme_reset_done,
3211 static const struct pci_device_id nvme_id_table[] = {
3212 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3213 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3214 NVME_QUIRK_DEALLOCATE_ZEROES, },
3215 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3216 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3217 NVME_QUIRK_DEALLOCATE_ZEROES, },
3218 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3219 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3220 NVME_QUIRK_DEALLOCATE_ZEROES, },
3221 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3222 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3223 NVME_QUIRK_DEALLOCATE_ZEROES, },
3224 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3225 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3226 NVME_QUIRK_MEDIUM_PRIO_SQ |
3227 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3228 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3229 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3230 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3231 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3232 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3233 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3234 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3235 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3236 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3237 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3238 NVME_QUIRK_NO_NS_DESC_LIST, },
3239 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3240 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3241 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3242 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3243 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3244 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3245 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3246 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3247 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3248 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3249 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3250 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3251 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3252 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3253 .driver_data = NVME_QUIRK_LIGHTNVM, },
3254 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3255 .driver_data = NVME_QUIRK_LIGHTNVM, },
3256 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3257 .driver_data = NVME_QUIRK_LIGHTNVM, },
3258 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3259 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3260 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3261 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3262 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3263 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3264 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3265 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3266 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3267 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3268 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3269 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3270 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3271 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3272 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3273 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3274 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3275 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3276 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3277 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3278 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3279 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3280 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3281 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3282 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3283 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3284 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3285 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3286 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3287 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3288 NVME_QUIRK_128_BYTES_SQES |
3289 NVME_QUIRK_SHARED_TAGS },
3291 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3294 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3296 static struct pci_driver nvme_driver = {
3298 .id_table = nvme_id_table,
3299 .probe = nvme_probe,
3300 .remove = nvme_remove,
3301 .shutdown = nvme_shutdown,
3302 #ifdef CONFIG_PM_SLEEP
3304 .pm = &nvme_dev_pm_ops,
3307 .sriov_configure = pci_sriov_configure_simple,
3308 .err_handler = &nvme_err_handler,
3311 static int __init nvme_init(void)
3313 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3314 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3315 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3316 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3318 return pci_register_driver(&nvme_driver);
3321 static void __exit nvme_exit(void)
3323 pci_unregister_driver(&nvme_driver);
3324 flush_workqueue(nvme_wq);
3327 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3328 MODULE_LICENSE("GPL");
3329 MODULE_VERSION("1.0");
3330 module_init(nvme_init);
3331 module_exit(nvme_exit);