drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/dmi.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/once.h>
  21 #include <linux/pci.h>
  22 #include <linux/suspend.h>
  23 #include <linux/t10-pi.h>
  24 #include <linux/types.h>
  25 #include <linux/io-64-nonatomic-lo-hi.h>
  26 #include <linux/sed-opal.h>
  27 #include <linux/pci-p2pdma.h>
  28
  29 #include "trace.h"
  30 #include "nvme.h"
  31
  32 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  33 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  34
  35 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  36
  37 /*
  38  * These can be higher, but we need to ensure that any command doesn't
  39  * require an sg allocation that needs more than a page of data.
  40  */
  41 #define NVME_MAX_KB_SZ  4096
  42 #define NVME_MAX_SEGS   127
  43
  44 static int use_threaded_interrupts;
  45 module_param(use_threaded_interrupts, int, 0);
  46
  47 static bool use_cmb_sqes = true;
  48 module_param(use_cmb_sqes, bool, 0444);
  49 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  50
  51 static unsigned int max_host_mem_size_mb = 128;
  52 module_param(max_host_mem_size_mb, uint, 0444);
  53 MODULE_PARM_DESC(max_host_mem_size_mb,
  54         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  55
  56 static unsigned int sgl_threshold = SZ_32K;
  57 module_param(sgl_threshold, uint, 0644);
  58 MODULE_PARM_DESC(sgl_threshold,
  59                 "Use SGLs when average request segment size is larger or equal to "
  60                 "this size. Use 0 to disable SGLs.");
  61
  62 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  63 static const struct kernel_param_ops io_queue_depth_ops = {
  64         .set = io_queue_depth_set,
  65         .get = param_get_uint,
  66 };
  67
  68 static unsigned int io_queue_depth = 1024;
  69 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  70 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  71
  72 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  73 {
  74         unsigned int n;
  75         int ret;
  76
  77         ret = kstrtouint(val, 10, &n);
  78         if (ret != 0 || n > num_possible_cpus())
  79                 return -EINVAL;
  80         return param_set_uint(val, kp);
  81 }
  82
  83 static const struct kernel_param_ops io_queue_count_ops = {
  84         .set = io_queue_count_set,
  85         .get = param_get_uint,
  86 };
  87
  88 static unsigned int write_queues;
  89 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  90 MODULE_PARM_DESC(write_queues,
  91         "Number of queues to use for writes. If not set, reads and writes "
  92         "will share a queue set.");
  93
  94 static unsigned int poll_queues;
  95 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
  96 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
  97
  98 static bool noacpi;
  99 module_param(noacpi, bool, 0444);
 100 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 101
 102 struct nvme_dev;
 103 struct nvme_queue;
 104
 105 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 106 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 107
 108 /*
 109  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 110  */
 111 struct nvme_dev {
 112         struct nvme_queue *queues;
 113         struct blk_mq_tag_set tagset;
 114         struct blk_mq_tag_set admin_tagset;
 115         u32 __iomem *dbs;
 116         struct device *dev;
 117         struct dma_pool *prp_page_pool;
 118         struct dma_pool *prp_small_pool;
 119         unsigned online_queues;
 120         unsigned max_qid;
 121         unsigned io_queues[HCTX_MAX_TYPES];
 122         unsigned int num_vecs;
 123         u32 q_depth;
 124         int io_sqes;
 125         u32 db_stride;
 126         void __iomem *bar;
 127         unsigned long bar_mapped_size;
 128         struct work_struct remove_work;
 129         struct mutex shutdown_lock;
 130         bool subsystem;
 131         u64 cmb_size;
 132         bool cmb_use_sqes;
 133         u32 cmbsz;
 134         u32 cmbloc;
 135         struct nvme_ctrl ctrl;
 136         u32 last_ps;
 137
 138         mempool_t *iod_mempool;
 139
 140         /* shadow doorbell buffer support: */
 141         u32 *dbbuf_dbs;
 142         dma_addr_t dbbuf_dbs_dma_addr;
 143         u32 *dbbuf_eis;
 144         dma_addr_t dbbuf_eis_dma_addr;
 145
 146         /* host memory buffer support: */
 147         u64 host_mem_size;
 148         u32 nr_host_mem_descs;
 149         dma_addr_t host_mem_descs_dma;
 150         struct nvme_host_mem_buf_desc *host_mem_descs;
 151         void **host_mem_desc_bufs;
 152         unsigned int nr_allocated_queues;
 153         unsigned int nr_write_queues;
 154         unsigned int nr_poll_queues;
 155 };
 156
 157 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 158 {
 159         int ret;
 160         u32 n;
 161
 162         ret = kstrtou32(val, 10, &n);
 163         if (ret != 0 || n < 2)
 164                 return -EINVAL;
 165
 166         return param_set_uint(val, kp);
 167 }
 168
 169 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 170 {
 171         return qid * 2 * stride;
 172 }
 173
 174 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 175 {
 176         return (qid * 2 + 1) * stride;
 177 }
 178
 179 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 180 {
 181         return container_of(ctrl, struct nvme_dev, ctrl);
 182 }
 183
 184 /*
 185  * An NVM Express queue.  Each device has at least two (one for admin
 186  * commands and one for I/O commands).
 187  */
 188 struct nvme_queue {
 189         struct nvme_dev *dev;
 190         spinlock_t sq_lock;
 191         void *sq_cmds;
 192          /* only used for poll queues: */
 193         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 194         struct nvme_completion *cqes;
 195         dma_addr_t sq_dma_addr;
 196         dma_addr_t cq_dma_addr;
 197         u32 __iomem *q_db;
 198         u32 q_depth;
 199         u16 cq_vector;
 200         u16 sq_tail;
 201         u16 last_sq_tail;
 202         u16 cq_head;
 203         u16 qid;
 204         u8 cq_phase;
 205         u8 sqes;
 206         unsigned long flags;
 207 #define NVMEQ_ENABLED           0
 208 #define NVMEQ_SQ_CMB            1
 209 #define NVMEQ_DELETE_ERROR      2
 210 #define NVMEQ_POLLED            3
 211         u32 *dbbuf_sq_db;
 212         u32 *dbbuf_cq_db;
 213         u32 *dbbuf_sq_ei;
 214         u32 *dbbuf_cq_ei;
 215         struct completion delete_done;
 216 };
 217
 218 /*
 219  * The nvme_iod describes the data in an I/O.
 220  *
 221  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 222  * to the actual struct scatterlist.
 223  */
 224 struct nvme_iod {
 225         struct nvme_request req;
 226         struct nvme_queue *nvmeq;
 227         bool use_sgl;
 228         int aborted;
 229         int npages;             /* In the PRP list. 0 means small pool in use */
 230         int nents;              /* Used in scatterlist */
 231         dma_addr_t first_dma;
 232         unsigned int dma_len;   /* length of single DMA segment mapping */
 233         dma_addr_t meta_dma;
 234         struct scatterlist *sg;
 235 };
 236
 237 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 238 {
 239         return dev->nr_allocated_queues * 8 * dev->db_stride;
 240 }
 241
 242 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 243 {
 244         unsigned int mem_size = nvme_dbbuf_size(dev);
 245
 246         if (dev->dbbuf_dbs)
 247                 return 0;
 248
 249         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 250                                             &dev->dbbuf_dbs_dma_addr,
 251                                             GFP_KERNEL);
 252         if (!dev->dbbuf_dbs)
 253                 return -ENOMEM;
 254         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 255                                             &dev->dbbuf_eis_dma_addr,
 256                                             GFP_KERNEL);
 257         if (!dev->dbbuf_eis) {
 258                 dma_free_coherent(dev->dev, mem_size,
 259                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 260                 dev->dbbuf_dbs = NULL;
 261                 return -ENOMEM;
 262         }
 263
 264         return 0;
 265 }
 266
 267 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 268 {
 269         unsigned int mem_size = nvme_dbbuf_size(dev);
 270
 271         if (dev->dbbuf_dbs) {
 272                 dma_free_coherent(dev->dev, mem_size,
 273                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 274                 dev->dbbuf_dbs = NULL;
 275         }
 276         if (dev->dbbuf_eis) {
 277                 dma_free_coherent(dev->dev, mem_size,
 278                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 279                 dev->dbbuf_eis = NULL;
 280         }
 281 }
 282
 283 static void nvme_dbbuf_init(struct nvme_dev *dev,
 284                             struct nvme_queue *nvmeq, int qid)
 285 {
 286         if (!dev->dbbuf_dbs || !qid)
 287                 return;
 288
 289         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 290         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 291         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 292         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 293 }
 294
 295 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 296 {
 297         if (!nvmeq->qid)
 298                 return;
 299
 300         nvmeq->dbbuf_sq_db = NULL;
 301         nvmeq->dbbuf_cq_db = NULL;
 302         nvmeq->dbbuf_sq_ei = NULL;
 303         nvmeq->dbbuf_cq_ei = NULL;
 304 }
 305
 306 static void nvme_dbbuf_set(struct nvme_dev *dev)
 307 {
 308         struct nvme_command c;
 309         unsigned int i;
 310
 311         if (!dev->dbbuf_dbs)
 312                 return;
 313
 314         memset(&c, 0, sizeof(c));
 315         c.dbbuf.opcode = nvme_admin_dbbuf;
 316         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 317         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 318
 319         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 320                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 321                 /* Free memory and continue on */
 322                 nvme_dbbuf_dma_free(dev);
 323
 324                 for (i = 1; i <= dev->online_queues; i++)
 325                         nvme_dbbuf_free(&dev->queues[i]);
 326         }
 327 }
 328
 329 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 330 {
 331         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 332 }
 333
 334 /* Update dbbuf and return true if an MMIO is required */
 335 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 336                                               volatile u32 *dbbuf_ei)
 337 {
 338         if (dbbuf_db) {
 339                 u16 old_value;
 340
 341                 /*
 342                  * Ensure that the queue is written before updating
 343                  * the doorbell in memory
 344                  */
 345                 wmb();
 346
 347                 old_value = *dbbuf_db;
 348                 *dbbuf_db = value;
 349
 350                 /*
 351                  * Ensure that the doorbell is updated before reading the event
 352                  * index from memory.  The controller needs to provide similar
 353                  * ordering to ensure the envent index is updated before reading
 354                  * the doorbell.
 355                  */
 356                 mb();
 357
 358                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 359                         return false;
 360         }
 361
 362         return true;
 363 }
 364
 365 /*
 366  * Will slightly overestimate the number of pages needed.  This is OK
 367  * as it only leads to a small amount of wasted memory for the lifetime of
 368  * the I/O.
 369  */
 370 static int nvme_pci_npages_prp(void)
 371 {
 372         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 373                                       NVME_CTRL_PAGE_SIZE);
 374         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 375 }
 376
 377 /*
 378  * Calculates the number of pages needed for the SGL segments. For example a 4k
 379  * page can accommodate 256 SGL descriptors.
 380  */
 381 static int nvme_pci_npages_sgl(void)
 382 {
 383         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 384                         PAGE_SIZE);
 385 }
 386
 387 static size_t nvme_pci_iod_alloc_size(void)
 388 {
 389         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 390
 391         return sizeof(__le64 *) * npages +
 392                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 393 }
 394
 395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 396                                 unsigned int hctx_idx)
 397 {
 398         struct nvme_dev *dev = data;
 399         struct nvme_queue *nvmeq = &dev->queues[0];
 400
 401         WARN_ON(hctx_idx != 0);
 402         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 403
 404         hctx->driver_data = nvmeq;
 405         return 0;
 406 }
 407
 408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 409                           unsigned int hctx_idx)
 410 {
 411         struct nvme_dev *dev = data;
 412         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 413
 414         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 415         hctx->driver_data = nvmeq;
 416         return 0;
 417 }
 418
 419 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 420                 unsigned int hctx_idx, unsigned int numa_node)
 421 {
 422         struct nvme_dev *dev = set->driver_data;
 423         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 424         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 425         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 426
 427         BUG_ON(!nvmeq);
 428         iod->nvmeq = nvmeq;
 429
 430         nvme_req(req)->ctrl = &dev->ctrl;
 431         return 0;
 432 }
 433
 434 static int queue_irq_offset(struct nvme_dev *dev)
 435 {
 436         /* if we have more than 1 vec, admin queue offsets us by 1 */
 437         if (dev->num_vecs > 1)
 438                 return 1;
 439
 440         return 0;
 441 }
 442
 443 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 444 {
 445         struct nvme_dev *dev = set->driver_data;
 446         int i, qoff, offset;
 447
 448         offset = queue_irq_offset(dev);
 449         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 450                 struct blk_mq_queue_map *map = &set->map[i];
 451
 452                 map->nr_queues = dev->io_queues[i];
 453                 if (!map->nr_queues) {
 454                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 455                         continue;
 456                 }
 457
 458                 /*
 459                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 460                  * affinity), so use the regular blk-mq cpu mapping
 461                  */
 462                 map->queue_offset = qoff;
 463                 if (i != HCTX_TYPE_POLL && offset)
 464                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 465                 else
 466                         blk_mq_map_queues(map);
 467                 qoff += map->nr_queues;
 468                 offset += map->nr_queues;
 469         }
 470
 471         return 0;
 472 }
 473
 474 /*
 475  * Write sq tail if we are asked to, or if the next command would wrap.
 476  */
 477 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 478 {
 479         if (!write_sq) {
 480                 u16 next_tail = nvmeq->sq_tail + 1;
 481
 482                 if (next_tail == nvmeq->q_depth)
 483                         next_tail = 0;
 484                 if (next_tail != nvmeq->last_sq_tail)
 485                         return;
 486         }
 487
 488         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 489                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 490                 writel(nvmeq->sq_tail, nvmeq->q_db);
 491         nvmeq->last_sq_tail = nvmeq->sq_tail;
 492 }
 493
 494 /**
 495  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 496  * @nvmeq: The queue to use
 497  * @cmd: The command to send
 498  * @write_sq: whether to write to the SQ doorbell
 499  */
 500 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 501                             bool write_sq)
 502 {
 503         spin_lock(&nvmeq->sq_lock);
 504         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 505                cmd, sizeof(*cmd));
 506         if (++nvmeq->sq_tail == nvmeq->q_depth)
 507                 nvmeq->sq_tail = 0;
 508         nvme_write_sq_db(nvmeq, write_sq);
 509         spin_unlock(&nvmeq->sq_lock);
 510 }
 511
 512 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 513 {
 514         struct nvme_queue *nvmeq = hctx->driver_data;
 515
 516         spin_lock(&nvmeq->sq_lock);
 517         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 518                 nvme_write_sq_db(nvmeq, true);
 519         spin_unlock(&nvmeq->sq_lock);
 520 }
 521
 522 static void **nvme_pci_iod_list(struct request *req)
 523 {
 524         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 525         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 526 }
 527
 528 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 529 {
 530         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 531         int nseg = blk_rq_nr_phys_segments(req);
 532         unsigned int avg_seg_size;
 533
 534         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 535
 536         if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
 537                 return false;
 538         if (!iod->nvmeq->qid)
 539                 return false;
 540         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 541                 return false;
 542         return true;
 543 }
 544
 545 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 546 {
 547         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 548         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 549         dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
 550         int i;
 551
 552         if (iod->dma_len) {
 553                 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
 554                                rq_dma_dir(req));
 555                 return;
 556         }
 557
 558         WARN_ON_ONCE(!iod->nents);
 559
 560         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 561                 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 562                                     rq_dma_dir(req));
 563         else
 564                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 565
 566
 567         if (iod->npages == 0)
 568                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 569                         dma_addr);
 570
 571         for (i = 0; i < iod->npages; i++) {
 572                 void *addr = nvme_pci_iod_list(req)[i];
 573
 574                 if (iod->use_sgl) {
 575                         struct nvme_sgl_desc *sg_list = addr;
 576
 577                         next_dma_addr =
 578                             le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
 579                 } else {
 580                         __le64 *prp_list = addr;
 581
 582                         next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 583                 }
 584
 585                 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
 586                 dma_addr = next_dma_addr;
 587         }
 588
 589         mempool_free(iod->sg, dev->iod_mempool);
 590 }
 591
 592 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 593 {
 594         int i;
 595         struct scatterlist *sg;
 596
 597         for_each_sg(sgl, sg, nents, i) {
 598                 dma_addr_t phys = sg_phys(sg);
 599                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 600                         "dma_address:%pad dma_length:%d\n",
 601                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 602                         sg_dma_len(sg));
 603         }
 604 }
 605
 606 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 607                 struct request *req, struct nvme_rw_command *cmnd)
 608 {
 609         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 610         struct dma_pool *pool;
 611         int length = blk_rq_payload_bytes(req);
 612         struct scatterlist *sg = iod->sg;
 613         int dma_len = sg_dma_len(sg);
 614         u64 dma_addr = sg_dma_address(sg);
 615         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 616         __le64 *prp_list;
 617         void **list = nvme_pci_iod_list(req);
 618         dma_addr_t prp_dma;
 619         int nprps, i;
 620
 621         length -= (NVME_CTRL_PAGE_SIZE - offset);
 622         if (length <= 0) {
 623                 iod->first_dma = 0;
 624                 goto done;
 625         }
 626
 627         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 628         if (dma_len) {
 629                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 630         } else {
 631                 sg = sg_next(sg);
 632                 dma_addr = sg_dma_address(sg);
 633                 dma_len = sg_dma_len(sg);
 634         }
 635
 636         if (length <= NVME_CTRL_PAGE_SIZE) {
 637                 iod->first_dma = dma_addr;
 638                 goto done;
 639         }
 640
 641         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 642         if (nprps <= (256 / 8)) {
 643                 pool = dev->prp_small_pool;
 644                 iod->npages = 0;
 645         } else {
 646                 pool = dev->prp_page_pool;
 647                 iod->npages = 1;
 648         }
 649
 650         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 651         if (!prp_list) {
 652                 iod->first_dma = dma_addr;
 653                 iod->npages = -1;
 654                 return BLK_STS_RESOURCE;
 655         }
 656         list[0] = prp_list;
 657         iod->first_dma = prp_dma;
 658         i = 0;
 659         for (;;) {
 660                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 661                         __le64 *old_prp_list = prp_list;
 662                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 663                         if (!prp_list)
 664                                 return BLK_STS_RESOURCE;
 665                         list[iod->npages++] = prp_list;
 666                         prp_list[0] = old_prp_list[i - 1];
 667                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 668                         i = 1;
 669                 }
 670                 prp_list[i++] = cpu_to_le64(dma_addr);
 671                 dma_len -= NVME_CTRL_PAGE_SIZE;
 672                 dma_addr += NVME_CTRL_PAGE_SIZE;
 673                 length -= NVME_CTRL_PAGE_SIZE;
 674                 if (length <= 0)
 675                         break;
 676                 if (dma_len > 0)
 677                         continue;
 678                 if (unlikely(dma_len < 0))
 679                         goto bad_sgl;
 680                 sg = sg_next(sg);
 681                 dma_addr = sg_dma_address(sg);
 682                 dma_len = sg_dma_len(sg);
 683         }
 684
 685 done:
 686         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 687         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 688
 689         return BLK_STS_OK;
 690
 691  bad_sgl:
 692         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 693                         "Invalid SGL for payload:%d nents:%d\n",
 694                         blk_rq_payload_bytes(req), iod->nents);
 695         return BLK_STS_IOERR;
 696 }
 697
 698 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 699                 struct scatterlist *sg)
 700 {
 701         sge->addr = cpu_to_le64(sg_dma_address(sg));
 702         sge->length = cpu_to_le32(sg_dma_len(sg));
 703         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 704 }
 705
 706 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 707                 dma_addr_t dma_addr, int entries)
 708 {
 709         sge->addr = cpu_to_le64(dma_addr);
 710         if (entries < SGES_PER_PAGE) {
 711                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 712                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 713         } else {
 714                 sge->length = cpu_to_le32(PAGE_SIZE);
 715                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 716         }
 717 }
 718
 719 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 720                 struct request *req, struct nvme_rw_command *cmd, int entries)
 721 {
 722         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 723         struct dma_pool *pool;
 724         struct nvme_sgl_desc *sg_list;
 725         struct scatterlist *sg = iod->sg;
 726         dma_addr_t sgl_dma;
 727         int i = 0;
 728
 729         /* setting the transfer type as SGL */
 730         cmd->flags = NVME_CMD_SGL_METABUF;
 731
 732         if (entries == 1) {
 733                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 734                 return BLK_STS_OK;
 735         }
 736
 737         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 738                 pool = dev->prp_small_pool;
 739                 iod->npages = 0;
 740         } else {
 741                 pool = dev->prp_page_pool;
 742                 iod->npages = 1;
 743         }
 744
 745         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 746         if (!sg_list) {
 747                 iod->npages = -1;
 748                 return BLK_STS_RESOURCE;
 749         }
 750
 751         nvme_pci_iod_list(req)[0] = sg_list;
 752         iod->first_dma = sgl_dma;
 753
 754         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 755
 756         do {
 757                 if (i == SGES_PER_PAGE) {
 758                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 759                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 760
 761                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 762                         if (!sg_list)
 763                                 return BLK_STS_RESOURCE;
 764
 765                         i = 0;
 766                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 767                         sg_list[i++] = *link;
 768                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 769                 }
 770
 771                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 772                 sg = sg_next(sg);
 773         } while (--entries > 0);
 774
 775         return BLK_STS_OK;
 776 }
 777
 778 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 779                 struct request *req, struct nvme_rw_command *cmnd,
 780                 struct bio_vec *bv)
 781 {
 782         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 783         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 784         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 785
 786         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 787         if (dma_mapping_error(dev->dev, iod->first_dma))
 788                 return BLK_STS_RESOURCE;
 789         iod->dma_len = bv->bv_len;
 790
 791         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 792         if (bv->bv_len > first_prp_len)
 793                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 794         return BLK_STS_OK;
 795 }
 796
 797 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 798                 struct request *req, struct nvme_rw_command *cmnd,
 799                 struct bio_vec *bv)
 800 {
 801         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 802
 803         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 804         if (dma_mapping_error(dev->dev, iod->first_dma))
 805                 return BLK_STS_RESOURCE;
 806         iod->dma_len = bv->bv_len;
 807
 808         cmnd->flags = NVME_CMD_SGL_METABUF;
 809         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 810         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 811         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 812         return BLK_STS_OK;
 813 }
 814
 815 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 816                 struct nvme_command *cmnd)
 817 {
 818         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 819         blk_status_t ret = BLK_STS_RESOURCE;
 820         int nr_mapped;
 821
 822         if (blk_rq_nr_phys_segments(req) == 1) {
 823                 struct bio_vec bv = req_bvec(req);
 824
 825                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 826                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 827                                 return nvme_setup_prp_simple(dev, req,
 828                                                              &cmnd->rw, &bv);
 829
 830                         if (iod->nvmeq->qid &&
 831                             dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
 832                                 return nvme_setup_sgl_simple(dev, req,
 833                                                              &cmnd->rw, &bv);
 834                 }
 835         }
 836
 837         iod->dma_len = 0;
 838         iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 839         if (!iod->sg)
 840                 return BLK_STS_RESOURCE;
 841         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 842         iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 843         if (!iod->nents)
 844                 goto out;
 845
 846         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 847                 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 848                                 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 849         else
 850                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 851                                              rq_dma_dir(req), DMA_ATTR_NO_WARN);
 852         if (!nr_mapped)
 853                 goto out;
 854
 855         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 856         if (iod->use_sgl)
 857                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 858         else
 859                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 860 out:
 861         if (ret != BLK_STS_OK)
 862                 nvme_unmap_data(dev, req);
 863         return ret;
 864 }
 865
 866 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 867                 struct nvme_command *cmnd)
 868 {
 869         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 870
 871         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 872                         rq_dma_dir(req), 0);
 873         if (dma_mapping_error(dev->dev, iod->meta_dma))
 874                 return BLK_STS_IOERR;
 875         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 876         return BLK_STS_OK;
 877 }
 878
 879 /*
 880  * NOTE: ns is NULL when called on the admin queue.
 881  */
 882 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 883                          const struct blk_mq_queue_data *bd)
 884 {
 885         struct nvme_ns *ns = hctx->queue->queuedata;
 886         struct nvme_queue *nvmeq = hctx->driver_data;
 887         struct nvme_dev *dev = nvmeq->dev;
 888         struct request *req = bd->rq;
 889         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 890         struct nvme_command cmnd;
 891         blk_status_t ret;
 892
 893         iod->aborted = 0;
 894         iod->npages = -1;
 895         iod->nents = 0;
 896
 897         /*
 898          * We should not need to do this, but we're still using this to
 899          * ensure we can drain requests on a dying queue.
 900          */
 901         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 902                 return BLK_STS_IOERR;
 903
 904         ret = nvme_setup_cmd(ns, req, &cmnd);
 905         if (ret)
 906                 return ret;
 907
 908         if (blk_rq_nr_phys_segments(req)) {
 909                 ret = nvme_map_data(dev, req, &cmnd);
 910                 if (ret)
 911                         goto out_free_cmd;
 912         }
 913
 914         if (blk_integrity_rq(req)) {
 915                 ret = nvme_map_metadata(dev, req, &cmnd);
 916                 if (ret)
 917                         goto out_unmap_data;
 918         }
 919
 920         blk_mq_start_request(req);
 921         nvme_submit_cmd(nvmeq, &cmnd, bd->last);
 922         return BLK_STS_OK;
 923 out_unmap_data:
 924         nvme_unmap_data(dev, req);
 925 out_free_cmd:
 926         nvme_cleanup_cmd(req);
 927         return ret;
 928 }
 929
 930 static void nvme_pci_complete_rq(struct request *req)
 931 {
 932         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 933         struct nvme_dev *dev = iod->nvmeq->dev;
 934
 935         if (blk_integrity_rq(req))
 936                 dma_unmap_page(dev->dev, iod->meta_dma,
 937                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
 938         if (blk_rq_nr_phys_segments(req))
 939                 nvme_unmap_data(dev, req);
 940         nvme_complete_rq(req);
 941 }
 942
 943 /* We read the CQE phase first to check if the rest of the entry is valid */
 944 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 945 {
 946         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 947
 948         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 949 }
 950
 951 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 952 {
 953         u16 head = nvmeq->cq_head;
 954
 955         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 956                                               nvmeq->dbbuf_cq_ei))
 957                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 958 }
 959
 960 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
 961 {
 962         if (!nvmeq->qid)
 963                 return nvmeq->dev->admin_tagset.tags[0];
 964         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
 965 }
 966
 967 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
 968 {
 969         struct nvme_completion *cqe = &nvmeq->cqes[idx];
 970         struct request *req;
 971
 972         /*
 973          * AEN requests are special as they don't time out and can
 974          * survive any kind of queue freeze and often don't respond to
 975          * aborts.  We don't even bother to allocate a struct request
 976          * for them but rather special case them here.
 977          */
 978         if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
 979                 nvme_complete_async_event(&nvmeq->dev->ctrl,
 980                                 cqe->status, &cqe->result);
 981                 return;
 982         }
 983
 984         req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
 985         if (unlikely(!req)) {
 986                 dev_warn(nvmeq->dev->ctrl.device,
 987                         "invalid id %d completed on queue %d\n",
 988                         cqe->command_id, le16_to_cpu(cqe->sq_id));
 989                 return;
 990         }
 991
 992         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
 993         if (!nvme_try_complete_req(req, cqe->status, cqe->result))
 994                 nvme_pci_complete_rq(req);
 995 }
 996
 997 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
 998 {
 999         u16 tmp = nvmeq->cq_head + 1;
1000
1001         if (tmp == nvmeq->q_depth) {
1002                 nvmeq->cq_head = 0;
1003                 nvmeq->cq_phase ^= 1;
1004         } else {
1005                 nvmeq->cq_head = tmp;
1006         }
1007 }
1008
1009 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1010 {
1011         int found = 0;
1012
1013         while (nvme_cqe_pending(nvmeq)) {
1014                 found++;
1015                 /*
1016                  * load-load control dependency between phase and the rest of
1017                  * the cqe requires a full read memory barrier
1018                  */
1019                 dma_rmb();
1020                 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1021                 nvme_update_cq_head(nvmeq);
1022         }
1023
1024         if (found)
1025                 nvme_ring_cq_doorbell(nvmeq);
1026         return found;
1027 }
1028
1029 static irqreturn_t nvme_irq(int irq, void *data)
1030 {
1031         struct nvme_queue *nvmeq = data;
1032         irqreturn_t ret = IRQ_NONE;
1033
1034         /*
1035          * The rmb/wmb pair ensures we see all updates from a previous run of
1036          * the irq handler, even if that was on another CPU.
1037          */
1038         rmb();
1039         if (nvme_process_cq(nvmeq))
1040                 ret = IRQ_HANDLED;
1041         wmb();
1042
1043         return ret;
1044 }
1045
1046 static irqreturn_t nvme_irq_check(int irq, void *data)
1047 {
1048         struct nvme_queue *nvmeq = data;
1049
1050         if (nvme_cqe_pending(nvmeq))
1051                 return IRQ_WAKE_THREAD;
1052         return IRQ_NONE;
1053 }
1054
1055 /*
1056  * Poll for completions for any interrupt driven queue
1057  * Can be called from any context.
1058  */
1059 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1060 {
1061         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1062
1063         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1064
1065         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1066         nvme_process_cq(nvmeq);
1067         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1068 }
1069
1070 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1071 {
1072         struct nvme_queue *nvmeq = hctx->driver_data;
1073         bool found;
1074
1075         if (!nvme_cqe_pending(nvmeq))
1076                 return 0;
1077
1078         spin_lock(&nvmeq->cq_poll_lock);
1079         found = nvme_process_cq(nvmeq);
1080         spin_unlock(&nvmeq->cq_poll_lock);
1081
1082         return found;
1083 }
1084
1085 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1086 {
1087         struct nvme_dev *dev = to_nvme_dev(ctrl);
1088         struct nvme_queue *nvmeq = &dev->queues[0];
1089         struct nvme_command c;
1090
1091         memset(&c, 0, sizeof(c));
1092         c.common.opcode = nvme_admin_async_event;
1093         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1094         nvme_submit_cmd(nvmeq, &c, true);
1095 }
1096
1097 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1098 {
1099         struct nvme_command c;
1100
1101         memset(&c, 0, sizeof(c));
1102         c.delete_queue.opcode = opcode;
1103         c.delete_queue.qid = cpu_to_le16(id);
1104
1105         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1106 }
1107
1108 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1109                 struct nvme_queue *nvmeq, s16 vector)
1110 {
1111         struct nvme_command c;
1112         int flags = NVME_QUEUE_PHYS_CONTIG;
1113
1114         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1115                 flags |= NVME_CQ_IRQ_ENABLED;
1116
1117         /*
1118          * Note: we (ab)use the fact that the prp fields survive if no data
1119          * is attached to the request.
1120          */
1121         memset(&c, 0, sizeof(c));
1122         c.create_cq.opcode = nvme_admin_create_cq;
1123         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1124         c.create_cq.cqid = cpu_to_le16(qid);
1125         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1126         c.create_cq.cq_flags = cpu_to_le16(flags);
1127         c.create_cq.irq_vector = cpu_to_le16(vector);
1128
1129         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1130 }
1131
1132 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1133                                                 struct nvme_queue *nvmeq)
1134 {
1135         struct nvme_ctrl *ctrl = &dev->ctrl;
1136         struct nvme_command c;
1137         int flags = NVME_QUEUE_PHYS_CONTIG;
1138
1139         /*
1140          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1141          * set. Since URGENT priority is zeroes, it makes all queues
1142          * URGENT.
1143          */
1144         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1145                 flags |= NVME_SQ_PRIO_MEDIUM;
1146
1147         /*
1148          * Note: we (ab)use the fact that the prp fields survive if no data
1149          * is attached to the request.
1150          */
1151         memset(&c, 0, sizeof(c));
1152         c.create_sq.opcode = nvme_admin_create_sq;
1153         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1154         c.create_sq.sqid = cpu_to_le16(qid);
1155         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1156         c.create_sq.sq_flags = cpu_to_le16(flags);
1157         c.create_sq.cqid = cpu_to_le16(qid);
1158
1159         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1160 }
1161
1162 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1163 {
1164         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1165 }
1166
1167 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1168 {
1169         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1170 }
1171
1172 static void abort_endio(struct request *req, blk_status_t error)
1173 {
1174         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1175         struct nvme_queue *nvmeq = iod->nvmeq;
1176
1177         dev_warn(nvmeq->dev->ctrl.device,
1178                  "Abort status: 0x%x", nvme_req(req)->status);
1179         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1180         blk_mq_free_request(req);
1181 }
1182
1183 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1184 {
1185         /* If true, indicates loss of adapter communication, possibly by a
1186          * NVMe Subsystem reset.
1187          */
1188         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1189
1190         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1191         switch (dev->ctrl.state) {
1192         case NVME_CTRL_RESETTING:
1193         case NVME_CTRL_CONNECTING:
1194                 return false;
1195         default:
1196                 break;
1197         }
1198
1199         /* We shouldn't reset unless the controller is on fatal error state
1200          * _or_ if we lost the communication with it.
1201          */
1202         if (!(csts & NVME_CSTS_CFS) && !nssro)
1203                 return false;
1204
1205         return true;
1206 }
1207
1208 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1209 {
1210         /* Read a config register to help see what died. */
1211         u16 pci_status;
1212         int result;
1213
1214         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1215                                       &pci_status);
1216         if (result == PCIBIOS_SUCCESSFUL)
1217                 dev_warn(dev->ctrl.device,
1218                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1219                          csts, pci_status);
1220         else
1221                 dev_warn(dev->ctrl.device,
1222                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1223                          csts, result);
1224 }
1225
1226 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1227 {
1228         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1229         struct nvme_queue *nvmeq = iod->nvmeq;
1230         struct nvme_dev *dev = nvmeq->dev;
1231         struct request *abort_req;
1232         struct nvme_command cmd;
1233         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1234
1235         /* If PCI error recovery process is happening, we cannot reset or
1236          * the recovery mechanism will surely fail.
1237          */
1238         mb();
1239         if (pci_channel_offline(to_pci_dev(dev->dev)))
1240                 return BLK_EH_RESET_TIMER;
1241
1242         /*
1243          * Reset immediately if the controller is failed
1244          */
1245         if (nvme_should_reset(dev, csts)) {
1246                 nvme_warn_reset(dev, csts);
1247                 nvme_dev_disable(dev, false);
1248                 nvme_reset_ctrl(&dev->ctrl);
1249                 return BLK_EH_DONE;
1250         }
1251
1252         /*
1253          * Did we miss an interrupt?
1254          */
1255         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1256                 nvme_poll(req->mq_hctx);
1257         else
1258                 nvme_poll_irqdisable(nvmeq);
1259
1260         if (blk_mq_request_completed(req)) {
1261                 dev_warn(dev->ctrl.device,
1262                          "I/O %d QID %d timeout, completion polled\n",
1263                          req->tag, nvmeq->qid);
1264                 return BLK_EH_DONE;
1265         }
1266
1267         /*
1268          * Shutdown immediately if controller times out while starting. The
1269          * reset work will see the pci device disabled when it gets the forced
1270          * cancellation error. All outstanding requests are completed on
1271          * shutdown, so we return BLK_EH_DONE.
1272          */
1273         switch (dev->ctrl.state) {
1274         case NVME_CTRL_CONNECTING:
1275                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1276                 fallthrough;
1277         case NVME_CTRL_DELETING:
1278                 dev_warn_ratelimited(dev->ctrl.device,
1279                          "I/O %d QID %d timeout, disable controller\n",
1280                          req->tag, nvmeq->qid);
1281                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1282                 nvme_dev_disable(dev, true);
1283                 return BLK_EH_DONE;
1284         case NVME_CTRL_RESETTING:
1285                 return BLK_EH_RESET_TIMER;
1286         default:
1287                 break;
1288         }
1289
1290         /*
1291          * Shutdown the controller immediately and schedule a reset if the
1292          * command was already aborted once before and still hasn't been
1293          * returned to the driver, or if this is the admin queue.
1294          */
1295         if (!nvmeq->qid || iod->aborted) {
1296                 dev_warn(dev->ctrl.device,
1297                          "I/O %d QID %d timeout, reset controller\n",
1298                          req->tag, nvmeq->qid);
1299                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1300                 nvme_dev_disable(dev, false);
1301                 nvme_reset_ctrl(&dev->ctrl);
1302
1303                 return BLK_EH_DONE;
1304         }
1305
1306         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1307                 atomic_inc(&dev->ctrl.abort_limit);
1308                 return BLK_EH_RESET_TIMER;
1309         }
1310         iod->aborted = 1;
1311
1312         memset(&cmd, 0, sizeof(cmd));
1313         cmd.abort.opcode = nvme_admin_abort_cmd;
1314         cmd.abort.cid = req->tag;
1315         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1316
1317         dev_warn(nvmeq->dev->ctrl.device,
1318                 "I/O %d QID %d timeout, aborting\n",
1319                  req->tag, nvmeq->qid);
1320
1321         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1322                         BLK_MQ_REQ_NOWAIT);
1323         if (IS_ERR(abort_req)) {
1324                 atomic_inc(&dev->ctrl.abort_limit);
1325                 return BLK_EH_RESET_TIMER;
1326         }
1327
1328         abort_req->end_io_data = NULL;
1329         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1330
1331         /*
1332          * The aborted req will be completed on receiving the abort req.
1333          * We enable the timer again. If hit twice, it'll cause a device reset,
1334          * as the device then is in a faulty state.
1335          */
1336         return BLK_EH_RESET_TIMER;
1337 }
1338
1339 static void nvme_free_queue(struct nvme_queue *nvmeq)
1340 {
1341         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1342                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1343         if (!nvmeq->sq_cmds)
1344                 return;
1345
1346         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1347                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1348                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1349         } else {
1350                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1351                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1352         }
1353 }
1354
1355 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1356 {
1357         int i;
1358
1359         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1360                 dev->ctrl.queue_count--;
1361                 nvme_free_queue(&dev->queues[i]);
1362         }
1363 }
1364
1365 /**
1366  * nvme_suspend_queue - put queue into suspended state
1367  * @nvmeq: queue to suspend
1368  */
1369 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1370 {
1371         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1372                 return 1;
1373
1374         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1375         mb();
1376
1377         nvmeq->dev->online_queues--;
1378         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1379                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1380         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1381                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1382         return 0;
1383 }
1384
1385 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1386 {
1387         int i;
1388
1389         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1390                 nvme_suspend_queue(&dev->queues[i]);
1391 }
1392
1393 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1394 {
1395         struct nvme_queue *nvmeq = &dev->queues[0];
1396
1397         if (shutdown)
1398                 nvme_shutdown_ctrl(&dev->ctrl);
1399         else
1400                 nvme_disable_ctrl(&dev->ctrl);
1401
1402         nvme_poll_irqdisable(nvmeq);
1403 }
1404
1405 /*
1406  * Called only on a device that has been disabled and after all other threads
1407  * that can check this device's completion queues have synced, except
1408  * nvme_poll(). This is the last chance for the driver to see a natural
1409  * completion before nvme_cancel_request() terminates all incomplete requests.
1410  */
1411 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1412 {
1413         int i;
1414
1415         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1416                 spin_lock(&dev->queues[i].cq_poll_lock);
1417                 nvme_process_cq(&dev->queues[i]);
1418                 spin_unlock(&dev->queues[i].cq_poll_lock);
1419         }
1420 }
1421
1422 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1423                                 int entry_size)
1424 {
1425         int q_depth = dev->q_depth;
1426         unsigned q_size_aligned = roundup(q_depth * entry_size,
1427                                           NVME_CTRL_PAGE_SIZE);
1428
1429         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1430                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1431
1432                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1433                 q_depth = div_u64(mem_per_q, entry_size);
1434
1435                 /*
1436                  * Ensure the reduced q_depth is above some threshold where it
1437                  * would be better to map queues in system memory with the
1438                  * original depth
1439                  */
1440                 if (q_depth < 64)
1441                         return -ENOMEM;
1442         }
1443
1444         return q_depth;
1445 }
1446
1447 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1448                                 int qid)
1449 {
1450         struct pci_dev *pdev = to_pci_dev(dev->dev);
1451
1452         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1453                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1454                 if (nvmeq->sq_cmds) {
1455                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1456                                                         nvmeq->sq_cmds);
1457                         if (nvmeq->sq_dma_addr) {
1458                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1459                                 return 0;
1460                         }
1461
1462                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1463                 }
1464         }
1465
1466         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1467                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1468         if (!nvmeq->sq_cmds)
1469                 return -ENOMEM;
1470         return 0;
1471 }
1472
1473 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1474 {
1475         struct nvme_queue *nvmeq = &dev->queues[qid];
1476
1477         if (dev->ctrl.queue_count > qid)
1478                 return 0;
1479
1480         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1481         nvmeq->q_depth = depth;
1482         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1483                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1484         if (!nvmeq->cqes)
1485                 goto free_nvmeq;
1486
1487         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1488                 goto free_cqdma;
1489
1490         nvmeq->dev = dev;
1491         spin_lock_init(&nvmeq->sq_lock);
1492         spin_lock_init(&nvmeq->cq_poll_lock);
1493         nvmeq->cq_head = 0;
1494         nvmeq->cq_phase = 1;
1495         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1496         nvmeq->qid = qid;
1497         dev->ctrl.queue_count++;
1498
1499         return 0;
1500
1501  free_cqdma:
1502         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1503                           nvmeq->cq_dma_addr);
1504  free_nvmeq:
1505         return -ENOMEM;
1506 }
1507
1508 static int queue_request_irq(struct nvme_queue *nvmeq)
1509 {
1510         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1511         int nr = nvmeq->dev->ctrl.instance;
1512
1513         if (use_threaded_interrupts) {
1514                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1515                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1516         } else {
1517                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1518                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1519         }
1520 }
1521
1522 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1523 {
1524         struct nvme_dev *dev = nvmeq->dev;
1525
1526         nvmeq->sq_tail = 0;
1527         nvmeq->last_sq_tail = 0;
1528         nvmeq->cq_head = 0;
1529         nvmeq->cq_phase = 1;
1530         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1531         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1532         nvme_dbbuf_init(dev, nvmeq, qid);
1533         dev->online_queues++;
1534         wmb(); /* ensure the first interrupt sees the initialization */
1535 }
1536
1537 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1538 {
1539         struct nvme_dev *dev = nvmeq->dev;
1540         int result;
1541         u16 vector = 0;
1542
1543         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1544
1545         /*
1546          * A queue's vector matches the queue identifier unless the controller
1547          * has only one vector available.
1548          */
1549         if (!polled)
1550                 vector = dev->num_vecs == 1 ? 0 : qid;
1551         else
1552                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1553
1554         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1555         if (result)
1556                 return result;
1557
1558         result = adapter_alloc_sq(dev, qid, nvmeq);
1559         if (result < 0)
1560                 return result;
1561         if (result)
1562                 goto release_cq;
1563
1564         nvmeq->cq_vector = vector;
1565         nvme_init_queue(nvmeq, qid);
1566
1567         if (!polled) {
1568                 result = queue_request_irq(nvmeq);
1569                 if (result < 0)
1570                         goto release_sq;
1571         }
1572
1573         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1574         return result;
1575
1576 release_sq:
1577         dev->online_queues--;
1578         adapter_delete_sq(dev, qid);
1579 release_cq:
1580         adapter_delete_cq(dev, qid);
1581         return result;
1582 }
1583
1584 static const struct blk_mq_ops nvme_mq_admin_ops = {
1585         .queue_rq       = nvme_queue_rq,
1586         .complete       = nvme_pci_complete_rq,
1587         .init_hctx      = nvme_admin_init_hctx,
1588         .init_request   = nvme_init_request,
1589         .timeout        = nvme_timeout,
1590 };
1591
1592 static const struct blk_mq_ops nvme_mq_ops = {
1593         .queue_rq       = nvme_queue_rq,
1594         .complete       = nvme_pci_complete_rq,
1595         .commit_rqs     = nvme_commit_rqs,
1596         .init_hctx      = nvme_init_hctx,
1597         .init_request   = nvme_init_request,
1598         .map_queues     = nvme_pci_map_queues,
1599         .timeout        = nvme_timeout,
1600         .poll           = nvme_poll,
1601 };
1602
1603 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1604 {
1605         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1606                 /*
1607                  * If the controller was reset during removal, it's possible
1608                  * user requests may be waiting on a stopped queue. Start the
1609                  * queue to flush these to completion.
1610                  */
1611                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1612                 blk_cleanup_queue(dev->ctrl.admin_q);
1613                 blk_mq_free_tag_set(&dev->admin_tagset);
1614         }
1615 }
1616
1617 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1618 {
1619         if (!dev->ctrl.admin_q) {
1620                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1621                 dev->admin_tagset.nr_hw_queues = 1;
1622
1623                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1624                 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1625                 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1626                 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1627                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1628                 dev->admin_tagset.driver_data = dev;
1629
1630                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1631                         return -ENOMEM;
1632                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1633
1634                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1635                 if (IS_ERR(dev->ctrl.admin_q)) {
1636                         blk_mq_free_tag_set(&dev->admin_tagset);
1637                         return -ENOMEM;
1638                 }
1639                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1640                         nvme_dev_remove_admin(dev);
1641                         dev->ctrl.admin_q = NULL;
1642                         return -ENODEV;
1643                 }
1644         } else
1645                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1646
1647         return 0;
1648 }
1649
1650 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1651 {
1652         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1653 }
1654
1655 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1656 {
1657         struct pci_dev *pdev = to_pci_dev(dev->dev);
1658
1659         if (size <= dev->bar_mapped_size)
1660                 return 0;
1661         if (size > pci_resource_len(pdev, 0))
1662                 return -ENOMEM;
1663         if (dev->bar)
1664                 iounmap(dev->bar);
1665         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1666         if (!dev->bar) {
1667                 dev->bar_mapped_size = 0;
1668                 return -ENOMEM;
1669         }
1670         dev->bar_mapped_size = size;
1671         dev->dbs = dev->bar + NVME_REG_DBS;
1672
1673         return 0;
1674 }
1675
1676 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1677 {
1678         int result;
1679         u32 aqa;
1680         struct nvme_queue *nvmeq;
1681
1682         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1683         if (result < 0)
1684                 return result;
1685
1686         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1687                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1688
1689         if (dev->subsystem &&
1690             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1691                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1692
1693         result = nvme_disable_ctrl(&dev->ctrl);
1694         if (result < 0)
1695                 return result;
1696
1697         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1698         if (result)
1699                 return result;
1700
1701         dev->ctrl.numa_node = dev_to_node(dev->dev);
1702
1703         nvmeq = &dev->queues[0];
1704         aqa = nvmeq->q_depth - 1;
1705         aqa |= aqa << 16;
1706
1707         writel(aqa, dev->bar + NVME_REG_AQA);
1708         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1709         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1710
1711         result = nvme_enable_ctrl(&dev->ctrl);
1712         if (result)
1713                 return result;
1714
1715         nvmeq->cq_vector = 0;
1716         nvme_init_queue(nvmeq, 0);
1717         result = queue_request_irq(nvmeq);
1718         if (result) {
1719                 dev->online_queues--;
1720                 return result;
1721         }
1722
1723         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1724         return result;
1725 }
1726
1727 static int nvme_create_io_queues(struct nvme_dev *dev)
1728 {
1729         unsigned i, max, rw_queues;
1730         int ret = 0;
1731
1732         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1733                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1734                         ret = -ENOMEM;
1735                         break;
1736                 }
1737         }
1738
1739         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1740         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1741                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1742                                 dev->io_queues[HCTX_TYPE_READ];
1743         } else {
1744                 rw_queues = max;
1745         }
1746
1747         for (i = dev->online_queues; i <= max; i++) {
1748                 bool polled = i > rw_queues;
1749
1750                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1751                 if (ret)
1752                         break;
1753         }
1754
1755         /*
1756          * Ignore failing Create SQ/CQ commands, we can continue with less
1757          * than the desired amount of queues, and even a controller without
1758          * I/O queues can still be used to issue admin commands.  This might
1759          * be useful to upgrade a buggy firmware for example.
1760          */
1761         return ret >= 0 ? 0 : ret;
1762 }
1763
1764 static ssize_t nvme_cmb_show(struct device *dev,
1765                              struct device_attribute *attr,
1766                              char *buf)
1767 {
1768         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1769
1770         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1771                        ndev->cmbloc, ndev->cmbsz);
1772 }
1773 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1774
1775 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1776 {
1777         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1778
1779         return 1ULL << (12 + 4 * szu);
1780 }
1781
1782 static u32 nvme_cmb_size(struct nvme_dev *dev)
1783 {
1784         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1785 }
1786
1787 static void nvme_map_cmb(struct nvme_dev *dev)
1788 {
1789         u64 size, offset;
1790         resource_size_t bar_size;
1791         struct pci_dev *pdev = to_pci_dev(dev->dev);
1792         int bar;
1793
1794         if (dev->cmb_size)
1795                 return;
1796
1797         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1798         if (!dev->cmbsz)
1799                 return;
1800         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1801
1802         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1803         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1804         bar = NVME_CMB_BIR(dev->cmbloc);
1805         bar_size = pci_resource_len(pdev, bar);
1806
1807         if (offset > bar_size)
1808                 return;
1809
1810         /*
1811          * Controllers may support a CMB size larger than their BAR,
1812          * for example, due to being behind a bridge. Reduce the CMB to
1813          * the reported size of the BAR
1814          */
1815         if (size > bar_size - offset)
1816                 size = bar_size - offset;
1817
1818         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1819                 dev_warn(dev->ctrl.device,
1820                          "failed to register the CMB\n");
1821                 return;
1822         }
1823
1824         dev->cmb_size = size;
1825         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1826
1827         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1828                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1829                 pci_p2pmem_publish(pdev, true);
1830
1831         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1832                                     &dev_attr_cmb.attr, NULL))
1833                 dev_warn(dev->ctrl.device,
1834                          "failed to add sysfs attribute for CMB\n");
1835 }
1836
1837 static inline void nvme_release_cmb(struct nvme_dev *dev)
1838 {
1839         if (dev->cmb_size) {
1840                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1841                                              &dev_attr_cmb.attr, NULL);
1842                 dev->cmb_size = 0;
1843         }
1844 }
1845
1846 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1847 {
1848         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1849         u64 dma_addr = dev->host_mem_descs_dma;
1850         struct nvme_command c;
1851         int ret;
1852
1853         memset(&c, 0, sizeof(c));
1854         c.features.opcode       = nvme_admin_set_features;
1855         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1856         c.features.dword11      = cpu_to_le32(bits);
1857         c.features.dword12      = cpu_to_le32(host_mem_size);
1858         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1859         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1860         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1861
1862         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1863         if (ret) {
1864                 dev_warn(dev->ctrl.device,
1865                          "failed to set host mem (err %d, flags %#x).\n",
1866                          ret, bits);
1867         }
1868         return ret;
1869 }
1870
1871 static void nvme_free_host_mem(struct nvme_dev *dev)
1872 {
1873         int i;
1874
1875         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1876                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1877                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1878
1879                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1880                                le64_to_cpu(desc->addr),
1881                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1882         }
1883
1884         kfree(dev->host_mem_desc_bufs);
1885         dev->host_mem_desc_bufs = NULL;
1886         dma_free_coherent(dev->dev,
1887                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1888                         dev->host_mem_descs, dev->host_mem_descs_dma);
1889         dev->host_mem_descs = NULL;
1890         dev->nr_host_mem_descs = 0;
1891 }
1892
1893 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1894                 u32 chunk_size)
1895 {
1896         struct nvme_host_mem_buf_desc *descs;
1897         u32 max_entries, len;
1898         dma_addr_t descs_dma;
1899         int i = 0;
1900         void **bufs;
1901         u64 size, tmp;
1902
1903         tmp = (preferred + chunk_size - 1);
1904         do_div(tmp, chunk_size);
1905         max_entries = tmp;
1906
1907         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1908                 max_entries = dev->ctrl.hmmaxd;
1909
1910         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1911                                    &descs_dma, GFP_KERNEL);
1912         if (!descs)
1913                 goto out;
1914
1915         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1916         if (!bufs)
1917                 goto out_free_descs;
1918
1919         for (size = 0; size < preferred && i < max_entries; size += len) {
1920                 dma_addr_t dma_addr;
1921
1922                 len = min_t(u64, chunk_size, preferred - size);
1923                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1924                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1925                 if (!bufs[i])
1926                         break;
1927
1928                 descs[i].addr = cpu_to_le64(dma_addr);
1929                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1930                 i++;
1931         }
1932
1933         if (!size)
1934                 goto out_free_bufs;
1935
1936         dev->nr_host_mem_descs = i;
1937         dev->host_mem_size = size;
1938         dev->host_mem_descs = descs;
1939         dev->host_mem_descs_dma = descs_dma;
1940         dev->host_mem_desc_bufs = bufs;
1941         return 0;
1942
1943 out_free_bufs:
1944         while (--i >= 0) {
1945                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1946
1947                 dma_free_attrs(dev->dev, size, bufs[i],
1948                                le64_to_cpu(descs[i].addr),
1949                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1950         }
1951
1952         kfree(bufs);
1953 out_free_descs:
1954         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1955                         descs_dma);
1956 out:
1957         dev->host_mem_descs = NULL;
1958         return -ENOMEM;
1959 }
1960
1961 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1962 {
1963         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1964         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1965         u64 chunk_size;
1966
1967         /* start big and work our way down */
1968         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
1969                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1970                         if (!min || dev->host_mem_size >= min)
1971                                 return 0;
1972                         nvme_free_host_mem(dev);
1973                 }
1974         }
1975
1976         return -ENOMEM;
1977 }
1978
1979 static int nvme_setup_host_mem(struct nvme_dev *dev)
1980 {
1981         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1982         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1983         u64 min = (u64)dev->ctrl.hmmin * 4096;
1984         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1985         int ret;
1986
1987         preferred = min(preferred, max);
1988         if (min > max) {
1989                 dev_warn(dev->ctrl.device,
1990                         "min host memory (%lld MiB) above limit (%d MiB).\n",
1991                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
1992                 nvme_free_host_mem(dev);
1993                 return 0;
1994         }
1995
1996         /*
1997          * If we already have a buffer allocated check if we can reuse it.
1998          */
1999         if (dev->host_mem_descs) {
2000                 if (dev->host_mem_size >= min)
2001                         enable_bits |= NVME_HOST_MEM_RETURN;
2002                 else
2003                         nvme_free_host_mem(dev);
2004         }
2005
2006         if (!dev->host_mem_descs) {
2007                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2008                         dev_warn(dev->ctrl.device,
2009                                 "failed to allocate host memory buffer.\n");
2010                         return 0; /* controller must work without HMB */
2011                 }
2012
2013                 dev_info(dev->ctrl.device,
2014                         "allocated %lld MiB host memory buffer.\n",
2015                         dev->host_mem_size >> ilog2(SZ_1M));
2016         }
2017
2018         ret = nvme_set_host_mem(dev, enable_bits);
2019         if (ret)
2020                 nvme_free_host_mem(dev);
2021         return ret;
2022 }
2023
2024 /*
2025  * nirqs is the number of interrupts available for write and read
2026  * queues. The core already reserved an interrupt for the admin queue.
2027  */
2028 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2029 {
2030         struct nvme_dev *dev = affd->priv;
2031         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2032
2033         /*
2034          * If there is no interrupt available for queues, ensure that
2035          * the default queue is set to 1. The affinity set size is
2036          * also set to one, but the irq core ignores it for this case.
2037          *
2038          * If only one interrupt is available or 'write_queue' == 0, combine
2039          * write and read queues.
2040          *
2041          * If 'write_queues' > 0, ensure it leaves room for at least one read
2042          * queue.
2043          */
2044         if (!nrirqs) {
2045                 nrirqs = 1;
2046                 nr_read_queues = 0;
2047         } else if (nrirqs == 1 || !nr_write_queues) {
2048                 nr_read_queues = 0;
2049         } else if (nr_write_queues >= nrirqs) {
2050                 nr_read_queues = 1;
2051         } else {
2052                 nr_read_queues = nrirqs - nr_write_queues;
2053         }
2054
2055         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2056         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2057         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2058         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2059         affd->nr_sets = nr_read_queues ? 2 : 1;
2060 }
2061
2062 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2063 {
2064         struct pci_dev *pdev = to_pci_dev(dev->dev);
2065         struct irq_affinity affd = {
2066                 .pre_vectors    = 1,
2067                 .calc_sets      = nvme_calc_irq_sets,
2068                 .priv           = dev,
2069         };
2070         unsigned int irq_queues, poll_queues;
2071
2072         /*
2073          * Poll queues don't need interrupts, but we need at least one I/O queue
2074          * left over for non-polled I/O.
2075          */
2076         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2077         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2078
2079         /*
2080          * Initialize for the single interrupt case, will be updated in
2081          * nvme_calc_irq_sets().
2082          */
2083         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2084         dev->io_queues[HCTX_TYPE_READ] = 0;
2085
2086         /*
2087          * We need interrupts for the admin queue and each non-polled I/O queue,
2088          * but some Apple controllers require all queues to use the first
2089          * vector.
2090          */
2091         irq_queues = 1;
2092         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2093                 irq_queues += (nr_io_queues - poll_queues);
2094         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2095                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2096 }
2097
2098 static void nvme_disable_io_queues(struct nvme_dev *dev)
2099 {
2100         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2101                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2102 }
2103
2104 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2105 {
2106         /*
2107          * If tags are shared with admin queue (Apple bug), then
2108          * make sure we only use one IO queue.
2109          */
2110         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2111                 return 1;
2112         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2113 }
2114
2115 static int nvme_setup_io_queues(struct nvme_dev *dev)
2116 {
2117         struct nvme_queue *adminq = &dev->queues[0];
2118         struct pci_dev *pdev = to_pci_dev(dev->dev);
2119         unsigned int nr_io_queues;
2120         unsigned long size;
2121         int result;
2122
2123         /*
2124          * Sample the module parameters once at reset time so that we have
2125          * stable values to work with.
2126          */
2127         dev->nr_write_queues = write_queues;
2128         dev->nr_poll_queues = poll_queues;
2129
2130         nr_io_queues = dev->nr_allocated_queues - 1;
2131         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2132         if (result < 0)
2133                 return result;
2134
2135         if (nr_io_queues == 0)
2136                 return 0;
2137
2138         clear_bit(NVMEQ_ENABLED, &adminq->flags);
2139
2140         if (dev->cmb_use_sqes) {
2141                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2142                                 sizeof(struct nvme_command));
2143                 if (result > 0)
2144                         dev->q_depth = result;
2145                 else
2146                         dev->cmb_use_sqes = false;
2147         }
2148
2149         do {
2150                 size = db_bar_size(dev, nr_io_queues);
2151                 result = nvme_remap_bar(dev, size);
2152                 if (!result)
2153                         break;
2154                 if (!--nr_io_queues)
2155                         return -ENOMEM;
2156         } while (1);
2157         adminq->q_db = dev->dbs;
2158
2159  retry:
2160         /* Deregister the admin queue's interrupt */
2161         pci_free_irq(pdev, 0, adminq);
2162
2163         /*
2164          * If we enable msix early due to not intx, disable it again before
2165          * setting up the full range we need.
2166          */
2167         pci_free_irq_vectors(pdev);
2168
2169         result = nvme_setup_irqs(dev, nr_io_queues);
2170         if (result <= 0)
2171                 return -EIO;
2172
2173         dev->num_vecs = result;
2174         result = max(result - 1, 1);
2175         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2176
2177         /*
2178          * Should investigate if there's a performance win from allocating
2179          * more queues than interrupt vectors; it might allow the submission
2180          * path to scale better, even if the receive path is limited by the
2181          * number of interrupts.
2182          */
2183         result = queue_request_irq(adminq);
2184         if (result)
2185                 return result;
2186         set_bit(NVMEQ_ENABLED, &adminq->flags);
2187
2188         result = nvme_create_io_queues(dev);
2189         if (result || dev->online_queues < 2)
2190                 return result;
2191
2192         if (dev->online_queues - 1 < dev->max_qid) {
2193                 nr_io_queues = dev->online_queues - 1;
2194                 nvme_disable_io_queues(dev);
2195                 nvme_suspend_io_queues(dev);
2196                 goto retry;
2197         }
2198         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2199                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2200                                         dev->io_queues[HCTX_TYPE_READ],
2201                                         dev->io_queues[HCTX_TYPE_POLL]);
2202         return 0;
2203 }
2204
2205 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2206 {
2207         struct nvme_queue *nvmeq = req->end_io_data;
2208
2209         blk_mq_free_request(req);
2210         complete(&nvmeq->delete_done);
2211 }
2212
2213 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2214 {
2215         struct nvme_queue *nvmeq = req->end_io_data;
2216
2217         if (error)
2218                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2219
2220         nvme_del_queue_end(req, error);
2221 }
2222
2223 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2224 {
2225         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2226         struct request *req;
2227         struct nvme_command cmd;
2228
2229         memset(&cmd, 0, sizeof(cmd));
2230         cmd.delete_queue.opcode = opcode;
2231         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2232
2233         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2234         if (IS_ERR(req))
2235                 return PTR_ERR(req);
2236
2237         req->end_io_data = nvmeq;
2238
2239         init_completion(&nvmeq->delete_done);
2240         blk_execute_rq_nowait(q, NULL, req, false,
2241                         opcode == nvme_admin_delete_cq ?
2242                                 nvme_del_cq_end : nvme_del_queue_end);
2243         return 0;
2244 }
2245
2246 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2247 {
2248         int nr_queues = dev->online_queues - 1, sent = 0;
2249         unsigned long timeout;
2250
2251  retry:
2252         timeout = NVME_ADMIN_TIMEOUT;
2253         while (nr_queues > 0) {
2254                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2255                         break;
2256                 nr_queues--;
2257                 sent++;
2258         }
2259         while (sent) {
2260                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2261
2262                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2263                                 timeout);
2264                 if (timeout == 0)
2265                         return false;
2266
2267                 sent--;
2268                 if (nr_queues)
2269                         goto retry;
2270         }
2271         return true;
2272 }
2273
2274 static void nvme_dev_add(struct nvme_dev *dev)
2275 {
2276         int ret;
2277
2278         if (!dev->ctrl.tagset) {
2279                 dev->tagset.ops = &nvme_mq_ops;
2280                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2281                 dev->tagset.nr_maps = 2; /* default + read */
2282                 if (dev->io_queues[HCTX_TYPE_POLL])
2283                         dev->tagset.nr_maps++;
2284                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2285                 dev->tagset.numa_node = dev->ctrl.numa_node;
2286                 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2287                                                 BLK_MQ_MAX_DEPTH) - 1;
2288                 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2289                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2290                 dev->tagset.driver_data = dev;
2291
2292                 /*
2293                  * Some Apple controllers requires tags to be unique
2294                  * across admin and IO queue, so reserve the first 32
2295                  * tags of the IO queue.
2296                  */
2297                 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2298                         dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2299
2300                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2301                 if (ret) {
2302                         dev_warn(dev->ctrl.device,
2303                                 "IO queues tagset allocation failed %d\n", ret);
2304                         return;
2305                 }
2306                 dev->ctrl.tagset = &dev->tagset;
2307         } else {
2308                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2309
2310                 /* Free previously allocated queues that are no longer usable */
2311                 nvme_free_queues(dev, dev->online_queues);
2312         }
2313
2314         nvme_dbbuf_set(dev);
2315 }
2316
2317 static int nvme_pci_enable(struct nvme_dev *dev)
2318 {
2319         int result = -ENOMEM;
2320         struct pci_dev *pdev = to_pci_dev(dev->dev);
2321
2322         if (pci_enable_device_mem(pdev))
2323                 return result;
2324
2325         pci_set_master(pdev);
2326
2327         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2328                 goto disable;
2329
2330         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2331                 result = -ENODEV;
2332                 goto disable;
2333         }
2334
2335         /*
2336          * Some devices and/or platforms don't advertise or work with INTx
2337          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2338          * adjust this later.
2339          */
2340         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2341         if (result < 0)
2342                 return result;
2343
2344         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2345
2346         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2347                                 io_queue_depth);
2348         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2349         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2350         dev->dbs = dev->bar + 4096;
2351
2352         /*
2353          * Some Apple controllers require a non-standard SQE size.
2354          * Interestingly they also seem to ignore the CC:IOSQES register
2355          * so we don't bother updating it here.
2356          */
2357         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2358                 dev->io_sqes = 7;
2359         else
2360                 dev->io_sqes = NVME_NVM_IOSQES;
2361
2362         /*
2363          * Temporary fix for the Apple controller found in the MacBook8,1 and
2364          * some MacBook7,1 to avoid controller resets and data loss.
2365          */
2366         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2367                 dev->q_depth = 2;
2368                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2369                         "set queue depth=%u to work around controller resets\n",
2370                         dev->q_depth);
2371         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2372                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2373                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2374                 dev->q_depth = 64;
2375                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2376                         "set queue depth=%u\n", dev->q_depth);
2377         }
2378
2379         /*
2380          * Controllers with the shared tags quirk need the IO queue to be
2381          * big enough so that we get 32 tags for the admin queue
2382          */
2383         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2384             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2385                 dev->q_depth = NVME_AQ_DEPTH + 2;
2386                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2387                          dev->q_depth);
2388         }
2389
2390
2391         nvme_map_cmb(dev);
2392
2393         pci_enable_pcie_error_reporting(pdev);
2394         pci_save_state(pdev);
2395         return 0;
2396
2397  disable:
2398         pci_disable_device(pdev);
2399         return result;
2400 }
2401
2402 static void nvme_dev_unmap(struct nvme_dev *dev)
2403 {
2404         if (dev->bar)
2405                 iounmap(dev->bar);
2406         pci_release_mem_regions(to_pci_dev(dev->dev));
2407 }
2408
2409 static void nvme_pci_disable(struct nvme_dev *dev)
2410 {
2411         struct pci_dev *pdev = to_pci_dev(dev->dev);
2412
2413         pci_free_irq_vectors(pdev);
2414
2415         if (pci_is_enabled(pdev)) {
2416                 pci_disable_pcie_error_reporting(pdev);
2417                 pci_disable_device(pdev);
2418         }
2419 }
2420
2421 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2422 {
2423         bool dead = true, freeze = false;
2424         struct pci_dev *pdev = to_pci_dev(dev->dev);
2425
2426         mutex_lock(&dev->shutdown_lock);
2427         if (pci_is_enabled(pdev)) {
2428                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2429
2430                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2431                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2432                         freeze = true;
2433                         nvme_start_freeze(&dev->ctrl);
2434                 }
2435                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2436                         pdev->error_state  != pci_channel_io_normal);
2437         }
2438
2439         /*
2440          * Give the controller a chance to complete all entered requests if
2441          * doing a safe shutdown.
2442          */
2443         if (!dead && shutdown && freeze)
2444                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2445
2446         nvme_stop_queues(&dev->ctrl);
2447
2448         if (!dead && dev->ctrl.queue_count > 0) {
2449                 nvme_disable_io_queues(dev);
2450                 nvme_disable_admin_queue(dev, shutdown);
2451         }
2452         nvme_suspend_io_queues(dev);
2453         nvme_suspend_queue(&dev->queues[0]);
2454         nvme_pci_disable(dev);
2455         nvme_reap_pending_cqes(dev);
2456
2457         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2458         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2459         blk_mq_tagset_wait_completed_request(&dev->tagset);
2460         blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2461
2462         /*
2463          * The driver will not be starting up queues again if shutting down so
2464          * must flush all entered requests to their failed completion to avoid
2465          * deadlocking blk-mq hot-cpu notifier.
2466          */
2467         if (shutdown) {
2468                 nvme_start_queues(&dev->ctrl);
2469                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2470                         blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2471         }
2472         mutex_unlock(&dev->shutdown_lock);
2473 }
2474
2475 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2476 {
2477         if (!nvme_wait_reset(&dev->ctrl))
2478                 return -EBUSY;
2479         nvme_dev_disable(dev, shutdown);
2480         return 0;
2481 }
2482
2483 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2484 {
2485         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2486                                                 NVME_CTRL_PAGE_SIZE,
2487                                                 NVME_CTRL_PAGE_SIZE, 0);
2488         if (!dev->prp_page_pool)
2489                 return -ENOMEM;
2490
2491         /* Optimisation for I/Os between 4k and 128k */
2492         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2493                                                 256, 256, 0);
2494         if (!dev->prp_small_pool) {
2495                 dma_pool_destroy(dev->prp_page_pool);
2496                 return -ENOMEM;
2497         }
2498         return 0;
2499 }
2500
2501 static void nvme_release_prp_pools(struct nvme_dev *dev)
2502 {
2503         dma_pool_destroy(dev->prp_page_pool);
2504         dma_pool_destroy(dev->prp_small_pool);
2505 }
2506
2507 static void nvme_free_tagset(struct nvme_dev *dev)
2508 {
2509         if (dev->tagset.tags)
2510                 blk_mq_free_tag_set(&dev->tagset);
2511         dev->ctrl.tagset = NULL;
2512 }
2513
2514 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2515 {
2516         struct nvme_dev *dev = to_nvme_dev(ctrl);
2517
2518         nvme_dbbuf_dma_free(dev);
2519         nvme_free_tagset(dev);
2520         if (dev->ctrl.admin_q)
2521                 blk_put_queue(dev->ctrl.admin_q);
2522         free_opal_dev(dev->ctrl.opal_dev);
2523         mempool_destroy(dev->iod_mempool);
2524         put_device(dev->dev);
2525         kfree(dev->queues);
2526         kfree(dev);
2527 }
2528
2529 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2530 {
2531         /*
2532          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2533          * may be holding this pci_dev's device lock.
2534          */
2535         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2536         nvme_get_ctrl(&dev->ctrl);
2537         nvme_dev_disable(dev, false);
2538         nvme_kill_queues(&dev->ctrl);
2539         if (!queue_work(nvme_wq, &dev->remove_work))
2540                 nvme_put_ctrl(&dev->ctrl);
2541 }
2542
2543 static void nvme_reset_work(struct work_struct *work)
2544 {
2545         struct nvme_dev *dev =
2546                 container_of(work, struct nvme_dev, ctrl.reset_work);
2547         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2548         int result;
2549
2550         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2551                 result = -ENODEV;
2552                 goto out;
2553         }
2554
2555         /*
2556          * If we're called to reset a live controller first shut it down before
2557          * moving on.
2558          */
2559         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2560                 nvme_dev_disable(dev, false);
2561         nvme_sync_queues(&dev->ctrl);
2562
2563         mutex_lock(&dev->shutdown_lock);
2564         result = nvme_pci_enable(dev);
2565         if (result)
2566                 goto out_unlock;
2567
2568         result = nvme_pci_configure_admin_queue(dev);
2569         if (result)
2570                 goto out_unlock;
2571
2572         result = nvme_alloc_admin_tags(dev);
2573         if (result)
2574                 goto out_unlock;
2575
2576         /*
2577          * Limit the max command size to prevent iod->sg allocations going
2578          * over a single page.
2579          */
2580         dev->ctrl.max_hw_sectors = min_t(u32,
2581                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2582         dev->ctrl.max_segments = NVME_MAX_SEGS;
2583
2584         /*
2585          * Don't limit the IOMMU merged segment size.
2586          */
2587         dma_set_max_seg_size(dev->dev, 0xffffffff);
2588
2589         mutex_unlock(&dev->shutdown_lock);
2590
2591         /*
2592          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2593          * initializing procedure here.
2594          */
2595         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2596                 dev_warn(dev->ctrl.device,
2597                         "failed to mark controller CONNECTING\n");
2598                 result = -EBUSY;
2599                 goto out;
2600         }
2601
2602         /*
2603          * We do not support an SGL for metadata (yet), so we are limited to a
2604          * single integrity segment for the separate metadata pointer.
2605          */
2606         dev->ctrl.max_integrity_segments = 1;
2607
2608         result = nvme_init_identify(&dev->ctrl);
2609         if (result)
2610                 goto out;
2611
2612         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2613                 if (!dev->ctrl.opal_dev)
2614                         dev->ctrl.opal_dev =
2615                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2616                 else if (was_suspend)
2617                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2618         } else {
2619                 free_opal_dev(dev->ctrl.opal_dev);
2620                 dev->ctrl.opal_dev = NULL;
2621         }
2622
2623         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2624                 result = nvme_dbbuf_dma_alloc(dev);
2625                 if (result)
2626                         dev_warn(dev->dev,
2627                                  "unable to allocate dma for dbbuf\n");
2628         }
2629
2630         if (dev->ctrl.hmpre) {
2631                 result = nvme_setup_host_mem(dev);
2632                 if (result < 0)
2633                         goto out;
2634         }
2635
2636         result = nvme_setup_io_queues(dev);
2637         if (result)
2638                 goto out;
2639
2640         /*
2641          * Keep the controller around but remove all namespaces if we don't have
2642          * any working I/O queue.
2643          */
2644         if (dev->online_queues < 2) {
2645                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2646                 nvme_kill_queues(&dev->ctrl);
2647                 nvme_remove_namespaces(&dev->ctrl);
2648                 nvme_free_tagset(dev);
2649         } else {
2650                 nvme_start_queues(&dev->ctrl);
2651                 nvme_wait_freeze(&dev->ctrl);
2652                 nvme_dev_add(dev);
2653                 nvme_unfreeze(&dev->ctrl);
2654         }
2655
2656         /*
2657          * If only admin queue live, keep it to do further investigation or
2658          * recovery.
2659          */
2660         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2661                 dev_warn(dev->ctrl.device,
2662                         "failed to mark controller live state\n");
2663                 result = -ENODEV;
2664                 goto out;
2665         }
2666
2667         nvme_start_ctrl(&dev->ctrl);
2668         return;
2669
2670  out_unlock:
2671         mutex_unlock(&dev->shutdown_lock);
2672  out:
2673         if (result)
2674                 dev_warn(dev->ctrl.device,
2675                          "Removing after probe failure status: %d\n", result);
2676         nvme_remove_dead_ctrl(dev);
2677 }
2678
2679 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2680 {
2681         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2682         struct pci_dev *pdev = to_pci_dev(dev->dev);
2683
2684         if (pci_get_drvdata(pdev))
2685                 device_release_driver(&pdev->dev);
2686         nvme_put_ctrl(&dev->ctrl);
2687 }
2688
2689 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2690 {
2691         *val = readl(to_nvme_dev(ctrl)->bar + off);
2692         return 0;
2693 }
2694
2695 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2696 {
2697         writel(val, to_nvme_dev(ctrl)->bar + off);
2698         return 0;
2699 }
2700
2701 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2702 {
2703         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2704         return 0;
2705 }
2706
2707 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2708 {
2709         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2710
2711         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2712 }
2713
2714 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2715         .name                   = "pcie",
2716         .module                 = THIS_MODULE,
2717         .flags                  = NVME_F_METADATA_SUPPORTED |
2718                                   NVME_F_PCI_P2PDMA,
2719         .reg_read32             = nvme_pci_reg_read32,
2720         .reg_write32            = nvme_pci_reg_write32,
2721         .reg_read64             = nvme_pci_reg_read64,
2722         .free_ctrl              = nvme_pci_free_ctrl,
2723         .submit_async_event     = nvme_pci_submit_async_event,
2724         .get_address            = nvme_pci_get_address,
2725 };
2726
2727 static int nvme_dev_map(struct nvme_dev *dev)
2728 {
2729         struct pci_dev *pdev = to_pci_dev(dev->dev);
2730
2731         if (pci_request_mem_regions(pdev, "nvme"))
2732                 return -ENODEV;
2733
2734         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2735                 goto release;
2736
2737         return 0;
2738   release:
2739         pci_release_mem_regions(pdev);
2740         return -ENODEV;
2741 }
2742
2743 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2744 {
2745         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2746                 /*
2747                  * Several Samsung devices seem to drop off the PCIe bus
2748                  * randomly when APST is on and uses the deepest sleep state.
2749                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2750                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2751                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2752                  * laptops.
2753                  */
2754                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2755                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2756                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2757                         return NVME_QUIRK_NO_DEEPEST_PS;
2758         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2759                 /*
2760                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2761                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2762                  * within few minutes after bootup on a Coffee Lake board -
2763                  * ASUS PRIME Z370-A
2764                  */
2765                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2766                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2767                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2768                         return NVME_QUIRK_NO_APST;
2769         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2770                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2771                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2772                 /*
2773                  * Forcing to use host managed nvme power settings for
2774                  * lowest idle power with quick resume latency on
2775                  * Samsung and Toshiba SSDs based on suspend behavior
2776                  * on Coffee Lake board for LENOVO C640
2777                  */
2778                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2779                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2780                         return NVME_QUIRK_SIMPLE_SUSPEND;
2781         }
2782
2783         return 0;
2784 }
2785
2786 #ifdef CONFIG_ACPI
2787 static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2788 {
2789         struct acpi_device *adev;
2790         struct pci_dev *root;
2791         acpi_handle handle;
2792         acpi_status status;
2793         u8 val;
2794
2795         /*
2796          * Look for _DSD property specifying that the storage device on the port
2797          * must use D3 to support deep platform power savings during
2798          * suspend-to-idle.
2799          */
2800         root = pcie_find_root_port(dev);
2801         if (!root)
2802                 return false;
2803
2804         adev = ACPI_COMPANION(&root->dev);
2805         if (!adev)
2806                 return false;
2807
2808         /*
2809          * The property is defined in the PXSX device for South complex ports
2810          * and in the PEGP device for North complex ports.
2811          */
2812         status = acpi_get_handle(adev->handle, "PXSX", &handle);
2813         if (ACPI_FAILURE(status)) {
2814                 status = acpi_get_handle(adev->handle, "PEGP", &handle);
2815                 if (ACPI_FAILURE(status))
2816                         return false;
2817         }
2818
2819         if (acpi_bus_get_device(handle, &adev))
2820                 return false;
2821
2822         if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2823                         &val))
2824                 return false;
2825         return val == 1;
2826 }
2827 #else
2828 static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2829 {
2830         return false;
2831 }
2832 #endif /* CONFIG_ACPI */
2833
2834 static void nvme_async_probe(void *data, async_cookie_t cookie)
2835 {
2836         struct nvme_dev *dev = data;
2837
2838         flush_work(&dev->ctrl.reset_work);
2839         flush_work(&dev->ctrl.scan_work);
2840         nvme_put_ctrl(&dev->ctrl);
2841 }
2842
2843 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2844 {
2845         int node, result = -ENOMEM;
2846         struct nvme_dev *dev;
2847         unsigned long quirks = id->driver_data;
2848         size_t alloc_size;
2849
2850         node = dev_to_node(&pdev->dev);
2851         if (node == NUMA_NO_NODE)
2852                 set_dev_node(&pdev->dev, first_memory_node);
2853
2854         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2855         if (!dev)
2856                 return -ENOMEM;
2857
2858         dev->nr_write_queues = write_queues;
2859         dev->nr_poll_queues = poll_queues;
2860         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2861         dev->queues = kcalloc_node(dev->nr_allocated_queues,
2862                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2863         if (!dev->queues)
2864                 goto free;
2865
2866         dev->dev = get_device(&pdev->dev);
2867         pci_set_drvdata(pdev, dev);
2868
2869         result = nvme_dev_map(dev);
2870         if (result)
2871                 goto put_pci;
2872
2873         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2874         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2875         mutex_init(&dev->shutdown_lock);
2876
2877         result = nvme_setup_prp_pools(dev);
2878         if (result)
2879                 goto unmap;
2880
2881         quirks |= check_vendor_combination_bug(pdev);
2882
2883         if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2884                 /*
2885                  * Some systems use a bios work around to ask for D3 on
2886                  * platforms that support kernel managed suspend.
2887                  */
2888                 dev_info(&pdev->dev,
2889                          "platform quirk: setting simple suspend\n");
2890                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2891         }
2892
2893         /*
2894          * Double check that our mempool alloc size will cover the biggest
2895          * command we support.
2896          */
2897         alloc_size = nvme_pci_iod_alloc_size();
2898         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2899
2900         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2901                                                 mempool_kfree,
2902                                                 (void *) alloc_size,
2903                                                 GFP_KERNEL, node);
2904         if (!dev->iod_mempool) {
2905                 result = -ENOMEM;
2906                 goto release_pools;
2907         }
2908
2909         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2910                         quirks);
2911         if (result)
2912                 goto release_mempool;
2913
2914         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2915
2916         nvme_reset_ctrl(&dev->ctrl);
2917         async_schedule(nvme_async_probe, dev);
2918
2919         return 0;
2920
2921  release_mempool:
2922         mempool_destroy(dev->iod_mempool);
2923  release_pools:
2924         nvme_release_prp_pools(dev);
2925  unmap:
2926         nvme_dev_unmap(dev);
2927  put_pci:
2928         put_device(dev->dev);
2929  free:
2930         kfree(dev->queues);
2931         kfree(dev);
2932         return result;
2933 }
2934
2935 static void nvme_reset_prepare(struct pci_dev *pdev)
2936 {
2937         struct nvme_dev *dev = pci_get_drvdata(pdev);
2938
2939         /*
2940          * We don't need to check the return value from waiting for the reset
2941          * state as pci_dev device lock is held, making it impossible to race
2942          * with ->remove().
2943          */
2944         nvme_disable_prepare_reset(dev, false);
2945         nvme_sync_queues(&dev->ctrl);
2946 }
2947
2948 static void nvme_reset_done(struct pci_dev *pdev)
2949 {
2950         struct nvme_dev *dev = pci_get_drvdata(pdev);
2951
2952         if (!nvme_try_sched_reset(&dev->ctrl))
2953                 flush_work(&dev->ctrl.reset_work);
2954 }
2955
2956 static void nvme_shutdown(struct pci_dev *pdev)
2957 {
2958         struct nvme_dev *dev = pci_get_drvdata(pdev);
2959
2960         nvme_disable_prepare_reset(dev, true);
2961 }
2962
2963 /*
2964  * The driver's remove may be called on a device in a partially initialized
2965  * state. This function must not have any dependencies on the device state in
2966  * order to proceed.
2967  */
2968 static void nvme_remove(struct pci_dev *pdev)
2969 {
2970         struct nvme_dev *dev = pci_get_drvdata(pdev);
2971
2972         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2973         pci_set_drvdata(pdev, NULL);
2974
2975         if (!pci_device_is_present(pdev)) {
2976                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2977                 nvme_dev_disable(dev, true);
2978                 nvme_dev_remove_admin(dev);
2979         }
2980
2981         flush_work(&dev->ctrl.reset_work);
2982         nvme_stop_ctrl(&dev->ctrl);
2983         nvme_remove_namespaces(&dev->ctrl);
2984         nvme_dev_disable(dev, true);
2985         nvme_release_cmb(dev);
2986         nvme_free_host_mem(dev);
2987         nvme_dev_remove_admin(dev);
2988         nvme_free_queues(dev, 0);
2989         nvme_release_prp_pools(dev);
2990         nvme_dev_unmap(dev);
2991         nvme_uninit_ctrl(&dev->ctrl);
2992 }
2993
2994 #ifdef CONFIG_PM_SLEEP
2995 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2996 {
2997         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2998 }
2999
3000 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3001 {
3002         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3003 }
3004
3005 static int nvme_resume(struct device *dev)
3006 {
3007         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3008         struct nvme_ctrl *ctrl = &ndev->ctrl;
3009
3010         if (ndev->last_ps == U32_MAX ||
3011             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3012                 return nvme_try_sched_reset(&ndev->ctrl);
3013         return 0;
3014 }
3015
3016 static int nvme_suspend(struct device *dev)
3017 {
3018         struct pci_dev *pdev = to_pci_dev(dev);
3019         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3020         struct nvme_ctrl *ctrl = &ndev->ctrl;
3021         int ret = -EBUSY;
3022
3023         ndev->last_ps = U32_MAX;
3024
3025         /*
3026          * The platform does not remove power for a kernel managed suspend so
3027          * use host managed nvme power settings for lowest idle power if
3028          * possible. This should have quicker resume latency than a full device
3029          * shutdown.  But if the firmware is involved after the suspend or the
3030          * device does not support any non-default power states, shut down the
3031          * device fully.
3032          *
3033          * If ASPM is not enabled for the device, shut down the device and allow
3034          * the PCI bus layer to put it into D3 in order to take the PCIe link
3035          * down, so as to allow the platform to achieve its minimum low-power
3036          * state (which may not be possible if the link is up).
3037          *
3038          * If a host memory buffer is enabled, shut down the device as the NVMe
3039          * specification allows the device to access the host memory buffer in
3040          * host DRAM from all power states, but hosts will fail access to DRAM
3041          * during S3.
3042          */
3043         if (pm_suspend_via_firmware() || !ctrl->npss ||
3044             !pcie_aspm_enabled(pdev) ||
3045             ndev->nr_host_mem_descs ||
3046             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3047                 return nvme_disable_prepare_reset(ndev, true);
3048
3049         nvme_start_freeze(ctrl);
3050         nvme_wait_freeze(ctrl);
3051         nvme_sync_queues(ctrl);
3052
3053         if (ctrl->state != NVME_CTRL_LIVE)
3054                 goto unfreeze;
3055
3056         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3057         if (ret < 0)
3058                 goto unfreeze;
3059
3060         /*
3061          * A saved state prevents pci pm from generically controlling the
3062          * device's power. If we're using protocol specific settings, we don't
3063          * want pci interfering.
3064          */
3065         pci_save_state(pdev);
3066
3067         ret = nvme_set_power_state(ctrl, ctrl->npss);
3068         if (ret < 0)
3069                 goto unfreeze;
3070
3071         if (ret) {
3072                 /* discard the saved state */
3073                 pci_load_saved_state(pdev, NULL);
3074
3075                 /*
3076                  * Clearing npss forces a controller reset on resume. The
3077                  * correct value will be rediscovered then.
3078                  */
3079                 ret = nvme_disable_prepare_reset(ndev, true);
3080                 ctrl->npss = 0;
3081         }
3082 unfreeze:
3083         nvme_unfreeze(ctrl);
3084         return ret;
3085 }
3086
3087 static int nvme_simple_suspend(struct device *dev)
3088 {
3089         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3090
3091         return nvme_disable_prepare_reset(ndev, true);
3092 }
3093
3094 static int nvme_simple_resume(struct device *dev)
3095 {
3096         struct pci_dev *pdev = to_pci_dev(dev);
3097         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3098
3099         return nvme_try_sched_reset(&ndev->ctrl);
3100 }
3101
3102 static const struct dev_pm_ops nvme_dev_pm_ops = {
3103         .suspend        = nvme_suspend,
3104         .resume         = nvme_resume,
3105         .freeze         = nvme_simple_suspend,
3106         .thaw           = nvme_simple_resume,
3107         .poweroff       = nvme_simple_suspend,
3108         .restore        = nvme_simple_resume,
3109 };
3110 #endif /* CONFIG_PM_SLEEP */
3111
3112 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3113                                                 pci_channel_state_t state)
3114 {
3115         struct nvme_dev *dev = pci_get_drvdata(pdev);
3116
3117         /*
3118          * A frozen channel requires a reset. When detected, this method will
3119          * shutdown the controller to quiesce. The controller will be restarted
3120          * after the slot reset through driver's slot_reset callback.
3121          */
3122         switch (state) {
3123         case pci_channel_io_normal:
3124                 return PCI_ERS_RESULT_CAN_RECOVER;
3125         case pci_channel_io_frozen:
3126                 dev_warn(dev->ctrl.device,
3127                         "frozen state error detected, reset controller\n");
3128                 nvme_dev_disable(dev, false);
3129                 return PCI_ERS_RESULT_NEED_RESET;
3130         case pci_channel_io_perm_failure:
3131                 dev_warn(dev->ctrl.device,
3132                         "failure state error detected, request disconnect\n");
3133                 return PCI_ERS_RESULT_DISCONNECT;
3134         }
3135         return PCI_ERS_RESULT_NEED_RESET;
3136 }
3137
3138 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3139 {
3140         struct nvme_dev *dev = pci_get_drvdata(pdev);
3141
3142         dev_info(dev->ctrl.device, "restart after slot reset\n");
3143         pci_restore_state(pdev);
3144         nvme_reset_ctrl(&dev->ctrl);
3145         return PCI_ERS_RESULT_RECOVERED;
3146 }
3147
3148 static void nvme_error_resume(struct pci_dev *pdev)
3149 {
3150         struct nvme_dev *dev = pci_get_drvdata(pdev);
3151
3152         flush_work(&dev->ctrl.reset_work);
3153 }
3154
3155 static const struct pci_error_handlers nvme_err_handler = {
3156         .error_detected = nvme_error_detected,
3157         .slot_reset     = nvme_slot_reset,
3158         .resume         = nvme_error_resume,
3159         .reset_prepare  = nvme_reset_prepare,
3160         .reset_done     = nvme_reset_done,
3161 };
3162
3163 static const struct pci_device_id nvme_id_table[] = {
3164         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3165                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3166                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3167         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3168                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3169                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3170         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3171                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3172                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3173         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3174                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3175                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3176         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3177                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3178                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3179                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3180                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3181         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3182                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3183         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3184                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3185                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3186         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3187                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3188         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3189                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3190         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3191                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3192         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3193                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3194         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3195                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3196         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3197                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3198         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3199                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3200                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3201         { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
3202                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3203         { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
3204                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3205         { PCI_DEVICE(0x1d1d, 0x2601),   /* CNEX Granby */
3206                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3207         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3208                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3209         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3210                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3211                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3212         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3213                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3214         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3215                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3216         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3217                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3218         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3219         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3220                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3221                                 NVME_QUIRK_128_BYTES_SQES |
3222                                 NVME_QUIRK_SHARED_TAGS },
3223
3224         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3225         { 0, }
3226 };
3227 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3228
3229 static struct pci_driver nvme_driver = {
3230         .name           = "nvme",
3231         .id_table       = nvme_id_table,
3232         .probe          = nvme_probe,
3233         .remove         = nvme_remove,
3234         .shutdown       = nvme_shutdown,
3235 #ifdef CONFIG_PM_SLEEP
3236         .driver         = {
3237                 .pm     = &nvme_dev_pm_ops,
3238         },
3239 #endif
3240         .sriov_configure = pci_sriov_configure_simple,
3241         .err_handler    = &nvme_err_handler,
3242 };
3243
3244 static int __init nvme_init(void)
3245 {
3246         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3247         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3248         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3249         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3250
3251         return pci_register_driver(&nvme_driver);
3252 }
3253
3254 static void __exit nvme_exit(void)
3255 {
3256         pci_unregister_driver(&nvme_driver);
3257         flush_workqueue(nvme_wq);
3258 }
3259
3260 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3261 MODULE_LICENSE("GPL");
3262 MODULE_VERSION("1.0");
3263 module_init(nvme_init);
3264 module_exit(nvme_exit);