drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/async.h>
   9 #include <linux/blkdev.h>
  10 #include <linux/blk-mq.h>
  11 #include <linux/blk-mq-pci.h>
  12 #include <linux/blk-integrity.h>
  13 #include <linux/dmi.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/kstrtox.h>
  18 #include <linux/memremap.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/mutex.h>
  22 #include <linux/once.h>
  23 #include <linux/pci.h>
  24 #include <linux/suspend.h>
  25 #include <linux/t10-pi.h>
  26 #include <linux/types.h>
  27 #include <linux/io-64-nonatomic-lo-hi.h>
  28 #include <linux/io-64-nonatomic-hi-lo.h>
  29 #include <linux/sed-opal.h>
  30 #include <linux/pci-p2pdma.h>
  31
  32 #include "trace.h"
  33 #include "nvme.h"
  34
  35 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  36 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  37
  38 #define SGES_PER_PAGE   (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  39
  40 /*
  41  * These can be higher, but we need to ensure that any command doesn't
  42  * require an sg allocation that needs more than a page of data.
  43  */
  44 #define NVME_MAX_KB_SZ  8192
  45 #define NVME_MAX_SEGS   128
  46 #define NVME_MAX_NR_ALLOCATIONS 5
  47
  48 static int use_threaded_interrupts;
  49 module_param(use_threaded_interrupts, int, 0444);
  50
  51 static bool use_cmb_sqes = true;
  52 module_param(use_cmb_sqes, bool, 0444);
  53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  54
  55 static unsigned int max_host_mem_size_mb = 128;
  56 module_param(max_host_mem_size_mb, uint, 0444);
  57 MODULE_PARM_DESC(max_host_mem_size_mb,
  58         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  59
  60 static unsigned int sgl_threshold = SZ_32K;
  61 module_param(sgl_threshold, uint, 0644);
  62 MODULE_PARM_DESC(sgl_threshold,
  63                 "Use SGLs when average request segment size is larger or equal to "
  64                 "this size. Use 0 to disable SGLs.");
  65
  66 #define NVME_PCI_MIN_QUEUE_SIZE 2
  67 #define NVME_PCI_MAX_QUEUE_SIZE 4095
  68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  69 static const struct kernel_param_ops io_queue_depth_ops = {
  70         .set = io_queue_depth_set,
  71         .get = param_get_uint,
  72 };
  73
  74 static unsigned int io_queue_depth = 1024;
  75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  77
  78 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  79 {
  80         unsigned int n;
  81         int ret;
  82
  83         ret = kstrtouint(val, 10, &n);
  84         if (ret != 0 || n > num_possible_cpus())
  85                 return -EINVAL;
  86         return param_set_uint(val, kp);
  87 }
  88
  89 static const struct kernel_param_ops io_queue_count_ops = {
  90         .set = io_queue_count_set,
  91         .get = param_get_uint,
  92 };
  93
  94 static unsigned int write_queues;
  95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  96 MODULE_PARM_DESC(write_queues,
  97         "Number of queues to use for writes. If not set, reads and writes "
  98         "will share a queue set.");
  99
 100 static unsigned int poll_queues;
 101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
 102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
 103
 104 static bool noacpi;
 105 module_param(noacpi, bool, 0444);
 106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 107
 108 struct nvme_dev;
 109 struct nvme_queue;
 110
 111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 112 static void nvme_delete_io_queues(struct nvme_dev *dev);
 113 static void nvme_update_attrs(struct nvme_dev *dev);
 114
 115 /*
 116  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 117  */
 118 struct nvme_dev {
 119         struct nvme_queue *queues;
 120         struct blk_mq_tag_set tagset;
 121         struct blk_mq_tag_set admin_tagset;
 122         u32 __iomem *dbs;
 123         struct device *dev;
 124         struct dma_pool *prp_page_pool;
 125         struct dma_pool *prp_small_pool;
 126         unsigned online_queues;
 127         unsigned max_qid;
 128         unsigned io_queues[HCTX_MAX_TYPES];
 129         unsigned int num_vecs;
 130         u32 q_depth;
 131         int io_sqes;
 132         u32 db_stride;
 133         void __iomem *bar;
 134         unsigned long bar_mapped_size;
 135         struct mutex shutdown_lock;
 136         bool subsystem;
 137         u64 cmb_size;
 138         bool cmb_use_sqes;
 139         u32 cmbsz;
 140         u32 cmbloc;
 141         struct nvme_ctrl ctrl;
 142         u32 last_ps;
 143         bool hmb;
 144
 145         mempool_t *iod_mempool;
 146
 147         /* shadow doorbell buffer support: */
 148         __le32 *dbbuf_dbs;
 149         dma_addr_t dbbuf_dbs_dma_addr;
 150         __le32 *dbbuf_eis;
 151         dma_addr_t dbbuf_eis_dma_addr;
 152
 153         /* host memory buffer support: */
 154         u64 host_mem_size;
 155         u32 nr_host_mem_descs;
 156         dma_addr_t host_mem_descs_dma;
 157         struct nvme_host_mem_buf_desc *host_mem_descs;
 158         void **host_mem_desc_bufs;
 159         unsigned int nr_allocated_queues;
 160         unsigned int nr_write_queues;
 161         unsigned int nr_poll_queues;
 162 };
 163
 164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 165 {
 166         return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
 167                         NVME_PCI_MAX_QUEUE_SIZE);
 168 }
 169
 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 171 {
 172         return qid * 2 * stride;
 173 }
 174
 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 176 {
 177         return (qid * 2 + 1) * stride;
 178 }
 179
 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 181 {
 182         return container_of(ctrl, struct nvme_dev, ctrl);
 183 }
 184
 185 /*
 186  * An NVM Express queue.  Each device has at least two (one for admin
 187  * commands and one for I/O commands).
 188  */
 189 struct nvme_queue {
 190         struct nvme_dev *dev;
 191         spinlock_t sq_lock;
 192         void *sq_cmds;
 193          /* only used for poll queues: */
 194         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 195         struct nvme_completion *cqes;
 196         dma_addr_t sq_dma_addr;
 197         dma_addr_t cq_dma_addr;
 198         u32 __iomem *q_db;
 199         u32 q_depth;
 200         u16 cq_vector;
 201         u16 sq_tail;
 202         u16 last_sq_tail;
 203         u16 cq_head;
 204         u16 qid;
 205         u8 cq_phase;
 206         u8 sqes;
 207         unsigned long flags;
 208 #define NVMEQ_ENABLED           0
 209 #define NVMEQ_SQ_CMB            1
 210 #define NVMEQ_DELETE_ERROR      2
 211 #define NVMEQ_POLLED            3
 212         __le32 *dbbuf_sq_db;
 213         __le32 *dbbuf_cq_db;
 214         __le32 *dbbuf_sq_ei;
 215         __le32 *dbbuf_cq_ei;
 216         struct completion delete_done;
 217 };
 218
 219 union nvme_descriptor {
 220         struct nvme_sgl_desc    *sg_list;
 221         __le64                  *prp_list;
 222 };
 223
 224 /*
 225  * The nvme_iod describes the data in an I/O.
 226  *
 227  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 228  * to the actual struct scatterlist.
 229  */
 230 struct nvme_iod {
 231         struct nvme_request req;
 232         struct nvme_command cmd;
 233         bool aborted;
 234         s8 nr_allocations;      /* PRP list pool allocations. 0 means small
 235                                    pool in use */
 236         unsigned int dma_len;   /* length of single DMA segment mapping */
 237         dma_addr_t first_dma;
 238         dma_addr_t meta_dma;
 239         struct sg_table sgt;
 240         union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
 241 };
 242
 243 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 244 {
 245         return dev->nr_allocated_queues * 8 * dev->db_stride;
 246 }
 247
 248 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 249 {
 250         unsigned int mem_size = nvme_dbbuf_size(dev);
 251
 252         if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
 253                 return;
 254
 255         if (dev->dbbuf_dbs) {
 256                 /*
 257                  * Clear the dbbuf memory so the driver doesn't observe stale
 258                  * values from the previous instantiation.
 259                  */
 260                 memset(dev->dbbuf_dbs, 0, mem_size);
 261                 memset(dev->dbbuf_eis, 0, mem_size);
 262                 return;
 263         }
 264
 265         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 266                                             &dev->dbbuf_dbs_dma_addr,
 267                                             GFP_KERNEL);
 268         if (!dev->dbbuf_dbs)
 269                 goto fail;
 270         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 271                                             &dev->dbbuf_eis_dma_addr,
 272                                             GFP_KERNEL);
 273         if (!dev->dbbuf_eis)
 274                 goto fail_free_dbbuf_dbs;
 275         return;
 276
 277 fail_free_dbbuf_dbs:
 278         dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
 279                           dev->dbbuf_dbs_dma_addr);
 280         dev->dbbuf_dbs = NULL;
 281 fail:
 282         dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
 283 }
 284
 285 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 286 {
 287         unsigned int mem_size = nvme_dbbuf_size(dev);
 288
 289         if (dev->dbbuf_dbs) {
 290                 dma_free_coherent(dev->dev, mem_size,
 291                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 292                 dev->dbbuf_dbs = NULL;
 293         }
 294         if (dev->dbbuf_eis) {
 295                 dma_free_coherent(dev->dev, mem_size,
 296                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 297                 dev->dbbuf_eis = NULL;
 298         }
 299 }
 300
 301 static void nvme_dbbuf_init(struct nvme_dev *dev,
 302                             struct nvme_queue *nvmeq, int qid)
 303 {
 304         if (!dev->dbbuf_dbs || !qid)
 305                 return;
 306
 307         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 308         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 309         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 310         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 311 }
 312
 313 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 314 {
 315         if (!nvmeq->qid)
 316                 return;
 317
 318         nvmeq->dbbuf_sq_db = NULL;
 319         nvmeq->dbbuf_cq_db = NULL;
 320         nvmeq->dbbuf_sq_ei = NULL;
 321         nvmeq->dbbuf_cq_ei = NULL;
 322 }
 323
 324 static void nvme_dbbuf_set(struct nvme_dev *dev)
 325 {
 326         struct nvme_command c = { };
 327         unsigned int i;
 328
 329         if (!dev->dbbuf_dbs)
 330                 return;
 331
 332         c.dbbuf.opcode = nvme_admin_dbbuf;
 333         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 334         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 335
 336         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 337                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 338                 /* Free memory and continue on */
 339                 nvme_dbbuf_dma_free(dev);
 340
 341                 for (i = 1; i <= dev->online_queues; i++)
 342                         nvme_dbbuf_free(&dev->queues[i]);
 343         }
 344 }
 345
 346 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 347 {
 348         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 349 }
 350
 351 /* Update dbbuf and return true if an MMIO is required */
 352 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
 353                                               volatile __le32 *dbbuf_ei)
 354 {
 355         if (dbbuf_db) {
 356                 u16 old_value, event_idx;
 357
 358                 /*
 359                  * Ensure that the queue is written before updating
 360                  * the doorbell in memory
 361                  */
 362                 wmb();
 363
 364                 old_value = le32_to_cpu(*dbbuf_db);
 365                 *dbbuf_db = cpu_to_le32(value);
 366
 367                 /*
 368                  * Ensure that the doorbell is updated before reading the event
 369                  * index from memory.  The controller needs to provide similar
 370                  * ordering to ensure the envent index is updated before reading
 371                  * the doorbell.
 372                  */
 373                 mb();
 374
 375                 event_idx = le32_to_cpu(*dbbuf_ei);
 376                 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
 377                         return false;
 378         }
 379
 380         return true;
 381 }
 382
 383 /*
 384  * Will slightly overestimate the number of pages needed.  This is OK
 385  * as it only leads to a small amount of wasted memory for the lifetime of
 386  * the I/O.
 387  */
 388 static int nvme_pci_npages_prp(void)
 389 {
 390         unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
 391         unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
 392         return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
 393 }
 394
 395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 396                                 unsigned int hctx_idx)
 397 {
 398         struct nvme_dev *dev = to_nvme_dev(data);
 399         struct nvme_queue *nvmeq = &dev->queues[0];
 400
 401         WARN_ON(hctx_idx != 0);
 402         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 403
 404         hctx->driver_data = nvmeq;
 405         return 0;
 406 }
 407
 408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 409                           unsigned int hctx_idx)
 410 {
 411         struct nvme_dev *dev = to_nvme_dev(data);
 412         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 413
 414         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 415         hctx->driver_data = nvmeq;
 416         return 0;
 417 }
 418
 419 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
 420                 struct request *req, unsigned int hctx_idx,
 421                 unsigned int numa_node)
 422 {
 423         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 424
 425         nvme_req(req)->ctrl = set->driver_data;
 426         nvme_req(req)->cmd = &iod->cmd;
 427         return 0;
 428 }
 429
 430 static int queue_irq_offset(struct nvme_dev *dev)
 431 {
 432         /* if we have more than 1 vec, admin queue offsets us by 1 */
 433         if (dev->num_vecs > 1)
 434                 return 1;
 435
 436         return 0;
 437 }
 438
 439 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
 440 {
 441         struct nvme_dev *dev = to_nvme_dev(set->driver_data);
 442         int i, qoff, offset;
 443
 444         offset = queue_irq_offset(dev);
 445         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 446                 struct blk_mq_queue_map *map = &set->map[i];
 447
 448                 map->nr_queues = dev->io_queues[i];
 449                 if (!map->nr_queues) {
 450                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 451                         continue;
 452                 }
 453
 454                 /*
 455                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 456                  * affinity), so use the regular blk-mq cpu mapping
 457                  */
 458                 map->queue_offset = qoff;
 459                 if (i != HCTX_TYPE_POLL && offset)
 460                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 461                 else
 462                         blk_mq_map_queues(map);
 463                 qoff += map->nr_queues;
 464                 offset += map->nr_queues;
 465         }
 466 }
 467
 468 /*
 469  * Write sq tail if we are asked to, or if the next command would wrap.
 470  */
 471 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 472 {
 473         if (!write_sq) {
 474                 u16 next_tail = nvmeq->sq_tail + 1;
 475
 476                 if (next_tail == nvmeq->q_depth)
 477                         next_tail = 0;
 478                 if (next_tail != nvmeq->last_sq_tail)
 479                         return;
 480         }
 481
 482         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 483                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 484                 writel(nvmeq->sq_tail, nvmeq->q_db);
 485         nvmeq->last_sq_tail = nvmeq->sq_tail;
 486 }
 487
 488 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
 489                                     struct nvme_command *cmd)
 490 {
 491         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 492                 absolute_pointer(cmd), sizeof(*cmd));
 493         if (++nvmeq->sq_tail == nvmeq->q_depth)
 494                 nvmeq->sq_tail = 0;
 495 }
 496
 497 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 498 {
 499         struct nvme_queue *nvmeq = hctx->driver_data;
 500
 501         spin_lock(&nvmeq->sq_lock);
 502         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 503                 nvme_write_sq_db(nvmeq, true);
 504         spin_unlock(&nvmeq->sq_lock);
 505 }
 506
 507 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
 508                                      int nseg)
 509 {
 510         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 511         unsigned int avg_seg_size;
 512
 513         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 514
 515         if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 516                 return false;
 517         if (!nvmeq->qid)
 518                 return false;
 519         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 520                 return false;
 521         return true;
 522 }
 523
 524 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 525 {
 526         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 527         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 528         dma_addr_t dma_addr = iod->first_dma;
 529         int i;
 530
 531         for (i = 0; i < iod->nr_allocations; i++) {
 532                 __le64 *prp_list = iod->list[i].prp_list;
 533                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 534
 535                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 536                 dma_addr = next_dma_addr;
 537         }
 538 }
 539
 540 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 541 {
 542         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 543
 544         if (iod->dma_len) {
 545                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 546                                rq_dma_dir(req));
 547                 return;
 548         }
 549
 550         WARN_ON_ONCE(!iod->sgt.nents);
 551
 552         dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
 553
 554         if (iod->nr_allocations == 0)
 555                 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
 556                               iod->first_dma);
 557         else if (iod->nr_allocations == 1)
 558                 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
 559                               iod->first_dma);
 560         else
 561                 nvme_free_prps(dev, req);
 562         mempool_free(iod->sgt.sgl, dev->iod_mempool);
 563 }
 564
 565 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 566 {
 567         int i;
 568         struct scatterlist *sg;
 569
 570         for_each_sg(sgl, sg, nents, i) {
 571                 dma_addr_t phys = sg_phys(sg);
 572                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 573                         "dma_address:%pad dma_length:%d\n",
 574                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 575                         sg_dma_len(sg));
 576         }
 577 }
 578
 579 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 580                 struct request *req, struct nvme_rw_command *cmnd)
 581 {
 582         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 583         struct dma_pool *pool;
 584         int length = blk_rq_payload_bytes(req);
 585         struct scatterlist *sg = iod->sgt.sgl;
 586         int dma_len = sg_dma_len(sg);
 587         u64 dma_addr = sg_dma_address(sg);
 588         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 589         __le64 *prp_list;
 590         dma_addr_t prp_dma;
 591         int nprps, i;
 592
 593         length -= (NVME_CTRL_PAGE_SIZE - offset);
 594         if (length <= 0) {
 595                 iod->first_dma = 0;
 596                 goto done;
 597         }
 598
 599         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 600         if (dma_len) {
 601                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 602         } else {
 603                 sg = sg_next(sg);
 604                 dma_addr = sg_dma_address(sg);
 605                 dma_len = sg_dma_len(sg);
 606         }
 607
 608         if (length <= NVME_CTRL_PAGE_SIZE) {
 609                 iod->first_dma = dma_addr;
 610                 goto done;
 611         }
 612
 613         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 614         if (nprps <= (256 / 8)) {
 615                 pool = dev->prp_small_pool;
 616                 iod->nr_allocations = 0;
 617         } else {
 618                 pool = dev->prp_page_pool;
 619                 iod->nr_allocations = 1;
 620         }
 621
 622         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 623         if (!prp_list) {
 624                 iod->nr_allocations = -1;
 625                 return BLK_STS_RESOURCE;
 626         }
 627         iod->list[0].prp_list = prp_list;
 628         iod->first_dma = prp_dma;
 629         i = 0;
 630         for (;;) {
 631                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 632                         __le64 *old_prp_list = prp_list;
 633                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 634                         if (!prp_list)
 635                                 goto free_prps;
 636                         iod->list[iod->nr_allocations++].prp_list = prp_list;
 637                         prp_list[0] = old_prp_list[i - 1];
 638                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 639                         i = 1;
 640                 }
 641                 prp_list[i++] = cpu_to_le64(dma_addr);
 642                 dma_len -= NVME_CTRL_PAGE_SIZE;
 643                 dma_addr += NVME_CTRL_PAGE_SIZE;
 644                 length -= NVME_CTRL_PAGE_SIZE;
 645                 if (length <= 0)
 646                         break;
 647                 if (dma_len > 0)
 648                         continue;
 649                 if (unlikely(dma_len < 0))
 650                         goto bad_sgl;
 651                 sg = sg_next(sg);
 652                 dma_addr = sg_dma_address(sg);
 653                 dma_len = sg_dma_len(sg);
 654         }
 655 done:
 656         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
 657         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 658         return BLK_STS_OK;
 659 free_prps:
 660         nvme_free_prps(dev, req);
 661         return BLK_STS_RESOURCE;
 662 bad_sgl:
 663         WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
 664                         "Invalid SGL for payload:%d nents:%d\n",
 665                         blk_rq_payload_bytes(req), iod->sgt.nents);
 666         return BLK_STS_IOERR;
 667 }
 668
 669 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 670                 struct scatterlist *sg)
 671 {
 672         sge->addr = cpu_to_le64(sg_dma_address(sg));
 673         sge->length = cpu_to_le32(sg_dma_len(sg));
 674         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 675 }
 676
 677 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 678                 dma_addr_t dma_addr, int entries)
 679 {
 680         sge->addr = cpu_to_le64(dma_addr);
 681         sge->length = cpu_to_le32(entries * sizeof(*sge));
 682         sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 683 }
 684
 685 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 686                 struct request *req, struct nvme_rw_command *cmd)
 687 {
 688         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 689         struct dma_pool *pool;
 690         struct nvme_sgl_desc *sg_list;
 691         struct scatterlist *sg = iod->sgt.sgl;
 692         unsigned int entries = iod->sgt.nents;
 693         dma_addr_t sgl_dma;
 694         int i = 0;
 695
 696         /* setting the transfer type as SGL */
 697         cmd->flags = NVME_CMD_SGL_METABUF;
 698
 699         if (entries == 1) {
 700                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 701                 return BLK_STS_OK;
 702         }
 703
 704         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 705                 pool = dev->prp_small_pool;
 706                 iod->nr_allocations = 0;
 707         } else {
 708                 pool = dev->prp_page_pool;
 709                 iod->nr_allocations = 1;
 710         }
 711
 712         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 713         if (!sg_list) {
 714                 iod->nr_allocations = -1;
 715                 return BLK_STS_RESOURCE;
 716         }
 717
 718         iod->list[0].sg_list = sg_list;
 719         iod->first_dma = sgl_dma;
 720
 721         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 722         do {
 723                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 724                 sg = sg_next(sg);
 725         } while (--entries > 0);
 726
 727         return BLK_STS_OK;
 728 }
 729
 730 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 731                 struct request *req, struct nvme_rw_command *cmnd,
 732                 struct bio_vec *bv)
 733 {
 734         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 735         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 736         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 737
 738         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 739         if (dma_mapping_error(dev->dev, iod->first_dma))
 740                 return BLK_STS_RESOURCE;
 741         iod->dma_len = bv->bv_len;
 742
 743         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 744         if (bv->bv_len > first_prp_len)
 745                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 746         else
 747                 cmnd->dptr.prp2 = 0;
 748         return BLK_STS_OK;
 749 }
 750
 751 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 752                 struct request *req, struct nvme_rw_command *cmnd,
 753                 struct bio_vec *bv)
 754 {
 755         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 756
 757         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 758         if (dma_mapping_error(dev->dev, iod->first_dma))
 759                 return BLK_STS_RESOURCE;
 760         iod->dma_len = bv->bv_len;
 761
 762         cmnd->flags = NVME_CMD_SGL_METABUF;
 763         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 764         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 765         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 766         return BLK_STS_OK;
 767 }
 768
 769 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 770                 struct nvme_command *cmnd)
 771 {
 772         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 773         blk_status_t ret = BLK_STS_RESOURCE;
 774         int rc;
 775
 776         if (blk_rq_nr_phys_segments(req) == 1) {
 777                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 778                 struct bio_vec bv = req_bvec(req);
 779
 780                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 781                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 782                                 return nvme_setup_prp_simple(dev, req,
 783                                                              &cmnd->rw, &bv);
 784
 785                         if (nvmeq->qid && sgl_threshold &&
 786                             nvme_ctrl_sgl_supported(&dev->ctrl))
 787                                 return nvme_setup_sgl_simple(dev, req,
 788                                                              &cmnd->rw, &bv);
 789                 }
 790         }
 791
 792         iod->dma_len = 0;
 793         iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 794         if (!iod->sgt.sgl)
 795                 return BLK_STS_RESOURCE;
 796         sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
 797         iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
 798         if (!iod->sgt.orig_nents)
 799                 goto out_free_sg;
 800
 801         rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
 802                              DMA_ATTR_NO_WARN);
 803         if (rc) {
 804                 if (rc == -EREMOTEIO)
 805                         ret = BLK_STS_TARGET;
 806                 goto out_free_sg;
 807         }
 808
 809         if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
 810                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
 811         else
 812                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 813         if (ret != BLK_STS_OK)
 814                 goto out_unmap_sg;
 815         return BLK_STS_OK;
 816
 817 out_unmap_sg:
 818         dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
 819 out_free_sg:
 820         mempool_free(iod->sgt.sgl, dev->iod_mempool);
 821         return ret;
 822 }
 823
 824 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 825                 struct nvme_command *cmnd)
 826 {
 827         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 828
 829         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 830                         rq_dma_dir(req), 0);
 831         if (dma_mapping_error(dev->dev, iod->meta_dma))
 832                 return BLK_STS_IOERR;
 833         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 834         return BLK_STS_OK;
 835 }
 836
 837 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
 838 {
 839         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 840         blk_status_t ret;
 841
 842         iod->aborted = false;
 843         iod->nr_allocations = -1;
 844         iod->sgt.nents = 0;
 845
 846         ret = nvme_setup_cmd(req->q->queuedata, req);
 847         if (ret)
 848                 return ret;
 849
 850         if (blk_rq_nr_phys_segments(req)) {
 851                 ret = nvme_map_data(dev, req, &iod->cmd);
 852                 if (ret)
 853                         goto out_free_cmd;
 854         }
 855
 856         if (blk_integrity_rq(req)) {
 857                 ret = nvme_map_metadata(dev, req, &iod->cmd);
 858                 if (ret)
 859                         goto out_unmap_data;
 860         }
 861
 862         nvme_start_request(req);
 863         return BLK_STS_OK;
 864 out_unmap_data:
 865         nvme_unmap_data(dev, req);
 866 out_free_cmd:
 867         nvme_cleanup_cmd(req);
 868         return ret;
 869 }
 870
 871 /*
 872  * NOTE: ns is NULL when called on the admin queue.
 873  */
 874 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 875                          const struct blk_mq_queue_data *bd)
 876 {
 877         struct nvme_queue *nvmeq = hctx->driver_data;
 878         struct nvme_dev *dev = nvmeq->dev;
 879         struct request *req = bd->rq;
 880         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 881         blk_status_t ret;
 882
 883         /*
 884          * We should not need to do this, but we're still using this to
 885          * ensure we can drain requests on a dying queue.
 886          */
 887         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 888                 return BLK_STS_IOERR;
 889
 890         if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
 891                 return nvme_fail_nonready_command(&dev->ctrl, req);
 892
 893         ret = nvme_prep_rq(dev, req);
 894         if (unlikely(ret))
 895                 return ret;
 896         spin_lock(&nvmeq->sq_lock);
 897         nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 898         nvme_write_sq_db(nvmeq, bd->last);
 899         spin_unlock(&nvmeq->sq_lock);
 900         return BLK_STS_OK;
 901 }
 902
 903 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
 904 {
 905         spin_lock(&nvmeq->sq_lock);
 906         while (!rq_list_empty(*rqlist)) {
 907                 struct request *req = rq_list_pop(rqlist);
 908                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 909
 910                 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 911         }
 912         nvme_write_sq_db(nvmeq, true);
 913         spin_unlock(&nvmeq->sq_lock);
 914 }
 915
 916 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
 917 {
 918         /*
 919          * We should not need to do this, but we're still using this to
 920          * ensure we can drain requests on a dying queue.
 921          */
 922         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 923                 return false;
 924         if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
 925                 return false;
 926
 927         req->mq_hctx->tags->rqs[req->tag] = req;
 928         return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
 929 }
 930
 931 static void nvme_queue_rqs(struct request **rqlist)
 932 {
 933         struct request *req, *next, *prev = NULL;
 934         struct request *requeue_list = NULL;
 935
 936         rq_list_for_each_safe(rqlist, req, next) {
 937                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 938
 939                 if (!nvme_prep_rq_batch(nvmeq, req)) {
 940                         /* detach 'req' and add to remainder list */
 941                         rq_list_move(rqlist, &requeue_list, req, prev);
 942
 943                         req = prev;
 944                         if (!req)
 945                                 continue;
 946                 }
 947
 948                 if (!next || req->mq_hctx != next->mq_hctx) {
 949                         /* detach rest of list, and submit */
 950                         req->rq_next = NULL;
 951                         nvme_submit_cmds(nvmeq, rqlist);
 952                         *rqlist = next;
 953                         prev = NULL;
 954                 } else
 955                         prev = req;
 956         }
 957
 958         *rqlist = requeue_list;
 959 }
 960
 961 static __always_inline void nvme_pci_unmap_rq(struct request *req)
 962 {
 963         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
 964         struct nvme_dev *dev = nvmeq->dev;
 965
 966         if (blk_integrity_rq(req)) {
 967                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 968
 969                 dma_unmap_page(dev->dev, iod->meta_dma,
 970                                rq_integrity_vec(req)->bv_len, rq_dma_dir(req));
 971         }
 972
 973         if (blk_rq_nr_phys_segments(req))
 974                 nvme_unmap_data(dev, req);
 975 }
 976
 977 static void nvme_pci_complete_rq(struct request *req)
 978 {
 979         nvme_pci_unmap_rq(req);
 980         nvme_complete_rq(req);
 981 }
 982
 983 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
 984 {
 985         nvme_complete_batch(iob, nvme_pci_unmap_rq);
 986 }
 987
 988 /* We read the CQE phase first to check if the rest of the entry is valid */
 989 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 990 {
 991         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 992
 993         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 994 }
 995
 996 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 997 {
 998         u16 head = nvmeq->cq_head;
 999
1000         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1001                                               nvmeq->dbbuf_cq_ei))
1002                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1003 }
1004
1005 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1006 {
1007         if (!nvmeq->qid)
1008                 return nvmeq->dev->admin_tagset.tags[0];
1009         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1010 }
1011
1012 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1013                                    struct io_comp_batch *iob, u16 idx)
1014 {
1015         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1016         __u16 command_id = READ_ONCE(cqe->command_id);
1017         struct request *req;
1018
1019         /*
1020          * AEN requests are special as they don't time out and can
1021          * survive any kind of queue freeze and often don't respond to
1022          * aborts.  We don't even bother to allocate a struct request
1023          * for them but rather special case them here.
1024          */
1025         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1026                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1027                                 cqe->status, &cqe->result);
1028                 return;
1029         }
1030
1031         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1032         if (unlikely(!req)) {
1033                 dev_warn(nvmeq->dev->ctrl.device,
1034                         "invalid id %d completed on queue %d\n",
1035                         command_id, le16_to_cpu(cqe->sq_id));
1036                 return;
1037         }
1038
1039         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1040         if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1041             !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1042                                         nvme_pci_complete_batch))
1043                 nvme_pci_complete_rq(req);
1044 }
1045
1046 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1047 {
1048         u32 tmp = nvmeq->cq_head + 1;
1049
1050         if (tmp == nvmeq->q_depth) {
1051                 nvmeq->cq_head = 0;
1052                 nvmeq->cq_phase ^= 1;
1053         } else {
1054                 nvmeq->cq_head = tmp;
1055         }
1056 }
1057
1058 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1059                                struct io_comp_batch *iob)
1060 {
1061         int found = 0;
1062
1063         while (nvme_cqe_pending(nvmeq)) {
1064                 found++;
1065                 /*
1066                  * load-load control dependency between phase and the rest of
1067                  * the cqe requires a full read memory barrier
1068                  */
1069                 dma_rmb();
1070                 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1071                 nvme_update_cq_head(nvmeq);
1072         }
1073
1074         if (found)
1075                 nvme_ring_cq_doorbell(nvmeq);
1076         return found;
1077 }
1078
1079 static irqreturn_t nvme_irq(int irq, void *data)
1080 {
1081         struct nvme_queue *nvmeq = data;
1082         DEFINE_IO_COMP_BATCH(iob);
1083
1084         if (nvme_poll_cq(nvmeq, &iob)) {
1085                 if (!rq_list_empty(iob.req_list))
1086                         nvme_pci_complete_batch(&iob);
1087                 return IRQ_HANDLED;
1088         }
1089         return IRQ_NONE;
1090 }
1091
1092 static irqreturn_t nvme_irq_check(int irq, void *data)
1093 {
1094         struct nvme_queue *nvmeq = data;
1095
1096         if (nvme_cqe_pending(nvmeq))
1097                 return IRQ_WAKE_THREAD;
1098         return IRQ_NONE;
1099 }
1100
1101 /*
1102  * Poll for completions for any interrupt driven queue
1103  * Can be called from any context.
1104  */
1105 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1106 {
1107         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1108
1109         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1110
1111         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1112         nvme_poll_cq(nvmeq, NULL);
1113         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1114 }
1115
1116 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1117 {
1118         struct nvme_queue *nvmeq = hctx->driver_data;
1119         bool found;
1120
1121         if (!nvme_cqe_pending(nvmeq))
1122                 return 0;
1123
1124         spin_lock(&nvmeq->cq_poll_lock);
1125         found = nvme_poll_cq(nvmeq, iob);
1126         spin_unlock(&nvmeq->cq_poll_lock);
1127
1128         return found;
1129 }
1130
1131 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1132 {
1133         struct nvme_dev *dev = to_nvme_dev(ctrl);
1134         struct nvme_queue *nvmeq = &dev->queues[0];
1135         struct nvme_command c = { };
1136
1137         c.common.opcode = nvme_admin_async_event;
1138         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1139
1140         spin_lock(&nvmeq->sq_lock);
1141         nvme_sq_copy_cmd(nvmeq, &c);
1142         nvme_write_sq_db(nvmeq, true);
1143         spin_unlock(&nvmeq->sq_lock);
1144 }
1145
1146 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1147 {
1148         struct nvme_command c = { };
1149
1150         c.delete_queue.opcode = opcode;
1151         c.delete_queue.qid = cpu_to_le16(id);
1152
1153         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1154 }
1155
1156 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1157                 struct nvme_queue *nvmeq, s16 vector)
1158 {
1159         struct nvme_command c = { };
1160         int flags = NVME_QUEUE_PHYS_CONTIG;
1161
1162         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1163                 flags |= NVME_CQ_IRQ_ENABLED;
1164
1165         /*
1166          * Note: we (ab)use the fact that the prp fields survive if no data
1167          * is attached to the request.
1168          */
1169         c.create_cq.opcode = nvme_admin_create_cq;
1170         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1171         c.create_cq.cqid = cpu_to_le16(qid);
1172         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1173         c.create_cq.cq_flags = cpu_to_le16(flags);
1174         c.create_cq.irq_vector = cpu_to_le16(vector);
1175
1176         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1177 }
1178
1179 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1180                                                 struct nvme_queue *nvmeq)
1181 {
1182         struct nvme_ctrl *ctrl = &dev->ctrl;
1183         struct nvme_command c = { };
1184         int flags = NVME_QUEUE_PHYS_CONTIG;
1185
1186         /*
1187          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1188          * set. Since URGENT priority is zeroes, it makes all queues
1189          * URGENT.
1190          */
1191         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1192                 flags |= NVME_SQ_PRIO_MEDIUM;
1193
1194         /*
1195          * Note: we (ab)use the fact that the prp fields survive if no data
1196          * is attached to the request.
1197          */
1198         c.create_sq.opcode = nvme_admin_create_sq;
1199         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1200         c.create_sq.sqid = cpu_to_le16(qid);
1201         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1202         c.create_sq.sq_flags = cpu_to_le16(flags);
1203         c.create_sq.cqid = cpu_to_le16(qid);
1204
1205         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1206 }
1207
1208 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1209 {
1210         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1211 }
1212
1213 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1214 {
1215         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1216 }
1217
1218 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1219 {
1220         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1221
1222         dev_warn(nvmeq->dev->ctrl.device,
1223                  "Abort status: 0x%x", nvme_req(req)->status);
1224         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1225         blk_mq_free_request(req);
1226         return RQ_END_IO_NONE;
1227 }
1228
1229 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1230 {
1231         /* If true, indicates loss of adapter communication, possibly by a
1232          * NVMe Subsystem reset.
1233          */
1234         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1235
1236         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1237         switch (dev->ctrl.state) {
1238         case NVME_CTRL_RESETTING:
1239         case NVME_CTRL_CONNECTING:
1240                 return false;
1241         default:
1242                 break;
1243         }
1244
1245         /* We shouldn't reset unless the controller is on fatal error state
1246          * _or_ if we lost the communication with it.
1247          */
1248         if (!(csts & NVME_CSTS_CFS) && !nssro)
1249                 return false;
1250
1251         return true;
1252 }
1253
1254 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1255 {
1256         /* Read a config register to help see what died. */
1257         u16 pci_status;
1258         int result;
1259
1260         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1261                                       &pci_status);
1262         if (result == PCIBIOS_SUCCESSFUL)
1263                 dev_warn(dev->ctrl.device,
1264                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1265                          csts, pci_status);
1266         else
1267                 dev_warn(dev->ctrl.device,
1268                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1269                          csts, result);
1270
1271         if (csts != ~0)
1272                 return;
1273
1274         dev_warn(dev->ctrl.device,
1275                  "Does your device have a faulty power saving mode enabled?\n");
1276         dev_warn(dev->ctrl.device,
1277                  "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
1278 }
1279
1280 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1281 {
1282         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1283         struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1284         struct nvme_dev *dev = nvmeq->dev;
1285         struct request *abort_req;
1286         struct nvme_command cmd = { };
1287         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1288
1289         /* If PCI error recovery process is happening, we cannot reset or
1290          * the recovery mechanism will surely fail.
1291          */
1292         mb();
1293         if (pci_channel_offline(to_pci_dev(dev->dev)))
1294                 return BLK_EH_RESET_TIMER;
1295
1296         /*
1297          * Reset immediately if the controller is failed
1298          */
1299         if (nvme_should_reset(dev, csts)) {
1300                 nvme_warn_reset(dev, csts);
1301                 goto disable;
1302         }
1303
1304         /*
1305          * Did we miss an interrupt?
1306          */
1307         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1308                 nvme_poll(req->mq_hctx, NULL);
1309         else
1310                 nvme_poll_irqdisable(nvmeq);
1311
1312         if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1313                 dev_warn(dev->ctrl.device,
1314                          "I/O %d QID %d timeout, completion polled\n",
1315                          req->tag, nvmeq->qid);
1316                 return BLK_EH_DONE;
1317         }
1318
1319         /*
1320          * Shutdown immediately if controller times out while starting. The
1321          * reset work will see the pci device disabled when it gets the forced
1322          * cancellation error. All outstanding requests are completed on
1323          * shutdown, so we return BLK_EH_DONE.
1324          */
1325         switch (dev->ctrl.state) {
1326         case NVME_CTRL_CONNECTING:
1327                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1328                 fallthrough;
1329         case NVME_CTRL_DELETING:
1330                 dev_warn_ratelimited(dev->ctrl.device,
1331                          "I/O %d QID %d timeout, disable controller\n",
1332                          req->tag, nvmeq->qid);
1333                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1334                 nvme_dev_disable(dev, true);
1335                 return BLK_EH_DONE;
1336         case NVME_CTRL_RESETTING:
1337                 return BLK_EH_RESET_TIMER;
1338         default:
1339                 break;
1340         }
1341
1342         /*
1343          * Shutdown the controller immediately and schedule a reset if the
1344          * command was already aborted once before and still hasn't been
1345          * returned to the driver, or if this is the admin queue.
1346          */
1347         if (!nvmeq->qid || iod->aborted) {
1348                 dev_warn(dev->ctrl.device,
1349                          "I/O %d QID %d timeout, reset controller\n",
1350                          req->tag, nvmeq->qid);
1351                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1352                 goto disable;
1353         }
1354
1355         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1356                 atomic_inc(&dev->ctrl.abort_limit);
1357                 return BLK_EH_RESET_TIMER;
1358         }
1359         iod->aborted = true;
1360
1361         cmd.abort.opcode = nvme_admin_abort_cmd;
1362         cmd.abort.cid = nvme_cid(req);
1363         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1364
1365         dev_warn(nvmeq->dev->ctrl.device,
1366                 "I/O %d (%s) QID %d timeout, aborting\n",
1367                  req->tag,
1368                  nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1369                  nvmeq->qid);
1370
1371         abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1372                                          BLK_MQ_REQ_NOWAIT);
1373         if (IS_ERR(abort_req)) {
1374                 atomic_inc(&dev->ctrl.abort_limit);
1375                 return BLK_EH_RESET_TIMER;
1376         }
1377         nvme_init_request(abort_req, &cmd);
1378
1379         abort_req->end_io = abort_endio;
1380         abort_req->end_io_data = NULL;
1381         blk_execute_rq_nowait(abort_req, false);
1382
1383         /*
1384          * The aborted req will be completed on receiving the abort req.
1385          * We enable the timer again. If hit twice, it'll cause a device reset,
1386          * as the device then is in a faulty state.
1387          */
1388         return BLK_EH_RESET_TIMER;
1389
1390 disable:
1391         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1392                 return BLK_EH_DONE;
1393
1394         nvme_dev_disable(dev, false);
1395         if (nvme_try_sched_reset(&dev->ctrl))
1396                 nvme_unquiesce_io_queues(&dev->ctrl);
1397         return BLK_EH_DONE;
1398 }
1399
1400 static void nvme_free_queue(struct nvme_queue *nvmeq)
1401 {
1402         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1403                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1404         if (!nvmeq->sq_cmds)
1405                 return;
1406
1407         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1408                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1409                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1410         } else {
1411                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1412                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1413         }
1414 }
1415
1416 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1417 {
1418         int i;
1419
1420         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1421                 dev->ctrl.queue_count--;
1422                 nvme_free_queue(&dev->queues[i]);
1423         }
1424 }
1425
1426 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1427 {
1428         struct nvme_queue *nvmeq = &dev->queues[qid];
1429
1430         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1431                 return;
1432
1433         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1434         mb();
1435
1436         nvmeq->dev->online_queues--;
1437         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1438                 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
1439         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1440                 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
1441 }
1442
1443 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1444 {
1445         int i;
1446
1447         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1448                 nvme_suspend_queue(dev, i);
1449 }
1450
1451 /*
1452  * Called only on a device that has been disabled and after all other threads
1453  * that can check this device's completion queues have synced, except
1454  * nvme_poll(). This is the last chance for the driver to see a natural
1455  * completion before nvme_cancel_request() terminates all incomplete requests.
1456  */
1457 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1458 {
1459         int i;
1460
1461         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1462                 spin_lock(&dev->queues[i].cq_poll_lock);
1463                 nvme_poll_cq(&dev->queues[i], NULL);
1464                 spin_unlock(&dev->queues[i].cq_poll_lock);
1465         }
1466 }
1467
1468 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1469                                 int entry_size)
1470 {
1471         int q_depth = dev->q_depth;
1472         unsigned q_size_aligned = roundup(q_depth * entry_size,
1473                                           NVME_CTRL_PAGE_SIZE);
1474
1475         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1476                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1477
1478                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1479                 q_depth = div_u64(mem_per_q, entry_size);
1480
1481                 /*
1482                  * Ensure the reduced q_depth is above some threshold where it
1483                  * would be better to map queues in system memory with the
1484                  * original depth
1485                  */
1486                 if (q_depth < 64)
1487                         return -ENOMEM;
1488         }
1489
1490         return q_depth;
1491 }
1492
1493 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1494                                 int qid)
1495 {
1496         struct pci_dev *pdev = to_pci_dev(dev->dev);
1497
1498         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1499                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1500                 if (nvmeq->sq_cmds) {
1501                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1502                                                         nvmeq->sq_cmds);
1503                         if (nvmeq->sq_dma_addr) {
1504                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1505                                 return 0;
1506                         }
1507
1508                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1509                 }
1510         }
1511
1512         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1513                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1514         if (!nvmeq->sq_cmds)
1515                 return -ENOMEM;
1516         return 0;
1517 }
1518
1519 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1520 {
1521         struct nvme_queue *nvmeq = &dev->queues[qid];
1522
1523         if (dev->ctrl.queue_count > qid)
1524                 return 0;
1525
1526         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1527         nvmeq->q_depth = depth;
1528         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1529                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1530         if (!nvmeq->cqes)
1531                 goto free_nvmeq;
1532
1533         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1534                 goto free_cqdma;
1535
1536         nvmeq->dev = dev;
1537         spin_lock_init(&nvmeq->sq_lock);
1538         spin_lock_init(&nvmeq->cq_poll_lock);
1539         nvmeq->cq_head = 0;
1540         nvmeq->cq_phase = 1;
1541         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1542         nvmeq->qid = qid;
1543         dev->ctrl.queue_count++;
1544
1545         return 0;
1546
1547  free_cqdma:
1548         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1549                           nvmeq->cq_dma_addr);
1550  free_nvmeq:
1551         return -ENOMEM;
1552 }
1553
1554 static int queue_request_irq(struct nvme_queue *nvmeq)
1555 {
1556         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1557         int nr = nvmeq->dev->ctrl.instance;
1558
1559         if (use_threaded_interrupts) {
1560                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1561                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1562         } else {
1563                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1564                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1565         }
1566 }
1567
1568 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1569 {
1570         struct nvme_dev *dev = nvmeq->dev;
1571
1572         nvmeq->sq_tail = 0;
1573         nvmeq->last_sq_tail = 0;
1574         nvmeq->cq_head = 0;
1575         nvmeq->cq_phase = 1;
1576         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1577         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1578         nvme_dbbuf_init(dev, nvmeq, qid);
1579         dev->online_queues++;
1580         wmb(); /* ensure the first interrupt sees the initialization */
1581 }
1582
1583 /*
1584  * Try getting shutdown_lock while setting up IO queues.
1585  */
1586 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1587 {
1588         /*
1589          * Give up if the lock is being held by nvme_dev_disable.
1590          */
1591         if (!mutex_trylock(&dev->shutdown_lock))
1592                 return -ENODEV;
1593
1594         /*
1595          * Controller is in wrong state, fail early.
1596          */
1597         if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1598                 mutex_unlock(&dev->shutdown_lock);
1599                 return -ENODEV;
1600         }
1601
1602         return 0;
1603 }
1604
1605 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1606 {
1607         struct nvme_dev *dev = nvmeq->dev;
1608         int result;
1609         u16 vector = 0;
1610
1611         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1612
1613         /*
1614          * A queue's vector matches the queue identifier unless the controller
1615          * has only one vector available.
1616          */
1617         if (!polled)
1618                 vector = dev->num_vecs == 1 ? 0 : qid;
1619         else
1620                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1621
1622         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1623         if (result)
1624                 return result;
1625
1626         result = adapter_alloc_sq(dev, qid, nvmeq);
1627         if (result < 0)
1628                 return result;
1629         if (result)
1630                 goto release_cq;
1631
1632         nvmeq->cq_vector = vector;
1633
1634         result = nvme_setup_io_queues_trylock(dev);
1635         if (result)
1636                 return result;
1637         nvme_init_queue(nvmeq, qid);
1638         if (!polled) {
1639                 result = queue_request_irq(nvmeq);
1640                 if (result < 0)
1641                         goto release_sq;
1642         }
1643
1644         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1645         mutex_unlock(&dev->shutdown_lock);
1646         return result;
1647
1648 release_sq:
1649         dev->online_queues--;
1650         mutex_unlock(&dev->shutdown_lock);
1651         adapter_delete_sq(dev, qid);
1652 release_cq:
1653         adapter_delete_cq(dev, qid);
1654         return result;
1655 }
1656
1657 static const struct blk_mq_ops nvme_mq_admin_ops = {
1658         .queue_rq       = nvme_queue_rq,
1659         .complete       = nvme_pci_complete_rq,
1660         .init_hctx      = nvme_admin_init_hctx,
1661         .init_request   = nvme_pci_init_request,
1662         .timeout        = nvme_timeout,
1663 };
1664
1665 static const struct blk_mq_ops nvme_mq_ops = {
1666         .queue_rq       = nvme_queue_rq,
1667         .queue_rqs      = nvme_queue_rqs,
1668         .complete       = nvme_pci_complete_rq,
1669         .commit_rqs     = nvme_commit_rqs,
1670         .init_hctx      = nvme_init_hctx,
1671         .init_request   = nvme_pci_init_request,
1672         .map_queues     = nvme_pci_map_queues,
1673         .timeout        = nvme_timeout,
1674         .poll           = nvme_poll,
1675 };
1676
1677 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1678 {
1679         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1680                 /*
1681                  * If the controller was reset during removal, it's possible
1682                  * user requests may be waiting on a stopped queue. Start the
1683                  * queue to flush these to completion.
1684                  */
1685                 nvme_unquiesce_admin_queue(&dev->ctrl);
1686                 nvme_remove_admin_tag_set(&dev->ctrl);
1687         }
1688 }
1689
1690 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1691 {
1692         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1693 }
1694
1695 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1696 {
1697         struct pci_dev *pdev = to_pci_dev(dev->dev);
1698
1699         if (size <= dev->bar_mapped_size)
1700                 return 0;
1701         if (size > pci_resource_len(pdev, 0))
1702                 return -ENOMEM;
1703         if (dev->bar)
1704                 iounmap(dev->bar);
1705         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1706         if (!dev->bar) {
1707                 dev->bar_mapped_size = 0;
1708                 return -ENOMEM;
1709         }
1710         dev->bar_mapped_size = size;
1711         dev->dbs = dev->bar + NVME_REG_DBS;
1712
1713         return 0;
1714 }
1715
1716 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1717 {
1718         int result;
1719         u32 aqa;
1720         struct nvme_queue *nvmeq;
1721
1722         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1723         if (result < 0)
1724                 return result;
1725
1726         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1727                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1728
1729         if (dev->subsystem &&
1730             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1731                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1732
1733         /*
1734          * If the device has been passed off to us in an enabled state, just
1735          * clear the enabled bit.  The spec says we should set the 'shutdown
1736          * notification bits', but doing so may cause the device to complete
1737          * commands to the admin queue ... and we don't know what memory that
1738          * might be pointing at!
1739          */
1740         result = nvme_disable_ctrl(&dev->ctrl, false);
1741         if (result < 0)
1742                 return result;
1743
1744         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1745         if (result)
1746                 return result;
1747
1748         dev->ctrl.numa_node = dev_to_node(dev->dev);
1749
1750         nvmeq = &dev->queues[0];
1751         aqa = nvmeq->q_depth - 1;
1752         aqa |= aqa << 16;
1753
1754         writel(aqa, dev->bar + NVME_REG_AQA);
1755         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1756         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1757
1758         result = nvme_enable_ctrl(&dev->ctrl);
1759         if (result)
1760                 return result;
1761
1762         nvmeq->cq_vector = 0;
1763         nvme_init_queue(nvmeq, 0);
1764         result = queue_request_irq(nvmeq);
1765         if (result) {
1766                 dev->online_queues--;
1767                 return result;
1768         }
1769
1770         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1771         return result;
1772 }
1773
1774 static int nvme_create_io_queues(struct nvme_dev *dev)
1775 {
1776         unsigned i, max, rw_queues;
1777         int ret = 0;
1778
1779         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1780                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1781                         ret = -ENOMEM;
1782                         break;
1783                 }
1784         }
1785
1786         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1787         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1788                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1789                                 dev->io_queues[HCTX_TYPE_READ];
1790         } else {
1791                 rw_queues = max;
1792         }
1793
1794         for (i = dev->online_queues; i <= max; i++) {
1795                 bool polled = i > rw_queues;
1796
1797                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1798                 if (ret)
1799                         break;
1800         }
1801
1802         /*
1803          * Ignore failing Create SQ/CQ commands, we can continue with less
1804          * than the desired amount of queues, and even a controller without
1805          * I/O queues can still be used to issue admin commands.  This might
1806          * be useful to upgrade a buggy firmware for example.
1807          */
1808         return ret >= 0 ? 0 : ret;
1809 }
1810
1811 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1812 {
1813         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1814
1815         return 1ULL << (12 + 4 * szu);
1816 }
1817
1818 static u32 nvme_cmb_size(struct nvme_dev *dev)
1819 {
1820         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1821 }
1822
1823 static void nvme_map_cmb(struct nvme_dev *dev)
1824 {
1825         u64 size, offset;
1826         resource_size_t bar_size;
1827         struct pci_dev *pdev = to_pci_dev(dev->dev);
1828         int bar;
1829
1830         if (dev->cmb_size)
1831                 return;
1832
1833         if (NVME_CAP_CMBS(dev->ctrl.cap))
1834                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1835
1836         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1837         if (!dev->cmbsz)
1838                 return;
1839         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1840
1841         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1842         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1843         bar = NVME_CMB_BIR(dev->cmbloc);
1844         bar_size = pci_resource_len(pdev, bar);
1845
1846         if (offset > bar_size)
1847                 return;
1848
1849         /*
1850          * Tell the controller about the host side address mapping the CMB,
1851          * and enable CMB decoding for the NVMe 1.4+ scheme:
1852          */
1853         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1854                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1855                              (pci_bus_address(pdev, bar) + offset),
1856                              dev->bar + NVME_REG_CMBMSC);
1857         }
1858
1859         /*
1860          * Controllers may support a CMB size larger than their BAR,
1861          * for example, due to being behind a bridge. Reduce the CMB to
1862          * the reported size of the BAR
1863          */
1864         if (size > bar_size - offset)
1865                 size = bar_size - offset;
1866
1867         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1868                 dev_warn(dev->ctrl.device,
1869                          "failed to register the CMB\n");
1870                 return;
1871         }
1872
1873         dev->cmb_size = size;
1874         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1875
1876         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1877                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1878                 pci_p2pmem_publish(pdev, true);
1879
1880         nvme_update_attrs(dev);
1881 }
1882
1883 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1884 {
1885         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1886         u64 dma_addr = dev->host_mem_descs_dma;
1887         struct nvme_command c = { };
1888         int ret;
1889
1890         c.features.opcode       = nvme_admin_set_features;
1891         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1892         c.features.dword11      = cpu_to_le32(bits);
1893         c.features.dword12      = cpu_to_le32(host_mem_size);
1894         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1895         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1896         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1897
1898         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1899         if (ret) {
1900                 dev_warn(dev->ctrl.device,
1901                          "failed to set host mem (err %d, flags %#x).\n",
1902                          ret, bits);
1903         } else
1904                 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1905
1906         return ret;
1907 }
1908
1909 static void nvme_free_host_mem(struct nvme_dev *dev)
1910 {
1911         int i;
1912
1913         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1914                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1915                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1916
1917                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1918                                le64_to_cpu(desc->addr),
1919                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1920         }
1921
1922         kfree(dev->host_mem_desc_bufs);
1923         dev->host_mem_desc_bufs = NULL;
1924         dma_free_coherent(dev->dev,
1925                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1926                         dev->host_mem_descs, dev->host_mem_descs_dma);
1927         dev->host_mem_descs = NULL;
1928         dev->nr_host_mem_descs = 0;
1929 }
1930
1931 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1932                 u32 chunk_size)
1933 {
1934         struct nvme_host_mem_buf_desc *descs;
1935         u32 max_entries, len;
1936         dma_addr_t descs_dma;
1937         int i = 0;
1938         void **bufs;
1939         u64 size, tmp;
1940
1941         tmp = (preferred + chunk_size - 1);
1942         do_div(tmp, chunk_size);
1943         max_entries = tmp;
1944
1945         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1946                 max_entries = dev->ctrl.hmmaxd;
1947
1948         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1949                                    &descs_dma, GFP_KERNEL);
1950         if (!descs)
1951                 goto out;
1952
1953         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1954         if (!bufs)
1955                 goto out_free_descs;
1956
1957         for (size = 0; size < preferred && i < max_entries; size += len) {
1958                 dma_addr_t dma_addr;
1959
1960                 len = min_t(u64, chunk_size, preferred - size);
1961                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1962                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1963                 if (!bufs[i])
1964                         break;
1965
1966                 descs[i].addr = cpu_to_le64(dma_addr);
1967                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1968                 i++;
1969         }
1970
1971         if (!size)
1972                 goto out_free_bufs;
1973
1974         dev->nr_host_mem_descs = i;
1975         dev->host_mem_size = size;
1976         dev->host_mem_descs = descs;
1977         dev->host_mem_descs_dma = descs_dma;
1978         dev->host_mem_desc_bufs = bufs;
1979         return 0;
1980
1981 out_free_bufs:
1982         while (--i >= 0) {
1983                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1984
1985                 dma_free_attrs(dev->dev, size, bufs[i],
1986                                le64_to_cpu(descs[i].addr),
1987                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1988         }
1989
1990         kfree(bufs);
1991 out_free_descs:
1992         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1993                         descs_dma);
1994 out:
1995         dev->host_mem_descs = NULL;
1996         return -ENOMEM;
1997 }
1998
1999 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2000 {
2001         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2002         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2003         u64 chunk_size;
2004
2005         /* start big and work our way down */
2006         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2007                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2008                         if (!min || dev->host_mem_size >= min)
2009                                 return 0;
2010                         nvme_free_host_mem(dev);
2011                 }
2012         }
2013
2014         return -ENOMEM;
2015 }
2016
2017 static int nvme_setup_host_mem(struct nvme_dev *dev)
2018 {
2019         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2020         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2021         u64 min = (u64)dev->ctrl.hmmin * 4096;
2022         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2023         int ret;
2024
2025         if (!dev->ctrl.hmpre)
2026                 return 0;
2027
2028         preferred = min(preferred, max);
2029         if (min > max) {
2030                 dev_warn(dev->ctrl.device,
2031                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2032                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2033                 nvme_free_host_mem(dev);
2034                 return 0;
2035         }
2036
2037         /*
2038          * If we already have a buffer allocated check if we can reuse it.
2039          */
2040         if (dev->host_mem_descs) {
2041                 if (dev->host_mem_size >= min)
2042                         enable_bits |= NVME_HOST_MEM_RETURN;
2043                 else
2044                         nvme_free_host_mem(dev);
2045         }
2046
2047         if (!dev->host_mem_descs) {
2048                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2049                         dev_warn(dev->ctrl.device,
2050                                 "failed to allocate host memory buffer.\n");
2051                         return 0; /* controller must work without HMB */
2052                 }
2053
2054                 dev_info(dev->ctrl.device,
2055                         "allocated %lld MiB host memory buffer.\n",
2056                         dev->host_mem_size >> ilog2(SZ_1M));
2057         }
2058
2059         ret = nvme_set_host_mem(dev, enable_bits);
2060         if (ret)
2061                 nvme_free_host_mem(dev);
2062         return ret;
2063 }
2064
2065 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2066                 char *buf)
2067 {
2068         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2069
2070         return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2071                        ndev->cmbloc, ndev->cmbsz);
2072 }
2073 static DEVICE_ATTR_RO(cmb);
2074
2075 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2076                 char *buf)
2077 {
2078         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2079
2080         return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2081 }
2082 static DEVICE_ATTR_RO(cmbloc);
2083
2084 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2085                 char *buf)
2086 {
2087         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2088
2089         return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2090 }
2091 static DEVICE_ATTR_RO(cmbsz);
2092
2093 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2094                         char *buf)
2095 {
2096         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2097
2098         return sysfs_emit(buf, "%d\n", ndev->hmb);
2099 }
2100
2101 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2102                          const char *buf, size_t count)
2103 {
2104         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2105         bool new;
2106         int ret;
2107
2108         if (kstrtobool(buf, &new) < 0)
2109                 return -EINVAL;
2110
2111         if (new == ndev->hmb)
2112                 return count;
2113
2114         if (new) {
2115                 ret = nvme_setup_host_mem(ndev);
2116         } else {
2117                 ret = nvme_set_host_mem(ndev, 0);
2118                 if (!ret)
2119                         nvme_free_host_mem(ndev);
2120         }
2121
2122         if (ret < 0)
2123                 return ret;
2124
2125         return count;
2126 }
2127 static DEVICE_ATTR_RW(hmb);
2128
2129 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2130                 struct attribute *a, int n)
2131 {
2132         struct nvme_ctrl *ctrl =
2133                 dev_get_drvdata(container_of(kobj, struct device, kobj));
2134         struct nvme_dev *dev = to_nvme_dev(ctrl);
2135
2136         if (a == &dev_attr_cmb.attr ||
2137             a == &dev_attr_cmbloc.attr ||
2138             a == &dev_attr_cmbsz.attr) {
2139                 if (!dev->cmbsz)
2140                         return 0;
2141         }
2142         if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2143                 return 0;
2144
2145         return a->mode;
2146 }
2147
2148 static struct attribute *nvme_pci_attrs[] = {
2149         &dev_attr_cmb.attr,
2150         &dev_attr_cmbloc.attr,
2151         &dev_attr_cmbsz.attr,
2152         &dev_attr_hmb.attr,
2153         NULL,
2154 };
2155
2156 static const struct attribute_group nvme_pci_dev_attrs_group = {
2157         .attrs          = nvme_pci_attrs,
2158         .is_visible     = nvme_pci_attrs_are_visible,
2159 };
2160
2161 static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2162         &nvme_dev_attrs_group,
2163         &nvme_pci_dev_attrs_group,
2164         NULL,
2165 };
2166
2167 static void nvme_update_attrs(struct nvme_dev *dev)
2168 {
2169         sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2170 }
2171
2172 /*
2173  * nirqs is the number of interrupts available for write and read
2174  * queues. The core already reserved an interrupt for the admin queue.
2175  */
2176 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2177 {
2178         struct nvme_dev *dev = affd->priv;
2179         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2180
2181         /*
2182          * If there is no interrupt available for queues, ensure that
2183          * the default queue is set to 1. The affinity set size is
2184          * also set to one, but the irq core ignores it for this case.
2185          *
2186          * If only one interrupt is available or 'write_queue' == 0, combine
2187          * write and read queues.
2188          *
2189          * If 'write_queues' > 0, ensure it leaves room for at least one read
2190          * queue.
2191          */
2192         if (!nrirqs) {
2193                 nrirqs = 1;
2194                 nr_read_queues = 0;
2195         } else if (nrirqs == 1 || !nr_write_queues) {
2196                 nr_read_queues = 0;
2197         } else if (nr_write_queues >= nrirqs) {
2198                 nr_read_queues = 1;
2199         } else {
2200                 nr_read_queues = nrirqs - nr_write_queues;
2201         }
2202
2203         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2204         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2205         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2206         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2207         affd->nr_sets = nr_read_queues ? 2 : 1;
2208 }
2209
2210 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2211 {
2212         struct pci_dev *pdev = to_pci_dev(dev->dev);
2213         struct irq_affinity affd = {
2214                 .pre_vectors    = 1,
2215                 .calc_sets      = nvme_calc_irq_sets,
2216                 .priv           = dev,
2217         };
2218         unsigned int irq_queues, poll_queues;
2219
2220         /*
2221          * Poll queues don't need interrupts, but we need at least one I/O queue
2222          * left over for non-polled I/O.
2223          */
2224         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2225         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2226
2227         /*
2228          * Initialize for the single interrupt case, will be updated in
2229          * nvme_calc_irq_sets().
2230          */
2231         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2232         dev->io_queues[HCTX_TYPE_READ] = 0;
2233
2234         /*
2235          * We need interrupts for the admin queue and each non-polled I/O queue,
2236          * but some Apple controllers require all queues to use the first
2237          * vector.
2238          */
2239         irq_queues = 1;
2240         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2241                 irq_queues += (nr_io_queues - poll_queues);
2242         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2243                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2244 }
2245
2246 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2247 {
2248         /*
2249          * If tags are shared with admin queue (Apple bug), then
2250          * make sure we only use one IO queue.
2251          */
2252         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2253                 return 1;
2254         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2255 }
2256
2257 static int nvme_setup_io_queues(struct nvme_dev *dev)
2258 {
2259         struct nvme_queue *adminq = &dev->queues[0];
2260         struct pci_dev *pdev = to_pci_dev(dev->dev);
2261         unsigned int nr_io_queues;
2262         unsigned long size;
2263         int result;
2264
2265         /*
2266          * Sample the module parameters once at reset time so that we have
2267          * stable values to work with.
2268          */
2269         dev->nr_write_queues = write_queues;
2270         dev->nr_poll_queues = poll_queues;
2271
2272         nr_io_queues = dev->nr_allocated_queues - 1;
2273         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2274         if (result < 0)
2275                 return result;
2276
2277         if (nr_io_queues == 0)
2278                 return 0;
2279
2280         /*
2281          * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2282          * from set to unset. If there is a window to it is truely freed,
2283          * pci_free_irq_vectors() jumping into this window will crash.
2284          * And take lock to avoid racing with pci_free_irq_vectors() in
2285          * nvme_dev_disable() path.
2286          */
2287         result = nvme_setup_io_queues_trylock(dev);
2288         if (result)
2289                 return result;
2290         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2291                 pci_free_irq(pdev, 0, adminq);
2292
2293         if (dev->cmb_use_sqes) {
2294                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2295                                 sizeof(struct nvme_command));
2296                 if (result > 0) {
2297                         dev->q_depth = result;
2298                         dev->ctrl.sqsize = result - 1;
2299                 } else {
2300                         dev->cmb_use_sqes = false;
2301                 }
2302         }
2303
2304         do {
2305                 size = db_bar_size(dev, nr_io_queues);
2306                 result = nvme_remap_bar(dev, size);
2307                 if (!result)
2308                         break;
2309                 if (!--nr_io_queues) {
2310                         result = -ENOMEM;
2311                         goto out_unlock;
2312                 }
2313         } while (1);
2314         adminq->q_db = dev->dbs;
2315
2316  retry:
2317         /* Deregister the admin queue's interrupt */
2318         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2319                 pci_free_irq(pdev, 0, adminq);
2320
2321         /*
2322          * If we enable msix early due to not intx, disable it again before
2323          * setting up the full range we need.
2324          */
2325         pci_free_irq_vectors(pdev);
2326
2327         result = nvme_setup_irqs(dev, nr_io_queues);
2328         if (result <= 0) {
2329                 result = -EIO;
2330                 goto out_unlock;
2331         }
2332
2333         dev->num_vecs = result;
2334         result = max(result - 1, 1);
2335         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2336
2337         /*
2338          * Should investigate if there's a performance win from allocating
2339          * more queues than interrupt vectors; it might allow the submission
2340          * path to scale better, even if the receive path is limited by the
2341          * number of interrupts.
2342          */
2343         result = queue_request_irq(adminq);
2344         if (result)
2345                 goto out_unlock;
2346         set_bit(NVMEQ_ENABLED, &adminq->flags);
2347         mutex_unlock(&dev->shutdown_lock);
2348
2349         result = nvme_create_io_queues(dev);
2350         if (result || dev->online_queues < 2)
2351                 return result;
2352
2353         if (dev->online_queues - 1 < dev->max_qid) {
2354                 nr_io_queues = dev->online_queues - 1;
2355                 nvme_delete_io_queues(dev);
2356                 result = nvme_setup_io_queues_trylock(dev);
2357                 if (result)
2358                         return result;
2359                 nvme_suspend_io_queues(dev);
2360                 goto retry;
2361         }
2362         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2363                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2364                                         dev->io_queues[HCTX_TYPE_READ],
2365                                         dev->io_queues[HCTX_TYPE_POLL]);
2366         return 0;
2367 out_unlock:
2368         mutex_unlock(&dev->shutdown_lock);
2369         return result;
2370 }
2371
2372 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2373                                              blk_status_t error)
2374 {
2375         struct nvme_queue *nvmeq = req->end_io_data;
2376
2377         blk_mq_free_request(req);
2378         complete(&nvmeq->delete_done);
2379         return RQ_END_IO_NONE;
2380 }
2381
2382 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2383                                           blk_status_t error)
2384 {
2385         struct nvme_queue *nvmeq = req->end_io_data;
2386
2387         if (error)
2388                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2389
2390         return nvme_del_queue_end(req, error);
2391 }
2392
2393 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2394 {
2395         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2396         struct request *req;
2397         struct nvme_command cmd = { };
2398
2399         cmd.delete_queue.opcode = opcode;
2400         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2401
2402         req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2403         if (IS_ERR(req))
2404                 return PTR_ERR(req);
2405         nvme_init_request(req, &cmd);
2406
2407         if (opcode == nvme_admin_delete_cq)
2408                 req->end_io = nvme_del_cq_end;
2409         else
2410                 req->end_io = nvme_del_queue_end;
2411         req->end_io_data = nvmeq;
2412
2413         init_completion(&nvmeq->delete_done);
2414         blk_execute_rq_nowait(req, false);
2415         return 0;
2416 }
2417
2418 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2419 {
2420         int nr_queues = dev->online_queues - 1, sent = 0;
2421         unsigned long timeout;
2422
2423  retry:
2424         timeout = NVME_ADMIN_TIMEOUT;
2425         while (nr_queues > 0) {
2426                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2427                         break;
2428                 nr_queues--;
2429                 sent++;
2430         }
2431         while (sent) {
2432                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2433
2434                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2435                                 timeout);
2436                 if (timeout == 0)
2437                         return false;
2438
2439                 sent--;
2440                 if (nr_queues)
2441                         goto retry;
2442         }
2443         return true;
2444 }
2445
2446 static void nvme_delete_io_queues(struct nvme_dev *dev)
2447 {
2448         if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2449                 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2450 }
2451
2452 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2453 {
2454         if (dev->io_queues[HCTX_TYPE_POLL])
2455                 return 3;
2456         if (dev->io_queues[HCTX_TYPE_READ])
2457                 return 2;
2458         return 1;
2459 }
2460
2461 static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2462 {
2463         blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2464         /* free previously allocated queues that are no longer usable */
2465         nvme_free_queues(dev, dev->online_queues);
2466 }
2467
2468 static int nvme_pci_enable(struct nvme_dev *dev)
2469 {
2470         int result = -ENOMEM;
2471         struct pci_dev *pdev = to_pci_dev(dev->dev);
2472
2473         if (pci_enable_device_mem(pdev))
2474                 return result;
2475
2476         pci_set_master(pdev);
2477
2478         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2479                 result = -ENODEV;
2480                 goto disable;
2481         }
2482
2483         /*
2484          * Some devices and/or platforms don't advertise or work with INTx
2485          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2486          * adjust this later.
2487          */
2488         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2489         if (result < 0)
2490                 goto disable;
2491
2492         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2493
2494         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2495                                 io_queue_depth);
2496         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2497         dev->dbs = dev->bar + 4096;
2498
2499         /*
2500          * Some Apple controllers require a non-standard SQE size.
2501          * Interestingly they also seem to ignore the CC:IOSQES register
2502          * so we don't bother updating it here.
2503          */
2504         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2505                 dev->io_sqes = 7;
2506         else
2507                 dev->io_sqes = NVME_NVM_IOSQES;
2508
2509         /*
2510          * Temporary fix for the Apple controller found in the MacBook8,1 and
2511          * some MacBook7,1 to avoid controller resets and data loss.
2512          */
2513         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2514                 dev->q_depth = 2;
2515                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2516                         "set queue depth=%u to work around controller resets\n",
2517                         dev->q_depth);
2518         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2519                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2520                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2521                 dev->q_depth = 64;
2522                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2523                         "set queue depth=%u\n", dev->q_depth);
2524         }
2525
2526         /*
2527          * Controllers with the shared tags quirk need the IO queue to be
2528          * big enough so that we get 32 tags for the admin queue
2529          */
2530         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2531             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2532                 dev->q_depth = NVME_AQ_DEPTH + 2;
2533                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2534                          dev->q_depth);
2535         }
2536         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2537
2538         nvme_map_cmb(dev);
2539
2540         pci_save_state(pdev);
2541
2542         result = nvme_pci_configure_admin_queue(dev);
2543         if (result)
2544                 goto free_irq;
2545         return result;
2546
2547  free_irq:
2548         pci_free_irq_vectors(pdev);
2549  disable:
2550         pci_disable_device(pdev);
2551         return result;
2552 }
2553
2554 static void nvme_dev_unmap(struct nvme_dev *dev)
2555 {
2556         if (dev->bar)
2557                 iounmap(dev->bar);
2558         pci_release_mem_regions(to_pci_dev(dev->dev));
2559 }
2560
2561 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2562 {
2563         struct pci_dev *pdev = to_pci_dev(dev->dev);
2564         u32 csts;
2565
2566         if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2567                 return true;
2568         if (pdev->error_state != pci_channel_io_normal)
2569                 return true;
2570
2571         csts = readl(dev->bar + NVME_REG_CSTS);
2572         return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2573 }
2574
2575 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2576 {
2577         struct pci_dev *pdev = to_pci_dev(dev->dev);
2578         bool dead;
2579
2580         mutex_lock(&dev->shutdown_lock);
2581         dead = nvme_pci_ctrl_is_dead(dev);
2582         if (dev->ctrl.state == NVME_CTRL_LIVE ||
2583             dev->ctrl.state == NVME_CTRL_RESETTING) {
2584                 if (pci_is_enabled(pdev))
2585                         nvme_start_freeze(&dev->ctrl);
2586                 /*
2587                  * Give the controller a chance to complete all entered requests
2588                  * if doing a safe shutdown.
2589                  */
2590                 if (!dead && shutdown)
2591                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2592         }
2593
2594         nvme_quiesce_io_queues(&dev->ctrl);
2595
2596         if (!dead && dev->ctrl.queue_count > 0) {
2597                 nvme_delete_io_queues(dev);
2598                 nvme_disable_ctrl(&dev->ctrl, shutdown);
2599                 nvme_poll_irqdisable(&dev->queues[0]);
2600         }
2601         nvme_suspend_io_queues(dev);
2602         nvme_suspend_queue(dev, 0);
2603         pci_free_irq_vectors(pdev);
2604         if (pci_is_enabled(pdev))
2605                 pci_disable_device(pdev);
2606         nvme_reap_pending_cqes(dev);
2607
2608         nvme_cancel_tagset(&dev->ctrl);
2609         nvme_cancel_admin_tagset(&dev->ctrl);
2610
2611         /*
2612          * The driver will not be starting up queues again if shutting down so
2613          * must flush all entered requests to their failed completion to avoid
2614          * deadlocking blk-mq hot-cpu notifier.
2615          */
2616         if (shutdown) {
2617                 nvme_unquiesce_io_queues(&dev->ctrl);
2618                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2619                         nvme_unquiesce_admin_queue(&dev->ctrl);
2620         }
2621         mutex_unlock(&dev->shutdown_lock);
2622 }
2623
2624 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2625 {
2626         if (!nvme_wait_reset(&dev->ctrl))
2627                 return -EBUSY;
2628         nvme_dev_disable(dev, shutdown);
2629         return 0;
2630 }
2631
2632 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2633 {
2634         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2635                                                 NVME_CTRL_PAGE_SIZE,
2636                                                 NVME_CTRL_PAGE_SIZE, 0);
2637         if (!dev->prp_page_pool)
2638                 return -ENOMEM;
2639
2640         /* Optimisation for I/Os between 4k and 128k */
2641         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2642                                                 256, 256, 0);
2643         if (!dev->prp_small_pool) {
2644                 dma_pool_destroy(dev->prp_page_pool);
2645                 return -ENOMEM;
2646         }
2647         return 0;
2648 }
2649
2650 static void nvme_release_prp_pools(struct nvme_dev *dev)
2651 {
2652         dma_pool_destroy(dev->prp_page_pool);
2653         dma_pool_destroy(dev->prp_small_pool);
2654 }
2655
2656 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2657 {
2658         size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2659
2660         dev->iod_mempool = mempool_create_node(1,
2661                         mempool_kmalloc, mempool_kfree,
2662                         (void *)alloc_size, GFP_KERNEL,
2663                         dev_to_node(dev->dev));
2664         if (!dev->iod_mempool)
2665                 return -ENOMEM;
2666         return 0;
2667 }
2668
2669 static void nvme_free_tagset(struct nvme_dev *dev)
2670 {
2671         if (dev->tagset.tags)
2672                 nvme_remove_io_tag_set(&dev->ctrl);
2673         dev->ctrl.tagset = NULL;
2674 }
2675
2676 /* pairs with nvme_pci_alloc_dev */
2677 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2678 {
2679         struct nvme_dev *dev = to_nvme_dev(ctrl);
2680
2681         nvme_free_tagset(dev);
2682         put_device(dev->dev);
2683         kfree(dev->queues);
2684         kfree(dev);
2685 }
2686
2687 static void nvme_reset_work(struct work_struct *work)
2688 {
2689         struct nvme_dev *dev =
2690                 container_of(work, struct nvme_dev, ctrl.reset_work);
2691         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2692         int result;
2693
2694         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2695                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2696                          dev->ctrl.state);
2697                 result = -ENODEV;
2698                 goto out;
2699         }
2700
2701         /*
2702          * If we're called to reset a live controller first shut it down before
2703          * moving on.
2704          */
2705         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2706                 nvme_dev_disable(dev, false);
2707         nvme_sync_queues(&dev->ctrl);
2708
2709         mutex_lock(&dev->shutdown_lock);
2710         result = nvme_pci_enable(dev);
2711         if (result)
2712                 goto out_unlock;
2713         nvme_unquiesce_admin_queue(&dev->ctrl);
2714         mutex_unlock(&dev->shutdown_lock);
2715
2716         /*
2717          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2718          * initializing procedure here.
2719          */
2720         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2721                 dev_warn(dev->ctrl.device,
2722                         "failed to mark controller CONNECTING\n");
2723                 result = -EBUSY;
2724                 goto out;
2725         }
2726
2727         result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
2728         if (result)
2729                 goto out;
2730
2731         nvme_dbbuf_dma_alloc(dev);
2732
2733         result = nvme_setup_host_mem(dev);
2734         if (result < 0)
2735                 goto out;
2736
2737         result = nvme_setup_io_queues(dev);
2738         if (result)
2739                 goto out;
2740
2741         /*
2742          * Freeze and update the number of I/O queues as thos might have
2743          * changed.  If there are no I/O queues left after this reset, keep the
2744          * controller around but remove all namespaces.
2745          */
2746         if (dev->online_queues > 1) {
2747                 nvme_unquiesce_io_queues(&dev->ctrl);
2748                 nvme_wait_freeze(&dev->ctrl);
2749                 nvme_pci_update_nr_queues(dev);
2750                 nvme_dbbuf_set(dev);
2751                 nvme_unfreeze(&dev->ctrl);
2752         } else {
2753                 dev_warn(dev->ctrl.device, "IO queues lost\n");
2754                 nvme_mark_namespaces_dead(&dev->ctrl);
2755                 nvme_unquiesce_io_queues(&dev->ctrl);
2756                 nvme_remove_namespaces(&dev->ctrl);
2757                 nvme_free_tagset(dev);
2758         }
2759
2760         /*
2761          * If only admin queue live, keep it to do further investigation or
2762          * recovery.
2763          */
2764         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2765                 dev_warn(dev->ctrl.device,
2766                         "failed to mark controller live state\n");
2767                 result = -ENODEV;
2768                 goto out;
2769         }
2770
2771         nvme_start_ctrl(&dev->ctrl);
2772         return;
2773
2774  out_unlock:
2775         mutex_unlock(&dev->shutdown_lock);
2776  out:
2777         /*
2778          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2779          * may be holding this pci_dev's device lock.
2780          */
2781         dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2782                  result);
2783         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2784         nvme_dev_disable(dev, true);
2785         nvme_sync_queues(&dev->ctrl);
2786         nvme_mark_namespaces_dead(&dev->ctrl);
2787         nvme_unquiesce_io_queues(&dev->ctrl);
2788         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2789 }
2790
2791 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2792 {
2793         *val = readl(to_nvme_dev(ctrl)->bar + off);
2794         return 0;
2795 }
2796
2797 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2798 {
2799         writel(val, to_nvme_dev(ctrl)->bar + off);
2800         return 0;
2801 }
2802
2803 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2804 {
2805         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2806         return 0;
2807 }
2808
2809 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2810 {
2811         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2812
2813         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2814 }
2815
2816 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2817 {
2818         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2819         struct nvme_subsystem *subsys = ctrl->subsys;
2820
2821         dev_err(ctrl->device,
2822                 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2823                 pdev->vendor, pdev->device,
2824                 nvme_strlen(subsys->model, sizeof(subsys->model)),
2825                 subsys->model, nvme_strlen(subsys->firmware_rev,
2826                                            sizeof(subsys->firmware_rev)),
2827                 subsys->firmware_rev);
2828 }
2829
2830 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2831 {
2832         struct nvme_dev *dev = to_nvme_dev(ctrl);
2833
2834         return dma_pci_p2pdma_supported(dev->dev);
2835 }
2836
2837 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2838         .name                   = "pcie",
2839         .module                 = THIS_MODULE,
2840         .flags                  = NVME_F_METADATA_SUPPORTED,
2841         .dev_attr_groups        = nvme_pci_dev_attr_groups,
2842         .reg_read32             = nvme_pci_reg_read32,
2843         .reg_write32            = nvme_pci_reg_write32,
2844         .reg_read64             = nvme_pci_reg_read64,
2845         .free_ctrl              = nvme_pci_free_ctrl,
2846         .submit_async_event     = nvme_pci_submit_async_event,
2847         .get_address            = nvme_pci_get_address,
2848         .print_device_info      = nvme_pci_print_device_info,
2849         .supports_pci_p2pdma    = nvme_pci_supports_pci_p2pdma,
2850 };
2851
2852 static int nvme_dev_map(struct nvme_dev *dev)
2853 {
2854         struct pci_dev *pdev = to_pci_dev(dev->dev);
2855
2856         if (pci_request_mem_regions(pdev, "nvme"))
2857                 return -ENODEV;
2858
2859         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2860                 goto release;
2861
2862         return 0;
2863   release:
2864         pci_release_mem_regions(pdev);
2865         return -ENODEV;
2866 }
2867
2868 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2869 {
2870         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2871                 /*
2872                  * Several Samsung devices seem to drop off the PCIe bus
2873                  * randomly when APST is on and uses the deepest sleep state.
2874                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2875                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2876                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2877                  * laptops.
2878                  */
2879                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2880                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2881                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2882                         return NVME_QUIRK_NO_DEEPEST_PS;
2883         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2884                 /*
2885                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2886                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2887                  * within few minutes after bootup on a Coffee Lake board -
2888                  * ASUS PRIME Z370-A
2889                  */
2890                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2891                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2892                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2893                         return NVME_QUIRK_NO_APST;
2894         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2895                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2896                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2897                 /*
2898                  * Forcing to use host managed nvme power settings for
2899                  * lowest idle power with quick resume latency on
2900                  * Samsung and Toshiba SSDs based on suspend behavior
2901                  * on Coffee Lake board for LENOVO C640
2902                  */
2903                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2904                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2905                         return NVME_QUIRK_SIMPLE_SUSPEND;
2906         }
2907
2908         return 0;
2909 }
2910
2911 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2912                 const struct pci_device_id *id)
2913 {
2914         unsigned long quirks = id->driver_data;
2915         int node = dev_to_node(&pdev->dev);
2916         struct nvme_dev *dev;
2917         int ret = -ENOMEM;
2918
2919         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2920         if (!dev)
2921                 return ERR_PTR(-ENOMEM);
2922         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2923         mutex_init(&dev->shutdown_lock);
2924
2925         dev->nr_write_queues = write_queues;
2926         dev->nr_poll_queues = poll_queues;
2927         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2928         dev->queues = kcalloc_node(dev->nr_allocated_queues,
2929                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2930         if (!dev->queues)
2931                 goto out_free_dev;
2932
2933         dev->dev = get_device(&pdev->dev);
2934
2935         quirks |= check_vendor_combination_bug(pdev);
2936         if (!noacpi && acpi_storage_d3(&pdev->dev)) {
2937                 /*
2938                  * Some systems use a bios work around to ask for D3 on
2939                  * platforms that support kernel managed suspend.
2940                  */
2941                 dev_info(&pdev->dev,
2942                          "platform quirk: setting simple suspend\n");
2943                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2944         }
2945         ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2946                              quirks);
2947         if (ret)
2948                 goto out_put_device;
2949
2950         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2951                 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
2952         else
2953                 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2954         dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2955         dma_set_max_seg_size(&pdev->dev, 0xffffffff);
2956
2957         /*
2958          * Limit the max command size to prevent iod->sg allocations going
2959          * over a single page.
2960          */
2961         dev->ctrl.max_hw_sectors = min_t(u32,
2962                 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
2963         dev->ctrl.max_segments = NVME_MAX_SEGS;
2964
2965         /*
2966          * There is no support for SGLs for metadata (yet), so we are limited to
2967          * a single integrity segment for the separate metadata pointer.
2968          */
2969         dev->ctrl.max_integrity_segments = 1;
2970         return dev;
2971
2972 out_put_device:
2973         put_device(dev->dev);
2974         kfree(dev->queues);
2975 out_free_dev:
2976         kfree(dev);
2977         return ERR_PTR(ret);
2978 }
2979
2980 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2981 {
2982         struct nvme_dev *dev;
2983         int result = -ENOMEM;
2984
2985         dev = nvme_pci_alloc_dev(pdev, id);
2986         if (IS_ERR(dev))
2987                 return PTR_ERR(dev);
2988
2989         result = nvme_dev_map(dev);
2990         if (result)
2991                 goto out_uninit_ctrl;
2992
2993         result = nvme_setup_prp_pools(dev);
2994         if (result)
2995                 goto out_dev_unmap;
2996
2997         result = nvme_pci_alloc_iod_mempool(dev);
2998         if (result)
2999                 goto out_release_prp_pools;
3000
3001         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3002
3003         result = nvme_pci_enable(dev);
3004         if (result)
3005                 goto out_release_iod_mempool;
3006
3007         result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3008                                 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
3009         if (result)
3010                 goto out_disable;
3011
3012         /*
3013          * Mark the controller as connecting before sending admin commands to
3014          * allow the timeout handler to do the right thing.
3015          */
3016         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3017                 dev_warn(dev->ctrl.device,
3018                         "failed to mark controller CONNECTING\n");
3019                 result = -EBUSY;
3020                 goto out_disable;
3021         }
3022
3023         result = nvme_init_ctrl_finish(&dev->ctrl, false);
3024         if (result)
3025                 goto out_disable;
3026
3027         nvme_dbbuf_dma_alloc(dev);
3028
3029         result = nvme_setup_host_mem(dev);
3030         if (result < 0)
3031                 goto out_disable;
3032
3033         result = nvme_setup_io_queues(dev);
3034         if (result)
3035                 goto out_disable;
3036
3037         if (dev->online_queues > 1) {
3038                 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3039                                 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3040                 nvme_dbbuf_set(dev);
3041         }
3042
3043         if (!dev->ctrl.tagset)
3044                 dev_warn(dev->ctrl.device, "IO queues not created\n");
3045
3046         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3047                 dev_warn(dev->ctrl.device,
3048                         "failed to mark controller live state\n");
3049                 result = -ENODEV;
3050                 goto out_disable;
3051         }
3052
3053         pci_set_drvdata(pdev, dev);
3054
3055         nvme_start_ctrl(&dev->ctrl);
3056         nvme_put_ctrl(&dev->ctrl);
3057         flush_work(&dev->ctrl.scan_work);
3058         return 0;
3059
3060 out_disable:
3061         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3062         nvme_dev_disable(dev, true);
3063         nvme_free_host_mem(dev);
3064         nvme_dev_remove_admin(dev);
3065         nvme_dbbuf_dma_free(dev);
3066         nvme_free_queues(dev, 0);
3067 out_release_iod_mempool:
3068         mempool_destroy(dev->iod_mempool);
3069 out_release_prp_pools:
3070         nvme_release_prp_pools(dev);
3071 out_dev_unmap:
3072         nvme_dev_unmap(dev);
3073 out_uninit_ctrl:
3074         nvme_uninit_ctrl(&dev->ctrl);
3075         nvme_put_ctrl(&dev->ctrl);
3076         return result;
3077 }
3078
3079 static void nvme_reset_prepare(struct pci_dev *pdev)
3080 {
3081         struct nvme_dev *dev = pci_get_drvdata(pdev);
3082
3083         /*
3084          * We don't need to check the return value from waiting for the reset
3085          * state as pci_dev device lock is held, making it impossible to race
3086          * with ->remove().
3087          */
3088         nvme_disable_prepare_reset(dev, false);
3089         nvme_sync_queues(&dev->ctrl);
3090 }
3091
3092 static void nvme_reset_done(struct pci_dev *pdev)
3093 {
3094         struct nvme_dev *dev = pci_get_drvdata(pdev);
3095
3096         if (!nvme_try_sched_reset(&dev->ctrl))
3097                 flush_work(&dev->ctrl.reset_work);
3098 }
3099
3100 static void nvme_shutdown(struct pci_dev *pdev)
3101 {
3102         struct nvme_dev *dev = pci_get_drvdata(pdev);
3103
3104         nvme_disable_prepare_reset(dev, true);
3105 }
3106
3107 /*
3108  * The driver's remove may be called on a device in a partially initialized
3109  * state. This function must not have any dependencies on the device state in
3110  * order to proceed.
3111  */
3112 static void nvme_remove(struct pci_dev *pdev)
3113 {
3114         struct nvme_dev *dev = pci_get_drvdata(pdev);
3115
3116         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3117         pci_set_drvdata(pdev, NULL);
3118
3119         if (!pci_device_is_present(pdev)) {
3120                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3121                 nvme_dev_disable(dev, true);
3122         }
3123
3124         flush_work(&dev->ctrl.reset_work);
3125         nvme_stop_ctrl(&dev->ctrl);
3126         nvme_remove_namespaces(&dev->ctrl);
3127         nvme_dev_disable(dev, true);
3128         nvme_free_host_mem(dev);
3129         nvme_dev_remove_admin(dev);
3130         nvme_dbbuf_dma_free(dev);
3131         nvme_free_queues(dev, 0);
3132         mempool_destroy(dev->iod_mempool);
3133         nvme_release_prp_pools(dev);
3134         nvme_dev_unmap(dev);
3135         nvme_uninit_ctrl(&dev->ctrl);
3136 }
3137
3138 #ifdef CONFIG_PM_SLEEP
3139 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3140 {
3141         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3142 }
3143
3144 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3145 {
3146         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3147 }
3148
3149 static int nvme_resume(struct device *dev)
3150 {
3151         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3152         struct nvme_ctrl *ctrl = &ndev->ctrl;
3153
3154         if (ndev->last_ps == U32_MAX ||
3155             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3156                 goto reset;
3157         if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3158                 goto reset;
3159
3160         return 0;
3161 reset:
3162         return nvme_try_sched_reset(ctrl);
3163 }
3164
3165 static int nvme_suspend(struct device *dev)
3166 {
3167         struct pci_dev *pdev = to_pci_dev(dev);
3168         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3169         struct nvme_ctrl *ctrl = &ndev->ctrl;
3170         int ret = -EBUSY;
3171
3172         ndev->last_ps = U32_MAX;
3173
3174         /*
3175          * The platform does not remove power for a kernel managed suspend so
3176          * use host managed nvme power settings for lowest idle power if
3177          * possible. This should have quicker resume latency than a full device
3178          * shutdown.  But if the firmware is involved after the suspend or the
3179          * device does not support any non-default power states, shut down the
3180          * device fully.
3181          *
3182          * If ASPM is not enabled for the device, shut down the device and allow
3183          * the PCI bus layer to put it into D3 in order to take the PCIe link
3184          * down, so as to allow the platform to achieve its minimum low-power
3185          * state (which may not be possible if the link is up).
3186          */
3187         if (pm_suspend_via_firmware() || !ctrl->npss ||
3188             !pcie_aspm_enabled(pdev) ||
3189             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3190                 return nvme_disable_prepare_reset(ndev, true);
3191
3192         nvme_start_freeze(ctrl);
3193         nvme_wait_freeze(ctrl);
3194         nvme_sync_queues(ctrl);
3195
3196         if (ctrl->state != NVME_CTRL_LIVE)
3197                 goto unfreeze;
3198
3199         /*
3200          * Host memory access may not be successful in a system suspend state,
3201          * but the specification allows the controller to access memory in a
3202          * non-operational power state.
3203          */
3204         if (ndev->hmb) {
3205                 ret = nvme_set_host_mem(ndev, 0);
3206                 if (ret < 0)
3207                         goto unfreeze;
3208         }
3209
3210         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3211         if (ret < 0)
3212                 goto unfreeze;
3213
3214         /*
3215          * A saved state prevents pci pm from generically controlling the
3216          * device's power. If we're using protocol specific settings, we don't
3217          * want pci interfering.
3218          */
3219         pci_save_state(pdev);
3220
3221         ret = nvme_set_power_state(ctrl, ctrl->npss);
3222         if (ret < 0)
3223                 goto unfreeze;
3224
3225         if (ret) {
3226                 /* discard the saved state */
3227                 pci_load_saved_state(pdev, NULL);
3228
3229                 /*
3230                  * Clearing npss forces a controller reset on resume. The
3231                  * correct value will be rediscovered then.
3232                  */
3233                 ret = nvme_disable_prepare_reset(ndev, true);
3234                 ctrl->npss = 0;
3235         }
3236 unfreeze:
3237         nvme_unfreeze(ctrl);
3238         return ret;
3239 }
3240
3241 static int nvme_simple_suspend(struct device *dev)
3242 {
3243         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3244
3245         return nvme_disable_prepare_reset(ndev, true);
3246 }
3247
3248 static int nvme_simple_resume(struct device *dev)
3249 {
3250         struct pci_dev *pdev = to_pci_dev(dev);
3251         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3252
3253         return nvme_try_sched_reset(&ndev->ctrl);
3254 }
3255
3256 static const struct dev_pm_ops nvme_dev_pm_ops = {
3257         .suspend        = nvme_suspend,
3258         .resume         = nvme_resume,
3259         .freeze         = nvme_simple_suspend,
3260         .thaw           = nvme_simple_resume,
3261         .poweroff       = nvme_simple_suspend,
3262         .restore        = nvme_simple_resume,
3263 };
3264 #endif /* CONFIG_PM_SLEEP */
3265
3266 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3267                                                 pci_channel_state_t state)
3268 {
3269         struct nvme_dev *dev = pci_get_drvdata(pdev);
3270
3271         /*
3272          * A frozen channel requires a reset. When detected, this method will
3273          * shutdown the controller to quiesce. The controller will be restarted
3274          * after the slot reset through driver's slot_reset callback.
3275          */
3276         switch (state) {
3277         case pci_channel_io_normal:
3278                 return PCI_ERS_RESULT_CAN_RECOVER;
3279         case pci_channel_io_frozen:
3280                 dev_warn(dev->ctrl.device,
3281                         "frozen state error detected, reset controller\n");
3282                 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
3283                         nvme_dev_disable(dev, true);
3284                         return PCI_ERS_RESULT_DISCONNECT;
3285                 }
3286                 nvme_dev_disable(dev, false);
3287                 return PCI_ERS_RESULT_NEED_RESET;
3288         case pci_channel_io_perm_failure:
3289                 dev_warn(dev->ctrl.device,
3290                         "failure state error detected, request disconnect\n");
3291                 return PCI_ERS_RESULT_DISCONNECT;
3292         }
3293         return PCI_ERS_RESULT_NEED_RESET;
3294 }
3295
3296 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3297 {
3298         struct nvme_dev *dev = pci_get_drvdata(pdev);
3299
3300         dev_info(dev->ctrl.device, "restart after slot reset\n");
3301         pci_restore_state(pdev);
3302         if (!nvme_try_sched_reset(&dev->ctrl))
3303                 nvme_unquiesce_io_queues(&dev->ctrl);
3304         return PCI_ERS_RESULT_RECOVERED;
3305 }
3306
3307 static void nvme_error_resume(struct pci_dev *pdev)
3308 {
3309         struct nvme_dev *dev = pci_get_drvdata(pdev);
3310
3311         flush_work(&dev->ctrl.reset_work);
3312 }
3313
3314 static const struct pci_error_handlers nvme_err_handler = {
3315         .error_detected = nvme_error_detected,
3316         .slot_reset     = nvme_slot_reset,
3317         .resume         = nvme_error_resume,
3318         .reset_prepare  = nvme_reset_prepare,
3319         .reset_done     = nvme_reset_done,
3320 };
3321
3322 static const struct pci_device_id nvme_id_table[] = {
3323         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3324                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3325                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3326         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3327                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3328                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3329         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3330                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3331                                 NVME_QUIRK_DEALLOCATE_ZEROES |
3332                                 NVME_QUIRK_IGNORE_DEV_SUBNQN |
3333                                 NVME_QUIRK_BOGUS_NID, },
3334         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3335                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3336                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3337         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3338                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3339                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3340                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3341                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3342         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3343                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3344         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3345                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3346                                 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3347                                 NVME_QUIRK_BOGUS_NID, },
3348         { PCI_VDEVICE(REDHAT, 0x0010),  /* Qemu emulated controller */
3349                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3350         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3351                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3352                                 NVME_QUIRK_BOGUS_NID, },
3353         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3354                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3355                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3356         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3357                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3358         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3359                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3360         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3361                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3362         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3363                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3364         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3365                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3366                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3367                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3368         { PCI_DEVICE(0x1987, 0x5012),   /* Phison E12 */
3369                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3370         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3371                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3372                                 NVME_QUIRK_BOGUS_NID, },
3373         { PCI_DEVICE(0x1987, 0x5019),  /* phison E19 */
3374                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3375         { PCI_DEVICE(0x1987, 0x5021),   /* Phison E21 */
3376                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3377         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3378                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3379                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3380         { PCI_DEVICE(0x1cc1, 0x33f8),   /* ADATA IM2P33F8ABR1 1 TB */
3381                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3382         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3383                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3384                                 NVME_QUIRK_BOGUS_NID, },
3385         { PCI_DEVICE(0x10ec, 0x5763),  /* ADATA SX6000PNP */
3386                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3387         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3388                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3389                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3390          { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3391                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3392          { PCI_DEVICE(0x1344, 0x6001),   /* Micron Nitro NVMe */
3393                  .driver_data = NVME_QUIRK_BOGUS_NID, },
3394         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3395                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3396         { PCI_DEVICE(0x1c5c, 0x174a),   /* SK Hynix P31 SSD */
3397                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3398         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3399                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3400         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3401                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3402         { PCI_DEVICE(0x144d, 0xa80b),   /* Samsung PM9B1 256G and 512G */
3403                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
3404                                 NVME_QUIRK_BOGUS_NID, },
3405         { PCI_DEVICE(0x144d, 0xa809),   /* Samsung MZALQ256HBJD 256G */
3406                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3407         { PCI_DEVICE(0x144d, 0xa802),   /* Samsung SM953 */
3408                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3409         { PCI_DEVICE(0x1cc4, 0x6303),   /* UMIS RPJTJ512MGE1QDY 512G */
3410                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3411         { PCI_DEVICE(0x1cc4, 0x6302),   /* UMIS RPJTJ256MGE1QDY 256G */
3412                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3413         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3414                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3415         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3416                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3417         { PCI_DEVICE(0x2646, 0x5013),   /* Kingston KC3000, Kingston FURY Renegade */
3418                 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
3419         { PCI_DEVICE(0x2646, 0x5018),   /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3420                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3421         { PCI_DEVICE(0x2646, 0x5016),   /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3422                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3423         { PCI_DEVICE(0x2646, 0x501A),   /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3424                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3425         { PCI_DEVICE(0x2646, 0x501B),   /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3426                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3427         { PCI_DEVICE(0x2646, 0x501E),   /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3428                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3429         { PCI_DEVICE(0x1f40, 0x1202),   /* Netac Technologies Co. NV3000 NVMe SSD */
3430                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3431         { PCI_DEVICE(0x1f40, 0x5236),   /* Netac Technologies Co. NV7000 NVMe SSD */
3432                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3433         { PCI_DEVICE(0x1e4B, 0x1001),   /* MAXIO MAP1001 */
3434                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3435         { PCI_DEVICE(0x1e4B, 0x1002),   /* MAXIO MAP1002 */
3436                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3437         { PCI_DEVICE(0x1e4B, 0x1202),   /* MAXIO MAP1202 */
3438                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3439         { PCI_DEVICE(0x1e4B, 0x1602),   /* MAXIO MAP1602 */
3440                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3441         { PCI_DEVICE(0x1cc1, 0x5350),   /* ADATA XPG GAMMIX S50 */
3442                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3443         { PCI_DEVICE(0x1dbe, 0x5236),   /* ADATA XPG GAMMIX S70 */
3444                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3445         { PCI_DEVICE(0x1e49, 0x0021),   /* ZHITAI TiPro5000 NVMe SSD */
3446                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3447         { PCI_DEVICE(0x1e49, 0x0041),   /* ZHITAI TiPro7000 NVMe SSD */
3448                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3449         { PCI_DEVICE(0xc0a9, 0x540a),   /* Crucial P2 */
3450                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3451         { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3452                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3453         { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3454                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3455         { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3456                 .driver_data = NVME_QUIRK_BOGUS_NID |
3457                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3458         { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3459                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3460         { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G  */
3461                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3462         { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3463                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3464         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3465                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3466         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3467                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3468         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3469                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3470         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3471                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3472         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3473                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3474         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3475                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3476         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3477                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3478         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3479         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3480                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3481                                 NVME_QUIRK_128_BYTES_SQES |
3482                                 NVME_QUIRK_SHARED_TAGS |
3483                                 NVME_QUIRK_SKIP_CID_GEN |
3484                                 NVME_QUIRK_IDENTIFY_CNS },
3485         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3486         { 0, }
3487 };
3488 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3489
3490 static struct pci_driver nvme_driver = {
3491         .name           = "nvme",
3492         .id_table       = nvme_id_table,
3493         .probe          = nvme_probe,
3494         .remove         = nvme_remove,
3495         .shutdown       = nvme_shutdown,
3496         .driver         = {
3497                 .probe_type     = PROBE_PREFER_ASYNCHRONOUS,
3498 #ifdef CONFIG_PM_SLEEP
3499                 .pm             = &nvme_dev_pm_ops,
3500 #endif
3501         },
3502         .sriov_configure = pci_sriov_configure_simple,
3503         .err_handler    = &nvme_err_handler,
3504 };
3505
3506 static int __init nvme_init(void)
3507 {
3508         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3509         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3510         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3511         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3512         BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
3513         BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3514         BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
3515
3516         return pci_register_driver(&nvme_driver);
3517 }
3518
3519 static void __exit nvme_exit(void)
3520 {
3521         pci_unregister_driver(&nvme_driver);
3522         flush_workqueue(nvme_wq);
3523 }
3524
3525 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3526 MODULE_LICENSE("GPL");
3527 MODULE_VERSION("1.0");
3528 module_init(nvme_init);
3529 module_exit(nvme_exit);