drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kthread.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_NR_AEN_COMMANDS    1
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  59
  60 unsigned char admin_timeout = 60;
  61 module_param(admin_timeout, byte, 0644);
  62 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  63
  64 unsigned char nvme_io_timeout = 30;
  65 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  66 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  67
  68 unsigned char shutdown_timeout = 5;
  69 module_param(shutdown_timeout, byte, 0644);
  70 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  71
  72 static int use_threaded_interrupts;
  73 module_param(use_threaded_interrupts, int, 0);
  74
  75 static bool use_cmb_sqes = true;
  76 module_param(use_cmb_sqes, bool, 0644);
  77 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  78
  79 static LIST_HEAD(dev_list);
  80 static struct task_struct *nvme_thread;
  81 static struct workqueue_struct *nvme_workq;
  82 static wait_queue_head_t nvme_kthread_wait;
  83
  84 struct nvme_dev;
  85 struct nvme_queue;
  86
  87 static int nvme_reset(struct nvme_dev *dev);
  88 static void nvme_process_cq(struct nvme_queue *nvmeq);
  89 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
  90 static void nvme_dev_shutdown(struct nvme_dev *dev);
  91
  92 struct async_cmd_info {
  93         struct kthread_work work;
  94         struct kthread_worker *worker;
  95         int status;
  96         void *ctx;
  97 };
  98
  99 /*
 100  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 101  */
 102 struct nvme_dev {
 103         struct list_head node;
 104         struct nvme_queue **queues;
 105         struct blk_mq_tag_set tagset;
 106         struct blk_mq_tag_set admin_tagset;
 107         u32 __iomem *dbs;
 108         struct device *dev;
 109         struct dma_pool *prp_page_pool;
 110         struct dma_pool *prp_small_pool;
 111         unsigned queue_count;
 112         unsigned online_queues;
 113         unsigned max_qid;
 114         int q_depth;
 115         u32 db_stride;
 116         struct msix_entry *entry;
 117         void __iomem *bar;
 118         struct work_struct reset_work;
 119         struct work_struct scan_work;
 120         struct work_struct remove_work;
 121         struct mutex shutdown_lock;
 122         bool subsystem;
 123         void __iomem *cmb;
 124         dma_addr_t cmb_dma_addr;
 125         u64 cmb_size;
 126         u32 cmbsz;
 127         unsigned long flags;
 128 #define NVME_CTRL_RESETTING    0
 129
 130         struct nvme_ctrl ctrl;
 131 };
 132
 133 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 134 {
 135         return container_of(ctrl, struct nvme_dev, ctrl);
 136 }
 137
 138 /*
 139  * An NVM Express queue.  Each device has at least two (one for admin
 140  * commands and one for I/O commands).
 141  */
 142 struct nvme_queue {
 143         struct device *q_dmadev;
 144         struct nvme_dev *dev;
 145         char irqname[24];       /* nvme4294967295-65535\0 */
 146         spinlock_t q_lock;
 147         struct nvme_command *sq_cmds;
 148         struct nvme_command __iomem *sq_cmds_io;
 149         volatile struct nvme_completion *cqes;
 150         struct blk_mq_tags **tags;
 151         dma_addr_t sq_dma_addr;
 152         dma_addr_t cq_dma_addr;
 153         u32 __iomem *q_db;
 154         u16 q_depth;
 155         s16 cq_vector;
 156         u16 sq_head;
 157         u16 sq_tail;
 158         u16 cq_head;
 159         u16 qid;
 160         u8 cq_phase;
 161         u8 cqe_seen;
 162         struct async_cmd_info cmdinfo;
 163 };
 164
 165 /*
 166  * The nvme_iod describes the data in an I/O, including the list of PRP
 167  * entries.  You can't see it in this data structure because C doesn't let
 168  * me express that.  Use nvme_init_iod to ensure there's enough space
 169  * allocated to store the PRP list.
 170  */
 171 struct nvme_iod {
 172         struct nvme_queue *nvmeq;
 173         int aborted;
 174         int npages;             /* In the PRP list. 0 means small pool in use */
 175         int nents;              /* Used in scatterlist */
 176         int length;             /* Of data, in bytes */
 177         dma_addr_t first_dma;
 178         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 179         struct scatterlist *sg;
 180         struct scatterlist inline_sg[0];
 181 };
 182
 183 /*
 184  * Check we didin't inadvertently grow the command struct
 185  */
 186 static inline void _nvme_check_size(void)
 187 {
 188         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 189         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 190         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 191         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 192         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 193         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 194         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 195         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 196         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 197         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 198         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 199         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 200 }
 201
 202 /*
 203  * Max size of iod being embedded in the request payload
 204  */
 205 #define NVME_INT_PAGES          2
 206 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 207
 208 /*
 209  * Will slightly overestimate the number of pages needed.  This is OK
 210  * as it only leads to a small amount of wasted memory for the lifetime of
 211  * the I/O.
 212  */
 213 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 214 {
 215         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 216                                       dev->ctrl.page_size);
 217         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 218 }
 219
 220 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 221                 unsigned int size, unsigned int nseg)
 222 {
 223         return sizeof(__le64 *) * nvme_npages(size, dev) +
 224                         sizeof(struct scatterlist) * nseg;
 225 }
 226
 227 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 228 {
 229         return sizeof(struct nvme_iod) +
 230                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 231 }
 232
 233 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 234                                 unsigned int hctx_idx)
 235 {
 236         struct nvme_dev *dev = data;
 237         struct nvme_queue *nvmeq = dev->queues[0];
 238
 239         WARN_ON(hctx_idx != 0);
 240         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 241         WARN_ON(nvmeq->tags);
 242
 243         hctx->driver_data = nvmeq;
 244         nvmeq->tags = &dev->admin_tagset.tags[0];
 245         return 0;
 246 }
 247
 248 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 249 {
 250         struct nvme_queue *nvmeq = hctx->driver_data;
 251
 252         nvmeq->tags = NULL;
 253 }
 254
 255 static int nvme_admin_init_request(void *data, struct request *req,
 256                                 unsigned int hctx_idx, unsigned int rq_idx,
 257                                 unsigned int numa_node)
 258 {
 259         struct nvme_dev *dev = data;
 260         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 261         struct nvme_queue *nvmeq = dev->queues[0];
 262
 263         BUG_ON(!nvmeq);
 264         iod->nvmeq = nvmeq;
 265         return 0;
 266 }
 267
 268 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 269                           unsigned int hctx_idx)
 270 {
 271         struct nvme_dev *dev = data;
 272         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 273
 274         if (!nvmeq->tags)
 275                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 276
 277         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 278         hctx->driver_data = nvmeq;
 279         return 0;
 280 }
 281
 282 static int nvme_init_request(void *data, struct request *req,
 283                                 unsigned int hctx_idx, unsigned int rq_idx,
 284                                 unsigned int numa_node)
 285 {
 286         struct nvme_dev *dev = data;
 287         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 288         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 289
 290         BUG_ON(!nvmeq);
 291         iod->nvmeq = nvmeq;
 292         return 0;
 293 }
 294
 295 static void nvme_complete_async_event(struct nvme_dev *dev,
 296                 struct nvme_completion *cqe)
 297 {
 298         u16 status = le16_to_cpu(cqe->status) >> 1;
 299         u32 result = le32_to_cpu(cqe->result);
 300
 301         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 302                 ++dev->ctrl.event_limit;
 303         if (status != NVME_SC_SUCCESS)
 304                 return;
 305
 306         switch (result & 0xff07) {
 307         case NVME_AER_NOTICE_NS_CHANGED:
 308                 dev_info(dev->dev, "rescanning\n");
 309                 queue_work(nvme_workq, &dev->scan_work);
 310         default:
 311                 dev_warn(dev->dev, "async event result %08x\n", result);
 312         }
 313 }
 314
 315 /**
 316  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 317  * @nvmeq: The queue to use
 318  * @cmd: The command to send
 319  *
 320  * Safe to use from interrupt context
 321  */
 322 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 323                                                 struct nvme_command *cmd)
 324 {
 325         u16 tail = nvmeq->sq_tail;
 326
 327         if (nvmeq->sq_cmds_io)
 328                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 329         else
 330                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 331
 332         if (++tail == nvmeq->q_depth)
 333                 tail = 0;
 334         writel(tail, nvmeq->q_db);
 335         nvmeq->sq_tail = tail;
 336 }
 337
 338 static __le64 **iod_list(struct request *req)
 339 {
 340         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 341         return (__le64 **)(iod->sg + req->nr_phys_segments);
 342 }
 343
 344 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 345 {
 346         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 347         int nseg = rq->nr_phys_segments;
 348         unsigned size;
 349
 350         if (rq->cmd_flags & REQ_DISCARD)
 351                 size = sizeof(struct nvme_dsm_range);
 352         else
 353                 size = blk_rq_bytes(rq);
 354
 355         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 356                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 357                 if (!iod->sg)
 358                         return BLK_MQ_RQ_QUEUE_BUSY;
 359         } else {
 360                 iod->sg = iod->inline_sg;
 361         }
 362
 363         iod->aborted = 0;
 364         iod->npages = -1;
 365         iod->nents = 0;
 366         iod->length = size;
 367         return 0;
 368 }
 369
 370 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 371 {
 372         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 373         const int last_prp = dev->ctrl.page_size / 8 - 1;
 374         int i;
 375         __le64 **list = iod_list(req);
 376         dma_addr_t prp_dma = iod->first_dma;
 377
 378         if (iod->npages == 0)
 379                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 380         for (i = 0; i < iod->npages; i++) {
 381                 __le64 *prp_list = list[i];
 382                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 383                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 384                 prp_dma = next_prp_dma;
 385         }
 386
 387         if (iod->sg != iod->inline_sg)
 388                 kfree(iod->sg);
 389 }
 390
 391 #ifdef CONFIG_BLK_DEV_INTEGRITY
 392 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 393 {
 394         if (be32_to_cpu(pi->ref_tag) == v)
 395                 pi->ref_tag = cpu_to_be32(p);
 396 }
 397
 398 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 399 {
 400         if (be32_to_cpu(pi->ref_tag) == p)
 401                 pi->ref_tag = cpu_to_be32(v);
 402 }
 403
 404 /**
 405  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 406  *
 407  * The virtual start sector is the one that was originally submitted by the
 408  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 409  * start sector may be different. Remap protection information to match the
 410  * physical LBA on writes, and back to the original seed on reads.
 411  *
 412  * Type 0 and 3 do not have a ref tag, so no remapping required.
 413  */
 414 static void nvme_dif_remap(struct request *req,
 415                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 416 {
 417         struct nvme_ns *ns = req->rq_disk->private_data;
 418         struct bio_integrity_payload *bip;
 419         struct t10_pi_tuple *pi;
 420         void *p, *pmap;
 421         u32 i, nlb, ts, phys, virt;
 422
 423         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 424                 return;
 425
 426         bip = bio_integrity(req->bio);
 427         if (!bip)
 428                 return;
 429
 430         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 431
 432         p = pmap;
 433         virt = bip_get_seed(bip);
 434         phys = nvme_block_nr(ns, blk_rq_pos(req));
 435         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 436         ts = ns->disk->queue->integrity.tuple_size;
 437
 438         for (i = 0; i < nlb; i++, virt++, phys++) {
 439                 pi = (struct t10_pi_tuple *)p;
 440                 dif_swap(phys, virt, pi);
 441                 p += ts;
 442         }
 443         kunmap_atomic(pmap);
 444 }
 445 #else /* CONFIG_BLK_DEV_INTEGRITY */
 446 static void nvme_dif_remap(struct request *req,
 447                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 448 {
 449 }
 450 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 451 {
 452 }
 453 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 454 {
 455 }
 456 #endif
 457
 458 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 459                 int total_len)
 460 {
 461         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 462         struct dma_pool *pool;
 463         int length = total_len;
 464         struct scatterlist *sg = iod->sg;
 465         int dma_len = sg_dma_len(sg);
 466         u64 dma_addr = sg_dma_address(sg);
 467         u32 page_size = dev->ctrl.page_size;
 468         int offset = dma_addr & (page_size - 1);
 469         __le64 *prp_list;
 470         __le64 **list = iod_list(req);
 471         dma_addr_t prp_dma;
 472         int nprps, i;
 473
 474         length -= (page_size - offset);
 475         if (length <= 0)
 476                 return true;
 477
 478         dma_len -= (page_size - offset);
 479         if (dma_len) {
 480                 dma_addr += (page_size - offset);
 481         } else {
 482                 sg = sg_next(sg);
 483                 dma_addr = sg_dma_address(sg);
 484                 dma_len = sg_dma_len(sg);
 485         }
 486
 487         if (length <= page_size) {
 488                 iod->first_dma = dma_addr;
 489                 return true;
 490         }
 491
 492         nprps = DIV_ROUND_UP(length, page_size);
 493         if (nprps <= (256 / 8)) {
 494                 pool = dev->prp_small_pool;
 495                 iod->npages = 0;
 496         } else {
 497                 pool = dev->prp_page_pool;
 498                 iod->npages = 1;
 499         }
 500
 501         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 502         if (!prp_list) {
 503                 iod->first_dma = dma_addr;
 504                 iod->npages = -1;
 505                 return false;
 506         }
 507         list[0] = prp_list;
 508         iod->first_dma = prp_dma;
 509         i = 0;
 510         for (;;) {
 511                 if (i == page_size >> 3) {
 512                         __le64 *old_prp_list = prp_list;
 513                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 514                         if (!prp_list)
 515                                 return false;
 516                         list[iod->npages++] = prp_list;
 517                         prp_list[0] = old_prp_list[i - 1];
 518                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 519                         i = 1;
 520                 }
 521                 prp_list[i++] = cpu_to_le64(dma_addr);
 522                 dma_len -= page_size;
 523                 dma_addr += page_size;
 524                 length -= page_size;
 525                 if (length <= 0)
 526                         break;
 527                 if (dma_len > 0)
 528                         continue;
 529                 BUG_ON(dma_len < 0);
 530                 sg = sg_next(sg);
 531                 dma_addr = sg_dma_address(sg);
 532                 dma_len = sg_dma_len(sg);
 533         }
 534
 535         return true;
 536 }
 537
 538 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 539                 struct nvme_command *cmnd)
 540 {
 541         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 542         struct request_queue *q = req->q;
 543         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 544                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 545         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 546
 547         sg_init_table(iod->sg, req->nr_phys_segments);
 548         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 549         if (!iod->nents)
 550                 goto out;
 551
 552         ret = BLK_MQ_RQ_QUEUE_BUSY;
 553         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 554                 goto out;
 555
 556         if (!nvme_setup_prps(dev, req, blk_rq_bytes(req)))
 557                 goto out_unmap;
 558
 559         ret = BLK_MQ_RQ_QUEUE_ERROR;
 560         if (blk_integrity_rq(req)) {
 561                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 562                         goto out_unmap;
 563
 564                 sg_init_table(&iod->meta_sg, 1);
 565                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 566                         goto out_unmap;
 567
 568                 if (rq_data_dir(req))
 569                         nvme_dif_remap(req, nvme_dif_prep);
 570
 571                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 572                         goto out_unmap;
 573         }
 574
 575         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 576         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 577         if (blk_integrity_rq(req))
 578                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 579         return BLK_MQ_RQ_QUEUE_OK;
 580
 581 out_unmap:
 582         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 583 out:
 584         return ret;
 585 }
 586
 587 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 588 {
 589         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 590         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 591                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 592
 593         if (iod->nents) {
 594                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 595                 if (blk_integrity_rq(req)) {
 596                         if (!rq_data_dir(req))
 597                                 nvme_dif_remap(req, nvme_dif_complete);
 598                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 599                 }
 600         }
 601
 602         nvme_free_iod(dev, req);
 603 }
 604
 605 /*
 606  * We reuse the small pool to allocate the 16-byte range here as it is not
 607  * worth having a special pool for these or additional cases to handle freeing
 608  * the iod.
 609  */
 610 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 611                 struct request *req, struct nvme_command *cmnd)
 612 {
 613         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 614         struct nvme_dsm_range *range;
 615
 616         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 617                                                 &iod->first_dma);
 618         if (!range)
 619                 return BLK_MQ_RQ_QUEUE_BUSY;
 620         iod_list(req)[0] = (__le64 *)range;
 621         iod->npages = 0;
 622
 623         range->cattr = cpu_to_le32(0);
 624         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 625         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 626
 627         memset(cmnd, 0, sizeof(*cmnd));
 628         cmnd->dsm.opcode = nvme_cmd_dsm;
 629         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 630         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 631         cmnd->dsm.nr = 0;
 632         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 633         return BLK_MQ_RQ_QUEUE_OK;
 634 }
 635
 636 /*
 637  * NOTE: ns is NULL when called on the admin queue.
 638  */
 639 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 640                          const struct blk_mq_queue_data *bd)
 641 {
 642         struct nvme_ns *ns = hctx->queue->queuedata;
 643         struct nvme_queue *nvmeq = hctx->driver_data;
 644         struct nvme_dev *dev = nvmeq->dev;
 645         struct request *req = bd->rq;
 646         struct nvme_command cmnd;
 647         int ret = BLK_MQ_RQ_QUEUE_OK;
 648
 649         /*
 650          * If formated with metadata, require the block layer provide a buffer
 651          * unless this namespace is formated such that the metadata can be
 652          * stripped/generated by the controller with PRACT=1.
 653          */
 654         if (ns && ns->ms && !blk_integrity_rq(req)) {
 655                 if (!(ns->pi_type && ns->ms == 8) &&
 656                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 657                         blk_mq_end_request(req, -EFAULT);
 658                         return BLK_MQ_RQ_QUEUE_OK;
 659                 }
 660         }
 661
 662         ret = nvme_init_iod(req, dev);
 663         if (ret)
 664                 return ret;
 665
 666         if (req->cmd_flags & REQ_DISCARD) {
 667                 ret = nvme_setup_discard(nvmeq, ns, req, &cmnd);
 668         } else {
 669                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 670                         memcpy(&cmnd, req->cmd, sizeof(cmnd));
 671                 else if (req->cmd_flags & REQ_FLUSH)
 672                         nvme_setup_flush(ns, &cmnd);
 673                 else
 674                         nvme_setup_rw(ns, req, &cmnd);
 675
 676                 if (req->nr_phys_segments)
 677                         ret = nvme_map_data(dev, req, &cmnd);
 678         }
 679
 680         if (ret)
 681                 goto out;
 682
 683         cmnd.common.command_id = req->tag;
 684         blk_mq_start_request(req);
 685
 686         spin_lock_irq(&nvmeq->q_lock);
 687         __nvme_submit_cmd(nvmeq, &cmnd);
 688         nvme_process_cq(nvmeq);
 689         spin_unlock_irq(&nvmeq->q_lock);
 690         return BLK_MQ_RQ_QUEUE_OK;
 691 out:
 692         nvme_free_iod(dev, req);
 693         return ret;
 694 }
 695
 696 static void nvme_complete_rq(struct request *req)
 697 {
 698         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 699         struct nvme_dev *dev = iod->nvmeq->dev;
 700         int error = 0;
 701
 702         nvme_unmap_data(dev, req);
 703
 704         if (unlikely(req->errors)) {
 705                 if (nvme_req_needs_retry(req, req->errors)) {
 706                         nvme_requeue_req(req);
 707                         return;
 708                 }
 709
 710                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 711                         error = req->errors;
 712                 else
 713                         error = nvme_error_status(req->errors);
 714         }
 715
 716         if (unlikely(iod->aborted)) {
 717                 dev_warn(dev->dev,
 718                         "completing aborted command with status: %04x\n",
 719                         req->errors);
 720         }
 721
 722         blk_mq_end_request(req, error);
 723 }
 724
 725 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 726 {
 727         u16 head, phase;
 728
 729         head = nvmeq->cq_head;
 730         phase = nvmeq->cq_phase;
 731
 732         for (;;) {
 733                 struct nvme_completion cqe = nvmeq->cqes[head];
 734                 u16 status = le16_to_cpu(cqe.status);
 735                 struct request *req;
 736
 737                 if ((status & 1) != phase)
 738                         break;
 739                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 740                 if (++head == nvmeq->q_depth) {
 741                         head = 0;
 742                         phase = !phase;
 743                 }
 744
 745                 if (tag && *tag == cqe.command_id)
 746                         *tag = -1;
 747
 748                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 749                         dev_warn(nvmeq->q_dmadev,
 750                                 "invalid id %d completed on queue %d\n",
 751                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 752                         continue;
 753                 }
 754
 755                 /*
 756                  * AEN requests are special as they don't time out and can
 757                  * survive any kind of queue freeze and often don't respond to
 758                  * aborts.  We don't even bother to allocate a struct request
 759                  * for them but rather special case them here.
 760                  */
 761                 if (unlikely(nvmeq->qid == 0 &&
 762                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 763                         nvme_complete_async_event(nvmeq->dev, &cqe);
 764                         continue;
 765                 }
 766
 767                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 768                 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 769                         u32 result = le32_to_cpu(cqe.result);
 770                         req->special = (void *)(uintptr_t)result;
 771                 }
 772                 blk_mq_complete_request(req, status >> 1);
 773
 774         }
 775
 776         /* If the controller ignores the cq head doorbell and continuously
 777          * writes to the queue, it is theoretically possible to wrap around
 778          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 779          * requires that 0.1% of your interrupts are handled, so this isn't
 780          * a big problem.
 781          */
 782         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 783                 return;
 784
 785         if (likely(nvmeq->cq_vector >= 0))
 786                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 787         nvmeq->cq_head = head;
 788         nvmeq->cq_phase = phase;
 789
 790         nvmeq->cqe_seen = 1;
 791 }
 792
 793 static void nvme_process_cq(struct nvme_queue *nvmeq)
 794 {
 795         __nvme_process_cq(nvmeq, NULL);
 796 }
 797
 798 static irqreturn_t nvme_irq(int irq, void *data)
 799 {
 800         irqreturn_t result;
 801         struct nvme_queue *nvmeq = data;
 802         spin_lock(&nvmeq->q_lock);
 803         nvme_process_cq(nvmeq);
 804         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 805         nvmeq->cqe_seen = 0;
 806         spin_unlock(&nvmeq->q_lock);
 807         return result;
 808 }
 809
 810 static irqreturn_t nvme_irq_check(int irq, void *data)
 811 {
 812         struct nvme_queue *nvmeq = data;
 813         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 814         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 815                 return IRQ_NONE;
 816         return IRQ_WAKE_THREAD;
 817 }
 818
 819 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 820 {
 821         struct nvme_queue *nvmeq = hctx->driver_data;
 822
 823         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 824             nvmeq->cq_phase) {
 825                 spin_lock_irq(&nvmeq->q_lock);
 826                 __nvme_process_cq(nvmeq, &tag);
 827                 spin_unlock_irq(&nvmeq->q_lock);
 828
 829                 if (tag == -1)
 830                         return 1;
 831         }
 832
 833         return 0;
 834 }
 835
 836 static void nvme_submit_async_event(struct nvme_dev *dev)
 837 {
 838         struct nvme_command c;
 839
 840         memset(&c, 0, sizeof(c));
 841         c.common.opcode = nvme_admin_async_event;
 842         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit;
 843
 844         __nvme_submit_cmd(dev->queues[0], &c);
 845 }
 846
 847 static void async_cmd_info_endio(struct request *req, int error)
 848 {
 849         struct async_cmd_info *cmdinfo = req->end_io_data;
 850
 851         cmdinfo->status = req->errors;
 852         queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
 853         blk_mq_free_request(req);
 854 }
 855
 856 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 857 {
 858         struct nvme_command c;
 859
 860         memset(&c, 0, sizeof(c));
 861         c.delete_queue.opcode = opcode;
 862         c.delete_queue.qid = cpu_to_le16(id);
 863
 864         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 865 }
 866
 867 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 868                                                 struct nvme_queue *nvmeq)
 869 {
 870         struct nvme_command c;
 871         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 872
 873         /*
 874          * Note: we (ab)use the fact the the prp fields survive if no data
 875          * is attached to the request.
 876          */
 877         memset(&c, 0, sizeof(c));
 878         c.create_cq.opcode = nvme_admin_create_cq;
 879         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 880         c.create_cq.cqid = cpu_to_le16(qid);
 881         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 882         c.create_cq.cq_flags = cpu_to_le16(flags);
 883         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 884
 885         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 886 }
 887
 888 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 889                                                 struct nvme_queue *nvmeq)
 890 {
 891         struct nvme_command c;
 892         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 893
 894         /*
 895          * Note: we (ab)use the fact the the prp fields survive if no data
 896          * is attached to the request.
 897          */
 898         memset(&c, 0, sizeof(c));
 899         c.create_sq.opcode = nvme_admin_create_sq;
 900         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 901         c.create_sq.sqid = cpu_to_le16(qid);
 902         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 903         c.create_sq.sq_flags = cpu_to_le16(flags);
 904         c.create_sq.cqid = cpu_to_le16(qid);
 905
 906         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 907 }
 908
 909 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 910 {
 911         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 912 }
 913
 914 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 915 {
 916         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 917 }
 918
 919 static void abort_endio(struct request *req, int error)
 920 {
 921         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 922         struct nvme_queue *nvmeq = iod->nvmeq;
 923         u32 result = (u32)(uintptr_t)req->special;
 924         u16 status = req->errors;
 925
 926         dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
 927         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 928
 929         blk_mq_free_request(req);
 930 }
 931
 932 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 933 {
 934         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 935         struct nvme_queue *nvmeq = iod->nvmeq;
 936         struct nvme_dev *dev = nvmeq->dev;
 937         struct request *abort_req;
 938         struct nvme_command cmd;
 939
 940         /*
 941          * Shutdown immediately if controller times out while starting. The
 942          * reset work will see the pci device disabled when it gets the forced
 943          * cancellation error. All outstanding requests are completed on
 944          * shutdown, so we return BLK_EH_HANDLED.
 945          */
 946         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
 947                 dev_warn(dev->dev,
 948                          "I/O %d QID %d timeout, disable controller\n",
 949                          req->tag, nvmeq->qid);
 950                 nvme_dev_shutdown(dev);
 951                 req->errors = NVME_SC_CANCELLED;
 952                 return BLK_EH_HANDLED;
 953         }
 954
 955         /*
 956          * Shutdown the controller immediately and schedule a reset if the
 957          * command was already aborted once before and still hasn't been
 958          * returned to the driver, or if this is the admin queue.
 959          */
 960         if (!nvmeq->qid || iod->aborted) {
 961                 dev_warn(dev->dev,
 962                          "I/O %d QID %d timeout, reset controller\n",
 963                          req->tag, nvmeq->qid);
 964                 nvme_dev_shutdown(dev);
 965                 queue_work(nvme_workq, &dev->reset_work);
 966
 967                 /*
 968                  * Mark the request as handled, since the inline shutdown
 969                  * forces all outstanding requests to complete.
 970                  */
 971                 req->errors = NVME_SC_CANCELLED;
 972                 return BLK_EH_HANDLED;
 973         }
 974
 975         iod->aborted = 1;
 976
 977         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 978                 atomic_inc(&dev->ctrl.abort_limit);
 979                 return BLK_EH_RESET_TIMER;
 980         }
 981
 982         memset(&cmd, 0, sizeof(cmd));
 983         cmd.abort.opcode = nvme_admin_abort_cmd;
 984         cmd.abort.cid = req->tag;
 985         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 986
 987         dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n",
 988                                  req->tag, nvmeq->qid);
 989
 990         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 991                         BLK_MQ_REQ_NOWAIT);
 992         if (IS_ERR(abort_req)) {
 993                 atomic_inc(&dev->ctrl.abort_limit);
 994                 return BLK_EH_RESET_TIMER;
 995         }
 996
 997         abort_req->timeout = ADMIN_TIMEOUT;
 998         abort_req->end_io_data = NULL;
 999         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1000
1001         /*
1002          * The aborted req will be completed on receiving the abort req.
1003          * We enable the timer again. If hit twice, it'll cause a device reset,
1004          * as the device then is in a faulty state.
1005          */
1006         return BLK_EH_RESET_TIMER;
1007 }
1008
1009 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1010 {
1011         struct nvme_queue *nvmeq = data;
1012         int status;
1013
1014         if (!blk_mq_request_started(req))
1015                 return;
1016
1017         dev_warn(nvmeq->q_dmadev,
1018                  "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid);
1019
1020         status = NVME_SC_CANCELLED;
1021         if (blk_queue_dying(req->q))
1022                 status |= NVME_SC_DNR;
1023         blk_mq_complete_request(req, status);
1024 }
1025
1026 static void nvme_free_queue(struct nvme_queue *nvmeq)
1027 {
1028         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1029                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1030         if (nvmeq->sq_cmds)
1031                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1032                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1033         kfree(nvmeq);
1034 }
1035
1036 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1037 {
1038         int i;
1039
1040         for (i = dev->queue_count - 1; i >= lowest; i--) {
1041                 struct nvme_queue *nvmeq = dev->queues[i];
1042                 dev->queue_count--;
1043                 dev->queues[i] = NULL;
1044                 nvme_free_queue(nvmeq);
1045         }
1046 }
1047
1048 /**
1049  * nvme_suspend_queue - put queue into suspended state
1050  * @nvmeq - queue to suspend
1051  */
1052 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1053 {
1054         int vector;
1055
1056         spin_lock_irq(&nvmeq->q_lock);
1057         if (nvmeq->cq_vector == -1) {
1058                 spin_unlock_irq(&nvmeq->q_lock);
1059                 return 1;
1060         }
1061         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1062         nvmeq->dev->online_queues--;
1063         nvmeq->cq_vector = -1;
1064         spin_unlock_irq(&nvmeq->q_lock);
1065
1066         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1067                 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q);
1068
1069         irq_set_affinity_hint(vector, NULL);
1070         free_irq(vector, nvmeq);
1071
1072         return 0;
1073 }
1074
1075 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1076 {
1077         spin_lock_irq(&nvmeq->q_lock);
1078         if (nvmeq->tags && *nvmeq->tags)
1079                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1080         spin_unlock_irq(&nvmeq->q_lock);
1081 }
1082
1083 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1084 {
1085         struct nvme_queue *nvmeq = dev->queues[qid];
1086
1087         if (!nvmeq)
1088                 return;
1089         if (nvme_suspend_queue(nvmeq))
1090                 return;
1091
1092         /* Don't tell the adapter to delete the admin queue.
1093          * Don't tell a removed adapter to delete IO queues. */
1094         if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) {
1095                 adapter_delete_sq(dev, qid);
1096                 adapter_delete_cq(dev, qid);
1097         }
1098
1099         spin_lock_irq(&nvmeq->q_lock);
1100         nvme_process_cq(nvmeq);
1101         spin_unlock_irq(&nvmeq->q_lock);
1102 }
1103
1104 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1105                                 int entry_size)
1106 {
1107         int q_depth = dev->q_depth;
1108         unsigned q_size_aligned = roundup(q_depth * entry_size,
1109                                           dev->ctrl.page_size);
1110
1111         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1112                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1113                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1114                 q_depth = div_u64(mem_per_q, entry_size);
1115
1116                 /*
1117                  * Ensure the reduced q_depth is above some threshold where it
1118                  * would be better to map queues in system memory with the
1119                  * original depth
1120                  */
1121                 if (q_depth < 64)
1122                         return -ENOMEM;
1123         }
1124
1125         return q_depth;
1126 }
1127
1128 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1129                                 int qid, int depth)
1130 {
1131         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1132                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1133                                                       dev->ctrl.page_size);
1134                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1135                 nvmeq->sq_cmds_io = dev->cmb + offset;
1136         } else {
1137                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1138                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1139                 if (!nvmeq->sq_cmds)
1140                         return -ENOMEM;
1141         }
1142
1143         return 0;
1144 }
1145
1146 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1147                                                         int depth)
1148 {
1149         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1150         if (!nvmeq)
1151                 return NULL;
1152
1153         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1154                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1155         if (!nvmeq->cqes)
1156                 goto free_nvmeq;
1157
1158         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1159                 goto free_cqdma;
1160
1161         nvmeq->q_dmadev = dev->dev;
1162         nvmeq->dev = dev;
1163         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1164                         dev->ctrl.instance, qid);
1165         spin_lock_init(&nvmeq->q_lock);
1166         nvmeq->cq_head = 0;
1167         nvmeq->cq_phase = 1;
1168         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1169         nvmeq->q_depth = depth;
1170         nvmeq->qid = qid;
1171         nvmeq->cq_vector = -1;
1172         dev->queues[qid] = nvmeq;
1173
1174         /* make sure queue descriptor is set before queue count, for kthread */
1175         mb();
1176         dev->queue_count++;
1177
1178         return nvmeq;
1179
1180  free_cqdma:
1181         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1182                                                         nvmeq->cq_dma_addr);
1183  free_nvmeq:
1184         kfree(nvmeq);
1185         return NULL;
1186 }
1187
1188 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1189                                                         const char *name)
1190 {
1191         if (use_threaded_interrupts)
1192                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1193                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1194                                         name, nvmeq);
1195         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1196                                 IRQF_SHARED, name, nvmeq);
1197 }
1198
1199 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1200 {
1201         struct nvme_dev *dev = nvmeq->dev;
1202
1203         spin_lock_irq(&nvmeq->q_lock);
1204         nvmeq->sq_tail = 0;
1205         nvmeq->cq_head = 0;
1206         nvmeq->cq_phase = 1;
1207         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1208         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1209         dev->online_queues++;
1210         spin_unlock_irq(&nvmeq->q_lock);
1211 }
1212
1213 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1214 {
1215         struct nvme_dev *dev = nvmeq->dev;
1216         int result;
1217
1218         nvmeq->cq_vector = qid - 1;
1219         result = adapter_alloc_cq(dev, qid, nvmeq);
1220         if (result < 0)
1221                 return result;
1222
1223         result = adapter_alloc_sq(dev, qid, nvmeq);
1224         if (result < 0)
1225                 goto release_cq;
1226
1227         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1228         if (result < 0)
1229                 goto release_sq;
1230
1231         nvme_init_queue(nvmeq, qid);
1232         return result;
1233
1234  release_sq:
1235         adapter_delete_sq(dev, qid);
1236  release_cq:
1237         adapter_delete_cq(dev, qid);
1238         return result;
1239 }
1240
1241 static struct blk_mq_ops nvme_mq_admin_ops = {
1242         .queue_rq       = nvme_queue_rq,
1243         .complete       = nvme_complete_rq,
1244         .map_queue      = blk_mq_map_queue,
1245         .init_hctx      = nvme_admin_init_hctx,
1246         .exit_hctx      = nvme_admin_exit_hctx,
1247         .init_request   = nvme_admin_init_request,
1248         .timeout        = nvme_timeout,
1249 };
1250
1251 static struct blk_mq_ops nvme_mq_ops = {
1252         .queue_rq       = nvme_queue_rq,
1253         .complete       = nvme_complete_rq,
1254         .map_queue      = blk_mq_map_queue,
1255         .init_hctx      = nvme_init_hctx,
1256         .init_request   = nvme_init_request,
1257         .timeout        = nvme_timeout,
1258         .poll           = nvme_poll,
1259 };
1260
1261 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1262 {
1263         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1264                 blk_cleanup_queue(dev->ctrl.admin_q);
1265                 blk_mq_free_tag_set(&dev->admin_tagset);
1266         }
1267 }
1268
1269 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1270 {
1271         if (!dev->ctrl.admin_q) {
1272                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1273                 dev->admin_tagset.nr_hw_queues = 1;
1274
1275                 /*
1276                  * Subtract one to leave an empty queue entry for 'Full Queue'
1277                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1278                  */
1279                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1280                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1281                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1282                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1283                 dev->admin_tagset.driver_data = dev;
1284
1285                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1286                         return -ENOMEM;
1287
1288                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1289                 if (IS_ERR(dev->ctrl.admin_q)) {
1290                         blk_mq_free_tag_set(&dev->admin_tagset);
1291                         return -ENOMEM;
1292                 }
1293                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1294                         nvme_dev_remove_admin(dev);
1295                         dev->ctrl.admin_q = NULL;
1296                         return -ENODEV;
1297                 }
1298         } else
1299                 blk_mq_unfreeze_queue(dev->ctrl.admin_q);
1300
1301         return 0;
1302 }
1303
1304 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1305 {
1306         int result;
1307         u32 aqa;
1308         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1309         struct nvme_queue *nvmeq;
1310
1311         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1312                                                 NVME_CAP_NSSRC(cap) : 0;
1313
1314         if (dev->subsystem &&
1315             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1316                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1317
1318         result = nvme_disable_ctrl(&dev->ctrl, cap);
1319         if (result < 0)
1320                 return result;
1321
1322         nvmeq = dev->queues[0];
1323         if (!nvmeq) {
1324                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1325                 if (!nvmeq)
1326                         return -ENOMEM;
1327         }
1328
1329         aqa = nvmeq->q_depth - 1;
1330         aqa |= aqa << 16;
1331
1332         writel(aqa, dev->bar + NVME_REG_AQA);
1333         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1334         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1335
1336         result = nvme_enable_ctrl(&dev->ctrl, cap);
1337         if (result)
1338                 goto free_nvmeq;
1339
1340         nvmeq->cq_vector = 0;
1341         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1342         if (result) {
1343                 nvmeq->cq_vector = -1;
1344                 goto free_nvmeq;
1345         }
1346
1347         return result;
1348
1349  free_nvmeq:
1350         nvme_free_queues(dev, 0);
1351         return result;
1352 }
1353
1354 static int nvme_kthread(void *data)
1355 {
1356         struct nvme_dev *dev, *next;
1357
1358         while (!kthread_should_stop()) {
1359                 set_current_state(TASK_INTERRUPTIBLE);
1360                 spin_lock(&dev_list_lock);
1361                 list_for_each_entry_safe(dev, next, &dev_list, node) {
1362                         int i;
1363                         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1364
1365                         /*
1366                          * Skip controllers currently under reset.
1367                          */
1368                         if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1369                                 continue;
1370
1371                         if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1372                                                         csts & NVME_CSTS_CFS) {
1373                                 if (queue_work(nvme_workq, &dev->reset_work)) {
1374                                         dev_warn(dev->dev,
1375                                                 "Failed status: %x, reset controller\n",
1376                                                 readl(dev->bar + NVME_REG_CSTS));
1377                                 }
1378                                 continue;
1379                         }
1380                         for (i = 0; i < dev->queue_count; i++) {
1381                                 struct nvme_queue *nvmeq = dev->queues[i];
1382                                 if (!nvmeq)
1383                                         continue;
1384                                 spin_lock_irq(&nvmeq->q_lock);
1385                                 nvme_process_cq(nvmeq);
1386
1387                                 while (i == 0 && dev->ctrl.event_limit > 0)
1388                                         nvme_submit_async_event(dev);
1389                                 spin_unlock_irq(&nvmeq->q_lock);
1390                         }
1391                 }
1392                 spin_unlock(&dev_list_lock);
1393                 schedule_timeout(round_jiffies_relative(HZ));
1394         }
1395         return 0;
1396 }
1397
1398 static int nvme_create_io_queues(struct nvme_dev *dev)
1399 {
1400         unsigned i;
1401         int ret = 0;
1402
1403         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1404                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1405                         ret = -ENOMEM;
1406                         break;
1407                 }
1408         }
1409
1410         for (i = dev->online_queues; i <= dev->queue_count - 1; i++) {
1411                 ret = nvme_create_queue(dev->queues[i], i);
1412                 if (ret) {
1413                         nvme_free_queues(dev, i);
1414                         break;
1415                 }
1416         }
1417
1418         /*
1419          * Ignore failing Create SQ/CQ commands, we can continue with less
1420          * than the desired aount of queues, and even a controller without
1421          * I/O queues an still be used to issue admin commands.  This might
1422          * be useful to upgrade a buggy firmware for example.
1423          */
1424         return ret >= 0 ? 0 : ret;
1425 }
1426
1427 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1428 {
1429         u64 szu, size, offset;
1430         u32 cmbloc;
1431         resource_size_t bar_size;
1432         struct pci_dev *pdev = to_pci_dev(dev->dev);
1433         void __iomem *cmb;
1434         dma_addr_t dma_addr;
1435
1436         if (!use_cmb_sqes)
1437                 return NULL;
1438
1439         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1440         if (!(NVME_CMB_SZ(dev->cmbsz)))
1441                 return NULL;
1442
1443         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1444
1445         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1446         size = szu * NVME_CMB_SZ(dev->cmbsz);
1447         offset = szu * NVME_CMB_OFST(cmbloc);
1448         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1449
1450         if (offset > bar_size)
1451                 return NULL;
1452
1453         /*
1454          * Controllers may support a CMB size larger than their BAR,
1455          * for example, due to being behind a bridge. Reduce the CMB to
1456          * the reported size of the BAR
1457          */
1458         if (size > bar_size - offset)
1459                 size = bar_size - offset;
1460
1461         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1462         cmb = ioremap_wc(dma_addr, size);
1463         if (!cmb)
1464                 return NULL;
1465
1466         dev->cmb_dma_addr = dma_addr;
1467         dev->cmb_size = size;
1468         return cmb;
1469 }
1470
1471 static inline void nvme_release_cmb(struct nvme_dev *dev)
1472 {
1473         if (dev->cmb) {
1474                 iounmap(dev->cmb);
1475                 dev->cmb = NULL;
1476         }
1477 }
1478
1479 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1480 {
1481         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1482 }
1483
1484 static int nvme_setup_io_queues(struct nvme_dev *dev)
1485 {
1486         struct nvme_queue *adminq = dev->queues[0];
1487         struct pci_dev *pdev = to_pci_dev(dev->dev);
1488         int result, i, vecs, nr_io_queues, size;
1489
1490         nr_io_queues = num_possible_cpus();
1491         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1492         if (result < 0)
1493                 return result;
1494
1495         /*
1496          * Degraded controllers might return an error when setting the queue
1497          * count.  We still want to be able to bring them online and offer
1498          * access to the admin queue, as that might be only way to fix them up.
1499          */
1500         if (result > 0) {
1501                 dev_err(dev->dev, "Could not set queue count (%d)\n", result);
1502                 nr_io_queues = 0;
1503                 result = 0;
1504         }
1505
1506         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1507                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1508                                 sizeof(struct nvme_command));
1509                 if (result > 0)
1510                         dev->q_depth = result;
1511                 else
1512                         nvme_release_cmb(dev);
1513         }
1514
1515         size = db_bar_size(dev, nr_io_queues);
1516         if (size > 8192) {
1517                 iounmap(dev->bar);
1518                 do {
1519                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1520                         if (dev->bar)
1521                                 break;
1522                         if (!--nr_io_queues)
1523                                 return -ENOMEM;
1524                         size = db_bar_size(dev, nr_io_queues);
1525                 } while (1);
1526                 dev->dbs = dev->bar + 4096;
1527                 adminq->q_db = dev->dbs;
1528         }
1529
1530         /* Deregister the admin queue's interrupt */
1531         free_irq(dev->entry[0].vector, adminq);
1532
1533         /*
1534          * If we enable msix early due to not intx, disable it again before
1535          * setting up the full range we need.
1536          */
1537         if (!pdev->irq)
1538                 pci_disable_msix(pdev);
1539
1540         for (i = 0; i < nr_io_queues; i++)
1541                 dev->entry[i].entry = i;
1542         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1543         if (vecs < 0) {
1544                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1545                 if (vecs < 0) {
1546                         vecs = 1;
1547                 } else {
1548                         for (i = 0; i < vecs; i++)
1549                                 dev->entry[i].vector = i + pdev->irq;
1550                 }
1551         }
1552
1553         /*
1554          * Should investigate if there's a performance win from allocating
1555          * more queues than interrupt vectors; it might allow the submission
1556          * path to scale better, even if the receive path is limited by the
1557          * number of interrupts.
1558          */
1559         nr_io_queues = vecs;
1560         dev->max_qid = nr_io_queues;
1561
1562         result = queue_request_irq(dev, adminq, adminq->irqname);
1563         if (result) {
1564                 adminq->cq_vector = -1;
1565                 goto free_queues;
1566         }
1567
1568         /* Free previously allocated queues that are no longer usable */
1569         nvme_free_queues(dev, nr_io_queues + 1);
1570         return nvme_create_io_queues(dev);
1571
1572  free_queues:
1573         nvme_free_queues(dev, 1);
1574         return result;
1575 }
1576
1577 static void nvme_set_irq_hints(struct nvme_dev *dev)
1578 {
1579         struct nvme_queue *nvmeq;
1580         int i;
1581
1582         for (i = 0; i < dev->online_queues; i++) {
1583                 nvmeq = dev->queues[i];
1584
1585                 if (!nvmeq->tags || !(*nvmeq->tags))
1586                         continue;
1587
1588                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1589                                         blk_mq_tags_cpumask(*nvmeq->tags));
1590         }
1591 }
1592
1593 static void nvme_dev_scan(struct work_struct *work)
1594 {
1595         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1596
1597         if (!dev->tagset.tags)
1598                 return;
1599         nvme_scan_namespaces(&dev->ctrl);
1600         nvme_set_irq_hints(dev);
1601 }
1602
1603 /*
1604  * Return: error value if an error occurred setting up the queues or calling
1605  * Identify Device.  0 if these succeeded, even if adding some of the
1606  * namespaces failed.  At the moment, these failures are silent.  TBD which
1607  * failures should be reported.
1608  */
1609 static int nvme_dev_add(struct nvme_dev *dev)
1610 {
1611         if (!dev->ctrl.tagset) {
1612                 dev->tagset.ops = &nvme_mq_ops;
1613                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1614                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1615                 dev->tagset.numa_node = dev_to_node(dev->dev);
1616                 dev->tagset.queue_depth =
1617                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1618                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1619                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1620                 dev->tagset.driver_data = dev;
1621
1622                 if (blk_mq_alloc_tag_set(&dev->tagset))
1623                         return 0;
1624                 dev->ctrl.tagset = &dev->tagset;
1625         }
1626         queue_work(nvme_workq, &dev->scan_work);
1627         return 0;
1628 }
1629
1630 static int nvme_dev_map(struct nvme_dev *dev)
1631 {
1632         u64 cap;
1633         int bars, result = -ENOMEM;
1634         struct pci_dev *pdev = to_pci_dev(dev->dev);
1635
1636         if (pci_enable_device_mem(pdev))
1637                 return result;
1638
1639         dev->entry[0].vector = pdev->irq;
1640         pci_set_master(pdev);
1641         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1642         if (!bars)
1643                 goto disable_pci;
1644
1645         if (pci_request_selected_regions(pdev, bars, "nvme"))
1646                 goto disable_pci;
1647
1648         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1649             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1650                 goto disable;
1651
1652         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1653         if (!dev->bar)
1654                 goto disable;
1655
1656         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1657                 result = -ENODEV;
1658                 goto unmap;
1659         }
1660
1661         /*
1662          * Some devices don't advertse INTx interrupts, pre-enable a single
1663          * MSIX vec for setup. We'll adjust this later.
1664          */
1665         if (!pdev->irq) {
1666                 result = pci_enable_msix(pdev, dev->entry, 1);
1667                 if (result < 0)
1668                         goto unmap;
1669         }
1670
1671         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1672
1673         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1674         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1675         dev->dbs = dev->bar + 4096;
1676         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1677                 dev->cmb = nvme_map_cmb(dev);
1678
1679         pci_enable_pcie_error_reporting(pdev);
1680         pci_save_state(pdev);
1681         return 0;
1682
1683  unmap:
1684         iounmap(dev->bar);
1685         dev->bar = NULL;
1686  disable:
1687         pci_release_regions(pdev);
1688  disable_pci:
1689         pci_disable_device(pdev);
1690         return result;
1691 }
1692
1693 static void nvme_dev_unmap(struct nvme_dev *dev)
1694 {
1695         struct pci_dev *pdev = to_pci_dev(dev->dev);
1696
1697         if (pdev->msi_enabled)
1698                 pci_disable_msi(pdev);
1699         else if (pdev->msix_enabled)
1700                 pci_disable_msix(pdev);
1701
1702         if (dev->bar) {
1703                 iounmap(dev->bar);
1704                 dev->bar = NULL;
1705                 pci_release_regions(pdev);
1706         }
1707
1708         if (pci_is_enabled(pdev)) {
1709                 pci_disable_pcie_error_reporting(pdev);
1710                 pci_disable_device(pdev);
1711         }
1712 }
1713
1714 struct nvme_delq_ctx {
1715         struct task_struct *waiter;
1716         struct kthread_worker *worker;
1717         atomic_t refcount;
1718 };
1719
1720 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
1721 {
1722         dq->waiter = current;
1723         mb();
1724
1725         for (;;) {
1726                 set_current_state(TASK_KILLABLE);
1727                 if (!atomic_read(&dq->refcount))
1728                         break;
1729                 if (!schedule_timeout(ADMIN_TIMEOUT) ||
1730                                         fatal_signal_pending(current)) {
1731                         /*
1732                          * Disable the controller first since we can't trust it
1733                          * at this point, but leave the admin queue enabled
1734                          * until all queue deletion requests are flushed.
1735                          * FIXME: This may take a while if there are more h/w
1736                          * queues than admin tags.
1737                          */
1738                         set_current_state(TASK_RUNNING);
1739                         nvme_disable_ctrl(&dev->ctrl,
1740                                 lo_hi_readq(dev->bar + NVME_REG_CAP));
1741                         nvme_clear_queue(dev->queues[0]);
1742                         flush_kthread_worker(dq->worker);
1743                         nvme_disable_queue(dev, 0);
1744                         return;
1745                 }
1746         }
1747         set_current_state(TASK_RUNNING);
1748 }
1749
1750 static void nvme_put_dq(struct nvme_delq_ctx *dq)
1751 {
1752         atomic_dec(&dq->refcount);
1753         if (dq->waiter)
1754                 wake_up_process(dq->waiter);
1755 }
1756
1757 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
1758 {
1759         atomic_inc(&dq->refcount);
1760         return dq;
1761 }
1762
1763 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
1764 {
1765         struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
1766         nvme_put_dq(dq);
1767
1768         spin_lock_irq(&nvmeq->q_lock);
1769         nvme_process_cq(nvmeq);
1770         spin_unlock_irq(&nvmeq->q_lock);
1771 }
1772
1773 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
1774                                                 kthread_work_func_t fn)
1775 {
1776         struct request *req;
1777         struct nvme_command c;
1778
1779         memset(&c, 0, sizeof(c));
1780         c.delete_queue.opcode = opcode;
1781         c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1782
1783         init_kthread_work(&nvmeq->cmdinfo.work, fn);
1784
1785         req = nvme_alloc_request(nvmeq->dev->ctrl.admin_q, &c, 0);
1786         if (IS_ERR(req))
1787                 return PTR_ERR(req);
1788
1789         req->timeout = ADMIN_TIMEOUT;
1790         req->end_io_data = &nvmeq->cmdinfo;
1791         blk_execute_rq_nowait(req->q, NULL, req, 0, async_cmd_info_endio);
1792         return 0;
1793 }
1794
1795 static void nvme_del_cq_work_handler(struct kthread_work *work)
1796 {
1797         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1798                                                         cmdinfo.work);
1799         nvme_del_queue_end(nvmeq);
1800 }
1801
1802 static int nvme_delete_cq(struct nvme_queue *nvmeq)
1803 {
1804         return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
1805                                                 nvme_del_cq_work_handler);
1806 }
1807
1808 static void nvme_del_sq_work_handler(struct kthread_work *work)
1809 {
1810         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1811                                                         cmdinfo.work);
1812         int status = nvmeq->cmdinfo.status;
1813
1814         if (!status)
1815                 status = nvme_delete_cq(nvmeq);
1816         if (status)
1817                 nvme_del_queue_end(nvmeq);
1818 }
1819
1820 static int nvme_delete_sq(struct nvme_queue *nvmeq)
1821 {
1822         return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
1823                                                 nvme_del_sq_work_handler);
1824 }
1825
1826 static void nvme_del_queue_start(struct kthread_work *work)
1827 {
1828         struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
1829                                                         cmdinfo.work);
1830         if (nvme_delete_sq(nvmeq))
1831                 nvme_del_queue_end(nvmeq);
1832 }
1833
1834 static void nvme_disable_io_queues(struct nvme_dev *dev)
1835 {
1836         int i;
1837         DEFINE_KTHREAD_WORKER_ONSTACK(worker);
1838         struct nvme_delq_ctx dq;
1839         struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
1840                                         &worker, "nvme%d", dev->ctrl.instance);
1841
1842         if (IS_ERR(kworker_task)) {
1843                 dev_err(dev->dev,
1844                         "Failed to create queue del task\n");
1845                 for (i = dev->queue_count - 1; i > 0; i--)
1846                         nvme_disable_queue(dev, i);
1847                 return;
1848         }
1849
1850         dq.waiter = NULL;
1851         atomic_set(&dq.refcount, 0);
1852         dq.worker = &worker;
1853         for (i = dev->queue_count - 1; i > 0; i--) {
1854                 struct nvme_queue *nvmeq = dev->queues[i];
1855
1856                 if (nvme_suspend_queue(nvmeq))
1857                         continue;
1858                 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
1859                 nvmeq->cmdinfo.worker = dq.worker;
1860                 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
1861                 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
1862         }
1863         nvme_wait_dq(&dq, dev);
1864         kthread_stop(kworker_task);
1865 }
1866
1867 static int nvme_dev_list_add(struct nvme_dev *dev)
1868 {
1869         bool start_thread = false;
1870
1871         spin_lock(&dev_list_lock);
1872         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
1873                 start_thread = true;
1874                 nvme_thread = NULL;
1875         }
1876         list_add(&dev->node, &dev_list);
1877         spin_unlock(&dev_list_lock);
1878
1879         if (start_thread) {
1880                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1881                 wake_up_all(&nvme_kthread_wait);
1882         } else
1883                 wait_event_killable(nvme_kthread_wait, nvme_thread);
1884
1885         if (IS_ERR_OR_NULL(nvme_thread))
1886                 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
1887
1888         return 0;
1889 }
1890
1891 /*
1892 * Remove the node from the device list and check
1893 * for whether or not we need to stop the nvme_thread.
1894 */
1895 static void nvme_dev_list_remove(struct nvme_dev *dev)
1896 {
1897         struct task_struct *tmp = NULL;
1898
1899         spin_lock(&dev_list_lock);
1900         list_del_init(&dev->node);
1901         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
1902                 tmp = nvme_thread;
1903                 nvme_thread = NULL;
1904         }
1905         spin_unlock(&dev_list_lock);
1906
1907         if (tmp)
1908                 kthread_stop(tmp);
1909 }
1910
1911 static void nvme_dev_shutdown(struct nvme_dev *dev)
1912 {
1913         int i;
1914         u32 csts = -1;
1915
1916         nvme_dev_list_remove(dev);
1917
1918         mutex_lock(&dev->shutdown_lock);
1919         if (dev->bar) {
1920                 nvme_freeze_queues(&dev->ctrl);
1921                 csts = readl(dev->bar + NVME_REG_CSTS);
1922         }
1923         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1924                 for (i = dev->queue_count - 1; i >= 0; i--) {
1925                         struct nvme_queue *nvmeq = dev->queues[i];
1926                         nvme_suspend_queue(nvmeq);
1927                 }
1928         } else {
1929                 nvme_disable_io_queues(dev);
1930                 nvme_shutdown_ctrl(&dev->ctrl);
1931                 nvme_disable_queue(dev, 0);
1932         }
1933         nvme_dev_unmap(dev);
1934
1935         for (i = dev->queue_count - 1; i >= 0; i--)
1936                 nvme_clear_queue(dev->queues[i]);
1937         mutex_unlock(&dev->shutdown_lock);
1938 }
1939
1940 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1941 {
1942         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1943                                                 PAGE_SIZE, PAGE_SIZE, 0);
1944         if (!dev->prp_page_pool)
1945                 return -ENOMEM;
1946
1947         /* Optimisation for I/Os between 4k and 128k */
1948         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1949                                                 256, 256, 0);
1950         if (!dev->prp_small_pool) {
1951                 dma_pool_destroy(dev->prp_page_pool);
1952                 return -ENOMEM;
1953         }
1954         return 0;
1955 }
1956
1957 static void nvme_release_prp_pools(struct nvme_dev *dev)
1958 {
1959         dma_pool_destroy(dev->prp_page_pool);
1960         dma_pool_destroy(dev->prp_small_pool);
1961 }
1962
1963 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1964 {
1965         struct nvme_dev *dev = to_nvme_dev(ctrl);
1966
1967         put_device(dev->dev);
1968         if (dev->tagset.tags)
1969                 blk_mq_free_tag_set(&dev->tagset);
1970         if (dev->ctrl.admin_q)
1971                 blk_put_queue(dev->ctrl.admin_q);
1972         kfree(dev->queues);
1973         kfree(dev->entry);
1974         kfree(dev);
1975 }
1976
1977 static void nvme_reset_work(struct work_struct *work)
1978 {
1979         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1980         int result;
1981
1982         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
1983                 goto out;
1984
1985         /*
1986          * If we're called to reset a live controller first shut it down before
1987          * moving on.
1988          */
1989         if (dev->bar)
1990                 nvme_dev_shutdown(dev);
1991
1992         set_bit(NVME_CTRL_RESETTING, &dev->flags);
1993
1994         result = nvme_dev_map(dev);
1995         if (result)
1996                 goto out;
1997
1998         result = nvme_configure_admin_queue(dev);
1999         if (result)
2000                 goto unmap;
2001
2002         nvme_init_queue(dev->queues[0], 0);
2003         result = nvme_alloc_admin_tags(dev);
2004         if (result)
2005                 goto disable;
2006
2007         result = nvme_init_identify(&dev->ctrl);
2008         if (result)
2009                 goto free_tags;
2010
2011         result = nvme_setup_io_queues(dev);
2012         if (result)
2013                 goto free_tags;
2014
2015         dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
2016
2017         result = nvme_dev_list_add(dev);
2018         if (result)
2019                 goto remove;
2020
2021         /*
2022          * Keep the controller around but remove all namespaces if we don't have
2023          * any working I/O queue.
2024          */
2025         if (dev->online_queues < 2) {
2026                 dev_warn(dev->dev, "IO queues not created\n");
2027                 nvme_remove_namespaces(&dev->ctrl);
2028         } else {
2029                 nvme_unfreeze_queues(&dev->ctrl);
2030                 nvme_dev_add(dev);
2031         }
2032
2033         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
2034         return;
2035
2036  remove:
2037         nvme_dev_list_remove(dev);
2038  free_tags:
2039         nvme_dev_remove_admin(dev);
2040         blk_put_queue(dev->ctrl.admin_q);
2041         dev->ctrl.admin_q = NULL;
2042         dev->queues[0]->tags = NULL;
2043  disable:
2044         nvme_disable_queue(dev, 0);
2045  unmap:
2046         nvme_dev_unmap(dev);
2047  out:
2048         nvme_remove_dead_ctrl(dev);
2049 }
2050
2051 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2052 {
2053         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2054         struct pci_dev *pdev = to_pci_dev(dev->dev);
2055
2056         if (pci_get_drvdata(pdev))
2057                 pci_stop_and_remove_bus_device_locked(pdev);
2058         nvme_put_ctrl(&dev->ctrl);
2059 }
2060
2061 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2062 {
2063         dev_warn(dev->dev, "Removing after probe failure\n");
2064         kref_get(&dev->ctrl.kref);
2065         if (!schedule_work(&dev->remove_work))
2066                 nvme_put_ctrl(&dev->ctrl);
2067 }
2068
2069 static int nvme_reset(struct nvme_dev *dev)
2070 {
2071         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2072                 return -ENODEV;
2073
2074         if (!queue_work(nvme_workq, &dev->reset_work))
2075                 return -EBUSY;
2076
2077         flush_work(&dev->reset_work);
2078         return 0;
2079 }
2080
2081 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2082 {
2083         *val = readl(to_nvme_dev(ctrl)->bar + off);
2084         return 0;
2085 }
2086
2087 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2088 {
2089         writel(val, to_nvme_dev(ctrl)->bar + off);
2090         return 0;
2091 }
2092
2093 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2094 {
2095         *val = readq(to_nvme_dev(ctrl)->bar + off);
2096         return 0;
2097 }
2098
2099 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2100 {
2101         struct nvme_dev *dev = to_nvme_dev(ctrl);
2102
2103         return !dev->bar || dev->online_queues < 2;
2104 }
2105
2106 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2107 {
2108         return nvme_reset(to_nvme_dev(ctrl));
2109 }
2110
2111 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2112         .reg_read32             = nvme_pci_reg_read32,
2113         .reg_write32            = nvme_pci_reg_write32,
2114         .reg_read64             = nvme_pci_reg_read64,
2115         .io_incapable           = nvme_pci_io_incapable,
2116         .reset_ctrl             = nvme_pci_reset_ctrl,
2117         .free_ctrl              = nvme_pci_free_ctrl,
2118 };
2119
2120 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2121 {
2122         int node, result = -ENOMEM;
2123         struct nvme_dev *dev;
2124
2125         node = dev_to_node(&pdev->dev);
2126         if (node == NUMA_NO_NODE)
2127                 set_dev_node(&pdev->dev, 0);
2128
2129         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2130         if (!dev)
2131                 return -ENOMEM;
2132         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2133                                                         GFP_KERNEL, node);
2134         if (!dev->entry)
2135                 goto free;
2136         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2137                                                         GFP_KERNEL, node);
2138         if (!dev->queues)
2139                 goto free;
2140
2141         dev->dev = get_device(&pdev->dev);
2142         pci_set_drvdata(pdev, dev);
2143
2144         INIT_LIST_HEAD(&dev->node);
2145         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2146         INIT_WORK(&dev->reset_work, nvme_reset_work);
2147         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2148         mutex_init(&dev->shutdown_lock);
2149
2150         result = nvme_setup_prp_pools(dev);
2151         if (result)
2152                 goto put_pci;
2153
2154         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2155                         id->driver_data);
2156         if (result)
2157                 goto release_pools;
2158
2159         queue_work(nvme_workq, &dev->reset_work);
2160         return 0;
2161
2162  release_pools:
2163         nvme_release_prp_pools(dev);
2164  put_pci:
2165         put_device(dev->dev);
2166  free:
2167         kfree(dev->queues);
2168         kfree(dev->entry);
2169         kfree(dev);
2170         return result;
2171 }
2172
2173 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2174 {
2175         struct nvme_dev *dev = pci_get_drvdata(pdev);
2176
2177         if (prepare)
2178                 nvme_dev_shutdown(dev);
2179         else
2180                 queue_work(nvme_workq, &dev->reset_work);
2181 }
2182
2183 static void nvme_shutdown(struct pci_dev *pdev)
2184 {
2185         struct nvme_dev *dev = pci_get_drvdata(pdev);
2186         nvme_dev_shutdown(dev);
2187 }
2188
2189 static void nvme_remove(struct pci_dev *pdev)
2190 {
2191         struct nvme_dev *dev = pci_get_drvdata(pdev);
2192
2193         spin_lock(&dev_list_lock);
2194         list_del_init(&dev->node);
2195         spin_unlock(&dev_list_lock);
2196
2197         pci_set_drvdata(pdev, NULL);
2198         flush_work(&dev->reset_work);
2199         flush_work(&dev->scan_work);
2200         nvme_remove_namespaces(&dev->ctrl);
2201         nvme_uninit_ctrl(&dev->ctrl);
2202         nvme_dev_shutdown(dev);
2203         nvme_dev_remove_admin(dev);
2204         nvme_free_queues(dev, 0);
2205         nvme_release_cmb(dev);
2206         nvme_release_prp_pools(dev);
2207         nvme_put_ctrl(&dev->ctrl);
2208 }
2209
2210 #ifdef CONFIG_PM_SLEEP
2211 static int nvme_suspend(struct device *dev)
2212 {
2213         struct pci_dev *pdev = to_pci_dev(dev);
2214         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2215
2216         nvme_dev_shutdown(ndev);
2217         return 0;
2218 }
2219
2220 static int nvme_resume(struct device *dev)
2221 {
2222         struct pci_dev *pdev = to_pci_dev(dev);
2223         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2224
2225         queue_work(nvme_workq, &ndev->reset_work);
2226         return 0;
2227 }
2228 #endif
2229
2230 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2231
2232 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2233                                                 pci_channel_state_t state)
2234 {
2235         struct nvme_dev *dev = pci_get_drvdata(pdev);
2236
2237         /*
2238          * A frozen channel requires a reset. When detected, this method will
2239          * shutdown the controller to quiesce. The controller will be restarted
2240          * after the slot reset through driver's slot_reset callback.
2241          */
2242         dev_warn(&pdev->dev, "error detected: state:%d\n", state);
2243         switch (state) {
2244         case pci_channel_io_normal:
2245                 return PCI_ERS_RESULT_CAN_RECOVER;
2246         case pci_channel_io_frozen:
2247                 nvme_dev_shutdown(dev);
2248                 return PCI_ERS_RESULT_NEED_RESET;
2249         case pci_channel_io_perm_failure:
2250                 return PCI_ERS_RESULT_DISCONNECT;
2251         }
2252         return PCI_ERS_RESULT_NEED_RESET;
2253 }
2254
2255 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2256 {
2257         struct nvme_dev *dev = pci_get_drvdata(pdev);
2258
2259         dev_info(&pdev->dev, "restart after slot reset\n");
2260         pci_restore_state(pdev);
2261         queue_work(nvme_workq, &dev->reset_work);
2262         return PCI_ERS_RESULT_RECOVERED;
2263 }
2264
2265 static void nvme_error_resume(struct pci_dev *pdev)
2266 {
2267         pci_cleanup_aer_uncorrect_error_status(pdev);
2268 }
2269
2270 static const struct pci_error_handlers nvme_err_handler = {
2271         .error_detected = nvme_error_detected,
2272         .slot_reset     = nvme_slot_reset,
2273         .resume         = nvme_error_resume,
2274         .reset_notify   = nvme_reset_notify,
2275 };
2276
2277 /* Move to pci_ids.h later */
2278 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2279
2280 static const struct pci_device_id nvme_id_table[] = {
2281         { PCI_VDEVICE(INTEL, 0x0953),
2282                 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2283         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2284                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2285         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2286         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2287         { 0, }
2288 };
2289 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2290
2291 static struct pci_driver nvme_driver = {
2292         .name           = "nvme",
2293         .id_table       = nvme_id_table,
2294         .probe          = nvme_probe,
2295         .remove         = nvme_remove,
2296         .shutdown       = nvme_shutdown,
2297         .driver         = {
2298                 .pm     = &nvme_dev_pm_ops,
2299         },
2300         .err_handler    = &nvme_err_handler,
2301 };
2302
2303 static int __init nvme_init(void)
2304 {
2305         int result;
2306
2307         init_waitqueue_head(&nvme_kthread_wait);
2308
2309         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2310         if (!nvme_workq)
2311                 return -ENOMEM;
2312
2313         result = nvme_core_init();
2314         if (result < 0)
2315                 goto kill_workq;
2316
2317         result = pci_register_driver(&nvme_driver);
2318         if (result)
2319                 goto core_exit;
2320         return 0;
2321
2322  core_exit:
2323         nvme_core_exit();
2324  kill_workq:
2325         destroy_workqueue(nvme_workq);
2326         return result;
2327 }
2328
2329 static void __exit nvme_exit(void)
2330 {
2331         pci_unregister_driver(&nvme_driver);
2332         nvme_core_exit();
2333         destroy_workqueue(nvme_workq);
2334         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2335         _nvme_check_size();
2336 }
2337
2338 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2339 MODULE_LICENSE("GPL");
2340 MODULE_VERSION("1.0");
2341 module_init(nvme_init);
2342 module_exit(nvme_exit);