2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
31 #include <linux/list_sort.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/types.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <asm/unaligned.h>
47 #include <uapi/linux/nvme_ioctl.h>
50 #define NVME_MINORS (1U << MINORBITS)
51 #define NVME_Q_DEPTH 1024
52 #define NVME_AQ_DEPTH 256
53 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
55 #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
57 unsigned char admin_timeout = 60;
58 module_param(admin_timeout, byte, 0644);
59 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
61 unsigned char nvme_io_timeout = 30;
62 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
63 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
65 static unsigned char shutdown_timeout = 5;
66 module_param(shutdown_timeout, byte, 0644);
67 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
69 static int nvme_major;
70 module_param(nvme_major, int, 0);
72 static int nvme_char_major;
73 module_param(nvme_char_major, int, 0);
75 static int use_threaded_interrupts;
76 module_param(use_threaded_interrupts, int, 0);
78 static bool use_cmb_sqes = true;
79 module_param(use_cmb_sqes, bool, 0644);
80 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
82 static LIST_HEAD(dev_list);
83 static struct task_struct *nvme_thread;
84 static struct workqueue_struct *nvme_workq;
85 static wait_queue_head_t nvme_kthread_wait;
87 static struct class *nvme_class;
93 static int __nvme_reset(struct nvme_dev *dev);
94 static int nvme_reset(struct nvme_dev *dev);
95 static void nvme_process_cq(struct nvme_queue *nvmeq);
96 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod);
97 static void nvme_dead_ctrl(struct nvme_dev *dev);
99 struct async_cmd_info {
100 struct kthread_work work;
101 struct kthread_worker *worker;
109 * Represents an NVM Express device. Each nvme_dev is a PCI function.
112 struct list_head node;
113 struct nvme_queue **queues;
114 struct blk_mq_tag_set tagset;
115 struct blk_mq_tag_set admin_tagset;
118 struct dma_pool *prp_page_pool;
119 struct dma_pool *prp_small_pool;
120 unsigned queue_count;
121 unsigned online_queues;
126 struct msix_entry *entry;
128 struct list_head namespaces;
129 struct device *device;
130 struct work_struct reset_work;
131 struct work_struct probe_work;
132 struct work_struct scan_work;
138 dma_addr_t cmb_dma_addr;
142 struct nvme_ctrl ctrl;
145 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
147 return container_of(ctrl, struct nvme_dev, ctrl);
151 * An NVM Express queue. Each device has at least two (one for admin
152 * commands and one for I/O commands).
155 struct device *q_dmadev;
156 struct nvme_dev *dev;
157 char irqname[24]; /* nvme4294967295-65535\0 */
159 struct nvme_command *sq_cmds;
160 struct nvme_command __iomem *sq_cmds_io;
161 volatile struct nvme_completion *cqes;
162 struct blk_mq_tags **tags;
163 dma_addr_t sq_dma_addr;
164 dma_addr_t cq_dma_addr;
174 struct async_cmd_info cmdinfo;
178 * The nvme_iod describes the data in an I/O, including the list of PRP
179 * entries. You can't see it in this data structure because C doesn't let
180 * me express that. Use nvme_alloc_iod to ensure there's enough space
181 * allocated to store the PRP list.
184 unsigned long private; /* For the use of the submitter of the I/O */
185 int npages; /* In the PRP list. 0 means small pool in use */
186 int offset; /* Of PRP list */
187 int nents; /* Used in scatterlist */
188 int length; /* Of data, in bytes */
189 dma_addr_t first_dma;
190 struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
191 struct scatterlist sg[0];
195 * Check we didin't inadvertently grow the command struct
197 static inline void _nvme_check_size(void)
199 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
205 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
206 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
207 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
208 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
209 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
210 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
213 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
214 struct nvme_completion *);
216 struct nvme_cmd_info {
217 nvme_completion_fn fn;
220 struct nvme_queue *nvmeq;
221 struct nvme_iod iod[0];
225 * Max size of iod being embedded in the request payload
227 #define NVME_INT_PAGES 2
228 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
229 #define NVME_INT_MASK 0x01
232 * Will slightly overestimate the number of pages needed. This is OK
233 * as it only leads to a small amount of wasted memory for the lifetime of
236 static int nvme_npages(unsigned size, struct nvme_dev *dev)
238 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
239 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
242 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
244 unsigned int ret = sizeof(struct nvme_cmd_info);
246 ret += sizeof(struct nvme_iod);
247 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
248 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
253 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
254 unsigned int hctx_idx)
256 struct nvme_dev *dev = data;
257 struct nvme_queue *nvmeq = dev->queues[0];
259 WARN_ON(hctx_idx != 0);
260 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
261 WARN_ON(nvmeq->tags);
263 hctx->driver_data = nvmeq;
264 nvmeq->tags = &dev->admin_tagset.tags[0];
268 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
270 struct nvme_queue *nvmeq = hctx->driver_data;
275 static int nvme_admin_init_request(void *data, struct request *req,
276 unsigned int hctx_idx, unsigned int rq_idx,
277 unsigned int numa_node)
279 struct nvme_dev *dev = data;
280 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
281 struct nvme_queue *nvmeq = dev->queues[0];
288 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
289 unsigned int hctx_idx)
291 struct nvme_dev *dev = data;
292 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
295 nvmeq->tags = &dev->tagset.tags[hctx_idx];
297 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
298 hctx->driver_data = nvmeq;
302 static int nvme_init_request(void *data, struct request *req,
303 unsigned int hctx_idx, unsigned int rq_idx,
304 unsigned int numa_node)
306 struct nvme_dev *dev = data;
307 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
308 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
315 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
316 nvme_completion_fn handler)
321 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
324 static void *iod_get_private(struct nvme_iod *iod)
326 return (void *) (iod->private & ~0x1UL);
330 * If bit 0 is set, the iod is embedded in the request payload.
332 static bool iod_should_kfree(struct nvme_iod *iod)
334 return (iod->private & NVME_INT_MASK) == 0;
337 /* Special values must be less than 0x1000 */
338 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
339 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
340 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
341 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
343 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
344 struct nvme_completion *cqe)
346 if (ctx == CMD_CTX_CANCELLED)
348 if (ctx == CMD_CTX_COMPLETED) {
349 dev_warn(nvmeq->q_dmadev,
350 "completed id %d twice on queue %d\n",
351 cqe->command_id, le16_to_cpup(&cqe->sq_id));
354 if (ctx == CMD_CTX_INVALID) {
355 dev_warn(nvmeq->q_dmadev,
356 "invalid id %d completed on queue %d\n",
357 cqe->command_id, le16_to_cpup(&cqe->sq_id));
360 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
363 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
370 cmd->fn = special_completion;
371 cmd->ctx = CMD_CTX_CANCELLED;
375 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
376 struct nvme_completion *cqe)
378 u32 result = le32_to_cpup(&cqe->result);
379 u16 status = le16_to_cpup(&cqe->status) >> 1;
381 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
382 ++nvmeq->dev->ctrl.event_limit;
383 if (status != NVME_SC_SUCCESS)
386 switch (result & 0xff07) {
387 case NVME_AER_NOTICE_NS_CHANGED:
388 dev_info(nvmeq->q_dmadev, "rescanning\n");
389 schedule_work(&nvmeq->dev->scan_work);
391 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
395 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
396 struct nvme_completion *cqe)
398 struct request *req = ctx;
400 u16 status = le16_to_cpup(&cqe->status) >> 1;
401 u32 result = le32_to_cpup(&cqe->result);
403 blk_mq_free_request(req);
405 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
406 ++nvmeq->dev->ctrl.abort_limit;
409 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
410 struct nvme_completion *cqe)
412 struct async_cmd_info *cmdinfo = ctx;
413 cmdinfo->result = le32_to_cpup(&cqe->result);
414 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
415 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
416 blk_mq_free_request(cmdinfo->req);
419 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
422 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
424 return blk_mq_rq_to_pdu(req);
428 * Called with local interrupts disabled and the q_lock held. May not sleep.
430 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
431 nvme_completion_fn *fn)
433 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
435 if (tag >= nvmeq->q_depth) {
436 *fn = special_completion;
437 return CMD_CTX_INVALID;
442 cmd->fn = special_completion;
443 cmd->ctx = CMD_CTX_COMPLETED;
448 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
449 * @nvmeq: The queue to use
450 * @cmd: The command to send
452 * Safe to use from interrupt context
454 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
455 struct nvme_command *cmd)
457 u16 tail = nvmeq->sq_tail;
459 if (nvmeq->sq_cmds_io)
460 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
462 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
464 if (++tail == nvmeq->q_depth)
466 writel(tail, nvmeq->q_db);
467 nvmeq->sq_tail = tail;
470 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
473 spin_lock_irqsave(&nvmeq->q_lock, flags);
474 __nvme_submit_cmd(nvmeq, cmd);
475 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
478 static __le64 **iod_list(struct nvme_iod *iod)
480 return ((void *)iod) + iod->offset;
483 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
484 unsigned nseg, unsigned long private)
486 iod->private = private;
487 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
489 iod->length = nbytes;
493 static struct nvme_iod *
494 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
495 unsigned long priv, gfp_t gfp)
497 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
498 sizeof(__le64 *) * nvme_npages(bytes, dev) +
499 sizeof(struct scatterlist) * nseg, gfp);
502 iod_init(iod, bytes, nseg, priv);
507 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
510 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
511 sizeof(struct nvme_dsm_range);
512 struct nvme_iod *iod;
514 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
515 size <= NVME_INT_BYTES(dev)) {
516 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
519 iod_init(iod, size, rq->nr_phys_segments,
520 (unsigned long) rq | NVME_INT_MASK);
524 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
525 (unsigned long) rq, gfp);
528 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
530 const int last_prp = dev->page_size / 8 - 1;
532 __le64 **list = iod_list(iod);
533 dma_addr_t prp_dma = iod->first_dma;
535 if (iod->npages == 0)
536 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
537 for (i = 0; i < iod->npages; i++) {
538 __le64 *prp_list = list[i];
539 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
540 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
541 prp_dma = next_prp_dma;
544 if (iod_should_kfree(iod))
548 #ifdef CONFIG_BLK_DEV_INTEGRITY
549 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
551 if (be32_to_cpu(pi->ref_tag) == v)
552 pi->ref_tag = cpu_to_be32(p);
555 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
557 if (be32_to_cpu(pi->ref_tag) == p)
558 pi->ref_tag = cpu_to_be32(v);
562 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
564 * The virtual start sector is the one that was originally submitted by the
565 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
566 * start sector may be different. Remap protection information to match the
567 * physical LBA on writes, and back to the original seed on reads.
569 * Type 0 and 3 do not have a ref tag, so no remapping required.
571 static void nvme_dif_remap(struct request *req,
572 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
574 struct nvme_ns *ns = req->rq_disk->private_data;
575 struct bio_integrity_payload *bip;
576 struct t10_pi_tuple *pi;
578 u32 i, nlb, ts, phys, virt;
580 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
583 bip = bio_integrity(req->bio);
587 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
590 virt = bip_get_seed(bip);
591 phys = nvme_block_nr(ns, blk_rq_pos(req));
592 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
593 ts = ns->disk->queue->integrity.tuple_size;
595 for (i = 0; i < nlb; i++, virt++, phys++) {
596 pi = (struct t10_pi_tuple *)p;
597 dif_swap(phys, virt, pi);
602 #else /* CONFIG_BLK_DEV_INTEGRITY */
603 static void nvme_dif_remap(struct request *req,
604 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
607 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
610 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
615 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
616 struct nvme_completion *cqe)
618 struct nvme_iod *iod = ctx;
619 struct request *req = iod_get_private(iod);
620 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
621 u16 status = le16_to_cpup(&cqe->status) >> 1;
624 if (unlikely(status)) {
625 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
626 && (jiffies - req->start_time) < req->timeout) {
629 nvme_unmap_data(nvmeq->dev, iod);
631 blk_mq_requeue_request(req);
632 spin_lock_irqsave(req->q->queue_lock, flags);
633 if (!blk_queue_stopped(req->q))
634 blk_mq_kick_requeue_list(req->q);
635 spin_unlock_irqrestore(req->q->queue_lock, flags);
639 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
640 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
645 error = nvme_error_status(status);
649 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
650 u32 result = le32_to_cpup(&cqe->result);
651 req->special = (void *)(uintptr_t)result;
655 dev_warn(nvmeq->dev->dev,
656 "completing aborted command with status:%04x\n",
659 nvme_unmap_data(nvmeq->dev, iod);
660 blk_mq_complete_request(req, error);
663 static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
666 struct dma_pool *pool;
667 int length = total_len;
668 struct scatterlist *sg = iod->sg;
669 int dma_len = sg_dma_len(sg);
670 u64 dma_addr = sg_dma_address(sg);
671 u32 page_size = dev->page_size;
672 int offset = dma_addr & (page_size - 1);
674 __le64 **list = iod_list(iod);
678 length -= (page_size - offset);
682 dma_len -= (page_size - offset);
684 dma_addr += (page_size - offset);
687 dma_addr = sg_dma_address(sg);
688 dma_len = sg_dma_len(sg);
691 if (length <= page_size) {
692 iod->first_dma = dma_addr;
696 nprps = DIV_ROUND_UP(length, page_size);
697 if (nprps <= (256 / 8)) {
698 pool = dev->prp_small_pool;
701 pool = dev->prp_page_pool;
705 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
707 iod->first_dma = dma_addr;
712 iod->first_dma = prp_dma;
715 if (i == page_size >> 3) {
716 __le64 *old_prp_list = prp_list;
717 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
720 list[iod->npages++] = prp_list;
721 prp_list[0] = old_prp_list[i - 1];
722 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
725 prp_list[i++] = cpu_to_le64(dma_addr);
726 dma_len -= page_size;
727 dma_addr += page_size;
735 dma_addr = sg_dma_address(sg);
736 dma_len = sg_dma_len(sg);
742 static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod,
743 struct nvme_command *cmnd)
745 struct request *req = iod_get_private(iod);
746 struct request_queue *q = req->q;
747 enum dma_data_direction dma_dir = rq_data_dir(req) ?
748 DMA_TO_DEVICE : DMA_FROM_DEVICE;
749 int ret = BLK_MQ_RQ_QUEUE_ERROR;
751 sg_init_table(iod->sg, req->nr_phys_segments);
752 iod->nents = blk_rq_map_sg(q, req, iod->sg);
756 ret = BLK_MQ_RQ_QUEUE_BUSY;
757 if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
760 if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req)))
763 ret = BLK_MQ_RQ_QUEUE_ERROR;
764 if (blk_integrity_rq(req)) {
765 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
768 sg_init_table(iod->meta_sg, 1);
769 if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1)
772 if (rq_data_dir(req))
773 nvme_dif_remap(req, nvme_dif_prep);
775 if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir))
779 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
780 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
781 if (blk_integrity_rq(req))
782 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
783 return BLK_MQ_RQ_QUEUE_OK;
786 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
791 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod)
793 struct request *req = iod_get_private(iod);
794 enum dma_data_direction dma_dir = rq_data_dir(req) ?
795 DMA_TO_DEVICE : DMA_FROM_DEVICE;
798 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
799 if (blk_integrity_rq(req)) {
800 if (!rq_data_dir(req))
801 nvme_dif_remap(req, nvme_dif_complete);
802 dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir);
806 nvme_free_iod(dev, iod);
810 * We reuse the small pool to allocate the 16-byte range here as it is not
811 * worth having a special pool for these or additional cases to handle freeing
814 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
815 struct nvme_iod *iod, struct nvme_command *cmnd)
817 struct request *req = iod_get_private(iod);
818 struct nvme_dsm_range *range;
820 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
823 return BLK_MQ_RQ_QUEUE_BUSY;
824 iod_list(iod)[0] = (__le64 *)range;
827 range->cattr = cpu_to_le32(0);
828 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
829 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
831 memset(cmnd, 0, sizeof(*cmnd));
832 cmnd->dsm.opcode = nvme_cmd_dsm;
833 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
834 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
836 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
837 return BLK_MQ_RQ_QUEUE_OK;
841 * NOTE: ns is NULL when called on the admin queue.
843 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
844 const struct blk_mq_queue_data *bd)
846 struct nvme_ns *ns = hctx->queue->queuedata;
847 struct nvme_queue *nvmeq = hctx->driver_data;
848 struct nvme_dev *dev = nvmeq->dev;
849 struct request *req = bd->rq;
850 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
851 struct nvme_iod *iod;
852 struct nvme_command cmnd;
853 int ret = BLK_MQ_RQ_QUEUE_OK;
856 * If formated with metadata, require the block layer provide a buffer
857 * unless this namespace is formated such that the metadata can be
858 * stripped/generated by the controller with PRACT=1.
860 if (ns && ns->ms && !blk_integrity_rq(req)) {
861 if (!(ns->pi_type && ns->ms == 8) &&
862 req->cmd_type != REQ_TYPE_DRV_PRIV) {
863 blk_mq_complete_request(req, -EFAULT);
864 return BLK_MQ_RQ_QUEUE_OK;
868 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
870 return BLK_MQ_RQ_QUEUE_BUSY;
872 if (req->cmd_flags & REQ_DISCARD) {
873 ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd);
875 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
876 memcpy(&cmnd, req->cmd, sizeof(cmnd));
877 else if (req->cmd_flags & REQ_FLUSH)
878 nvme_setup_flush(ns, &cmnd);
880 nvme_setup_rw(ns, req, &cmnd);
882 if (req->nr_phys_segments)
883 ret = nvme_map_data(dev, iod, &cmnd);
889 cmnd.common.command_id = req->tag;
890 nvme_set_info(cmd, iod, req_completion);
892 spin_lock_irq(&nvmeq->q_lock);
893 __nvme_submit_cmd(nvmeq, &cmnd);
894 nvme_process_cq(nvmeq);
895 spin_unlock_irq(&nvmeq->q_lock);
896 return BLK_MQ_RQ_QUEUE_OK;
898 nvme_free_iod(dev, iod);
902 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
906 head = nvmeq->cq_head;
907 phase = nvmeq->cq_phase;
911 nvme_completion_fn fn;
912 struct nvme_completion cqe = nvmeq->cqes[head];
913 if ((le16_to_cpu(cqe.status) & 1) != phase)
915 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
916 if (++head == nvmeq->q_depth) {
920 if (tag && *tag == cqe.command_id)
922 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
923 fn(nvmeq, ctx, &cqe);
926 /* If the controller ignores the cq head doorbell and continuously
927 * writes to the queue, it is theoretically possible to wrap around
928 * the queue twice and mistakenly return IRQ_NONE. Linux only
929 * requires that 0.1% of your interrupts are handled, so this isn't
932 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
935 if (likely(nvmeq->cq_vector >= 0))
936 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
937 nvmeq->cq_head = head;
938 nvmeq->cq_phase = phase;
943 static void nvme_process_cq(struct nvme_queue *nvmeq)
945 __nvme_process_cq(nvmeq, NULL);
948 static irqreturn_t nvme_irq(int irq, void *data)
951 struct nvme_queue *nvmeq = data;
952 spin_lock(&nvmeq->q_lock);
953 nvme_process_cq(nvmeq);
954 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
956 spin_unlock(&nvmeq->q_lock);
960 static irqreturn_t nvme_irq_check(int irq, void *data)
962 struct nvme_queue *nvmeq = data;
963 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
964 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
966 return IRQ_WAKE_THREAD;
969 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
971 struct nvme_queue *nvmeq = hctx->driver_data;
973 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
975 spin_lock_irq(&nvmeq->q_lock);
976 __nvme_process_cq(nvmeq, &tag);
977 spin_unlock_irq(&nvmeq->q_lock);
986 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
988 struct nvme_queue *nvmeq = dev->queues[0];
989 struct nvme_command c;
990 struct nvme_cmd_info *cmd_info;
993 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE,
994 BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED);
998 req->cmd_flags |= REQ_NO_TIMEOUT;
999 cmd_info = blk_mq_rq_to_pdu(req);
1000 nvme_set_info(cmd_info, NULL, async_req_completion);
1002 memset(&c, 0, sizeof(c));
1003 c.common.opcode = nvme_admin_async_event;
1004 c.common.command_id = req->tag;
1006 blk_mq_free_request(req);
1007 __nvme_submit_cmd(nvmeq, &c);
1011 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1012 struct nvme_command *cmd,
1013 struct async_cmd_info *cmdinfo, unsigned timeout)
1015 struct nvme_queue *nvmeq = dev->queues[0];
1016 struct request *req;
1017 struct nvme_cmd_info *cmd_rq;
1019 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0);
1021 return PTR_ERR(req);
1023 req->timeout = timeout;
1024 cmd_rq = blk_mq_rq_to_pdu(req);
1026 nvme_set_info(cmd_rq, cmdinfo, async_completion);
1027 cmdinfo->status = -EINTR;
1029 cmd->common.command_id = req->tag;
1031 nvme_submit_cmd(nvmeq, cmd);
1035 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1037 struct nvme_command c;
1039 memset(&c, 0, sizeof(c));
1040 c.delete_queue.opcode = opcode;
1041 c.delete_queue.qid = cpu_to_le16(id);
1043 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1046 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1047 struct nvme_queue *nvmeq)
1049 struct nvme_command c;
1050 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1053 * Note: we (ab)use the fact the the prp fields survive if no data
1054 * is attached to the request.
1056 memset(&c, 0, sizeof(c));
1057 c.create_cq.opcode = nvme_admin_create_cq;
1058 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1059 c.create_cq.cqid = cpu_to_le16(qid);
1060 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1061 c.create_cq.cq_flags = cpu_to_le16(flags);
1062 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1064 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1067 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1068 struct nvme_queue *nvmeq)
1070 struct nvme_command c;
1071 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1074 * Note: we (ab)use the fact the the prp fields survive if no data
1075 * is attached to the request.
1077 memset(&c, 0, sizeof(c));
1078 c.create_sq.opcode = nvme_admin_create_sq;
1079 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1080 c.create_sq.sqid = cpu_to_le16(qid);
1081 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1082 c.create_sq.sq_flags = cpu_to_le16(flags);
1083 c.create_sq.cqid = cpu_to_le16(qid);
1085 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1088 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1090 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1093 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1095 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1099 * nvme_abort_req - Attempt aborting a request
1101 * Schedule controller reset if the command was already aborted once before and
1102 * still hasn't been returned to the driver, or if this is the admin queue.
1104 static void nvme_abort_req(struct request *req)
1106 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1107 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1108 struct nvme_dev *dev = nvmeq->dev;
1109 struct request *abort_req;
1110 struct nvme_cmd_info *abort_cmd;
1111 struct nvme_command cmd;
1113 if (!nvmeq->qid || cmd_rq->aborted) {
1114 spin_lock(&dev_list_lock);
1115 if (!__nvme_reset(dev)) {
1117 "I/O %d QID %d timeout, reset controller\n",
1118 req->tag, nvmeq->qid);
1120 spin_unlock(&dev_list_lock);
1124 if (!dev->ctrl.abort_limit)
1127 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE,
1129 if (IS_ERR(abort_req))
1132 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1133 nvme_set_info(abort_cmd, abort_req, abort_completion);
1135 memset(&cmd, 0, sizeof(cmd));
1136 cmd.abort.opcode = nvme_admin_abort_cmd;
1137 cmd.abort.cid = req->tag;
1138 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1139 cmd.abort.command_id = abort_req->tag;
1141 --dev->ctrl.abort_limit;
1142 cmd_rq->aborted = 1;
1144 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1146 nvme_submit_cmd(dev->queues[0], &cmd);
1149 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1151 struct nvme_queue *nvmeq = data;
1153 nvme_completion_fn fn;
1154 struct nvme_cmd_info *cmd;
1155 struct nvme_completion cqe;
1157 if (!blk_mq_request_started(req))
1160 cmd = blk_mq_rq_to_pdu(req);
1162 if (cmd->ctx == CMD_CTX_CANCELLED)
1165 if (blk_queue_dying(req->q))
1166 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1168 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1171 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1172 req->tag, nvmeq->qid);
1173 ctx = cancel_cmd_info(cmd, &fn);
1174 fn(nvmeq, ctx, &cqe);
1177 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1179 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1180 struct nvme_queue *nvmeq = cmd->nvmeq;
1182 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1184 spin_lock_irq(&nvmeq->q_lock);
1185 nvme_abort_req(req);
1186 spin_unlock_irq(&nvmeq->q_lock);
1189 * The aborted req will be completed on receiving the abort req.
1190 * We enable the timer again. If hit twice, it'll cause a device reset,
1191 * as the device then is in a faulty state.
1193 return BLK_EH_RESET_TIMER;
1196 static void nvme_free_queue(struct nvme_queue *nvmeq)
1198 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1199 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1201 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1202 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1206 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1210 for (i = dev->queue_count - 1; i >= lowest; i--) {
1211 struct nvme_queue *nvmeq = dev->queues[i];
1213 dev->queues[i] = NULL;
1214 nvme_free_queue(nvmeq);
1219 * nvme_suspend_queue - put queue into suspended state
1220 * @nvmeq - queue to suspend
1222 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1226 spin_lock_irq(&nvmeq->q_lock);
1227 if (nvmeq->cq_vector == -1) {
1228 spin_unlock_irq(&nvmeq->q_lock);
1231 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1232 nvmeq->dev->online_queues--;
1233 nvmeq->cq_vector = -1;
1234 spin_unlock_irq(&nvmeq->q_lock);
1236 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1237 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q);
1239 irq_set_affinity_hint(vector, NULL);
1240 free_irq(vector, nvmeq);
1245 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1247 spin_lock_irq(&nvmeq->q_lock);
1248 if (nvmeq->tags && *nvmeq->tags)
1249 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1250 spin_unlock_irq(&nvmeq->q_lock);
1253 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1255 struct nvme_queue *nvmeq = dev->queues[qid];
1259 if (nvme_suspend_queue(nvmeq))
1262 /* Don't tell the adapter to delete the admin queue.
1263 * Don't tell a removed adapter to delete IO queues. */
1264 if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) {
1265 adapter_delete_sq(dev, qid);
1266 adapter_delete_cq(dev, qid);
1269 spin_lock_irq(&nvmeq->q_lock);
1270 nvme_process_cq(nvmeq);
1271 spin_unlock_irq(&nvmeq->q_lock);
1274 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1277 int q_depth = dev->q_depth;
1278 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1280 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1281 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1282 mem_per_q = round_down(mem_per_q, dev->page_size);
1283 q_depth = div_u64(mem_per_q, entry_size);
1286 * Ensure the reduced q_depth is above some threshold where it
1287 * would be better to map queues in system memory with the
1297 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1300 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1301 unsigned offset = (qid - 1) *
1302 roundup(SQ_SIZE(depth), dev->page_size);
1303 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1304 nvmeq->sq_cmds_io = dev->cmb + offset;
1306 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1307 &nvmeq->sq_dma_addr, GFP_KERNEL);
1308 if (!nvmeq->sq_cmds)
1315 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1318 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1322 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1323 &nvmeq->cq_dma_addr, GFP_KERNEL);
1327 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1330 nvmeq->q_dmadev = dev->dev;
1332 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1333 dev->ctrl.instance, qid);
1334 spin_lock_init(&nvmeq->q_lock);
1336 nvmeq->cq_phase = 1;
1337 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1338 nvmeq->q_depth = depth;
1340 nvmeq->cq_vector = -1;
1341 dev->queues[qid] = nvmeq;
1343 /* make sure queue descriptor is set before queue count, for kthread */
1350 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1351 nvmeq->cq_dma_addr);
1357 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1360 if (use_threaded_interrupts)
1361 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1362 nvme_irq_check, nvme_irq, IRQF_SHARED,
1364 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1365 IRQF_SHARED, name, nvmeq);
1368 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1370 struct nvme_dev *dev = nvmeq->dev;
1372 spin_lock_irq(&nvmeq->q_lock);
1375 nvmeq->cq_phase = 1;
1376 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1377 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1378 dev->online_queues++;
1379 spin_unlock_irq(&nvmeq->q_lock);
1382 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1384 struct nvme_dev *dev = nvmeq->dev;
1387 nvmeq->cq_vector = qid - 1;
1388 result = adapter_alloc_cq(dev, qid, nvmeq);
1392 result = adapter_alloc_sq(dev, qid, nvmeq);
1396 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1400 nvme_init_queue(nvmeq, qid);
1404 adapter_delete_sq(dev, qid);
1406 adapter_delete_cq(dev, qid);
1410 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1412 unsigned long timeout;
1413 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1415 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1417 while ((readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_RDY) != bit) {
1419 if (fatal_signal_pending(current))
1421 if (time_after(jiffies, timeout)) {
1423 "Device not ready; aborting %s\n", enabled ?
1424 "initialisation" : "reset");
1433 * If the device has been passed off to us in an enabled state, just clear
1434 * the enabled bit. The spec says we should set the 'shutdown notification
1435 * bits', but doing so may cause the device to complete commands to the
1436 * admin queue ... and we don't know what memory that might be pointing at!
1438 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1440 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1441 dev->ctrl_config &= ~NVME_CC_ENABLE;
1442 writel(dev->ctrl_config, dev->bar + NVME_REG_CC);
1444 return nvme_wait_ready(dev, cap, false);
1447 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1449 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1450 dev->ctrl_config |= NVME_CC_ENABLE;
1451 writel(dev->ctrl_config, dev->bar + NVME_REG_CC);
1453 return nvme_wait_ready(dev, cap, true);
1456 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1458 unsigned long timeout;
1460 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1461 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1463 writel(dev->ctrl_config, dev->bar + NVME_REG_CC);
1465 timeout = SHUTDOWN_TIMEOUT + jiffies;
1466 while ((readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_SHST_MASK) !=
1467 NVME_CSTS_SHST_CMPLT) {
1469 if (fatal_signal_pending(current))
1471 if (time_after(jiffies, timeout)) {
1473 "Device shutdown incomplete; abort shutdown\n");
1481 static struct blk_mq_ops nvme_mq_admin_ops = {
1482 .queue_rq = nvme_queue_rq,
1483 .map_queue = blk_mq_map_queue,
1484 .init_hctx = nvme_admin_init_hctx,
1485 .exit_hctx = nvme_admin_exit_hctx,
1486 .init_request = nvme_admin_init_request,
1487 .timeout = nvme_timeout,
1490 static struct blk_mq_ops nvme_mq_ops = {
1491 .queue_rq = nvme_queue_rq,
1492 .map_queue = blk_mq_map_queue,
1493 .init_hctx = nvme_init_hctx,
1494 .init_request = nvme_init_request,
1495 .timeout = nvme_timeout,
1499 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1501 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1502 blk_cleanup_queue(dev->ctrl.admin_q);
1503 blk_mq_free_tag_set(&dev->admin_tagset);
1507 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1509 if (!dev->ctrl.admin_q) {
1510 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1511 dev->admin_tagset.nr_hw_queues = 1;
1512 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1513 dev->admin_tagset.reserved_tags = 1;
1514 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1515 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1516 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1517 dev->admin_tagset.driver_data = dev;
1519 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1522 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1523 if (IS_ERR(dev->ctrl.admin_q)) {
1524 blk_mq_free_tag_set(&dev->admin_tagset);
1527 if (!blk_get_queue(dev->ctrl.admin_q)) {
1528 nvme_dev_remove_admin(dev);
1529 dev->ctrl.admin_q = NULL;
1533 blk_mq_unfreeze_queue(dev->ctrl.admin_q);
1538 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1542 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1543 struct nvme_queue *nvmeq;
1545 * default to a 4K page size, with the intention to update this
1546 * path in the future to accomodate architectures with differing
1547 * kernel and IO page sizes.
1549 unsigned page_shift = 12;
1550 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1552 if (page_shift < dev_page_min) {
1554 "Minimum device page size (%u) too large for "
1555 "host (%u)\n", 1 << dev_page_min,
1560 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1561 NVME_CAP_NSSRC(cap) : 0;
1563 if (dev->subsystem &&
1564 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1565 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1567 result = nvme_disable_ctrl(dev, cap);
1571 nvmeq = dev->queues[0];
1573 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1578 aqa = nvmeq->q_depth - 1;
1581 dev->page_size = 1 << page_shift;
1583 dev->ctrl_config = NVME_CC_CSS_NVM;
1584 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1585 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1586 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1588 writel(aqa, dev->bar + NVME_REG_AQA);
1589 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1590 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1592 result = nvme_enable_ctrl(dev, cap);
1596 nvmeq->cq_vector = 0;
1597 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1599 nvmeq->cq_vector = -1;
1606 nvme_free_queues(dev, 0);
1610 static int nvme_subsys_reset(struct nvme_dev *dev)
1612 if (!dev->subsystem)
1615 writel(0x4E564D65, dev->bar + NVME_REG_NSSR); /* "NVMe" */
1619 static int nvme_kthread(void *data)
1621 struct nvme_dev *dev, *next;
1623 while (!kthread_should_stop()) {
1624 set_current_state(TASK_INTERRUPTIBLE);
1625 spin_lock(&dev_list_lock);
1626 list_for_each_entry_safe(dev, next, &dev_list, node) {
1628 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1630 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1631 csts & NVME_CSTS_CFS) {
1632 if (!__nvme_reset(dev)) {
1634 "Failed status: %x, reset controller\n",
1635 readl(dev->bar + NVME_REG_CSTS));
1639 for (i = 0; i < dev->queue_count; i++) {
1640 struct nvme_queue *nvmeq = dev->queues[i];
1643 spin_lock_irq(&nvmeq->q_lock);
1644 nvme_process_cq(nvmeq);
1646 while (i == 0 && dev->ctrl.event_limit > 0) {
1647 if (nvme_submit_async_admin_req(dev))
1649 dev->ctrl.event_limit--;
1651 spin_unlock_irq(&nvmeq->q_lock);
1654 spin_unlock(&dev_list_lock);
1655 schedule_timeout(round_jiffies_relative(HZ));
1660 static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
1663 struct gendisk *disk;
1664 int node = dev_to_node(dev->dev);
1666 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
1670 ns->queue = blk_mq_init_queue(&dev->tagset);
1671 if (IS_ERR(ns->queue))
1673 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1674 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1675 ns->ctrl = &dev->ctrl;
1676 ns->queue->queuedata = ns;
1678 disk = alloc_disk_node(0, node);
1680 goto out_free_queue;
1682 kref_init(&ns->kref);
1685 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
1686 list_add_tail(&ns->list, &dev->namespaces);
1688 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1689 if (dev->max_hw_sectors) {
1690 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1691 blk_queue_max_segments(ns->queue,
1692 (dev->max_hw_sectors / (dev->page_size >> 9)) + 1);
1694 if (dev->stripe_size)
1695 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
1696 if (dev->ctrl.vwc & NVME_CTRL_VWC_PRESENT)
1697 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
1698 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
1700 disk->major = nvme_major;
1701 disk->first_minor = 0;
1702 disk->fops = &nvme_fops;
1703 disk->private_data = ns;
1704 disk->queue = ns->queue;
1705 disk->driverfs_dev = dev->device;
1706 disk->flags = GENHD_FL_EXT_DEVT;
1707 sprintf(disk->disk_name, "nvme%dn%d", dev->ctrl.instance, nsid);
1710 * Initialize capacity to 0 until we establish the namespace format and
1711 * setup integrity extentions if necessary. The revalidate_disk after
1712 * add_disk allows the driver to register with integrity if the format
1715 set_capacity(disk, 0);
1716 if (nvme_revalidate_disk(ns->disk))
1719 kref_get(&dev->ctrl.kref);
1720 if (ns->type != NVME_NS_LIGHTNVM) {
1723 struct block_device *bd = bdget_disk(ns->disk, 0);
1726 if (blkdev_get(bd, FMODE_READ, NULL)) {
1730 blkdev_reread_part(bd);
1731 blkdev_put(bd, FMODE_READ);
1737 list_del(&ns->list);
1739 blk_cleanup_queue(ns->queue);
1745 * Create I/O queues. Failing to create an I/O queue is not an issue,
1746 * we can continue with less than the desired amount of queues, and
1747 * even a controller without I/O queues an still be used to issue
1748 * admin commands. This might be useful to upgrade a buggy firmware
1751 static void nvme_create_io_queues(struct nvme_dev *dev)
1755 for (i = dev->queue_count; i <= dev->max_qid; i++)
1756 if (!nvme_alloc_queue(dev, i, dev->q_depth))
1759 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1760 if (nvme_create_queue(dev->queues[i], i)) {
1761 nvme_free_queues(dev, i);
1766 static int set_queue_count(struct nvme_dev *dev, int count)
1770 u32 q_count = (count - 1) | ((count - 1) << 16);
1772 status = nvme_set_features(&dev->ctrl, NVME_FEAT_NUM_QUEUES, q_count, 0,
1777 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
1780 return min(result & 0xffff, result >> 16) + 1;
1783 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1785 u64 szu, size, offset;
1787 resource_size_t bar_size;
1788 struct pci_dev *pdev = to_pci_dev(dev->dev);
1790 dma_addr_t dma_addr;
1795 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1796 if (!(NVME_CMB_SZ(dev->cmbsz)))
1799 cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1801 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1802 size = szu * NVME_CMB_SZ(dev->cmbsz);
1803 offset = szu * NVME_CMB_OFST(cmbloc);
1804 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1806 if (offset > bar_size)
1810 * Controllers may support a CMB size larger than their BAR,
1811 * for example, due to being behind a bridge. Reduce the CMB to
1812 * the reported size of the BAR
1814 if (size > bar_size - offset)
1815 size = bar_size - offset;
1817 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1818 cmb = ioremap_wc(dma_addr, size);
1822 dev->cmb_dma_addr = dma_addr;
1823 dev->cmb_size = size;
1827 static inline void nvme_release_cmb(struct nvme_dev *dev)
1835 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1837 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1840 static int nvme_setup_io_queues(struct nvme_dev *dev)
1842 struct nvme_queue *adminq = dev->queues[0];
1843 struct pci_dev *pdev = to_pci_dev(dev->dev);
1844 int result, i, vecs, nr_io_queues, size;
1846 nr_io_queues = num_possible_cpus();
1847 result = set_queue_count(dev, nr_io_queues);
1850 if (result < nr_io_queues)
1851 nr_io_queues = result;
1853 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1854 result = nvme_cmb_qdepth(dev, nr_io_queues,
1855 sizeof(struct nvme_command));
1857 dev->q_depth = result;
1859 nvme_release_cmb(dev);
1862 size = db_bar_size(dev, nr_io_queues);
1866 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1869 if (!--nr_io_queues)
1871 size = db_bar_size(dev, nr_io_queues);
1873 dev->dbs = dev->bar + 4096;
1874 adminq->q_db = dev->dbs;
1877 /* Deregister the admin queue's interrupt */
1878 free_irq(dev->entry[0].vector, adminq);
1881 * If we enable msix early due to not intx, disable it again before
1882 * setting up the full range we need.
1885 pci_disable_msix(pdev);
1887 for (i = 0; i < nr_io_queues; i++)
1888 dev->entry[i].entry = i;
1889 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1891 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1895 for (i = 0; i < vecs; i++)
1896 dev->entry[i].vector = i + pdev->irq;
1901 * Should investigate if there's a performance win from allocating
1902 * more queues than interrupt vectors; it might allow the submission
1903 * path to scale better, even if the receive path is limited by the
1904 * number of interrupts.
1906 nr_io_queues = vecs;
1907 dev->max_qid = nr_io_queues;
1909 result = queue_request_irq(dev, adminq, adminq->irqname);
1911 adminq->cq_vector = -1;
1915 /* Free previously allocated queues that are no longer usable */
1916 nvme_free_queues(dev, nr_io_queues + 1);
1917 nvme_create_io_queues(dev);
1922 nvme_free_queues(dev, 1);
1926 static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
1928 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
1929 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
1931 return nsa->ns_id - nsb->ns_id;
1934 static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
1938 list_for_each_entry(ns, &dev->namespaces, list) {
1939 if (ns->ns_id == nsid)
1941 if (ns->ns_id > nsid)
1947 static inline bool nvme_io_incapable(struct nvme_dev *dev)
1949 return (!dev->bar ||
1950 readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_CFS ||
1951 dev->online_queues < 2);
1954 static void nvme_ns_remove(struct nvme_ns *ns)
1956 bool kill = nvme_io_incapable(to_nvme_dev(ns->ctrl)) &&
1957 !blk_queue_dying(ns->queue);
1960 blk_set_queue_dying(ns->queue);
1961 if (ns->disk->flags & GENHD_FL_UP)
1962 del_gendisk(ns->disk);
1963 if (kill || !blk_queue_dying(ns->queue)) {
1964 blk_mq_abort_requeue_list(ns->queue);
1965 blk_cleanup_queue(ns->queue);
1967 list_del_init(&ns->list);
1971 static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
1973 struct nvme_ns *ns, *next;
1976 for (i = 1; i <= nn; i++) {
1977 ns = nvme_find_ns(dev, i);
1979 if (revalidate_disk(ns->disk))
1982 nvme_alloc_ns(dev, i);
1984 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1988 list_sort(NULL, &dev->namespaces, ns_cmp);
1991 static void nvme_set_irq_hints(struct nvme_dev *dev)
1993 struct nvme_queue *nvmeq;
1996 for (i = 0; i < dev->online_queues; i++) {
1997 nvmeq = dev->queues[i];
1999 if (!nvmeq->tags || !(*nvmeq->tags))
2002 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2003 blk_mq_tags_cpumask(*nvmeq->tags));
2007 static void nvme_dev_scan(struct work_struct *work)
2009 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2010 struct nvme_id_ctrl *ctrl;
2012 if (!dev->tagset.tags)
2014 if (nvme_identify_ctrl(&dev->ctrl, &ctrl))
2016 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2018 nvme_set_irq_hints(dev);
2022 * Return: error value if an error occurred setting up the queues or calling
2023 * Identify Device. 0 if these succeeded, even if adding some of the
2024 * namespaces failed. At the moment, these failures are silent. TBD which
2025 * failures should be reported.
2027 static int nvme_dev_add(struct nvme_dev *dev)
2030 struct nvme_id_ctrl *ctrl;
2031 int shift = NVME_CAP_MPSMIN(lo_hi_readq(dev->bar + NVME_REG_CAP)) + 12;
2033 res = nvme_identify_ctrl(&dev->ctrl, &ctrl);
2035 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
2039 dev->ctrl.oncs = le16_to_cpup(&ctrl->oncs);
2040 dev->ctrl.abort_limit = ctrl->acl + 1;
2041 dev->ctrl.vwc = ctrl->vwc;
2042 memcpy(dev->ctrl.serial, ctrl->sn, sizeof(ctrl->sn));
2043 memcpy(dev->ctrl.model, ctrl->mn, sizeof(ctrl->mn));
2044 memcpy(dev->ctrl.firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2046 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2048 dev->max_hw_sectors = UINT_MAX;
2050 if ((dev->ctrl.quirks & NVME_QUIRK_STRIPE_SIZE) && ctrl->vs[3]) {
2051 unsigned int max_hw_sectors;
2053 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2054 max_hw_sectors = dev->stripe_size >> (shift - 9);
2055 if (dev->max_hw_sectors) {
2056 dev->max_hw_sectors = min(max_hw_sectors,
2057 dev->max_hw_sectors);
2059 dev->max_hw_sectors = max_hw_sectors;
2063 if (!dev->tagset.tags) {
2064 dev->tagset.ops = &nvme_mq_ops;
2065 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2066 dev->tagset.timeout = NVME_IO_TIMEOUT;
2067 dev->tagset.numa_node = dev_to_node(dev->dev);
2068 dev->tagset.queue_depth =
2069 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2070 dev->tagset.cmd_size = nvme_cmd_size(dev);
2071 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2072 dev->tagset.driver_data = dev;
2074 if (blk_mq_alloc_tag_set(&dev->tagset))
2077 schedule_work(&dev->scan_work);
2081 static int nvme_dev_map(struct nvme_dev *dev)
2084 int bars, result = -ENOMEM;
2085 struct pci_dev *pdev = to_pci_dev(dev->dev);
2087 if (pci_enable_device_mem(pdev))
2090 dev->entry[0].vector = pdev->irq;
2091 pci_set_master(pdev);
2092 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2096 if (pci_request_selected_regions(pdev, bars, "nvme"))
2099 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2100 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2103 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2107 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2113 * Some devices don't advertse INTx interrupts, pre-enable a single
2114 * MSIX vec for setup. We'll adjust this later.
2117 result = pci_enable_msix(pdev, dev->entry, 1);
2122 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2124 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2125 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2126 dev->dbs = dev->bar + 4096;
2127 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
2128 dev->cmb = nvme_map_cmb(dev);
2136 pci_release_regions(pdev);
2138 pci_disable_device(pdev);
2142 static void nvme_dev_unmap(struct nvme_dev *dev)
2144 struct pci_dev *pdev = to_pci_dev(dev->dev);
2146 if (pdev->msi_enabled)
2147 pci_disable_msi(pdev);
2148 else if (pdev->msix_enabled)
2149 pci_disable_msix(pdev);
2154 pci_release_regions(pdev);
2157 if (pci_is_enabled(pdev))
2158 pci_disable_device(pdev);
2161 struct nvme_delq_ctx {
2162 struct task_struct *waiter;
2163 struct kthread_worker *worker;
2167 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2169 dq->waiter = current;
2173 set_current_state(TASK_KILLABLE);
2174 if (!atomic_read(&dq->refcount))
2176 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2177 fatal_signal_pending(current)) {
2179 * Disable the controller first since we can't trust it
2180 * at this point, but leave the admin queue enabled
2181 * until all queue deletion requests are flushed.
2182 * FIXME: This may take a while if there are more h/w
2183 * queues than admin tags.
2185 set_current_state(TASK_RUNNING);
2186 nvme_disable_ctrl(dev,
2187 lo_hi_readq(dev->bar + NVME_REG_CAP));
2188 nvme_clear_queue(dev->queues[0]);
2189 flush_kthread_worker(dq->worker);
2190 nvme_disable_queue(dev, 0);
2194 set_current_state(TASK_RUNNING);
2197 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2199 atomic_dec(&dq->refcount);
2201 wake_up_process(dq->waiter);
2204 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2206 atomic_inc(&dq->refcount);
2210 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2212 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2215 spin_lock_irq(&nvmeq->q_lock);
2216 nvme_process_cq(nvmeq);
2217 spin_unlock_irq(&nvmeq->q_lock);
2220 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2221 kthread_work_func_t fn)
2223 struct nvme_command c;
2225 memset(&c, 0, sizeof(c));
2226 c.delete_queue.opcode = opcode;
2227 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2229 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2230 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2234 static void nvme_del_cq_work_handler(struct kthread_work *work)
2236 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2238 nvme_del_queue_end(nvmeq);
2241 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2243 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2244 nvme_del_cq_work_handler);
2247 static void nvme_del_sq_work_handler(struct kthread_work *work)
2249 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2251 int status = nvmeq->cmdinfo.status;
2254 status = nvme_delete_cq(nvmeq);
2256 nvme_del_queue_end(nvmeq);
2259 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2261 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2262 nvme_del_sq_work_handler);
2265 static void nvme_del_queue_start(struct kthread_work *work)
2267 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2269 if (nvme_delete_sq(nvmeq))
2270 nvme_del_queue_end(nvmeq);
2273 static void nvme_disable_io_queues(struct nvme_dev *dev)
2276 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2277 struct nvme_delq_ctx dq;
2278 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2279 &worker, "nvme%d", dev->ctrl.instance);
2281 if (IS_ERR(kworker_task)) {
2283 "Failed to create queue del task\n");
2284 for (i = dev->queue_count - 1; i > 0; i--)
2285 nvme_disable_queue(dev, i);
2290 atomic_set(&dq.refcount, 0);
2291 dq.worker = &worker;
2292 for (i = dev->queue_count - 1; i > 0; i--) {
2293 struct nvme_queue *nvmeq = dev->queues[i];
2295 if (nvme_suspend_queue(nvmeq))
2297 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2298 nvmeq->cmdinfo.worker = dq.worker;
2299 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2300 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2302 nvme_wait_dq(&dq, dev);
2303 kthread_stop(kworker_task);
2307 * Remove the node from the device list and check
2308 * for whether or not we need to stop the nvme_thread.
2310 static void nvme_dev_list_remove(struct nvme_dev *dev)
2312 struct task_struct *tmp = NULL;
2314 spin_lock(&dev_list_lock);
2315 list_del_init(&dev->node);
2316 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2320 spin_unlock(&dev_list_lock);
2326 static void nvme_freeze_queues(struct nvme_dev *dev)
2330 list_for_each_entry(ns, &dev->namespaces, list) {
2331 blk_mq_freeze_queue_start(ns->queue);
2333 spin_lock_irq(ns->queue->queue_lock);
2334 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2335 spin_unlock_irq(ns->queue->queue_lock);
2337 blk_mq_cancel_requeue_work(ns->queue);
2338 blk_mq_stop_hw_queues(ns->queue);
2342 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2346 list_for_each_entry(ns, &dev->namespaces, list) {
2347 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2348 blk_mq_unfreeze_queue(ns->queue);
2349 blk_mq_start_stopped_hw_queues(ns->queue, true);
2350 blk_mq_kick_requeue_list(ns->queue);
2354 static void nvme_dev_shutdown(struct nvme_dev *dev)
2359 nvme_dev_list_remove(dev);
2362 nvme_freeze_queues(dev);
2363 csts = readl(dev->bar + NVME_REG_CSTS);
2365 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2366 for (i = dev->queue_count - 1; i >= 0; i--) {
2367 struct nvme_queue *nvmeq = dev->queues[i];
2368 nvme_suspend_queue(nvmeq);
2371 nvme_disable_io_queues(dev);
2372 nvme_shutdown_ctrl(dev);
2373 nvme_disable_queue(dev, 0);
2375 nvme_dev_unmap(dev);
2377 for (i = dev->queue_count - 1; i >= 0; i--)
2378 nvme_clear_queue(dev->queues[i]);
2381 static void nvme_dev_remove(struct nvme_dev *dev)
2383 struct nvme_ns *ns, *next;
2385 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2389 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2391 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2392 PAGE_SIZE, PAGE_SIZE, 0);
2393 if (!dev->prp_page_pool)
2396 /* Optimisation for I/Os between 4k and 128k */
2397 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2399 if (!dev->prp_small_pool) {
2400 dma_pool_destroy(dev->prp_page_pool);
2406 static void nvme_release_prp_pools(struct nvme_dev *dev)
2408 dma_pool_destroy(dev->prp_page_pool);
2409 dma_pool_destroy(dev->prp_small_pool);
2412 static DEFINE_IDA(nvme_instance_ida);
2414 static int nvme_set_instance(struct nvme_dev *dev)
2416 int instance, error;
2419 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2422 spin_lock(&dev_list_lock);
2423 error = ida_get_new(&nvme_instance_ida, &instance);
2424 spin_unlock(&dev_list_lock);
2425 } while (error == -EAGAIN);
2430 dev->ctrl.instance = instance;
2434 static void nvme_release_instance(struct nvme_dev *dev)
2436 spin_lock(&dev_list_lock);
2437 ida_remove(&nvme_instance_ida, dev->ctrl.instance);
2438 spin_unlock(&dev_list_lock);
2441 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2443 struct nvme_dev *dev = to_nvme_dev(ctrl);
2445 put_device(dev->dev);
2446 put_device(dev->device);
2447 nvme_release_instance(dev);
2448 if (dev->tagset.tags)
2449 blk_mq_free_tag_set(&dev->tagset);
2450 if (dev->ctrl.admin_q)
2451 blk_put_queue(dev->ctrl.admin_q);
2457 static int nvme_dev_open(struct inode *inode, struct file *f)
2459 struct nvme_dev *dev;
2460 int instance = iminor(inode);
2463 spin_lock(&dev_list_lock);
2464 list_for_each_entry(dev, &dev_list, node) {
2465 if (dev->ctrl.instance == instance) {
2466 if (!dev->ctrl.admin_q) {
2470 if (!kref_get_unless_zero(&dev->ctrl.kref))
2472 f->private_data = dev;
2477 spin_unlock(&dev_list_lock);
2482 static int nvme_dev_release(struct inode *inode, struct file *f)
2484 struct nvme_dev *dev = f->private_data;
2485 nvme_put_ctrl(&dev->ctrl);
2489 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2491 struct nvme_dev *dev = f->private_data;
2495 case NVME_IOCTL_ADMIN_CMD:
2496 return nvme_user_cmd(&dev->ctrl, NULL, (void __user *)arg);
2497 case NVME_IOCTL_IO_CMD:
2498 if (list_empty(&dev->namespaces))
2500 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2501 return nvme_user_cmd(&dev->ctrl, ns, (void __user *)arg);
2502 case NVME_IOCTL_RESET:
2503 dev_warn(dev->dev, "resetting controller\n");
2504 return nvme_reset(dev);
2505 case NVME_IOCTL_SUBSYS_RESET:
2506 return nvme_subsys_reset(dev);
2512 static const struct file_operations nvme_dev_fops = {
2513 .owner = THIS_MODULE,
2514 .open = nvme_dev_open,
2515 .release = nvme_dev_release,
2516 .unlocked_ioctl = nvme_dev_ioctl,
2517 .compat_ioctl = nvme_dev_ioctl,
2520 static void nvme_probe_work(struct work_struct *work)
2522 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
2523 bool start_thread = false;
2526 result = nvme_dev_map(dev);
2530 result = nvme_configure_admin_queue(dev);
2534 spin_lock(&dev_list_lock);
2535 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2536 start_thread = true;
2539 list_add(&dev->node, &dev_list);
2540 spin_unlock(&dev_list_lock);
2543 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2544 wake_up_all(&nvme_kthread_wait);
2546 wait_event_killable(nvme_kthread_wait, nvme_thread);
2548 if (IS_ERR_OR_NULL(nvme_thread)) {
2549 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2553 nvme_init_queue(dev->queues[0], 0);
2554 result = nvme_alloc_admin_tags(dev);
2558 result = nvme_setup_io_queues(dev);
2562 dev->ctrl.event_limit = 1;
2565 * Keep the controller around but remove all namespaces if we don't have
2566 * any working I/O queue.
2568 if (dev->online_queues < 2) {
2569 dev_warn(dev->dev, "IO queues not created\n");
2570 nvme_dev_remove(dev);
2572 nvme_unfreeze_queues(dev);
2579 nvme_dev_remove_admin(dev);
2580 blk_put_queue(dev->ctrl.admin_q);
2581 dev->ctrl.admin_q = NULL;
2582 dev->queues[0]->tags = NULL;
2584 nvme_disable_queue(dev, 0);
2585 nvme_dev_list_remove(dev);
2587 nvme_dev_unmap(dev);
2589 if (!work_busy(&dev->reset_work))
2590 nvme_dead_ctrl(dev);
2593 static int nvme_remove_dead_ctrl(void *arg)
2595 struct nvme_dev *dev = (struct nvme_dev *)arg;
2596 struct pci_dev *pdev = to_pci_dev(dev->dev);
2598 if (pci_get_drvdata(pdev))
2599 pci_stop_and_remove_bus_device_locked(pdev);
2600 nvme_put_ctrl(&dev->ctrl);
2604 static void nvme_dead_ctrl(struct nvme_dev *dev)
2606 dev_warn(dev->dev, "Device failed to resume\n");
2607 kref_get(&dev->ctrl.kref);
2608 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2609 dev->ctrl.instance))) {
2611 "Failed to start controller remove task\n");
2612 nvme_put_ctrl(&dev->ctrl);
2616 static void nvme_reset_work(struct work_struct *ws)
2618 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2619 bool in_probe = work_busy(&dev->probe_work);
2621 nvme_dev_shutdown(dev);
2623 /* Synchronize with device probe so that work will see failure status
2624 * and exit gracefully without trying to schedule another reset */
2625 flush_work(&dev->probe_work);
2627 /* Fail this device if reset occured during probe to avoid
2628 * infinite initialization loops. */
2630 nvme_dead_ctrl(dev);
2633 /* Schedule device resume asynchronously so the reset work is available
2634 * to cleanup errors that may occur during reinitialization */
2635 schedule_work(&dev->probe_work);
2638 static int __nvme_reset(struct nvme_dev *dev)
2640 if (work_pending(&dev->reset_work))
2642 list_del_init(&dev->node);
2643 queue_work(nvme_workq, &dev->reset_work);
2647 static int nvme_reset(struct nvme_dev *dev)
2651 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2654 spin_lock(&dev_list_lock);
2655 ret = __nvme_reset(dev);
2656 spin_unlock(&dev_list_lock);
2659 flush_work(&dev->reset_work);
2660 flush_work(&dev->probe_work);
2667 static ssize_t nvme_sysfs_reset(struct device *dev,
2668 struct device_attribute *attr, const char *buf,
2671 struct nvme_dev *ndev = dev_get_drvdata(dev);
2674 ret = nvme_reset(ndev);
2680 static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
2682 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2684 *val = readl(to_nvme_dev(ctrl)->bar + off);
2688 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2689 .reg_read32 = nvme_pci_reg_read32,
2690 .free_ctrl = nvme_pci_free_ctrl,
2693 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2695 int node, result = -ENOMEM;
2696 struct nvme_dev *dev;
2698 node = dev_to_node(&pdev->dev);
2699 if (node == NUMA_NO_NODE)
2700 set_dev_node(&pdev->dev, 0);
2702 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2705 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2709 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2714 INIT_LIST_HEAD(&dev->namespaces);
2715 INIT_WORK(&dev->reset_work, nvme_reset_work);
2716 dev->dev = get_device(&pdev->dev);
2717 pci_set_drvdata(pdev, dev);
2719 dev->ctrl.ops = &nvme_pci_ctrl_ops;
2720 dev->ctrl.dev = dev->dev;
2721 dev->ctrl.quirks = id->driver_data;
2723 result = nvme_set_instance(dev);
2727 result = nvme_setup_prp_pools(dev);
2731 kref_init(&dev->ctrl.kref);
2732 dev->device = device_create(nvme_class, &pdev->dev,
2733 MKDEV(nvme_char_major, dev->ctrl.instance),
2734 dev, "nvme%d", dev->ctrl.instance);
2735 if (IS_ERR(dev->device)) {
2736 result = PTR_ERR(dev->device);
2739 get_device(dev->device);
2740 dev_set_drvdata(dev->device, dev);
2742 result = device_create_file(dev->device, &dev_attr_reset_controller);
2746 INIT_LIST_HEAD(&dev->node);
2747 INIT_WORK(&dev->scan_work, nvme_dev_scan);
2748 INIT_WORK(&dev->probe_work, nvme_probe_work);
2749 schedule_work(&dev->probe_work);
2753 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->ctrl.instance));
2754 put_device(dev->device);
2756 nvme_release_prp_pools(dev);
2758 nvme_release_instance(dev);
2760 put_device(dev->dev);
2768 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2770 struct nvme_dev *dev = pci_get_drvdata(pdev);
2773 nvme_dev_shutdown(dev);
2775 schedule_work(&dev->probe_work);
2778 static void nvme_shutdown(struct pci_dev *pdev)
2780 struct nvme_dev *dev = pci_get_drvdata(pdev);
2781 nvme_dev_shutdown(dev);
2784 static void nvme_remove(struct pci_dev *pdev)
2786 struct nvme_dev *dev = pci_get_drvdata(pdev);
2788 spin_lock(&dev_list_lock);
2789 list_del_init(&dev->node);
2790 spin_unlock(&dev_list_lock);
2792 pci_set_drvdata(pdev, NULL);
2793 flush_work(&dev->probe_work);
2794 flush_work(&dev->reset_work);
2795 flush_work(&dev->scan_work);
2796 device_remove_file(dev->device, &dev_attr_reset_controller);
2797 nvme_dev_remove(dev);
2798 nvme_dev_shutdown(dev);
2799 nvme_dev_remove_admin(dev);
2800 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->ctrl.instance));
2801 nvme_free_queues(dev, 0);
2802 nvme_release_cmb(dev);
2803 nvme_release_prp_pools(dev);
2804 nvme_put_ctrl(&dev->ctrl);
2807 /* These functions are yet to be implemented */
2808 #define nvme_error_detected NULL
2809 #define nvme_dump_registers NULL
2810 #define nvme_link_reset NULL
2811 #define nvme_slot_reset NULL
2812 #define nvme_error_resume NULL
2814 #ifdef CONFIG_PM_SLEEP
2815 static int nvme_suspend(struct device *dev)
2817 struct pci_dev *pdev = to_pci_dev(dev);
2818 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2820 nvme_dev_shutdown(ndev);
2824 static int nvme_resume(struct device *dev)
2826 struct pci_dev *pdev = to_pci_dev(dev);
2827 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2829 schedule_work(&ndev->probe_work);
2834 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2836 static const struct pci_error_handlers nvme_err_handler = {
2837 .error_detected = nvme_error_detected,
2838 .mmio_enabled = nvme_dump_registers,
2839 .link_reset = nvme_link_reset,
2840 .slot_reset = nvme_slot_reset,
2841 .resume = nvme_error_resume,
2842 .reset_notify = nvme_reset_notify,
2845 /* Move to pci_ids.h later */
2846 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2848 static const struct pci_device_id nvme_id_table[] = {
2849 { PCI_VDEVICE(INTEL, 0x0953),
2850 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2851 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2852 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2855 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2857 static struct pci_driver nvme_driver = {
2859 .id_table = nvme_id_table,
2860 .probe = nvme_probe,
2861 .remove = nvme_remove,
2862 .shutdown = nvme_shutdown,
2864 .pm = &nvme_dev_pm_ops,
2866 .err_handler = &nvme_err_handler,
2869 static int __init nvme_init(void)
2873 init_waitqueue_head(&nvme_kthread_wait);
2875 nvme_workq = create_singlethread_workqueue("nvme");
2879 result = register_blkdev(nvme_major, "nvme");
2882 else if (result > 0)
2883 nvme_major = result;
2885 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
2888 goto unregister_blkdev;
2889 else if (result > 0)
2890 nvme_char_major = result;
2892 nvme_class = class_create(THIS_MODULE, "nvme");
2893 if (IS_ERR(nvme_class)) {
2894 result = PTR_ERR(nvme_class);
2895 goto unregister_chrdev;
2898 result = pci_register_driver(&nvme_driver);
2904 class_destroy(nvme_class);
2906 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
2908 unregister_blkdev(nvme_major, "nvme");
2910 destroy_workqueue(nvme_workq);
2914 static void __exit nvme_exit(void)
2916 pci_unregister_driver(&nvme_driver);
2917 unregister_blkdev(nvme_major, "nvme");
2918 destroy_workqueue(nvme_workq);
2919 class_destroy(nvme_class);
2920 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
2921 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2925 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2926 MODULE_LICENSE("GPL");
2927 MODULE_VERSION("1.0");
2928 module_init(nvme_init);
2929 module_exit(nvme_exit);