2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
8 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
16 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copy
26 * notice, this list of conditions and the following disclaimer in
27 * the documentation and/or other materials provided with the
29 * * Neither the name of Intel Corporation nor the names of its
30 * contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 * Intel PCIe NTB Linux driver
47 * Contact Information:
48 * Jon Mason <jon.mason@intel.com>
51 #ifndef NTB_HW_INTEL_H
52 #define NTB_HW_INTEL_H
54 #include <linux/ntb.h>
55 #include <linux/pci.h>
57 #define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
58 #define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
59 #define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
60 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
61 #define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E
62 #define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
63 #define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
64 #define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E
65 #define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F
66 #define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
67 #define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
68 #define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
69 #define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E
71 /* SNB hardware (and JSF, IVT, HSX) */
73 #define SNB_PBAR23LMT_OFFSET 0x0000
74 #define SNB_PBAR45LMT_OFFSET 0x0008
75 #define SNB_PBAR4LMT_OFFSET 0x0008
76 #define SNB_PBAR5LMT_OFFSET 0x000c
77 #define SNB_PBAR23XLAT_OFFSET 0x0010
78 #define SNB_PBAR45XLAT_OFFSET 0x0018
79 #define SNB_PBAR4XLAT_OFFSET 0x0018
80 #define SNB_PBAR5XLAT_OFFSET 0x001c
81 #define SNB_SBAR23LMT_OFFSET 0x0020
82 #define SNB_SBAR45LMT_OFFSET 0x0028
83 #define SNB_SBAR4LMT_OFFSET 0x0028
84 #define SNB_SBAR5LMT_OFFSET 0x002c
85 #define SNB_SBAR23XLAT_OFFSET 0x0030
86 #define SNB_SBAR45XLAT_OFFSET 0x0038
87 #define SNB_SBAR4XLAT_OFFSET 0x0038
88 #define SNB_SBAR5XLAT_OFFSET 0x003c
89 #define SNB_SBAR0BASE_OFFSET 0x0040
90 #define SNB_SBAR23BASE_OFFSET 0x0048
91 #define SNB_SBAR45BASE_OFFSET 0x0050
92 #define SNB_SBAR4BASE_OFFSET 0x0050
93 #define SNB_SBAR5BASE_OFFSET 0x0054
94 #define SNB_SBDF_OFFSET 0x005c
95 #define SNB_NTBCNTL_OFFSET 0x0058
96 #define SNB_PDOORBELL_OFFSET 0x0060
97 #define SNB_PDBMSK_OFFSET 0x0062
98 #define SNB_SDOORBELL_OFFSET 0x0064
99 #define SNB_SDBMSK_OFFSET 0x0066
100 #define SNB_USMEMMISS_OFFSET 0x0070
101 #define SNB_SPAD_OFFSET 0x0080
102 #define SNB_PBAR23SZ_OFFSET 0x00d0
103 #define SNB_PBAR45SZ_OFFSET 0x00d1
104 #define SNB_PBAR4SZ_OFFSET 0x00d1
105 #define SNB_SBAR23SZ_OFFSET 0x00d2
106 #define SNB_SBAR45SZ_OFFSET 0x00d3
107 #define SNB_SBAR4SZ_OFFSET 0x00d3
108 #define SNB_PPD_OFFSET 0x00d4
109 #define SNB_PBAR5SZ_OFFSET 0x00d5
110 #define SNB_SBAR5SZ_OFFSET 0x00d6
111 #define SNB_WCCNTRL_OFFSET 0x00e0
112 #define SNB_UNCERRSTS_OFFSET 0x014c
113 #define SNB_CORERRSTS_OFFSET 0x0158
114 #define SNB_LINK_STATUS_OFFSET 0x01a2
115 #define SNB_SPCICMD_OFFSET 0x0504
116 #define SNB_DEVCTRL_OFFSET 0x0598
117 #define SNB_DEVSTS_OFFSET 0x059a
118 #define SNB_SLINK_STATUS_OFFSET 0x05a2
119 #define SNB_B2B_SPAD_OFFSET 0x0100
120 #define SNB_B2B_DOORBELL_OFFSET 0x0140
121 #define SNB_B2B_XLAT_OFFSETL 0x0144
122 #define SNB_B2B_XLAT_OFFSETU 0x0148
123 #define SNB_PPD_CONN_MASK 0x03
124 #define SNB_PPD_CONN_TRANSPARENT 0x00
125 #define SNB_PPD_CONN_B2B 0x01
126 #define SNB_PPD_CONN_RP 0x02
127 #define SNB_PPD_DEV_MASK 0x10
128 #define SNB_PPD_DEV_USD 0x00
129 #define SNB_PPD_DEV_DSD 0x10
130 #define SNB_PPD_SPLIT_BAR_MASK 0x40
132 #define SNB_PPD_TOPO_MASK (SNB_PPD_CONN_MASK | SNB_PPD_DEV_MASK)
133 #define SNB_PPD_TOPO_PRI_USD (SNB_PPD_CONN_RP | SNB_PPD_DEV_USD)
134 #define SNB_PPD_TOPO_PRI_DSD (SNB_PPD_CONN_RP | SNB_PPD_DEV_DSD)
135 #define SNB_PPD_TOPO_SEC_USD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_USD)
136 #define SNB_PPD_TOPO_SEC_DSD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_DSD)
137 #define SNB_PPD_TOPO_B2B_USD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_USD)
138 #define SNB_PPD_TOPO_B2B_DSD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_DSD)
140 #define SNB_MW_COUNT 2
141 #define HSX_SPLIT_BAR_MW_COUNT 3
142 #define SNB_DB_COUNT 15
143 #define SNB_DB_LINK 15
144 #define SNB_DB_LINK_BIT BIT_ULL(SNB_DB_LINK)
145 #define SNB_DB_MSIX_VECTOR_COUNT 4
146 #define SNB_DB_MSIX_VECTOR_SHIFT 5
147 #define SNB_DB_TOTAL_SHIFT 16
148 #define SNB_SPAD_COUNT 16
152 #define BWD_SBAR2XLAT_OFFSET 0x0008
153 #define BWD_PDOORBELL_OFFSET 0x0020
154 #define BWD_PDBMSK_OFFSET 0x0028
155 #define BWD_NTBCNTL_OFFSET 0x0060
156 #define BWD_SPAD_OFFSET 0x0080
157 #define BWD_PPD_OFFSET 0x00d4
158 #define BWD_PBAR2XLAT_OFFSET 0x8008
159 #define BWD_B2B_DOORBELL_OFFSET 0x8020
160 #define BWD_B2B_SPAD_OFFSET 0x8080
161 #define BWD_SPCICMD_OFFSET 0xb004
162 #define BWD_LINK_STATUS_OFFSET 0xb052
163 #define BWD_ERRCORSTS_OFFSET 0xb110
164 #define BWD_IP_BASE 0xc000
165 #define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024)
166 #define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180)
167 #define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040)
168 #define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324)
169 #define BWD_MODPHY_PCSREG4 0x1c004
170 #define BWD_MODPHY_PCSREG6 0x1c006
172 #define BWD_PPD_INIT_LINK 0x0008
173 #define BWD_PPD_CONN_MASK 0x0300
174 #define BWD_PPD_CONN_TRANSPARENT 0x0000
175 #define BWD_PPD_CONN_B2B 0x0100
176 #define BWD_PPD_CONN_RP 0x0200
177 #define BWD_PPD_DEV_MASK 0x1000
178 #define BWD_PPD_DEV_USD 0x0000
179 #define BWD_PPD_DEV_DSD 0x1000
180 #define BWD_PPD_TOPO_MASK (BWD_PPD_CONN_MASK | BWD_PPD_DEV_MASK)
181 #define BWD_PPD_TOPO_PRI_USD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_USD)
182 #define BWD_PPD_TOPO_PRI_DSD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_DSD)
183 #define BWD_PPD_TOPO_SEC_USD (BWD_PPD_CONN_RP | BWD_PPD_DEV_USD)
184 #define BWD_PPD_TOPO_SEC_DSD (BWD_PPD_CONN_RP | BWD_PPD_DEV_DSD)
185 #define BWD_PPD_TOPO_B2B_USD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_USD)
186 #define BWD_PPD_TOPO_B2B_DSD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_DSD)
188 #define BWD_MW_COUNT 2
189 #define BWD_DB_COUNT 34
190 #define BWD_DB_VALID_MASK (BIT_ULL(BWD_DB_COUNT) - 1)
191 #define BWD_DB_MSIX_VECTOR_COUNT 34
192 #define BWD_DB_MSIX_VECTOR_SHIFT 1
193 #define BWD_DB_TOTAL_SHIFT 34
194 #define BWD_SPAD_COUNT 16
196 #define BWD_NTB_CTL_DOWN_BIT BIT(16)
197 #define BWD_NTB_CTL_ACTIVE(x) !(x & BWD_NTB_CTL_DOWN_BIT)
199 #define BWD_DESKEWSTS_DBERR BIT(15)
200 #define BWD_LTSSMERRSTS0_UNEXPECTEDEI BIT(20)
201 #define BWD_LTSSMSTATEJMP_FORCEDETECT BIT(2)
202 #define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF
204 #define BWD_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
205 #define BWD_LINK_RECOVERY_TIME msecs_to_jiffies(500)
207 /* Ntb control and link status */
209 #define NTB_CTL_CFG_LOCK BIT(0)
210 #define NTB_CTL_DISABLE BIT(1)
211 #define NTB_CTL_S2P_BAR2_SNOOP BIT(2)
212 #define NTB_CTL_P2S_BAR2_SNOOP BIT(4)
213 #define NTB_CTL_S2P_BAR4_SNOOP BIT(6)
214 #define NTB_CTL_P2S_BAR4_SNOOP BIT(8)
215 #define NTB_CTL_S2P_BAR5_SNOOP BIT(12)
216 #define NTB_CTL_P2S_BAR5_SNOOP BIT(14)
218 #define NTB_LNK_STA_ACTIVE_BIT 0x2000
219 #define NTB_LNK_STA_SPEED_MASK 0x000f
220 #define NTB_LNK_STA_WIDTH_MASK 0x03f0
221 #define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
222 #define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
223 #define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
225 /* Use the following addresses for translation between b2b ntb devices in case
226 * the hardware default values are not reliable. */
227 #define SNB_B2B_BAR0_USD_ADDR 0x1000000000000000ull
228 #define SNB_B2B_BAR2_USD_ADDR64 0x2000000000000000ull
229 #define SNB_B2B_BAR4_USD_ADDR64 0x4000000000000000ull
230 #define SNB_B2B_BAR4_USD_ADDR32 0x20000000u
231 #define SNB_B2B_BAR5_USD_ADDR32 0x40000000u
232 #define SNB_B2B_BAR0_DSD_ADDR 0x9000000000000000ull
233 #define SNB_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull
234 #define SNB_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull
235 #define SNB_B2B_BAR4_DSD_ADDR32 0xa0000000u
236 #define SNB_B2B_BAR5_DSD_ADDR32 0xc0000000u
238 /* The peer ntb secondary config space is 32KB fixed size */
239 #define SNB_B2B_MIN_SIZE 0x8000
241 /* flags to indicate hardware errata */
242 #define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
243 #define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1)
244 #define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
246 /* flags to indicate unsafe api */
247 #define NTB_UNSAFE_DB BIT_ULL(0)
248 #define NTB_UNSAFE_SPAD BIT_ULL(1)
250 struct intel_ntb_dev;
252 struct intel_ntb_reg {
253 int (*poll_link)(struct intel_ntb_dev *ndev);
254 int (*link_is_up)(struct intel_ntb_dev *ndev);
255 u64 (*db_ioread)(void __iomem *mmio);
256 void (*db_iowrite)(u64 db_bits, void __iomem *mmio);
257 unsigned long ntb_ctl;
258 resource_size_t db_size;
262 struct intel_ntb_alt_reg {
263 unsigned long db_bell;
264 unsigned long db_mask;
268 struct intel_ntb_xlat_reg {
269 unsigned long bar0_base;
270 unsigned long bar2_xlat;
271 unsigned long bar2_limit;
274 struct intel_b2b_addr {
275 phys_addr_t bar0_addr;
276 phys_addr_t bar2_addr64;
277 phys_addr_t bar4_addr64;
278 phys_addr_t bar4_addr32;
279 phys_addr_t bar5_addr32;
282 struct intel_ntb_vec {
283 struct intel_ntb_dev *ndev;
287 struct intel_ntb_dev {
290 /* offset of peer bar0 in b2b bar */
291 unsigned long b2b_off;
292 /* mw idx used to access peer bar0 */
293 unsigned int b2b_idx;
295 /* BAR45 is split into BAR4 and BAR5 */
301 unsigned char mw_count;
302 unsigned char spad_count;
303 unsigned char db_count;
304 unsigned char db_vec_count;
305 unsigned char db_vec_shift;
311 /* synchronize rmw access of db_mask and hw reg */
312 spinlock_t db_mask_lock;
314 struct msix_entry *msix;
315 struct intel_ntb_vec *vec;
317 const struct intel_ntb_reg *reg;
318 const struct intel_ntb_alt_reg *self_reg;
319 const struct intel_ntb_alt_reg *peer_reg;
320 const struct intel_ntb_xlat_reg *xlat_reg;
321 void __iomem *self_mmio;
322 void __iomem *peer_mmio;
323 phys_addr_t peer_addr;
325 unsigned long last_ts;
326 struct delayed_work hb_timer;
328 unsigned long hwerr_flags;
329 unsigned long unsafe_flags;
330 unsigned long unsafe_flags_ignore;
332 struct dentry *debugfs_dir;
333 struct dentry *debugfs_info;
336 #define ndev_pdev(ndev) ((ndev)->ntb.pdev)
337 #define ndev_name(ndev) pci_name(ndev_pdev(ndev))
338 #define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
339 #define ntb_ndev(ntb) container_of(ntb, struct intel_ntb_dev, ntb)
340 #define hb_ndev(work) container_of(work, struct intel_ntb_dev, hb_timer.work)