2 * This file is part of wl1271
4 * Copyright (C) 2008-2009 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/gpio.h>
25 #include <linux/slab.h>
27 #include "wl1271_acx.h"
28 #include "wl1271_reg.h"
29 #include "wl1271_boot.h"
30 #include "wl1271_spi.h"
31 #include "wl1271_io.h"
32 #include "wl1271_event.h"
34 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
41 .start = REGISTERS_BASE,
60 .start = REGISTERS_BASE,
93 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
97 /* 10.5.0 run the firmware (I) */
98 cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
100 /* 10.5.1 run the firmware (II) */
102 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
105 static void wl1271_boot_fw_version(struct wl1271 *wl)
107 struct wl1271_static_data static_data;
109 wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
112 strncpy(wl->chip.fw_ver, static_data.fw_version,
113 sizeof(wl->chip.fw_ver));
115 /* make sure the string is NULL-terminated */
116 wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
119 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
120 size_t fw_data_len, u32 dest)
122 struct wl1271_partition_set partition;
123 int addr, chunk_num, partition_limit;
126 /* whal_FwCtrl_LoadFwImageSm() */
128 wl1271_debug(DEBUG_BOOT, "starting firmware upload");
130 wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
131 fw_data_len, CHUNK_SIZE);
133 if ((fw_data_len % 4) != 0) {
134 wl1271_error("firmware length not multiple of four");
138 chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
140 wl1271_error("allocation for firmware upload chunk failed");
144 memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
145 partition.mem.start = dest;
146 wl1271_set_partition(wl, &partition);
148 /* 10.1 set partition limit and chunk num */
150 partition_limit = part_table[PART_DOWN].mem.size;
152 while (chunk_num < fw_data_len / CHUNK_SIZE) {
153 /* 10.2 update partition, if needed */
154 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
155 if (addr > partition_limit) {
156 addr = dest + chunk_num * CHUNK_SIZE;
157 partition_limit = chunk_num * CHUNK_SIZE +
158 part_table[PART_DOWN].mem.size;
159 partition.mem.start = addr;
160 wl1271_set_partition(wl, &partition);
163 /* 10.3 upload the chunk */
164 addr = dest + chunk_num * CHUNK_SIZE;
165 p = buf + chunk_num * CHUNK_SIZE;
166 memcpy(chunk, p, CHUNK_SIZE);
167 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
169 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
174 /* 10.4 upload the last chunk */
175 addr = dest + chunk_num * CHUNK_SIZE;
176 p = buf + chunk_num * CHUNK_SIZE;
177 memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
178 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
179 fw_data_len % CHUNK_SIZE, p, addr);
180 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
186 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
188 u32 chunks, addr, len;
193 chunks = be32_to_cpup((__be32 *) fw);
196 wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
199 addr = be32_to_cpup((__be32 *) fw);
201 len = be32_to_cpup((__be32 *) fw);
205 wl1271_info("firmware chunk too long: %u", len);
208 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
210 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
219 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
221 size_t nvs_len, burst_len;
224 u8 *nvs_ptr, *nvs_aligned;
229 /* only the first part of the NVS needs to be uploaded */
230 nvs_len = sizeof(wl->nvs->nvs);
231 nvs_ptr = (u8 *)wl->nvs->nvs;
234 * Layout before the actual NVS tables:
235 * 1 byte : burst length.
236 * 2 bytes: destination address.
237 * n bytes: data to burst copy.
239 * This is ended by a 0 length, then the NVS tables.
242 /* FIXME: Do we need to check here whether the LSB is 1? */
244 burst_len = nvs_ptr[0];
245 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
247 /* FIXME: Due to our new wl1271_translate_reg_addr function,
248 we need to add the REGISTER_BASE to the destination */
249 dest_addr += REGISTERS_BASE;
251 /* We move our pointer to the data */
254 for (i = 0; i < burst_len; i++) {
255 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
256 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
258 wl1271_debug(DEBUG_BOOT,
259 "nvs burst write 0x%x: 0x%x",
261 wl1271_write32(wl, dest_addr, val);
269 * We've reached the first zero length, the first NVS table
270 * is 7 bytes further.
273 nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
274 nvs_len = ALIGN(nvs_len, 4);
276 /* FIXME: The driver sets the partition here, but this is not needed,
277 since it sets to the same one as currently in use */
278 /* Now we must set the partition correctly */
279 wl1271_set_partition(wl, &part_table[PART_WORK]);
281 /* Copy the NVS tables to a new block to ensure alignment */
282 /* FIXME: We jump 3 more bytes before uploading the NVS. It seems
283 that our NVS files have three extra zeros here. I'm not sure whether
284 the problem is in our NVS generation or we should really jumpt these
288 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL); if
289 (!nvs_aligned) return -ENOMEM;
291 /* And finally we upload the NVS tables */
292 /* FIXME: In wl1271, we upload everything at once.
293 No endianness handling needed here?! The ref driver doesn't do
294 anything about it at this point */
295 wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
301 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
304 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
305 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
306 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
309 static int wl1271_boot_soft_reset(struct wl1271 *wl)
311 unsigned long timeout;
314 /* perform soft reset */
315 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
317 /* SOFT_RESET is self clearing */
318 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
320 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
321 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
322 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
325 if (time_after(jiffies, timeout)) {
326 /* 1.2 check pWhalBus->uSelfClearTime if the
327 * timeout was reached */
328 wl1271_error("soft reset timeout");
332 udelay(SOFT_RESET_STALL_TIME);
336 wl1271_write32(wl, ENABLE, 0x0);
338 /* disable auto calibration on start*/
339 wl1271_write32(wl, SPARE_A2, 0xffff);
344 static int wl1271_boot_run_firmware(struct wl1271 *wl)
347 u32 chip_id, interrupt;
349 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
351 chip_id = wl1271_read32(wl, CHIP_ID_B);
353 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
355 if (chip_id != wl->chip.id) {
356 wl1271_error("chip id doesn't match after firmware boot");
360 /* wait for init to complete */
362 while (loop++ < INIT_LOOP) {
363 udelay(INIT_LOOP_DELAY);
364 interrupt = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
366 if (interrupt == 0xffffffff) {
367 wl1271_error("error reading hardware complete "
371 /* check that ACX_INTR_INIT_COMPLETE is enabled */
372 else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
373 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
374 WL1271_ACX_INTR_INIT_COMPLETE);
379 if (loop > INIT_LOOP) {
380 wl1271_error("timeout waiting for the hardware to "
381 "complete initialization");
385 /* get hardware config command mail box */
386 wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
388 /* get hardware config event mail box */
389 wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
391 /* set the working partition to its "running" mode offset */
392 wl1271_set_partition(wl, &part_table[PART_WORK]);
394 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
395 wl->cmd_box_addr, wl->event_box_addr);
397 wl1271_boot_fw_version(wl);
400 * in case of full asynchronous mode the firmware event must be
401 * ready to receive event from the command mailbox
404 /* unmask required mbox events */
405 wl->event_mask = BSS_LOSE_EVENT_ID |
406 SCAN_COMPLETE_EVENT_ID |
409 ret = wl1271_event_unmask(wl);
411 wl1271_error("EVENT mask setting failed");
415 wl1271_event_mbox_config(wl);
417 /* firmware startup completed */
421 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
425 polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
427 /* We use HIGH polarity, so unset the LOW bit */
428 polarity &= ~POLARITY_LOW;
429 wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
434 int wl1271_boot(struct wl1271 *wl)
439 if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4)
440 /* ref clk: 19.2/38.4/38.4-XTAL */
442 else if (REF_CLOCK == 1 || REF_CLOCK == 3)
446 if (REF_CLOCK != 0) {
449 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
450 val &= FREF_CLK_TYPE_BITS;
452 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
455 /* Set clock polarity */
456 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
457 val &= FREF_CLK_POLARITY_BITS;
458 val |= CLK_REQ_OUTN_SEL;
459 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
462 wl1271_write32(wl, PLL_PARAMETERS, clk);
464 pause = wl1271_read32(wl, PLL_PARAMETERS);
466 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
468 pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
469 * WU_COUNTER_PAUSE_VAL instead of
470 * 0x3ff (magic number ). How does
472 pause |= WU_COUNTER_PAUSE_VAL;
473 wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
475 /* Continue the ELP wake up sequence */
476 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
479 wl1271_set_partition(wl, &part_table[PART_DRPW]);
481 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
482 to be used by DRPw FW. The RTRIM value will be added by the FW
483 before taking DRPw out of reset */
485 wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
486 clk = wl1271_read32(wl, DRPW_SCRATCH_START);
488 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
491 clk |= (REF_CLOCK << 1) << 4;
492 wl1271_write32(wl, DRPW_SCRATCH_START, clk);
494 wl1271_set_partition(wl, &part_table[PART_WORK]);
496 /* Disable interrupts */
497 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
499 ret = wl1271_boot_soft_reset(wl);
503 /* 2. start processing NVS file */
504 ret = wl1271_boot_upload_nvs(wl);
508 /* write firmware's last address (ie. it's length) to
509 * ACX_EEPROMLESS_IND_REG */
510 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
512 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
514 tmp = wl1271_read32(wl, CHIP_ID_B);
516 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
518 /* 6. read the EEPROM parameters */
519 tmp = wl1271_read32(wl, SCR_PAD2);
521 ret = wl1271_boot_write_irq_polarity(wl);
525 /* FIXME: Need to check whether this is really what we want */
526 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
527 WL1271_ACX_ALL_EVENTS_VECTOR);
529 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
532 ret = wl1271_boot_upload_firmware(wl);
536 /* 10.5 start firmware */
537 ret = wl1271_boot_run_firmware(wl);
541 /* Enable firmware interrupts now */
542 wl1271_boot_enable_interrupts(wl);
544 /* set the wl1271 default filters */
545 wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
546 wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
548 wl1271_event_mbox_config(wl);