drivers/net/wireless/wl12xx/boot.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/slab.h>
  25 #include <linux/wl12xx.h>
  26 #include <linux/export.h>
  27
  28 #include "debug.h"
  29 #include "acx.h"
  30 #include "reg.h"
  31 #include "boot.h"
  32 #include "io.h"
  33 #include "event.h"
  34 #include "rx.h"
  35
  36 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
  37 {
  38         u32 cpu_ctrl;
  39
  40         /* 10.5.0 run the firmware (I) */
  41         cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
  42
  43         /* 10.5.1 run the firmware (II) */
  44         cpu_ctrl |= flag;
  45         wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
  46 }
  47
  48 static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271 *wl)
  49 {
  50         unsigned int quirks = 0;
  51         unsigned int *fw_ver = wl->chip.fw_ver;
  52
  53         /* Only new station firmwares support routing fw logs to the host */
  54         if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
  55             (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
  56                 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED;
  57
  58         /* This feature is not yet supported for AP mode */
  59         if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
  60                 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED;
  61
  62         return quirks;
  63 }
  64
  65 static void wl1271_parse_fw_ver(struct wl1271 *wl)
  66 {
  67         int ret;
  68
  69         ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
  70                      &wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
  71                      &wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
  72                      &wl->chip.fw_ver[4]);
  73
  74         if (ret != 5) {
  75                 wl1271_warning("fw version incorrect value");
  76                 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
  77                 return;
  78         }
  79
  80         /* Check if any quirks are needed with older fw versions */
  81         wl->quirks |= wl12xx_get_fw_ver_quirks(wl);
  82 }
  83
  84 static void wl1271_boot_fw_version(struct wl1271 *wl)
  85 {
  86         struct wl1271_static_data *static_data;
  87
  88         static_data = kmalloc(sizeof(*static_data), GFP_DMA);
  89         if (!static_data) {
  90                 __WARN();
  91                 return;
  92         }
  93
  94         wl1271_read(wl, wl->cmd_box_addr, static_data, sizeof(*static_data),
  95                     false);
  96
  97         strncpy(wl->chip.fw_ver_str, static_data->fw_version,
  98                 sizeof(wl->chip.fw_ver_str));
  99
 100         kfree(static_data);
 101
 102         /* make sure the string is NULL-terminated */
 103         wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';
 104
 105         wl1271_parse_fw_ver(wl);
 106 }
 107
 108 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
 109                                              size_t fw_data_len, u32 dest)
 110 {
 111         struct wl1271_partition_set partition;
 112         int addr, chunk_num, partition_limit;
 113         u8 *p, *chunk;
 114
 115         /* whal_FwCtrl_LoadFwImageSm() */
 116
 117         wl1271_debug(DEBUG_BOOT, "starting firmware upload");
 118
 119         wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
 120                      fw_data_len, CHUNK_SIZE);
 121
 122         if ((fw_data_len % 4) != 0) {
 123                 wl1271_error("firmware length not multiple of four");
 124                 return -EIO;
 125         }
 126
 127         chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
 128         if (!chunk) {
 129                 wl1271_error("allocation for firmware upload chunk failed");
 130                 return -ENOMEM;
 131         }
 132
 133         memcpy(&partition, &wl12xx_part_table[PART_DOWN], sizeof(partition));
 134         partition.mem.start = dest;
 135         wl1271_set_partition(wl, &partition);
 136
 137         /* 10.1 set partition limit and chunk num */
 138         chunk_num = 0;
 139         partition_limit = wl12xx_part_table[PART_DOWN].mem.size;
 140
 141         while (chunk_num < fw_data_len / CHUNK_SIZE) {
 142                 /* 10.2 update partition, if needed */
 143                 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
 144                 if (addr > partition_limit) {
 145                         addr = dest + chunk_num * CHUNK_SIZE;
 146                         partition_limit = chunk_num * CHUNK_SIZE +
 147                                 wl12xx_part_table[PART_DOWN].mem.size;
 148                         partition.mem.start = addr;
 149                         wl1271_set_partition(wl, &partition);
 150                 }
 151
 152                 /* 10.3 upload the chunk */
 153                 addr = dest + chunk_num * CHUNK_SIZE;
 154                 p = buf + chunk_num * CHUNK_SIZE;
 155                 memcpy(chunk, p, CHUNK_SIZE);
 156                 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
 157                              p, addr);
 158                 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
 159
 160                 chunk_num++;
 161         }
 162
 163         /* 10.4 upload the last chunk */
 164         addr = dest + chunk_num * CHUNK_SIZE;
 165         p = buf + chunk_num * CHUNK_SIZE;
 166         memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
 167         wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
 168                      fw_data_len % CHUNK_SIZE, p, addr);
 169         wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
 170
 171         kfree(chunk);
 172         return 0;
 173 }
 174
 175 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
 176 {
 177         u32 chunks, addr, len;
 178         int ret = 0;
 179         u8 *fw;
 180
 181         fw = wl->fw;
 182         chunks = be32_to_cpup((__be32 *) fw);
 183         fw += sizeof(u32);
 184
 185         wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
 186
 187         while (chunks--) {
 188                 addr = be32_to_cpup((__be32 *) fw);
 189                 fw += sizeof(u32);
 190                 len = be32_to_cpup((__be32 *) fw);
 191                 fw += sizeof(u32);
 192
 193                 if (len > 300000) {
 194                         wl1271_info("firmware chunk too long: %u", len);
 195                         return -EINVAL;
 196                 }
 197                 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
 198                              chunks, addr, len);
 199                 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
 200                 if (ret != 0)
 201                         break;
 202                 fw += len;
 203         }
 204
 205         return ret;
 206 }
 207
 208 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
 209 {
 210         size_t nvs_len, burst_len;
 211         int i;
 212         u32 dest_addr, val;
 213         u8 *nvs_ptr, *nvs_aligned;
 214
 215         if (wl->nvs == NULL)
 216                 return -ENODEV;
 217
 218         if (wl->chip.id == CHIP_ID_1283_PG20) {
 219                 struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs;
 220
 221                 if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) {
 222                         if (nvs->general_params.dual_mode_select)
 223                                 wl->enable_11a = true;
 224                 } else {
 225                         wl1271_error("nvs size is not as expected: %zu != %zu",
 226                                      wl->nvs_len,
 227                                      sizeof(struct wl128x_nvs_file));
 228                         kfree(wl->nvs);
 229                         wl->nvs = NULL;
 230                         wl->nvs_len = 0;
 231                         return -EILSEQ;
 232                 }
 233
 234                 /* only the first part of the NVS needs to be uploaded */
 235                 nvs_len = sizeof(nvs->nvs);
 236                 nvs_ptr = (u8 *)nvs->nvs;
 237
 238         } else {
 239                 struct wl1271_nvs_file *nvs =
 240                         (struct wl1271_nvs_file *)wl->nvs;
 241                 /*
 242                  * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
 243                  * band configurations) can be removed when those NVS files stop
 244                  * floating around.
 245                  */
 246                 if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
 247                     wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
 248                         if (nvs->general_params.dual_mode_select)
 249                                 wl->enable_11a = true;
 250                 }
 251
 252                 if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
 253                     (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
 254                      wl->enable_11a)) {
 255                         wl1271_error("nvs size is not as expected: %zu != %zu",
 256                                 wl->nvs_len, sizeof(struct wl1271_nvs_file));
 257                         kfree(wl->nvs);
 258                         wl->nvs = NULL;
 259                         wl->nvs_len = 0;
 260                         return -EILSEQ;
 261                 }
 262
 263                 /* only the first part of the NVS needs to be uploaded */
 264                 nvs_len = sizeof(nvs->nvs);
 265                 nvs_ptr = (u8 *) nvs->nvs;
 266         }
 267
 268         /* update current MAC address to NVS */
 269         nvs_ptr[11] = wl->addresses[0].addr[0];
 270         nvs_ptr[10] = wl->addresses[0].addr[1];
 271         nvs_ptr[6] = wl->addresses[0].addr[2];
 272         nvs_ptr[5] = wl->addresses[0].addr[3];
 273         nvs_ptr[4] = wl->addresses[0].addr[4];
 274         nvs_ptr[3] = wl->addresses[0].addr[5];
 275
 276         /*
 277          * Layout before the actual NVS tables:
 278          * 1 byte : burst length.
 279          * 2 bytes: destination address.
 280          * n bytes: data to burst copy.
 281          *
 282          * This is ended by a 0 length, then the NVS tables.
 283          */
 284
 285         /* FIXME: Do we need to check here whether the LSB is 1? */
 286         while (nvs_ptr[0]) {
 287                 burst_len = nvs_ptr[0];
 288                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
 289
 290                 /*
 291                  * Due to our new wl1271_translate_reg_addr function,
 292                  * we need to add the REGISTER_BASE to the destination
 293                  */
 294                 dest_addr += REGISTERS_BASE;
 295
 296                 /* We move our pointer to the data */
 297                 nvs_ptr += 3;
 298
 299                 for (i = 0; i < burst_len; i++) {
 300                         if (nvs_ptr + 3 >= (u8 *) wl->nvs + nvs_len)
 301                                 goto out_badnvs;
 302
 303                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 304                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 305
 306                         wl1271_debug(DEBUG_BOOT,
 307                                      "nvs burst write 0x%x: 0x%x",
 308                                      dest_addr, val);
 309                         wl1271_write32(wl, dest_addr, val);
 310
 311                         nvs_ptr += 4;
 312                         dest_addr += 4;
 313                 }
 314
 315                 if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
 316                         goto out_badnvs;
 317         }
 318
 319         /*
 320          * We've reached the first zero length, the first NVS table
 321          * is located at an aligned offset which is at least 7 bytes further.
 322          * NOTE: The wl->nvs->nvs element must be first, in order to
 323          * simplify the casting, we assume it is at the beginning of
 324          * the wl->nvs structure.
 325          */
 326         nvs_ptr = (u8 *)wl->nvs +
 327                         ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4);
 328
 329         if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
 330                 goto out_badnvs;
 331
 332         nvs_len -= nvs_ptr - (u8 *)wl->nvs;
 333
 334         /* Now we must set the partition correctly */
 335         wl1271_set_partition(wl, &wl12xx_part_table[PART_WORK]);
 336
 337         /* Copy the NVS tables to a new block to ensure alignment */
 338         nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
 339         if (!nvs_aligned)
 340                 return -ENOMEM;
 341
 342         /* And finally we upload the NVS tables */
 343         wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
 344
 345         kfree(nvs_aligned);
 346         return 0;
 347
 348 out_badnvs:
 349         wl1271_error("nvs data is malformed");
 350         return -EILSEQ;
 351 }
 352
 353 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
 354 {
 355         wl1271_enable_interrupts(wl);
 356         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 357                        WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 358         wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
 359 }
 360
 361 static int wl1271_boot_soft_reset(struct wl1271 *wl)
 362 {
 363         unsigned long timeout;
 364         u32 boot_data;
 365
 366         /* perform soft reset */
 367         wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
 368
 369         /* SOFT_RESET is self clearing */
 370         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
 371         while (1) {
 372                 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
 373                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
 374                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
 375                         break;
 376
 377                 if (time_after(jiffies, timeout)) {
 378                         /* 1.2 check pWhalBus->uSelfClearTime if the
 379                          * timeout was reached */
 380                         wl1271_error("soft reset timeout");
 381                         return -1;
 382                 }
 383
 384                 udelay(SOFT_RESET_STALL_TIME);
 385         }
 386
 387         /* disable Rx/Tx */
 388         wl1271_write32(wl, ENABLE, 0x0);
 389
 390         /* disable auto calibration on start*/
 391         wl1271_write32(wl, SPARE_A2, 0xffff);
 392
 393         return 0;
 394 }
 395
 396 static int wl1271_boot_run_firmware(struct wl1271 *wl)
 397 {
 398         int loop, ret;
 399         u32 chip_id, intr;
 400
 401         wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
 402
 403         chip_id = wl1271_read32(wl, CHIP_ID_B);
 404
 405         wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
 406
 407         if (chip_id != wl->chip.id) {
 408                 wl1271_error("chip id doesn't match after firmware boot");
 409                 return -EIO;
 410         }
 411
 412         /* wait for init to complete */
 413         loop = 0;
 414         while (loop++ < INIT_LOOP) {
 415                 udelay(INIT_LOOP_DELAY);
 416                 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
 417
 418                 if (intr == 0xffffffff) {
 419                         wl1271_error("error reading hardware complete "
 420                                      "init indication");
 421                         return -EIO;
 422                 }
 423                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
 424                 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
 425                         wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
 426                                        WL1271_ACX_INTR_INIT_COMPLETE);
 427                         break;
 428                 }
 429         }
 430
 431         if (loop > INIT_LOOP) {
 432                 wl1271_error("timeout waiting for the hardware to "
 433                              "complete initialization");
 434                 return -EIO;
 435         }
 436
 437         /* get hardware config command mail box */
 438         wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
 439
 440         /* get hardware config event mail box */
 441         wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
 442
 443         /* set the working partition to its "running" mode offset */
 444         wl1271_set_partition(wl, &wl12xx_part_table[PART_WORK]);
 445
 446         wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
 447                      wl->cmd_box_addr, wl->event_box_addr);
 448
 449         wl1271_boot_fw_version(wl);
 450
 451         /*
 452          * in case of full asynchronous mode the firmware event must be
 453          * ready to receive event from the command mailbox
 454          */
 455
 456         /* unmask required mbox events  */
 457         wl->event_mask = BSS_LOSE_EVENT_ID |
 458                 SCAN_COMPLETE_EVENT_ID |
 459                 ROLE_STOP_COMPLETE_EVENT_ID |
 460                 RSSI_SNR_TRIGGER_0_EVENT_ID |
 461                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
 462                 SOFT_GEMINI_SENSE_EVENT_ID |
 463                 PERIODIC_SCAN_REPORT_EVENT_ID |
 464                 PERIODIC_SCAN_COMPLETE_EVENT_ID |
 465                 DUMMY_PACKET_EVENT_ID |
 466                 PEER_REMOVE_COMPLETE_EVENT_ID |
 467                 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
 468                 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
 469                 INACTIVE_STA_EVENT_ID |
 470                 MAX_TX_RETRY_EVENT_ID |
 471                 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
 472
 473         ret = wl1271_event_unmask(wl);
 474         if (ret < 0) {
 475                 wl1271_error("EVENT mask setting failed");
 476                 return ret;
 477         }
 478
 479         wl1271_event_mbox_config(wl);
 480
 481         /* firmware startup completed */
 482         return 0;
 483 }
 484
 485 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
 486 {
 487         u32 polarity;
 488
 489         polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
 490
 491         /* We use HIGH polarity, so unset the LOW bit */
 492         polarity &= ~POLARITY_LOW;
 493         wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
 494
 495         return 0;
 496 }
 497
 498 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
 499 {
 500         u16 spare_reg;
 501
 502         /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
 503         spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG);
 504         if (spare_reg == 0xFFFF)
 505                 return -EFAULT;
 506         spare_reg |= (BIT(3) | BIT(5) | BIT(6));
 507         wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 508
 509         /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
 510         wl1271_top_reg_write(wl, SYS_CLK_CFG_REG,
 511                              WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 512
 513         /* Delay execution for 15msec, to let the HW settle */
 514         mdelay(15);
 515
 516         return 0;
 517 }
 518
 519 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
 520 {
 521         u16 tcxo_detection;
 522
 523         tcxo_detection = wl1271_top_reg_read(wl, TCXO_CLK_DETECT_REG);
 524         if (tcxo_detection & TCXO_DET_FAILED)
 525                 return false;
 526
 527         return true;
 528 }
 529
 530 static bool wl128x_is_fref_valid(struct wl1271 *wl)
 531 {
 532         u16 fref_detection;
 533
 534         fref_detection = wl1271_top_reg_read(wl, FREF_CLK_DETECT_REG);
 535         if (fref_detection & FREF_CLK_DETECT_FAIL)
 536                 return false;
 537
 538         return true;
 539 }
 540
 541 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
 542 {
 543         wl1271_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 544         wl1271_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 545         wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, MCS_PLL_CONFIG_REG_VAL);
 546
 547         return 0;
 548 }
 549
 550 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
 551 {
 552         u16 spare_reg;
 553         u16 pll_config;
 554         u8 input_freq;
 555
 556         /* Mask bits [3:1] in the sys_clk_cfg register */
 557         spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG);
 558         if (spare_reg == 0xFFFF)
 559                 return -EFAULT;
 560         spare_reg |= BIT(2);
 561         wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 562
 563         /* Handle special cases of the TCXO clock */
 564         if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
 565             wl->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
 566                 return wl128x_manually_configure_mcs_pll(wl);
 567
 568         /* Set the input frequency according to the selected clock source */
 569         input_freq = (clk & 1) + 1;
 570
 571         pll_config = wl1271_top_reg_read(wl, MCS_PLL_CONFIG_REG);
 572         if (pll_config == 0xFFFF)
 573                 return -EFAULT;
 574         pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
 575         pll_config |= MCS_PLL_ENABLE_HP;
 576         wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
 577
 578         return 0;
 579 }
 580
 581 /*
 582  * WL128x has two clocks input - TCXO and FREF.
 583  * TCXO is the main clock of the device, while FREF is used to sync
 584  * between the GPS and the cellular modem.
 585  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 586  * as the WLAN/BT main clock.
 587  */
 588 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
 589 {
 590         u16 sys_clk_cfg;
 591
 592         /* For XTAL-only modes, FREF will be used after switching from TCXO */
 593         if (wl->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
 594             wl->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
 595                 if (!wl128x_switch_tcxo_to_fref(wl))
 596                         return -EINVAL;
 597                 goto fref_clk;
 598         }
 599
 600         /* Query the HW, to determine which clock source we should use */
 601         sys_clk_cfg = wl1271_top_reg_read(wl, SYS_CLK_CFG_REG);
 602         if (sys_clk_cfg == 0xFFFF)
 603                 return -EINVAL;
 604         if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
 605                 goto fref_clk;
 606
 607         /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
 608         if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
 609             wl->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
 610                 if (!wl128x_switch_tcxo_to_fref(wl))
 611                         return -EINVAL;
 612                 goto fref_clk;
 613         }
 614
 615         /* TCXO clock is selected */
 616         if (!wl128x_is_tcxo_valid(wl))
 617                 return -EINVAL;
 618         *selected_clock = wl->tcxo_clock;
 619         goto config_mcs_pll;
 620
 621 fref_clk:
 622         /* FREF clock is selected */
 623         if (!wl128x_is_fref_valid(wl))
 624                 return -EINVAL;
 625         *selected_clock = wl->ref_clock;
 626
 627 config_mcs_pll:
 628         return wl128x_configure_mcs_pll(wl, *selected_clock);
 629 }
 630
 631 static int wl127x_boot_clk(struct wl1271 *wl)
 632 {
 633         u32 pause;
 634         u32 clk;
 635
 636         if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
 637                 wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION;
 638
 639         if (wl->ref_clock == CONF_REF_CLK_19_2_E ||
 640             wl->ref_clock == CONF_REF_CLK_38_4_E ||
 641             wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 642                 /* ref clk: 19.2/38.4/38.4-XTAL */
 643                 clk = 0x3;
 644         else if (wl->ref_clock == CONF_REF_CLK_26_E ||
 645                  wl->ref_clock == CONF_REF_CLK_52_E)
 646                 /* ref clk: 26/52 */
 647                 clk = 0x5;
 648         else
 649                 return -EINVAL;
 650
 651         if (wl->ref_clock != CONF_REF_CLK_19_2_E) {
 652                 u16 val;
 653                 /* Set clock type (open drain) */
 654                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
 655                 val &= FREF_CLK_TYPE_BITS;
 656                 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
 657
 658                 /* Set clock pull mode (no pull) */
 659                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
 660                 val |= NO_PULL;
 661                 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
 662         } else {
 663                 u16 val;
 664                 /* Set clock polarity */
 665                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
 666                 val &= FREF_CLK_POLARITY_BITS;
 667                 val |= CLK_REQ_OUTN_SEL;
 668                 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
 669         }
 670
 671         wl1271_write32(wl, PLL_PARAMETERS, clk);
 672
 673         pause = wl1271_read32(wl, PLL_PARAMETERS);
 674
 675         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
 676
 677         pause &= ~(WU_COUNTER_PAUSE_VAL);
 678         pause |= WU_COUNTER_PAUSE_VAL;
 679         wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
 680
 681         return 0;
 682 }
 683
 684 /* uploads NVS and firmware */
 685 int wl1271_load_firmware(struct wl1271 *wl)
 686 {
 687         int ret = 0;
 688         u32 tmp, clk;
 689         int selected_clock = -1;
 690
 691         if (wl->chip.id == CHIP_ID_1283_PG20) {
 692                 ret = wl128x_boot_clk(wl, &selected_clock);
 693                 if (ret < 0)
 694                         goto out;
 695         } else {
 696                 ret = wl127x_boot_clk(wl);
 697                 if (ret < 0)
 698                         goto out;
 699         }
 700
 701         /* Continue the ELP wake up sequence */
 702         wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 703         udelay(500);
 704
 705         wl1271_set_partition(wl, &wl12xx_part_table[PART_DRPW]);
 706
 707         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
 708            to be used by DRPw FW. The RTRIM value will be added by the FW
 709            before taking DRPw out of reset */
 710
 711         wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
 712         clk = wl1271_read32(wl, DRPW_SCRATCH_START);
 713
 714         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
 715
 716         if (wl->chip.id == CHIP_ID_1283_PG20) {
 717                 clk |= ((selected_clock & 0x3) << 1) << 4;
 718         } else {
 719                 clk |= (wl->ref_clock << 1) << 4;
 720         }
 721
 722         wl1271_write32(wl, DRPW_SCRATCH_START, clk);
 723
 724         wl1271_set_partition(wl, &wl12xx_part_table[PART_WORK]);
 725
 726         /* Disable interrupts */
 727         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 728
 729         ret = wl1271_boot_soft_reset(wl);
 730         if (ret < 0)
 731                 goto out;
 732
 733         /* 2. start processing NVS file */
 734         ret = wl1271_boot_upload_nvs(wl);
 735         if (ret < 0)
 736                 goto out;
 737
 738         /* write firmware's last address (ie. it's length) to
 739          * ACX_EEPROMLESS_IND_REG */
 740         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
 741
 742         wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
 743
 744         tmp = wl1271_read32(wl, CHIP_ID_B);
 745
 746         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 747
 748         /* 6. read the EEPROM parameters */
 749         tmp = wl1271_read32(wl, SCR_PAD2);
 750
 751         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
 752          * to upload_fw) */
 753
 754         if (wl->chip.id == CHIP_ID_1283_PG20)
 755                 wl1271_top_reg_write(wl, SDIO_IO_DS, wl->conf.hci_io_ds);
 756
 757         ret = wl1271_boot_upload_firmware(wl);
 758         if (ret < 0)
 759                 goto out;
 760
 761 out:
 762         return ret;
 763 }
 764 EXPORT_SYMBOL_GPL(wl1271_load_firmware);
 765
 766 int wl1271_boot(struct wl1271 *wl)
 767 {
 768         int ret;
 769
 770         /* upload NVS and firmware */
 771         ret = wl1271_load_firmware(wl);
 772         if (ret)
 773                 return ret;
 774
 775         /* 10.5 start firmware */
 776         ret = wl1271_boot_run_firmware(wl);
 777         if (ret < 0)
 778                 goto out;
 779
 780         ret = wl1271_boot_write_irq_polarity(wl);
 781         if (ret < 0)
 782                 goto out;
 783
 784         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 785                        WL1271_ACX_ALL_EVENTS_VECTOR);
 786
 787         /* Enable firmware interrupts now */
 788         wl1271_boot_enable_interrupts(wl);
 789
 790         wl1271_event_mbox_config(wl);
 791
 792 out:
 793         return ret;
 794 }