drivers/net/wireless/ti/wl18xx/main.c

   1 /*
   2  * This file is part of wl18xx
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ip.h>
  25 #include <linux/firmware.h>
  26
  27 #include "../wlcore/wlcore.h"
  28 #include "../wlcore/debug.h"
  29 #include "../wlcore/io.h"
  30 #include "../wlcore/acx.h"
  31 #include "../wlcore/tx.h"
  32 #include "../wlcore/rx.h"
  33 #include "../wlcore/io.h"
  34 #include "../wlcore/boot.h"
  35
  36 #include "reg.h"
  37 #include "conf.h"
  38 #include "acx.h"
  39 #include "tx.h"
  40 #include "wl18xx.h"
  41 #include "io.h"
  42 #include "debugfs.h"
  43
  44 #define WL18XX_RX_CHECKSUM_MASK      0x40
  45
  46 static char *ht_mode_param = "default";
  47 static char *board_type_param = "hdk";
  48 static bool checksum_param = false;
  49 static bool enable_11a_param = true;
  50 static int num_rx_desc_param = -1;
  51
  52 /* phy paramters */
  53 static int dc2dc_param = -1;
  54 static int n_antennas_2_param = -1;
  55 static int n_antennas_5_param = -1;
  56 static int low_band_component_param = -1;
  57 static int low_band_component_type_param = -1;
  58 static int high_band_component_param = -1;
  59 static int high_band_component_type_param = -1;
  60 static int pwr_limit_reference_11_abg_param = -1;
  61
  62 static const u8 wl18xx_rate_to_idx_2ghz[] = {
  63         /* MCS rates are used only with 11n */
  64         15,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  65         14,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  66         13,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  67         12,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  68         11,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  69         10,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  70         9,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  71         8,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
  72         7,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
  73         6,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
  74         5,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
  75         4,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
  76         3,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
  77         2,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
  78         1,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
  79         0,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
  80
  81         11,                            /* WL18XX_CONF_HW_RXTX_RATE_54   */
  82         10,                            /* WL18XX_CONF_HW_RXTX_RATE_48   */
  83         9,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
  84         8,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
  85
  86         /* TI-specific rate */
  87         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
  88
  89         7,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
  90         6,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
  91         3,                             /* WL18XX_CONF_HW_RXTX_RATE_11   */
  92         5,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
  93         4,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
  94         2,                             /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
  95         1,                             /* WL18XX_CONF_HW_RXTX_RATE_2    */
  96         0                              /* WL18XX_CONF_HW_RXTX_RATE_1    */
  97 };
  98
  99 static const u8 wl18xx_rate_to_idx_5ghz[] = {
 100         /* MCS rates are used only with 11n */
 101         15,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
 102         14,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
 103         13,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
 104         12,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
 105         11,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
 106         10,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
 107         9,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
 108         8,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
 109         7,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
 110         6,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
 111         5,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
 112         4,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
 113         3,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
 114         2,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
 115         1,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
 116         0,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
 117
 118         7,                             /* WL18XX_CONF_HW_RXTX_RATE_54   */
 119         6,                             /* WL18XX_CONF_HW_RXTX_RATE_48   */
 120         5,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
 121         4,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
 122
 123         /* TI-specific rate */
 124         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
 125
 126         3,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
 127         2,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
 128         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11   */
 129         1,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
 130         0,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
 131         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
 132         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2    */
 133         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1    */
 134 };
 135
 136 static const u8 *wl18xx_band_rate_to_idx[] = {
 137         [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
 138         [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
 139 };
 140
 141 enum wl18xx_hw_rates {
 142         WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
 143         WL18XX_CONF_HW_RXTX_RATE_MCS14,
 144         WL18XX_CONF_HW_RXTX_RATE_MCS13,
 145         WL18XX_CONF_HW_RXTX_RATE_MCS12,
 146         WL18XX_CONF_HW_RXTX_RATE_MCS11,
 147         WL18XX_CONF_HW_RXTX_RATE_MCS10,
 148         WL18XX_CONF_HW_RXTX_RATE_MCS9,
 149         WL18XX_CONF_HW_RXTX_RATE_MCS8,
 150         WL18XX_CONF_HW_RXTX_RATE_MCS7,
 151         WL18XX_CONF_HW_RXTX_RATE_MCS6,
 152         WL18XX_CONF_HW_RXTX_RATE_MCS5,
 153         WL18XX_CONF_HW_RXTX_RATE_MCS4,
 154         WL18XX_CONF_HW_RXTX_RATE_MCS3,
 155         WL18XX_CONF_HW_RXTX_RATE_MCS2,
 156         WL18XX_CONF_HW_RXTX_RATE_MCS1,
 157         WL18XX_CONF_HW_RXTX_RATE_MCS0,
 158         WL18XX_CONF_HW_RXTX_RATE_54,
 159         WL18XX_CONF_HW_RXTX_RATE_48,
 160         WL18XX_CONF_HW_RXTX_RATE_36,
 161         WL18XX_CONF_HW_RXTX_RATE_24,
 162         WL18XX_CONF_HW_RXTX_RATE_22,
 163         WL18XX_CONF_HW_RXTX_RATE_18,
 164         WL18XX_CONF_HW_RXTX_RATE_12,
 165         WL18XX_CONF_HW_RXTX_RATE_11,
 166         WL18XX_CONF_HW_RXTX_RATE_9,
 167         WL18XX_CONF_HW_RXTX_RATE_6,
 168         WL18XX_CONF_HW_RXTX_RATE_5_5,
 169         WL18XX_CONF_HW_RXTX_RATE_2,
 170         WL18XX_CONF_HW_RXTX_RATE_1,
 171         WL18XX_CONF_HW_RXTX_RATE_MAX,
 172 };
 173
 174 static struct wlcore_conf wl18xx_conf = {
 175         .sg = {
 176                 .params = {
 177                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
 178                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
 179                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
 180                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
 181                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
 182                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
 183                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
 184                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
 185                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
 186                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
 187                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
 188                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
 189                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
 190                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
 191                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
 192                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
 193                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
 194                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
 195                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
 196                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
 197                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
 198                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
 199                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
 200                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
 201                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
 202                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
 203                         /* active scan params */
 204                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
 205                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
 206                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
 207                         /* passive scan params */
 208                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
 209                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
 210                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
 211                         /* passive scan in dual antenna params */
 212                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
 213                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
 214                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
 215                         /* general params */
 216                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
 217                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
 218                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
 219                         [CONF_SG_DHCP_TIME] = 5000,
 220                         [CONF_SG_RXT] = 1200,
 221                         [CONF_SG_TXT] = 1000,
 222                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
 223                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
 224                         [CONF_SG_HV3_MAX_SERVED] = 6,
 225                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
 226                         [CONF_SG_UPSD_TIMEOUT] = 10,
 227                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 228                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 229                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 230                         /* AP params */
 231                         [CONF_AP_BEACON_MISS_TX] = 3,
 232                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 233                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 234                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 235                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 236                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 237                         /* CTS Diluting params */
 238                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 239                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 240                 },
 241                 .state = CONF_SG_PROTECTIVE,
 242         },
 243         .rx = {
 244                 .rx_msdu_life_time           = 512000,
 245                 .packet_detection_threshold  = 0,
 246                 .ps_poll_timeout             = 15,
 247                 .upsd_timeout                = 15,
 248                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 249                 .rx_cca_threshold            = 0,
 250                 .irq_blk_threshold           = 0xFFFF,
 251                 .irq_pkt_threshold           = 0,
 252                 .irq_timeout                 = 600,
 253                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 254         },
 255         .tx = {
 256                 .tx_energy_detection         = 0,
 257                 .sta_rc_conf                 = {
 258                         .enabled_rates       = 0,
 259                         .short_retry_limit   = 10,
 260                         .long_retry_limit    = 10,
 261                         .aflags              = 0,
 262                 },
 263                 .ac_conf_count               = 4,
 264                 .ac_conf                     = {
 265                         [CONF_TX_AC_BE] = {
 266                                 .ac          = CONF_TX_AC_BE,
 267                                 .cw_min      = 15,
 268                                 .cw_max      = 63,
 269                                 .aifsn       = 3,
 270                                 .tx_op_limit = 0,
 271                         },
 272                         [CONF_TX_AC_BK] = {
 273                                 .ac          = CONF_TX_AC_BK,
 274                                 .cw_min      = 15,
 275                                 .cw_max      = 63,
 276                                 .aifsn       = 7,
 277                                 .tx_op_limit = 0,
 278                         },
 279                         [CONF_TX_AC_VI] = {
 280                                 .ac          = CONF_TX_AC_VI,
 281                                 .cw_min      = 15,
 282                                 .cw_max      = 63,
 283                                 .aifsn       = CONF_TX_AIFS_PIFS,
 284                                 .tx_op_limit = 3008,
 285                         },
 286                         [CONF_TX_AC_VO] = {
 287                                 .ac          = CONF_TX_AC_VO,
 288                                 .cw_min      = 15,
 289                                 .cw_max      = 63,
 290                                 .aifsn       = CONF_TX_AIFS_PIFS,
 291                                 .tx_op_limit = 1504,
 292                         },
 293                 },
 294                 .max_tx_retries = 100,
 295                 .ap_aging_period = 300,
 296                 .tid_conf_count = 4,
 297                 .tid_conf = {
 298                         [CONF_TX_AC_BE] = {
 299                                 .queue_id    = CONF_TX_AC_BE,
 300                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 301                                 .tsid        = CONF_TX_AC_BE,
 302                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 303                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 304                                 .apsd_conf   = {0, 0},
 305                         },
 306                         [CONF_TX_AC_BK] = {
 307                                 .queue_id    = CONF_TX_AC_BK,
 308                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 309                                 .tsid        = CONF_TX_AC_BK,
 310                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 311                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 312                                 .apsd_conf   = {0, 0},
 313                         },
 314                         [CONF_TX_AC_VI] = {
 315                                 .queue_id    = CONF_TX_AC_VI,
 316                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 317                                 .tsid        = CONF_TX_AC_VI,
 318                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 319                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 320                                 .apsd_conf   = {0, 0},
 321                         },
 322                         [CONF_TX_AC_VO] = {
 323                                 .queue_id    = CONF_TX_AC_VO,
 324                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 325                                 .tsid        = CONF_TX_AC_VO,
 326                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 327                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 328                                 .apsd_conf   = {0, 0},
 329                         },
 330                 },
 331                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 332                 .tx_compl_timeout            = 350,
 333                 .tx_compl_threshold          = 10,
 334                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 335                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 336                 .tmpl_short_retry_limit      = 10,
 337                 .tmpl_long_retry_limit       = 10,
 338                 .tx_watchdog_timeout         = 5000,
 339         },
 340         .conn = {
 341                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 342                 .listen_interval             = 1,
 343                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 344                 .suspend_listen_interval     = 3,
 345                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 346                 .bcn_filt_ie_count           = 3,
 347                 .bcn_filt_ie = {
 348                         [0] = {
 349                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 350                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 351                         },
 352                         [1] = {
 353                                 .ie          = WLAN_EID_HT_OPERATION,
 354                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 355                         },
 356                         [2] = {
 357                                 .ie          = WLAN_EID_ERP_INFO,
 358                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 359                         },
 360                 },
 361                 .synch_fail_thold            = 12,
 362                 .bss_lose_timeout            = 400,
 363                 .beacon_rx_timeout           = 10000,
 364                 .broadcast_timeout           = 20000,
 365                 .rx_broadcast_in_ps          = 1,
 366                 .ps_poll_threshold           = 10,
 367                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 368                 .bet_max_consecutive         = 50,
 369                 .psm_entry_retries           = 8,
 370                 .psm_exit_retries            = 16,
 371                 .psm_entry_nullfunc_retries  = 3,
 372                 .dynamic_ps_timeout          = 200,
 373                 .forced_ps                   = false,
 374                 .keep_alive_interval         = 55000,
 375                 .max_listen_interval         = 20,
 376                 .sta_sleep_auth              = WL1271_PSM_ILLEGAL,
 377         },
 378         .itrim = {
 379                 .enable = false,
 380                 .timeout = 50000,
 381         },
 382         .pm_config = {
 383                 .host_clk_settling_time = 5000,
 384                 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
 385         },
 386         .roam_trigger = {
 387                 .trigger_pacing               = 1,
 388                 .avg_weight_rssi_beacon       = 20,
 389                 .avg_weight_rssi_data         = 10,
 390                 .avg_weight_snr_beacon        = 20,
 391                 .avg_weight_snr_data          = 10,
 392         },
 393         .scan = {
 394                 .min_dwell_time_active        = 7500,
 395                 .max_dwell_time_active        = 30000,
 396                 .min_dwell_time_passive       = 100000,
 397                 .max_dwell_time_passive       = 100000,
 398                 .num_probe_reqs               = 2,
 399                 .split_scan_timeout           = 50000,
 400         },
 401         .sched_scan = {
 402                 /*
 403                  * Values are in TU/1000 but since sched scan FW command
 404                  * params are in TUs rounding up may occur.
 405                  */
 406                 .base_dwell_time                = 7500,
 407                 .max_dwell_time_delta           = 22500,
 408                 /* based on 250bits per probe @1Mbps */
 409                 .dwell_time_delta_per_probe     = 2000,
 410                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 411                 .dwell_time_delta_per_probe_5   = 350,
 412                 .dwell_time_passive             = 100000,
 413                 .dwell_time_dfs                 = 150000,
 414                 .num_probe_reqs                 = 2,
 415                 .rssi_threshold                 = -90,
 416                 .snr_threshold                  = 0,
 417         },
 418         .ht = {
 419                 .rx_ba_win_size = 10,
 420                 .tx_ba_win_size = 64,
 421                 .inactivity_timeout = 10000,
 422                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 423         },
 424         .mem = {
 425                 .num_stations                 = 1,
 426                 .ssid_profiles                = 1,
 427                 .rx_block_num                 = 40,
 428                 .tx_min_block_num             = 40,
 429                 .dynamic_memory               = 1,
 430                 .min_req_tx_blocks            = 45,
 431                 .min_req_rx_blocks            = 22,
 432                 .tx_min                       = 27,
 433         },
 434         .fm_coex = {
 435                 .enable                       = true,
 436                 .swallow_period               = 5,
 437                 .n_divider_fref_set_1         = 0xff,       /* default */
 438                 .n_divider_fref_set_2         = 12,
 439                 .m_divider_fref_set_1         = 0xffff,
 440                 .m_divider_fref_set_2         = 148,        /* default */
 441                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 442                 .ldo_stabilization_time       = 0xffff,     /* default */
 443                 .fm_disturbed_band_margin     = 0xff,       /* default */
 444                 .swallow_clk_diff             = 0xff,       /* default */
 445         },
 446         .rx_streaming = {
 447                 .duration                      = 150,
 448                 .queues                        = 0x1,
 449                 .interval                      = 20,
 450                 .always                        = 0,
 451         },
 452         .fwlog = {
 453                 .mode                         = WL12XX_FWLOG_ON_DEMAND,
 454                 .mem_blocks                   = 2,
 455                 .severity                     = 0,
 456                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 457                 .output                       = WL12XX_FWLOG_OUTPUT_HOST,
 458                 .threshold                    = 0,
 459         },
 460         .rate = {
 461                 .rate_retry_score = 32000,
 462                 .per_add = 8192,
 463                 .per_th1 = 2048,
 464                 .per_th2 = 4096,
 465                 .max_per = 8100,
 466                 .inverse_curiosity_factor = 5,
 467                 .tx_fail_low_th = 4,
 468                 .tx_fail_high_th = 10,
 469                 .per_alpha_shift = 4,
 470                 .per_add_shift = 13,
 471                 .per_beta1_shift = 10,
 472                 .per_beta2_shift = 8,
 473                 .rate_check_up = 2,
 474                 .rate_check_down = 12,
 475                 .rate_retry_policy = {
 476                         0x00, 0x00, 0x00, 0x00, 0x00,
 477                         0x00, 0x00, 0x00, 0x00, 0x00,
 478                         0x00, 0x00, 0x00,
 479                 },
 480         },
 481         .hangover = {
 482                 .recover_time               = 0,
 483                 .hangover_period            = 20,
 484                 .dynamic_mode               = 1,
 485                 .early_termination_mode     = 1,
 486                 .max_period                 = 20,
 487                 .min_period                 = 1,
 488                 .increase_delta             = 1,
 489                 .decrease_delta             = 2,
 490                 .quiet_time                 = 4,
 491                 .increase_time              = 1,
 492                 .window_size                = 16,
 493         },
 494 };
 495
 496 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
 497         .phy = {
 498                 .phy_standalone                 = 0x00,
 499                 .primary_clock_setting_time     = 0x05,
 500                 .clock_valid_on_wake_up         = 0x00,
 501                 .secondary_clock_setting_time   = 0x05,
 502                 .rdl                            = 0x01,
 503                 .auto_detect                    = 0x00,
 504                 .dedicated_fem                  = FEM_NONE,
 505                 .low_band_component             = COMPONENT_2_WAY_SWITCH,
 506                 .low_band_component_type        = 0x05,
 507                 .high_band_component            = COMPONENT_2_WAY_SWITCH,
 508                 .high_band_component_type       = 0x09,
 509                 .tcxo_ldo_voltage               = 0x00,
 510                 .xtal_itrim_val                 = 0x04,
 511                 .srf_state                      = 0x00,
 512                 .io_configuration               = 0x01,
 513                 .sdio_configuration             = 0x00,
 514                 .settings                       = 0x00,
 515                 .enable_clpc                    = 0x00,
 516                 .enable_tx_low_pwr_on_siso_rdl  = 0x00,
 517                 .rx_profile                     = 0x00,
 518                 .pwr_limit_reference_11_abg     = 0xc8,
 519                 .psat                           = 0,
 520                 .low_power_val                  = 0x00,
 521                 .med_power_val                  = 0x0a,
 522                 .high_power_val                 = 0x1e,
 523                 .external_pa_dc2dc              = 0,
 524                 .number_of_assembled_ant2_4     = 1,
 525                 .number_of_assembled_ant5       = 1,
 526         },
 527 };
 528
 529 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
 530         [PART_TOP_PRCM_ELP_SOC] = {
 531                 .mem  = { .start = 0x00A02000, .size  = 0x00010000 },
 532                 .reg  = { .start = 0x00807000, .size  = 0x00005000 },
 533                 .mem2 = { .start = 0x00800000, .size  = 0x0000B000 },
 534                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 535         },
 536         [PART_DOWN] = {
 537                 .mem  = { .start = 0x00000000, .size  = 0x00014000 },
 538                 .reg  = { .start = 0x00810000, .size  = 0x0000BFFF },
 539                 .mem2 = { .start = 0x00000000, .size  = 0x00000000 },
 540                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 541         },
 542         [PART_BOOT] = {
 543                 .mem  = { .start = 0x00700000, .size = 0x0000030c },
 544                 .reg  = { .start = 0x00802000, .size = 0x00014578 },
 545                 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
 546                 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
 547         },
 548         [PART_WORK] = {
 549                 .mem  = { .start = 0x00800000, .size  = 0x000050FC },
 550                 .reg  = { .start = 0x00B00404, .size  = 0x00001000 },
 551                 .mem2 = { .start = 0x00C00000, .size  = 0x00000400 },
 552                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 553         },
 554         [PART_PHY_INIT] = {
 555                 .mem  = { .start = 0x80926000,
 556                           .size = sizeof(struct wl18xx_mac_and_phy_params) },
 557                 .reg  = { .start = 0x00000000, .size = 0x00000000 },
 558                 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
 559                 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
 560         },
 561 };
 562
 563 static const int wl18xx_rtable[REG_TABLE_LEN] = {
 564         [REG_ECPU_CONTROL]              = WL18XX_REG_ECPU_CONTROL,
 565         [REG_INTERRUPT_NO_CLEAR]        = WL18XX_REG_INTERRUPT_NO_CLEAR,
 566         [REG_INTERRUPT_ACK]             = WL18XX_REG_INTERRUPT_ACK,
 567         [REG_COMMAND_MAILBOX_PTR]       = WL18XX_REG_COMMAND_MAILBOX_PTR,
 568         [REG_EVENT_MAILBOX_PTR]         = WL18XX_REG_EVENT_MAILBOX_PTR,
 569         [REG_INTERRUPT_TRIG]            = WL18XX_REG_INTERRUPT_TRIG_H,
 570         [REG_INTERRUPT_MASK]            = WL18XX_REG_INTERRUPT_MASK,
 571         [REG_PC_ON_RECOVERY]            = WL18XX_SCR_PAD4,
 572         [REG_CHIP_ID_B]                 = WL18XX_REG_CHIP_ID_B,
 573         [REG_CMD_MBOX_ADDRESS]          = WL18XX_CMD_MBOX_ADDRESS,
 574
 575         /* data access memory addresses, used with partition translation */
 576         [REG_SLV_MEM_DATA]              = WL18XX_SLV_MEM_DATA,
 577         [REG_SLV_REG_DATA]              = WL18XX_SLV_REG_DATA,
 578
 579         /* raw data access memory addresses */
 580         [REG_RAW_FW_STATUS_ADDR]        = WL18XX_FW_STATUS_ADDR,
 581 };
 582
 583 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
 584         [CLOCK_CONFIG_16_2_M]   = { 7,  104,  801, 4,  true },
 585         [CLOCK_CONFIG_16_368_M] = { 9,  132, 3751, 4,  true },
 586         [CLOCK_CONFIG_16_8_M]   = { 7,  100,    0, 0, false },
 587         [CLOCK_CONFIG_19_2_M]   = { 8,  100,    0, 0, false },
 588         [CLOCK_CONFIG_26_M]     = { 13, 120,    0, 0, false },
 589         [CLOCK_CONFIG_32_736_M] = { 9,  132, 3751, 4,  true },
 590         [CLOCK_CONFIG_33_6_M]   = { 7,  100,    0, 0, false },
 591         [CLOCK_CONFIG_38_468_M] = { 8,  100,    0, 0, false },
 592         [CLOCK_CONFIG_52_M]     = { 13, 120,    0, 0, false },
 593 };
 594
 595 /* TODO: maybe move to a new header file? */
 596 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
 597
 598 static int wl18xx_identify_chip(struct wl1271 *wl)
 599 {
 600         int ret = 0;
 601
 602         switch (wl->chip.id) {
 603         case CHIP_ID_185x_PG20:
 604                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
 605                                  wl->chip.id);
 606                 wl->sr_fw_name = WL18XX_FW_NAME;
 607                 /* wl18xx uses the same firmware for PLT */
 608                 wl->plt_fw_name = WL18XX_FW_NAME;
 609                 wl->quirks |= WLCORE_QUIRK_NO_ELP |
 610                               WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
 611                               WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
 612                               WLCORE_QUIRK_TX_PAD_LAST_FRAME;
 613                 break;
 614         case CHIP_ID_185x_PG10:
 615                 wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
 616                                wl->chip.id);
 617                 ret = -ENODEV;
 618                 goto out;
 619
 620         default:
 621                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 622                 ret = -ENODEV;
 623                 goto out;
 624         }
 625
 626 out:
 627         return ret;
 628 }
 629
 630 static int wl18xx_set_clk(struct wl1271 *wl)
 631 {
 632         u16 clk_freq;
 633         int ret;
 634
 635         ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 636         if (ret < 0)
 637                 goto out;
 638
 639         /* TODO: PG2: apparently we need to read the clk type */
 640
 641         ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
 642         if (ret < 0)
 643                 goto out;
 644
 645         wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
 646                      wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
 647                      wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
 648                      wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
 649
 650         ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
 651                                    wl18xx_clk_table[clk_freq].n);
 652         if (ret < 0)
 653                 goto out;
 654
 655         ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
 656                                    wl18xx_clk_table[clk_freq].m);
 657         if (ret < 0)
 658                 goto out;
 659
 660         if (wl18xx_clk_table[clk_freq].swallow) {
 661                 /* first the 16 lower bits */
 662                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
 663                                            wl18xx_clk_table[clk_freq].q &
 664                                            PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
 665                 if (ret < 0)
 666                         goto out;
 667
 668                 /* then the 16 higher bits, masked out */
 669                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
 670                                         (wl18xx_clk_table[clk_freq].q >> 16) &
 671                                         PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
 672                 if (ret < 0)
 673                         goto out;
 674
 675                 /* first the 16 lower bits */
 676                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
 677                                            wl18xx_clk_table[clk_freq].p &
 678                                            PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
 679                 if (ret < 0)
 680                         goto out;
 681
 682                 /* then the 16 higher bits, masked out */
 683                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
 684                                         (wl18xx_clk_table[clk_freq].p >> 16) &
 685                                         PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
 686         } else {
 687                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
 688                                            PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
 689         }
 690
 691 out:
 692         return ret;
 693 }
 694
 695 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
 696 {
 697         int ret;
 698
 699         /* disable Rx/Tx */
 700         ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
 701         if (ret < 0)
 702                 goto out;
 703
 704         /* disable auto calibration on start*/
 705         ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
 706
 707 out:
 708         return ret;
 709 }
 710
 711 static int wl18xx_pre_boot(struct wl1271 *wl)
 712 {
 713         int ret;
 714
 715         ret = wl18xx_set_clk(wl);
 716         if (ret < 0)
 717                 goto out;
 718
 719         /* Continue the ELP wake up sequence */
 720         ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 721         if (ret < 0)
 722                 goto out;
 723
 724         udelay(500);
 725
 726         ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 727         if (ret < 0)
 728                 goto out;
 729
 730         /* Disable interrupts */
 731         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 732         if (ret < 0)
 733                 goto out;
 734
 735         ret = wl18xx_boot_soft_reset(wl);
 736
 737 out:
 738         return ret;
 739 }
 740
 741 static int wl18xx_pre_upload(struct wl1271 *wl)
 742 {
 743         u32 tmp;
 744         int ret;
 745
 746         ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 747         if (ret < 0)
 748                 goto out;
 749
 750         /* TODO: check if this is all needed */
 751         ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
 752         if (ret < 0)
 753                 goto out;
 754
 755         ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
 756         if (ret < 0)
 757                 goto out;
 758
 759         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 760
 761         ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
 762
 763 out:
 764         return ret;
 765 }
 766
 767 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
 768 {
 769         struct wl18xx_priv *priv = wl->priv;
 770         int ret;
 771
 772         ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
 773         if (ret < 0)
 774                 goto out;
 775
 776         ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&priv->conf.phy,
 777                            sizeof(struct wl18xx_mac_and_phy_params), false);
 778
 779 out:
 780         return ret;
 781 }
 782
 783 static int wl18xx_enable_interrupts(struct wl1271 *wl)
 784 {
 785         u32 event_mask, intr_mask;
 786         int ret;
 787
 788         event_mask = WL18XX_ACX_EVENTS_VECTOR;
 789         intr_mask = WL18XX_INTR_MASK;
 790
 791         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
 792         if (ret < 0)
 793                 goto out;
 794
 795         wlcore_enable_interrupts(wl);
 796
 797         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
 798                                WL1271_ACX_INTR_ALL & ~intr_mask);
 799
 800 out:
 801         return ret;
 802 }
 803
 804 static int wl18xx_boot(struct wl1271 *wl)
 805 {
 806         int ret;
 807
 808         ret = wl18xx_pre_boot(wl);
 809         if (ret < 0)
 810                 goto out;
 811
 812         ret = wl18xx_pre_upload(wl);
 813         if (ret < 0)
 814                 goto out;
 815
 816         ret = wlcore_boot_upload_firmware(wl);
 817         if (ret < 0)
 818                 goto out;
 819
 820         ret = wl18xx_set_mac_and_phy(wl);
 821         if (ret < 0)
 822                 goto out;
 823
 824         ret = wlcore_boot_run_firmware(wl);
 825         if (ret < 0)
 826                 goto out;
 827
 828         ret = wl18xx_enable_interrupts(wl);
 829
 830 out:
 831         return ret;
 832 }
 833
 834 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
 835                                void *buf, size_t len)
 836 {
 837         struct wl18xx_priv *priv = wl->priv;
 838
 839         memcpy(priv->cmd_buf, buf, len);
 840         memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
 841
 842         return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
 843                             WL18XX_CMD_MAX_SIZE, false);
 844 }
 845
 846 static int wl18xx_ack_event(struct wl1271 *wl)
 847 {
 848         return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
 849                                 WL18XX_INTR_TRIG_EVENT_ACK);
 850 }
 851
 852 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
 853 {
 854         u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
 855         return (len + blk_size - 1) / blk_size + spare_blks;
 856 }
 857
 858 static void
 859 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 860                           u32 blks, u32 spare_blks)
 861 {
 862         desc->wl18xx_mem.total_mem_blocks = blks;
 863 }
 864
 865 static void
 866 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 867                             struct sk_buff *skb)
 868 {
 869         desc->length = cpu_to_le16(skb->len);
 870
 871         /* if only the last frame is to be padded, we unset this bit on Tx */
 872         if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
 873                 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
 874         else
 875                 desc->wl18xx_mem.ctrl = 0;
 876
 877         wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
 878                      "len: %d life: %d mem: %d", desc->hlid,
 879                      le16_to_cpu(desc->length),
 880                      le16_to_cpu(desc->life_time),
 881                      desc->wl18xx_mem.total_mem_blocks);
 882 }
 883
 884 static enum wl_rx_buf_align
 885 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
 886 {
 887         if (rx_desc & RX_BUF_PADDED_PAYLOAD)
 888                 return WLCORE_RX_BUF_PADDED;
 889
 890         return WLCORE_RX_BUF_ALIGNED;
 891 }
 892
 893 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
 894                                     u32 data_len)
 895 {
 896         struct wl1271_rx_descriptor *desc = rx_data;
 897
 898         /* invalid packet */
 899         if (data_len < sizeof(*desc))
 900                 return 0;
 901
 902         return data_len - sizeof(*desc);
 903 }
 904
 905 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
 906 {
 907         wl18xx_tx_immediate_complete(wl);
 908 }
 909
 910 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
 911 {
 912         int ret;
 913         u32 sdio_align_size = 0;
 914         u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
 915                               HOST_IF_CFG_ADD_RX_ALIGNMENT;
 916
 917         /* Enable Tx SDIO padding */
 918         if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
 919                 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
 920                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 921         }
 922
 923         /* Enable Rx SDIO padding */
 924         if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
 925                 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
 926                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 927         }
 928
 929         ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
 930                                             sdio_align_size, extra_mem_blk,
 931                                             WL18XX_HOST_IF_LEN_SIZE_FIELD);
 932         if (ret < 0)
 933                 return ret;
 934
 935         return 0;
 936 }
 937
 938 static int wl18xx_hw_init(struct wl1271 *wl)
 939 {
 940         int ret;
 941         struct wl18xx_priv *priv = wl->priv;
 942
 943         /* (re)init private structures. Relevant on recovery as well. */
 944         priv->last_fw_rls_idx = 0;
 945         priv->extra_spare_vif_count = 0;
 946
 947         /* set the default amount of spare blocks in the bitmap */
 948         ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
 949         if (ret < 0)
 950                 return ret;
 951
 952         if (checksum_param) {
 953                 ret = wl18xx_acx_set_checksum_state(wl);
 954                 if (ret != 0)
 955                         return ret;
 956         }
 957
 958         return ret;
 959 }
 960
 961 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
 962                                     struct wl1271_tx_hw_descr *desc,
 963                                     struct sk_buff *skb)
 964 {
 965         u32 ip_hdr_offset;
 966         struct iphdr *ip_hdr;
 967
 968         if (!checksum_param) {
 969                 desc->wl18xx_checksum_data = 0;
 970                 return;
 971         }
 972
 973         if (skb->ip_summed != CHECKSUM_PARTIAL) {
 974                 desc->wl18xx_checksum_data = 0;
 975                 return;
 976         }
 977
 978         ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
 979         if (WARN_ON(ip_hdr_offset >= (1<<7))) {
 980                 desc->wl18xx_checksum_data = 0;
 981                 return;
 982         }
 983
 984         desc->wl18xx_checksum_data = ip_hdr_offset << 1;
 985
 986         /* FW is interested only in the LSB of the protocol  TCP=0 UDP=1 */
 987         ip_hdr = (void *)skb_network_header(skb);
 988         desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
 989 }
 990
 991 static void wl18xx_set_rx_csum(struct wl1271 *wl,
 992                                struct wl1271_rx_descriptor *desc,
 993                                struct sk_buff *skb)
 994 {
 995         if (desc->status & WL18XX_RX_CHECKSUM_MASK)
 996                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 997 }
 998
 999 /*
1000  * TODO: instead of having these two functions to get the rate mask,
1001  * we should modify the wlvif->rate_set instead
1002  */
1003 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1004                                        struct wl12xx_vif *wlvif)
1005 {
1006         u32 hw_rate_set = wlvif->rate_set;
1007
1008         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1009             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1010                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1011                 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1012
1013                 /* we don't support MIMO in wide-channel mode */
1014                 hw_rate_set &= ~CONF_TX_MIMO_RATES;
1015         }
1016
1017         return hw_rate_set;
1018 }
1019
1020 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1021                                              struct wl12xx_vif *wlvif)
1022 {
1023         if ((wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1024              wlvif->channel_type == NL80211_CHAN_HT40PLUS) &&
1025             !strcmp(ht_mode_param, "wide")) {
1026                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1027                 return CONF_TX_RATE_USE_WIDE_CHAN;
1028         } else if (!strcmp(ht_mode_param, "mimo")) {
1029                 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
1030
1031                 return CONF_TX_MIMO_RATES;
1032         } else {
1033                 return 0;
1034         }
1035 }
1036
1037 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1038 {
1039         u32 fuse;
1040         int ret;
1041
1042         ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1043         if (ret < 0)
1044                 goto out;
1045
1046         ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1047         if (ret < 0)
1048                 goto out;
1049
1050         if (ver)
1051                 *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1052
1053         ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1054
1055 out:
1056         return ret;
1057 }
1058
1059 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
1060 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1061 {
1062         struct wl18xx_priv *priv = wl->priv;
1063         struct wlcore_conf_file *conf_file;
1064         const struct firmware *fw;
1065         int ret;
1066
1067         ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev);
1068         if (ret < 0) {
1069                 wl1271_error("could not get configuration binary %s: %d",
1070                              WL18XX_CONF_FILE_NAME, ret);
1071                 goto out_fallback;
1072         }
1073
1074         if (fw->size != WL18XX_CONF_SIZE) {
1075                 wl1271_error("configuration binary file size is wrong, expected %zu got %zu",
1076                              WL18XX_CONF_SIZE, fw->size);
1077                 ret = -EINVAL;
1078                 goto out;
1079         }
1080
1081         conf_file = (struct wlcore_conf_file *) fw->data;
1082
1083         if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1084                 wl1271_error("configuration binary file magic number mismatch, "
1085                              "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1086                              conf_file->header.magic);
1087                 ret = -EINVAL;
1088                 goto out;
1089         }
1090
1091         if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1092                 wl1271_error("configuration binary file version not supported, "
1093                              "expected 0x%08x got 0x%08x",
1094                              WL18XX_CONF_VERSION, conf_file->header.version);
1095                 ret = -EINVAL;
1096                 goto out;
1097         }
1098
1099         memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf));
1100         memcpy(&priv->conf, &conf_file->priv, sizeof(priv->conf));
1101
1102         goto out;
1103
1104 out_fallback:
1105         wl1271_warning("falling back to default config");
1106
1107         /* apply driver default configuration */
1108         memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
1109         /* apply default private configuration */
1110         memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
1111
1112         /* For now we just fallback */
1113         return 0;
1114
1115 out:
1116         release_firmware(fw);
1117         return ret;
1118 }
1119
1120 static int wl18xx_plt_init(struct wl1271 *wl)
1121 {
1122         int ret;
1123
1124         ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1125         if (ret < 0)
1126                 return ret;
1127
1128         return wl->ops->boot(wl);
1129 }
1130
1131 static int wl18xx_get_mac(struct wl1271 *wl)
1132 {
1133         u32 mac1, mac2;
1134         int ret;
1135
1136         ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1137         if (ret < 0)
1138                 goto out;
1139
1140         ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1141         if (ret < 0)
1142                 goto out;
1143
1144         ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1145         if (ret < 0)
1146                 goto out;
1147
1148         /* these are the two parts of the BD_ADDR */
1149         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1150                 ((mac1 & 0xff000000) >> 24);
1151         wl->fuse_nic_addr = (mac1 & 0xffffff);
1152
1153         ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1154
1155 out:
1156         return ret;
1157 }
1158
1159 static int wl18xx_handle_static_data(struct wl1271 *wl,
1160                                      struct wl1271_static_data *static_data)
1161 {
1162         struct wl18xx_static_data_priv *static_data_priv =
1163                 (struct wl18xx_static_data_priv *) static_data->priv;
1164
1165         wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1166
1167         return 0;
1168 }
1169
1170 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1171 {
1172         struct wl18xx_priv *priv = wl->priv;
1173
1174         /* If we have VIFs requiring extra spare, indulge them */
1175         if (priv->extra_spare_vif_count)
1176                 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1177
1178         return WL18XX_TX_HW_BLOCK_SPARE;
1179 }
1180
1181 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1182                           struct ieee80211_vif *vif,
1183                           struct ieee80211_sta *sta,
1184                           struct ieee80211_key_conf *key_conf)
1185 {
1186         struct wl18xx_priv *priv = wl->priv;
1187         bool change_spare = false;
1188         int ret;
1189
1190         /*
1191          * when adding the first or removing the last GEM/TKIP interface,
1192          * we have to adjust the number of spare blocks.
1193          */
1194         change_spare = (key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1195                 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP) &&
1196                 ((priv->extra_spare_vif_count == 0 && cmd == SET_KEY) ||
1197                  (priv->extra_spare_vif_count == 1 && cmd == DISABLE_KEY));
1198
1199         /* no need to change spare - just regular set_key */
1200         if (!change_spare)
1201                 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1202
1203         /*
1204          * stop the queues and flush to ensure the next packets are
1205          * in sync with FW spare block accounting
1206          */
1207         wlcore_stop_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK);
1208         wl1271_tx_flush(wl);
1209
1210         ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1211         if (ret < 0)
1212                 goto out;
1213
1214         /* key is now set, change the spare blocks */
1215         if (cmd == SET_KEY) {
1216                 ret = wl18xx_set_host_cfg_bitmap(wl,
1217                                         WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1218                 if (ret < 0)
1219                         goto out;
1220
1221                 priv->extra_spare_vif_count++;
1222         } else {
1223                 ret = wl18xx_set_host_cfg_bitmap(wl,
1224                                         WL18XX_TX_HW_BLOCK_SPARE);
1225                 if (ret < 0)
1226                         goto out;
1227
1228                 priv->extra_spare_vif_count--;
1229         }
1230
1231 out:
1232         wlcore_wake_queues(wl, WLCORE_QUEUE_STOP_REASON_SPARE_BLK);
1233         return ret;
1234 }
1235
1236 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1237                                u32 buf_offset, u32 last_len)
1238 {
1239         if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1240                 struct wl1271_tx_hw_descr *last_desc;
1241
1242                 /* get the last TX HW descriptor written to the aggr buf */
1243                 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1244                                                         buf_offset - last_len);
1245
1246                 /* the last frame is padded up to an SDIO block */
1247                 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1248                 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1249         }
1250
1251         /* no modifications */
1252         return buf_offset;
1253 }
1254
1255 static struct wlcore_ops wl18xx_ops = {
1256         .identify_chip  = wl18xx_identify_chip,
1257         .boot           = wl18xx_boot,
1258         .plt_init       = wl18xx_plt_init,
1259         .trigger_cmd    = wl18xx_trigger_cmd,
1260         .ack_event      = wl18xx_ack_event,
1261         .calc_tx_blocks = wl18xx_calc_tx_blocks,
1262         .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1263         .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1264         .get_rx_buf_align = wl18xx_get_rx_buf_align,
1265         .get_rx_packet_len = wl18xx_get_rx_packet_len,
1266         .tx_immediate_compl = wl18xx_tx_immediate_completion,
1267         .tx_delayed_compl = NULL,
1268         .hw_init        = wl18xx_hw_init,
1269         .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1270         .get_pg_ver     = wl18xx_get_pg_ver,
1271         .set_rx_csum = wl18xx_set_rx_csum,
1272         .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1273         .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1274         .get_mac        = wl18xx_get_mac,
1275         .debugfs_init   = wl18xx_debugfs_add_files,
1276         .handle_static_data     = wl18xx_handle_static_data,
1277         .get_spare_blocks = wl18xx_get_spare_blocks,
1278         .set_key        = wl18xx_set_key,
1279         .pre_pkt_send   = wl18xx_pre_pkt_send,
1280 };
1281
1282 /* HT cap appropriate for wide channels in 2Ghz */
1283 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1284         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1285                IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
1286         .ht_supported = true,
1287         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1288         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1289         .mcs = {
1290                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1291                 .rx_highest = cpu_to_le16(150),
1292                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1293                 },
1294 };
1295
1296 /* HT cap appropriate for wide channels in 5Ghz */
1297 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1298         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1299                IEEE80211_HT_CAP_SUP_WIDTH_20_40,
1300         .ht_supported = true,
1301         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1302         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1303         .mcs = {
1304                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1305                 .rx_highest = cpu_to_le16(150),
1306                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1307                 },
1308 };
1309
1310 /* HT cap appropriate for SISO 20 */
1311 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1312         .cap = IEEE80211_HT_CAP_SGI_20,
1313         .ht_supported = true,
1314         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1315         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1316         .mcs = {
1317                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1318                 .rx_highest = cpu_to_le16(72),
1319                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1320                 },
1321 };
1322
1323 /* HT cap appropriate for MIMO rates in 20mhz channel */
1324 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1325         .cap = IEEE80211_HT_CAP_SGI_20,
1326         .ht_supported = true,
1327         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1328         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1329         .mcs = {
1330                 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1331                 .rx_highest = cpu_to_le16(144),
1332                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1333                 },
1334 };
1335
1336 static int __devinit wl18xx_probe(struct platform_device *pdev)
1337 {
1338         struct wl1271 *wl;
1339         struct ieee80211_hw *hw;
1340         struct wl18xx_priv *priv;
1341         int ret;
1342
1343         hw = wlcore_alloc_hw(sizeof(*priv));
1344         if (IS_ERR(hw)) {
1345                 wl1271_error("can't allocate hw");
1346                 ret = PTR_ERR(hw);
1347                 goto out;
1348         }
1349
1350         wl = hw->priv;
1351         priv = wl->priv;
1352         wl->ops = &wl18xx_ops;
1353         wl->ptable = wl18xx_ptable;
1354         wl->rtable = wl18xx_rtable;
1355         wl->num_tx_desc = 32;
1356         wl->num_rx_desc = 32;
1357         wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1358         wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1359         wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1360         wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1361         wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1362         wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1363
1364         if (num_rx_desc_param != -1)
1365                 wl->num_rx_desc = num_rx_desc_param;
1366
1367         ret = wl18xx_conf_init(wl, &pdev->dev);
1368         if (ret < 0)
1369                 goto out_free;
1370
1371         if (!strcmp(board_type_param, "fpga")) {
1372                 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1373         } else if (!strcmp(board_type_param, "hdk")) {
1374                 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1375                 /* HACK! Just for now we hardcode HDK to 0x06 */
1376                 priv->conf.phy.low_band_component_type = 0x06;
1377         } else if (!strcmp(board_type_param, "dvp")) {
1378                 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1379         } else if (!strcmp(board_type_param, "evb")) {
1380                 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1381         } else if (!strcmp(board_type_param, "com8")) {
1382                 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1383                 /* HACK! Just for now we hardcode COM8 to 0x06 */
1384                 priv->conf.phy.low_band_component_type = 0x06;
1385         } else {
1386                 wl1271_error("invalid board type '%s'", board_type_param);
1387                 ret = -EINVAL;
1388                 goto out_free;
1389         }
1390
1391         /* If the module param is set, update it in conf */
1392         if (low_band_component_param != -1)
1393                 priv->conf.phy.low_band_component = low_band_component_param;
1394         if (low_band_component_type_param != -1)
1395                 priv->conf.phy.low_band_component_type =
1396                         low_band_component_type_param;
1397         if (high_band_component_param != -1)
1398                 priv->conf.phy.high_band_component = high_band_component_param;
1399         if (high_band_component_type_param != -1)
1400                 priv->conf.phy.high_band_component_type =
1401                         high_band_component_type_param;
1402         if (pwr_limit_reference_11_abg_param != -1)
1403                 priv->conf.phy.pwr_limit_reference_11_abg =
1404                         pwr_limit_reference_11_abg_param;
1405         if (n_antennas_2_param != -1)
1406                 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1407         if (n_antennas_5_param != -1)
1408                 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1409         if (dc2dc_param != -1)
1410                 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1411
1412         if (!strcmp(ht_mode_param, "default")) {
1413                 /*
1414                  * Only support mimo with multiple antennas. Fall back to
1415                  * siso20.
1416                  */
1417                 if (priv->conf.phy.number_of_assembled_ant2_4 >= 2)
1418                         wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1419                                           &wl18xx_mimo_ht_cap_2ghz);
1420                 else
1421                         wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1422                                           &wl18xx_siso20_ht_cap);
1423
1424                 /* 5Ghz is always wide */
1425                 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1426                                   &wl18xx_siso40_ht_cap_5ghz);
1427         } else if (!strcmp(ht_mode_param, "wide")) {
1428                 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1429                                   &wl18xx_siso40_ht_cap_2ghz);
1430                 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1431                                   &wl18xx_siso40_ht_cap_5ghz);
1432         } else if (!strcmp(ht_mode_param, "siso20")) {
1433                 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1434                                   &wl18xx_siso20_ht_cap);
1435                 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1436                                   &wl18xx_siso20_ht_cap);
1437         } else {
1438                 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1439                 ret = -EINVAL;
1440                 goto out_free;
1441         }
1442
1443         if (!checksum_param) {
1444                 wl18xx_ops.set_rx_csum = NULL;
1445                 wl18xx_ops.init_vif = NULL;
1446         }
1447
1448         wl->enable_11a = enable_11a_param;
1449
1450         return wlcore_probe(wl, pdev);
1451
1452 out_free:
1453         wlcore_free_hw(wl);
1454 out:
1455         return ret;
1456 }
1457
1458 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1459         { "wl18xx", 0 },
1460         {  } /* Terminating Entry */
1461 };
1462 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1463
1464 static struct platform_driver wl18xx_driver = {
1465         .probe          = wl18xx_probe,
1466         .remove         = __devexit_p(wlcore_remove),
1467         .id_table       = wl18xx_id_table,
1468         .driver = {
1469                 .name   = "wl18xx_driver",
1470                 .owner  = THIS_MODULE,
1471         }
1472 };
1473
1474 static int __init wl18xx_init(void)
1475 {
1476         return platform_driver_register(&wl18xx_driver);
1477 }
1478 module_init(wl18xx_init);
1479
1480 static void __exit wl18xx_exit(void)
1481 {
1482         platform_driver_unregister(&wl18xx_driver);
1483 }
1484 module_exit(wl18xx_exit);
1485
1486 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1487 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
1488
1489 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1490 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1491                  "dvp");
1492
1493 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1494 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
1495
1496 module_param_named(enable_11a, enable_11a_param, bool, S_IRUSR);
1497 MODULE_PARM_DESC(enable_11a, "Enable 11a (5GHz): boolean (defaults to true)");
1498
1499 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
1500 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
1501
1502 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
1503 MODULE_PARM_DESC(n_antennas_2,
1504                  "Number of installed 2.4GHz antennas: 1 (default) or 2");
1505
1506 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
1507 MODULE_PARM_DESC(n_antennas_5,
1508                  "Number of installed 5GHz antennas: 1 (default) or 2");
1509
1510 module_param_named(low_band_component, low_band_component_param, int,
1511                    S_IRUSR);
1512 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
1513                  "(default is 0x01)");
1514
1515 module_param_named(low_band_component_type, low_band_component_type_param,
1516                    int, S_IRUSR);
1517 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
1518                  "(default is 0x05 or 0x06 depending on the board_type)");
1519
1520 module_param_named(high_band_component, high_band_component_param, int,
1521                    S_IRUSR);
1522 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
1523                  "(default is 0x01)");
1524
1525 module_param_named(high_band_component_type, high_band_component_type_param,
1526                    int, S_IRUSR);
1527 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
1528                  "(default is 0x09)");
1529
1530 module_param_named(pwr_limit_reference_11_abg,
1531                    pwr_limit_reference_11_abg_param, int, S_IRUSR);
1532 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
1533                  "(default is 0xc8)");
1534
1535 module_param_named(num_rx_desc,
1536                    num_rx_desc_param, int, S_IRUSR);
1537 MODULE_PARM_DESC(num_rx_desc_param,
1538                  "Number of Rx descriptors: u8 (default is 32)");
1539
1540 MODULE_LICENSE("GPL v2");
1541 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1542 MODULE_FIRMWARE(WL18XX_FW_NAME);