drivers/net/wireless/rtlwifi/rtl8723be/phy.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __RTL8723BE_PHY_H__
  27 #define __RTL8723BE_PHY_H__
  28
  29 /*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
  30 #define MAX_TX_COUNT            4
  31 #define TX_1S                   0
  32 #define TX_2S                   1
  33
  34 #define MAX_POWER_INDEX         0x3F
  35
  36 #define MAX_PRECMD_CNT                  16
  37 #define MAX_RFDEPENDCMD_CNT             16
  38 #define MAX_POSTCMD_CNT         16
  39
  40 #define MAX_DOZE_WAITING_TIMES_9x       64
  41
  42 #define RT_CANNOT_IO(hw)                false
  43 #define HIGHPOWER_RADIOA_ARRAYLEN       22
  44
  45 #define IQK_ADDA_REG_NUM                16
  46 #define IQK_BB_REG_NUM                  9
  47 #define MAX_TOLERANCE                   5
  48 #define IQK_DELAY_TIME                  10
  49 #define index_mapping_NUM               15
  50
  51 #define APK_BB_REG_NUM                  5
  52 #define APK_AFE_REG_NUM                 16
  53 #define APK_CURVE_REG_NUM               4
  54 #define PATH_NUM                        1
  55
  56 #define LOOP_LIMIT                      5
  57 #define MAX_STALL_TIME                  50
  58 #define ANTENNADIVERSITYVALUE           0x80
  59 #define MAX_TXPWR_IDX_NMODE_92S         63
  60 #define RESET_CNT_LIMIT                 3
  61
  62 #define IQK_ADDA_REG_NUM                16
  63 #define IQK_MAC_REG_NUM                 4
  64
  65 #define RF6052_MAX_PATH                 2
  66
  67 #define CT_OFFSET_MAC_ADDR              0X16
  68
  69 #define CT_OFFSET_CCK_TX_PWR_IDX                0x5A
  70 #define CT_OFFSET_HT401S_TX_PWR_IDX             0x60
  71 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF        0x66
  72 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF          0x69
  73 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF          0x6C
  74
  75 #define CT_OFFSET_HT40_MAX_PWR_OFFSET           0x6F
  76 #define CT_OFFSET_HT20_MAX_PWR_OFFSET           0x72
  77
  78 #define CT_OFFSET_CHANNEL_PLAH                  0x75
  79 #define CT_OFFSET_THERMAL_METER                 0x78
  80 #define CT_OFFSET_RF_OPTION                     0x79
  81 #define CT_OFFSET_VERSION                       0x7E
  82 #define CT_OFFSET_CUSTOMER_ID                   0x7F
  83
  84 #define RTL92C_MAX_PATH_NUM                     2
  85
  86 enum hw90_block_e {
  87         HW90_BLOCK_MAC = 0,
  88         HW90_BLOCK_PHY0 = 1,
  89         HW90_BLOCK_PHY1 = 2,
  90         HW90_BLOCK_RF = 3,
  91         HW90_BLOCK_MAXIMUM = 4,
  92 };
  93
  94 enum baseband_config_type {
  95         BASEBAND_CONFIG_PHY_REG = 0,
  96         BASEBAND_CONFIG_AGC_TAB = 1,
  97 };
  98
  99 enum ra_offset_area {
 100         RA_OFFSET_LEGACY_OFDM1,
 101         RA_OFFSET_LEGACY_OFDM2,
 102         RA_OFFSET_HT_OFDM1,
 103         RA_OFFSET_HT_OFDM2,
 104         RA_OFFSET_HT_OFDM3,
 105         RA_OFFSET_HT_OFDM4,
 106         RA_OFFSET_HT_CCK,
 107 };
 108
 109 enum antenna_path {
 110         ANTENNA_NONE,
 111         ANTENNA_D,
 112         ANTENNA_C,
 113         ANTENNA_CD,
 114         ANTENNA_B,
 115         ANTENNA_BD,
 116         ANTENNA_BC,
 117         ANTENNA_BCD,
 118         ANTENNA_A,
 119         ANTENNA_AD,
 120         ANTENNA_AC,
 121         ANTENNA_ACD,
 122         ANTENNA_AB,
 123         ANTENNA_ABD,
 124         ANTENNA_ABC,
 125         ANTENNA_ABCD
 126 };
 127
 128 struct r_antenna_select_ofdm {
 129         u32 r_tx_antenna:4;
 130         u32 r_ant_l:4;
 131         u32 r_ant_non_ht:4;
 132         u32 r_ant_ht1:4;
 133         u32 r_ant_ht2:4;
 134         u32 r_ant_ht_s1:4;
 135         u32 r_ant_non_ht_s1:4;
 136         u32 ofdm_txsc:2;
 137         u32 reserved:2;
 138 };
 139
 140 struct r_antenna_select_cck {
 141         u8 r_cckrx_enable_2:2;
 142         u8 r_cckrx_enable:2;
 143         u8 r_ccktx_enable:4;
 144 };
 145
 146
 147 struct efuse_contents {
 148         u8 mac_addr[ETH_ALEN];
 149         u8 cck_tx_power_idx[6];
 150         u8 ht40_1s_tx_power_idx[6];
 151         u8 ht40_2s_tx_power_idx_diff[3];
 152         u8 ht20_tx_power_idx_diff[3];
 153         u8 ofdm_tx_power_idx_diff[3];
 154         u8 ht40_max_power_offset[3];
 155         u8 ht20_max_power_offset[3];
 156         u8 channel_plan;
 157         u8 thermal_meter;
 158         u8 rf_option[5];
 159         u8 version;
 160         u8 oem_id;
 161         u8 regulatory;
 162 };
 163
 164 struct tx_power_struct {
 165         u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 166         u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 167         u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 168         u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 169         u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 170         u8 legacy_ht_txpowerdiff;
 171         u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 172         u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 173         u8 pwrgroup_cnt;
 174         u32 mcs_original_offset[4][16];
 175 };
 176
 177 enum _ANT_DIV_TYPE {
 178         NO_ANTDIV                               = 0xFF,
 179         CG_TRX_HW_ANTDIV                = 0x01,
 180         CGCS_RX_HW_ANTDIV               = 0x02,
 181         FIXED_HW_ANTDIV         = 0x03,
 182         CG_TRX_SMART_ANTDIV             = 0x04,
 183         CGCS_RX_SW_ANTDIV               = 0x05,
 184 };
 185
 186 u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw,
 187                                enum radio_path rfpath,
 188                                u32 regaddr, u32 bitmask);
 189 void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw,
 190                               enum radio_path rfpath,
 191                               u32 regaddr, u32 bitmask, u32 data);
 192 bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw);
 193 bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw);
 194 bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw);
 195 void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
 196 void rtl8723be_phy_get_txpower_level(struct ieee80211_hw *hw,
 197                                      long *powerlevel);
 198 void rtl8723be_phy_set_txpower_level(struct ieee80211_hw *hw,
 199                                      u8 channel);
 200 void rtl8723be_phy_scan_operation_backup(struct ieee80211_hw *hw,
 201                                          u8 operation);
 202 void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
 203 void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw,
 204                                enum nl80211_channel_type ch_type);
 205 void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw);
 206 u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw);
 207 void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
 208                                 bool b_recovery);
 209 void rtl23b_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
 210 void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw);
 211 void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
 212 bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 213                                              enum radio_path rfpath);
 214 bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
 215 bool rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
 216                                       enum rf_pwrstate rfpwr_state);
 217 #endif