drivers/net/wireless/rtlwifi/rtl8192ce/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../cam.h"
  34 #include "../ps.h"
  35 #include "../pci.h"
  36 #include "reg.h"
  37 #include "def.h"
  38 #include "phy.h"
  39 #include "dm.h"
  40 #include "led.h"
  41 #include "hw.h"
  42
  43 #define LLT_CONFIG      5
  44
  45 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  46                                       u8 set_bits, u8 clear_bits)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50
  51         rtlpci->reg_bcn_ctrl_val |= set_bits;
  52         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  53
  54         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  55 }
  56
  57 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
  58 {
  59         struct rtl_priv *rtlpriv = rtl_priv(hw);
  60         u8 tmp1byte;
  61
  62         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  63         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  64         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  65         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  66         tmp1byte &= ~(BIT(0));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  68 }
  69
  70 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         u8 tmp1byte;
  74
  75         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  76         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  77         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  78         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  79         tmp1byte |= BIT(0);
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  81 }
  82
  83 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
  84 {
  85         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
  86 }
  87
  88 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
  89 {
  90         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
  91 }
  92
  93 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  94 {
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  97         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  98
  99         switch (variable) {
 100         case HW_VAR_RCR:
 101                 *((u32 *) (val)) = rtlpci->receive_config;
 102                 break;
 103         case HW_VAR_RF_STATE:
 104                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 105                 break;
 106         case HW_VAR_FWLPS_RF_ON:{
 107                         enum rf_pwrstate rfState;
 108                         u32 val_rcr;
 109
 110                         rtlpriv->cfg->ops->get_hw_reg(hw,
 111                                                       HW_VAR_RF_STATE,
 112                                                       (u8 *) (&rfState));
 113                         if (rfState == ERFOFF) {
 114                                 *((bool *) (val)) = true;
 115                         } else {
 116                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 117                                 val_rcr &= 0x00070000;
 118                                 if (val_rcr)
 119                                         *((bool *) (val)) = false;
 120                                 else
 121                                         *((bool *) (val)) = true;
 122                         }
 123                         break;
 124                 }
 125         case HW_VAR_FW_PSMODE_STATUS:
 126                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 127                 break;
 128         case HW_VAR_CORRECT_TSF:{
 129                 u64 tsf;
 130                 u32 *ptsf_low = (u32 *)&tsf;
 131                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 132
 133                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 134                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 135
 136                 *((u64 *) (val)) = tsf;
 137
 138                 break;
 139                 }
 140         case HW_VAR_MGT_FILTER:
 141                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
 142                 break;
 143         case HW_VAR_CTRL_FILTER:
 144                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
 145                 break;
 146         case HW_VAR_DATA_FILTER:
 147                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
 148                 break;
 149         default:
 150                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 151                          ("switch case not process\n"));
 152                 break;
 153         }
 154 }
 155
 156 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 157 {
 158         struct rtl_priv *rtlpriv = rtl_priv(hw);
 159         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 160         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 161         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 162         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 163         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 164         u8 idx;
 165
 166         switch (variable) {
 167         case HW_VAR_ETHER_ADDR:{
 168                         for (idx = 0; idx < ETH_ALEN; idx++) {
 169                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 170                                                val[idx]);
 171                         }
 172                         break;
 173                 }
 174         case HW_VAR_BASIC_RATE:{
 175                         u16 rate_cfg = ((u16 *) val)[0];
 176                         u8 rate_index = 0;
 177                         rate_cfg &= 0x15f;
 178                         rate_cfg |= 0x01;
 179                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 180                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 181                                        (rate_cfg >> 8)&0xff);
 182                         while (rate_cfg > 0x1) {
 183                                 rate_cfg = (rate_cfg >> 1);
 184                                 rate_index++;
 185                         }
 186                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 187                                        rate_index);
 188                         break;
 189                 }
 190         case HW_VAR_BSSID:{
 191                         for (idx = 0; idx < ETH_ALEN; idx++) {
 192                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 193                                                val[idx]);
 194                         }
 195                         break;
 196                 }
 197         case HW_VAR_SIFS:{
 198                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 199                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 200
 201                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 202                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 203
 204                         if (!mac->ht_enable)
 205                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 206                                                0x0e0e);
 207                         else
 208                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 209                                                *((u16 *) val));
 210                         break;
 211                 }
 212         case HW_VAR_SLOT_TIME:{
 213                         u8 e_aci;
 214
 215                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 216                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
 217
 218                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 219
 220                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 221                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 222                                                               HW_VAR_AC_PARAM,
 223                                                               (u8 *) (&e_aci));
 224                         }
 225                         break;
 226                 }
 227         case HW_VAR_ACK_PREAMBLE:{
 228                         u8 reg_tmp;
 229                         u8 short_preamble = (bool) (*(u8 *) val);
 230                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 231                         if (short_preamble)
 232                                 reg_tmp |= 0x80;
 233
 234                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 235                         break;
 236                 }
 237         case HW_VAR_AMPDU_MIN_SPACE:{
 238                         u8 min_spacing_to_set;
 239                         u8 sec_min_space;
 240
 241                         min_spacing_to_set = *((u8 *) val);
 242                         if (min_spacing_to_set <= 7) {
 243                                 sec_min_space = 0;
 244
 245                                 if (min_spacing_to_set < sec_min_space)
 246                                         min_spacing_to_set = sec_min_space;
 247
 248                                 mac->min_space_cfg = ((mac->min_space_cfg &
 249                                                        0xf8) |
 250                                                       min_spacing_to_set);
 251
 252                                 *val = min_spacing_to_set;
 253
 254                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 255                                          ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 256                                           mac->min_space_cfg));
 257
 258                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 259                                                mac->min_space_cfg);
 260                         }
 261                         break;
 262                 }
 263         case HW_VAR_SHORTGI_DENSITY:{
 264                         u8 density_to_set;
 265
 266                         density_to_set = *((u8 *) val);
 267                         mac->min_space_cfg |= (density_to_set << 3);
 268
 269                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 270                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 271                                   mac->min_space_cfg));
 272
 273                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 274                                        mac->min_space_cfg);
 275
 276                         break;
 277                 }
 278         case HW_VAR_AMPDU_FACTOR:{
 279                         u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 280
 281                         u8 factor_toset;
 282                         u8 *p_regtoset = NULL;
 283                         u8 index = 0;
 284
 285                         p_regtoset = regtoset_normal;
 286
 287                         factor_toset = *((u8 *) val);
 288                         if (factor_toset <= 3) {
 289                                 factor_toset = (1 << (factor_toset + 2));
 290                                 if (factor_toset > 0xf)
 291                                         factor_toset = 0xf;
 292
 293                                 for (index = 0; index < 4; index++) {
 294                                         if ((p_regtoset[index] & 0xf0) >
 295                                             (factor_toset << 4))
 296                                                 p_regtoset[index] =
 297                                                     (p_regtoset[index] & 0x0f) |
 298                                                     (factor_toset << 4);
 299
 300                                         if ((p_regtoset[index] & 0x0f) >
 301                                             factor_toset)
 302                                                 p_regtoset[index] =
 303                                                     (p_regtoset[index] & 0xf0) |
 304                                                     (factor_toset);
 305
 306                                         rtl_write_byte(rtlpriv,
 307                                                        (REG_AGGLEN_LMT + index),
 308                                                        p_regtoset[index]);
 309
 310                                 }
 311
 312                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 313                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
 314                                           factor_toset));
 315                         }
 316                         break;
 317                 }
 318         case HW_VAR_AC_PARAM:{
 319                         u8 e_aci = *((u8 *) val);
 320                         u32 u4b_ac_param;
 321                         u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
 322                         u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
 323                         u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
 324
 325                         u4b_ac_param = (u32) mac->ac[e_aci].aifs;
 326                         u4b_ac_param |= ((u32)cw_min
 327                                          & 0xF) << AC_PARAM_ECW_MIN_OFFSET;
 328                         u4b_ac_param |= ((u32)cw_max &
 329                                          0xF) << AC_PARAM_ECW_MAX_OFFSET;
 330                         u4b_ac_param |= (u32)tx_op << AC_PARAM_TXOP_OFFSET;
 331
 332                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 333                                  ("queue:%x, ac_param:%x\n", e_aci,
 334                                   u4b_ac_param));
 335
 336                         switch (e_aci) {
 337                         case AC1_BK:
 338                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
 339                                                 u4b_ac_param);
 340                                 break;
 341                         case AC0_BE:
 342                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
 343                                                 u4b_ac_param);
 344                                 break;
 345                         case AC2_VI:
 346                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
 347                                                 u4b_ac_param);
 348                                 break;
 349                         case AC3_VO:
 350                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
 351                                                 u4b_ac_param);
 352                                 break;
 353                         default:
 354                                 RT_ASSERT(false,
 355                                   ("SetHwReg8185(): invalid aci: %d !\n",
 356                                    e_aci));
 357                                 break;
 358                         }
 359
 360                         if (rtlpci->acm_method != eAcmWay2_SW)
 361                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 362                                                               HW_VAR_ACM_CTRL,
 363                                                               (u8 *) (&e_aci));
 364                         break;
 365                 }
 366         case HW_VAR_ACM_CTRL:{
 367                         u8 e_aci = *((u8 *) val);
 368                         union aci_aifsn *p_aci_aifsn =
 369                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 370                         u8 acm = p_aci_aifsn->f.acm;
 371                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 372
 373                         acm_ctrl =
 374                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 375
 376                         if (acm) {
 377                                 switch (e_aci) {
 378                                 case AC0_BE:
 379                                         acm_ctrl |= AcmHw_BeqEn;
 380                                         break;
 381                                 case AC2_VI:
 382                                         acm_ctrl |= AcmHw_ViqEn;
 383                                         break;
 384                                 case AC3_VO:
 385                                         acm_ctrl |= AcmHw_VoqEn;
 386                                         break;
 387                                 default:
 388                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 389                                                  ("HW_VAR_ACM_CTRL acm set "
 390                                                   "failed: eACI is %d\n", acm));
 391                                         break;
 392                                 }
 393                         } else {
 394                                 switch (e_aci) {
 395                                 case AC0_BE:
 396                                         acm_ctrl &= (~AcmHw_BeqEn);
 397                                         break;
 398                                 case AC2_VI:
 399                                         acm_ctrl &= (~AcmHw_ViqEn);
 400                                         break;
 401                                 case AC3_VO:
 402                                         acm_ctrl &= (~AcmHw_BeqEn);
 403                                         break;
 404                                 default:
 405                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 406                                                  ("switch case not process\n"));
 407                                         break;
 408                                 }
 409                         }
 410
 411                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 412                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
 413                                   "Write 0x%X\n", acm_ctrl));
 414                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 415                         break;
 416                 }
 417         case HW_VAR_RCR:{
 418                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 419                         rtlpci->receive_config = ((u32 *) (val))[0];
 420                         break;
 421                 }
 422         case HW_VAR_RETRY_LIMIT:{
 423                         u8 retry_limit = ((u8 *) (val))[0];
 424
 425                         rtl_write_word(rtlpriv, REG_RL,
 426                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 427                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 428                         break;
 429                 }
 430         case HW_VAR_DUAL_TSF_RST:
 431                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 432                 break;
 433         case HW_VAR_EFUSE_BYTES:
 434                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 435                 break;
 436         case HW_VAR_EFUSE_USAGE:
 437                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
 438                 break;
 439         case HW_VAR_IO_CMD:
 440                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
 441                 break;
 442         case HW_VAR_WPA_CONFIG:
 443                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
 444                 break;
 445         case HW_VAR_SET_RPWM:{
 446                         u8 rpwm_val;
 447
 448                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 449                         udelay(1);
 450
 451                         if (rpwm_val & BIT(7)) {
 452                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 453                                                (*(u8 *) val));
 454                         } else {
 455                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 456                                                ((*(u8 *) val) | BIT(7)));
 457                         }
 458
 459                         break;
 460                 }
 461         case HW_VAR_H2C_FW_PWRMODE:{
 462                         u8 psmode = (*(u8 *) val);
 463
 464                         if ((psmode != FW_PS_ACTIVE_MODE) &&
 465                             (!IS_92C_SERIAL(rtlhal->version))) {
 466                                 rtl92c_dm_rf_saving(hw, true);
 467                         }
 468
 469                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
 470                         break;
 471                 }
 472         case HW_VAR_FW_PSMODE_STATUS:
 473                 ppsc->fw_current_inpsmode = *((bool *) val);
 474                 break;
 475         case HW_VAR_H2C_FW_JOINBSSRPT:{
 476                         u8 mstatus = (*(u8 *) val);
 477                         u8 tmp_regcr, tmp_reg422;
 478                         bool recover = false;
 479
 480                         if (mstatus == RT_MEDIA_CONNECT) {
 481                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 482                                                               NULL);
 483
 484                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 485                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 486                                                (tmp_regcr | BIT(0)));
 487
 488                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 489                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
 490
 491                                 tmp_reg422 =
 492                                     rtl_read_byte(rtlpriv,
 493                                                   REG_FWHW_TXQ_CTRL + 2);
 494                                 if (tmp_reg422 & BIT(6))
 495                                         recover = true;
 496                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 497                                                tmp_reg422 & (~BIT(6)));
 498
 499                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
 500
 501                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 502                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
 503
 504                                 if (recover) {
 505                                         rtl_write_byte(rtlpriv,
 506                                                        REG_FWHW_TXQ_CTRL + 2,
 507                                                        tmp_reg422);
 508                                 }
 509
 510                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 511                                                (tmp_regcr & ~(BIT(0))));
 512                         }
 513                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
 514
 515                         break;
 516                 }
 517         case HW_VAR_AID:{
 518                         u16 u2btmp;
 519                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 520                         u2btmp &= 0xC000;
 521                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 522                                                 mac->assoc_id));
 523
 524                         break;
 525                 }
 526         case HW_VAR_CORRECT_TSF:{
 527                         u8 btype_ibss = ((u8 *) (val))[0];
 528
 529                         /*btype_ibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ?
 530                                         1 : 0;*/
 531
 532                         if (btype_ibss == true)
 533                                 _rtl92ce_stop_tx_beacon(hw);
 534
 535                         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 536
 537                         rtl_write_dword(rtlpriv, REG_TSFTR,
 538                                         (u32) (mac->tsf & 0xffffffff));
 539                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 540                                         (u32) ((mac->tsf >> 32)&0xffffffff));
 541
 542                         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 543
 544                         if (btype_ibss == true)
 545                                 _rtl92ce_resume_tx_beacon(hw);
 546
 547                         break;
 548
 549                 }
 550         case HW_VAR_MGT_FILTER:
 551                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *) val);
 552                 break;
 553         case HW_VAR_CTRL_FILTER:
 554                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *) val);
 555                 break;
 556         case HW_VAR_DATA_FILTER:
 557                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *) val);
 558                 break;
 559         default:
 560                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
 561                                                         "not process\n"));
 562                 break;
 563         }
 564 }
 565
 566 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 567 {
 568         struct rtl_priv *rtlpriv = rtl_priv(hw);
 569         bool status = true;
 570         long count = 0;
 571         u32 value = _LLT_INIT_ADDR(address) |
 572             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 573
 574         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 575
 576         do {
 577                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 578                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 579                         break;
 580
 581                 if (count > POLLING_LLT_THRESHOLD) {
 582                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 583                                  ("Failed to polling write LLT done at "
 584                                   "address %d!\n", address));
 585                         status = false;
 586                         break;
 587                 }
 588         } while (++count);
 589
 590         return status;
 591 }
 592
 593 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
 594 {
 595         struct rtl_priv *rtlpriv = rtl_priv(hw);
 596         unsigned short i;
 597         u8 txpktbuf_bndy;
 598         u8 maxPage;
 599         bool status;
 600
 601 #if LLT_CONFIG == 1
 602         maxPage = 255;
 603         txpktbuf_bndy = 252;
 604 #elif LLT_CONFIG == 2
 605         maxPage = 127;
 606         txpktbuf_bndy = 124;
 607 #elif LLT_CONFIG == 3
 608         maxPage = 255;
 609         txpktbuf_bndy = 174;
 610 #elif LLT_CONFIG == 4
 611         maxPage = 255;
 612         txpktbuf_bndy = 246;
 613 #elif LLT_CONFIG == 5
 614         maxPage = 255;
 615         txpktbuf_bndy = 246;
 616 #endif
 617
 618 #if LLT_CONFIG == 1
 619         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 620         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 621 #elif LLT_CONFIG == 2
 622         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 623 #elif LLT_CONFIG == 3
 624         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 625 #elif LLT_CONFIG == 4
 626         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 627 #elif LLT_CONFIG == 5
 628         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 629
 630         rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
 631 #endif
 632
 633         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 634         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 635
 636         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 637         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 638
 639         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 640         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 641         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 642
 643         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 644                 status = _rtl92ce_llt_write(hw, i, i + 1);
 645                 if (true != status)
 646                         return status;
 647         }
 648
 649         status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 650         if (true != status)
 651                 return status;
 652
 653         for (i = txpktbuf_bndy; i < maxPage; i++) {
 654                 status = _rtl92ce_llt_write(hw, i, (i + 1));
 655                 if (true != status)
 656                         return status;
 657         }
 658
 659         status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
 660         if (true != status)
 661                 return status;
 662
 663         return true;
 664 }
 665
 666 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
 667 {
 668         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 669         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 670         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 671         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 672
 673         if (rtlpci->up_first_time)
 674                 return;
 675
 676         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 677                 rtl92ce_sw_led_on(hw, pLed0);
 678         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 679                 rtl92ce_sw_led_on(hw, pLed0);
 680         else
 681                 rtl92ce_sw_led_off(hw, pLed0);
 682
 683 }
 684
 685 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
 686 {
 687         struct rtl_priv *rtlpriv = rtl_priv(hw);
 688         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 689         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 690
 691         unsigned char bytetmp;
 692         unsigned short wordtmp;
 693         u16 retry;
 694
 695         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 696         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 697         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 698
 699         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 700         udelay(2);
 701
 702         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 703         udelay(2);
 704
 705         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 706         udelay(2);
 707
 708         retry = 0;
 709         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 710                                                 rtl_read_dword(rtlpriv, 0xEC),
 711                                                 bytetmp));
 712
 713         while ((bytetmp & BIT(0)) && retry < 1000) {
 714                 retry++;
 715                 udelay(50);
 716                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 717                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 718                                                         rtl_read_dword(rtlpriv,
 719                                                                        0xEC),
 720                                                         bytetmp));
 721                 udelay(50);
 722         }
 723
 724         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 725
 726         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 727         udelay(2);
 728
 729         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 730
 731         if (_rtl92ce_llt_table_init(hw) == false)
 732                 return false;
 733
 734         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 735         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 736
 737         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 738
 739         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 740         wordtmp &= 0xf;
 741         wordtmp |= 0xF771;
 742         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 743
 744         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 745         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 746         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 747
 748         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 749
 750         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 751                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 752                         DMA_BIT_MASK(32));
 753         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 754                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 755                         DMA_BIT_MASK(32));
 756         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 757                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 758         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 759                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 760         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 761                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 762         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 763                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 764         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 765                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 766                         DMA_BIT_MASK(32));
 767         rtl_write_dword(rtlpriv, REG_RX_DESA,
 768                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 769                         DMA_BIT_MASK(32));
 770
 771         if (IS_92C_SERIAL(rtlhal->version))
 772                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 773         else
 774                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
 775
 776         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 777
 778         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 779         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 780         do {
 781                 retry++;
 782                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 783         } while ((retry < 200) && (bytetmp & BIT(7)));
 784
 785         _rtl92ce_gen_refresh_led_state(hw);
 786
 787         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 788
 789         return true;
 790 }
 791
 792 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
 793 {
 794         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 795         struct rtl_priv *rtlpriv = rtl_priv(hw);
 796         u8 reg_bw_opmode;
 797         u32 reg_ratr, reg_prsr;
 798
 799         reg_bw_opmode = BW_OPMODE_20MHZ;
 800         reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 801             RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 802         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 803
 804         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 805
 806         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 807
 808         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 809
 810         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 811
 812         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 813
 814         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 815
 816         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 817
 818         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 819
 820         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 821
 822         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 823         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 824         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 825         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 826
 827         rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 828
 829         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 830
 831         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 832
 833         rtlpci->reg_bcn_ctrl_val = 0x1f;
 834         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 835
 836         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 837
 838         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 839
 840         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 841         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 842
 843         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 844
 845         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 846
 847         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 848
 849         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 850
 851         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 852         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 853
 854         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 855
 856         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 857
 858         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 859         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 860
 861 }
 862
 863 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
 864 {
 865         struct rtl_priv *rtlpriv = rtl_priv(hw);
 866         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 867
 868         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 869         rtl_write_word(rtlpriv, 0x350, 0x870c);
 870         rtl_write_byte(rtlpriv, 0x352, 0x1);
 871
 872         if (ppsc->support_backdoor)
 873                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 874         else
 875                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 876
 877         rtl_write_word(rtlpriv, 0x350, 0x2718);
 878         rtl_write_byte(rtlpriv, 0x352, 0x1);
 879 }
 880
 881 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
 882 {
 883         struct rtl_priv *rtlpriv = rtl_priv(hw);
 884         u8 sec_reg_value;
 885
 886         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 887                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 888                   rtlpriv->sec.pairwise_enc_algorithm,
 889                   rtlpriv->sec.group_enc_algorithm));
 890
 891         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 892                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("not open "
 893                                                         "hw encryption\n"));
 894                 return;
 895         }
 896
 897         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 898
 899         if (rtlpriv->sec.use_defaultkey) {
 900                 sec_reg_value |= SCR_TxUseDK;
 901                 sec_reg_value |= SCR_RxUseDK;
 902         }
 903
 904         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 905
 906         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 907
 908         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 909                  ("The SECR-value %x\n", sec_reg_value));
 910
 911         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 912
 913 }
 914
 915 int rtl92ce_hw_init(struct ieee80211_hw *hw)
 916 {
 917         struct rtl_priv *rtlpriv = rtl_priv(hw);
 918         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 919         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 920         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 921         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 922         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 923         static bool iqk_initialized; /* initialized to false */
 924         bool rtstatus = true;
 925         bool is92c;
 926         int err;
 927         u8 tmp_u1b;
 928
 929         rtlpci->being_init_adapter = true;
 930         rtlpriv->intf_ops->disable_aspm(hw);
 931         rtstatus = _rtl92ce_init_mac(hw);
 932         if (rtstatus != true) {
 933                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
 934                 err = 1;
 935                 return err;
 936         }
 937
 938         err = rtl92c_download_fw(hw);
 939         if (err) {
 940                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 941                          ("Failed to download FW. Init HW "
 942                           "without FW now..\n"));
 943                 err = 1;
 944                 rtlhal->fw_ready = false;
 945                 return err;
 946         } else {
 947                 rtlhal->fw_ready = true;
 948         }
 949
 950         rtlhal->last_hmeboxnum = 0;
 951         rtl92ce_phy_mac_config(hw);
 952         rtl92ce_phy_bb_config(hw);
 953         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 954         rtl92c_phy_rf_config(hw);
 955         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 956                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 957         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 958                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 959         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 960         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 961         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 962         _rtl92ce_hw_configure(hw);
 963         rtl_cam_reset_all_entry(hw);
 964         rtl92ce_enable_hw_security_config(hw);
 965         ppsc->rfpwr_state = ERFON;
 966         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
 967         _rtl92ce_enable_aspm_back_door(hw);
 968         rtlpriv->intf_ops->enable_aspm(hw);
 969         if (ppsc->rfpwr_state == ERFON) {
 970                 rtl92c_phy_set_rfpath_switch(hw, 1);
 971                 if (iqk_initialized)
 972                         rtl92c_phy_iq_calibrate(hw, true);
 973                 else {
 974                         rtl92c_phy_iq_calibrate(hw, false);
 975                         iqk_initialized = true;
 976                 }
 977
 978                 rtl92c_dm_check_txpower_tracking(hw);
 979                 rtl92c_phy_lc_calibrate(hw);
 980         }
 981
 982         is92c = IS_92C_SERIAL(rtlhal->version);
 983         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
 984         if (!(tmp_u1b & BIT(0))) {
 985                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
 986                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path A\n"));
 987         }
 988
 989         if (!(tmp_u1b & BIT(1)) && is92c) {
 990                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
 991                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path B\n"));
 992         }
 993
 994         if (!(tmp_u1b & BIT(4))) {
 995                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
 996                 tmp_u1b &= 0x0F;
 997                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
 998                 udelay(10);
 999                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1000                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("under 1.5V\n"));
1001         }
1002         rtl92c_dm_init(hw);
1003         rtlpci->being_init_adapter = false;
1004         return err;
1005 }
1006
1007 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1008 {
1009         struct rtl_priv *rtlpriv = rtl_priv(hw);
1010         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1011         enum version_8192c version = VERSION_UNKNOWN;
1012         u32 value32;
1013
1014         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1015         if (value32 & TRP_VAUX_EN) {
1016                 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1017                            VERSION_A_CHIP_88C;
1018         } else {
1019                 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
1020                            VERSION_B_CHIP_88C;
1021         }
1022
1023         switch (version) {
1024         case VERSION_B_CHIP_92C:
1025                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1026                          ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
1027                 break;
1028         case VERSION_B_CHIP_88C:
1029                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1030                          ("Chip Version ID: VERSION_B_CHIP_88C.\n"));
1031                 break;
1032         case VERSION_A_CHIP_92C:
1033                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1034                          ("Chip Version ID: VERSION_A_CHIP_92C.\n"));
1035                 break;
1036         case VERSION_A_CHIP_88C:
1037                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1038                          ("Chip Version ID: VERSION_A_CHIP_88C.\n"));
1039                 break;
1040         default:
1041                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1042                          ("Chip Version ID: Unknown. Bug?\n"));
1043                 break;
1044         }
1045
1046         switch (version & 0x3) {
1047         case CHIP_88C:
1048                 rtlphy->rf_type = RF_1T1R;
1049                 break;
1050         case CHIP_92C:
1051                 rtlphy->rf_type = RF_2T2R;
1052                 break;
1053         case CHIP_92C_1T2R:
1054                 rtlphy->rf_type = RF_1T2R;
1055                 break;
1056         default:
1057                 rtlphy->rf_type = RF_1T1R;
1058                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1059                          ("ERROR RF_Type is set!!"));
1060                 break;
1061         }
1062
1063         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1064                  ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1065                   "RF_2T2R" : "RF_1T1R"));
1066
1067         return version;
1068 }
1069
1070 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1071                                      enum nl80211_iftype type)
1072 {
1073         struct rtl_priv *rtlpriv = rtl_priv(hw);
1074         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1075         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1076         bt_msr &= 0xfc;
1077
1078         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1079             type == NL80211_IFTYPE_STATION) {
1080                 _rtl92ce_stop_tx_beacon(hw);
1081                 _rtl92ce_enable_bcn_sub_func(hw);
1082         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1083                 _rtl92ce_resume_tx_beacon(hw);
1084                 _rtl92ce_disable_bcn_sub_func(hw);
1085         } else {
1086                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1087                          ("Set HW_VAR_MEDIA_STATUS: "
1088                           "No such media status(%x).\n", type));
1089         }
1090
1091         switch (type) {
1092         case NL80211_IFTYPE_UNSPECIFIED:
1093                 bt_msr |= MSR_NOLINK;
1094                 ledaction = LED_CTL_LINK;
1095                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1096                          ("Set Network type to NO LINK!\n"));
1097                 break;
1098         case NL80211_IFTYPE_ADHOC:
1099                 bt_msr |= MSR_ADHOC;
1100                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1101                          ("Set Network type to Ad Hoc!\n"));
1102                 break;
1103         case NL80211_IFTYPE_STATION:
1104                 bt_msr |= MSR_INFRA;
1105                 ledaction = LED_CTL_LINK;
1106                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1107                          ("Set Network type to STA!\n"));
1108                 break;
1109         case NL80211_IFTYPE_AP:
1110                 bt_msr |= MSR_AP;
1111                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1112                          ("Set Network type to AP!\n"));
1113                 break;
1114         default:
1115                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1116                          ("Network type %d not support!\n", type));
1117                 return 1;
1118                 break;
1119
1120         }
1121
1122         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1123         rtlpriv->cfg->ops->led_control(hw, ledaction);
1124         if ((bt_msr & 0xfc) == MSR_AP)
1125                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1126         else
1127                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1128         return 0;
1129 }
1130
1131 static void _rtl92ce_set_check_bssid(struct ieee80211_hw *hw,
1132                                      enum nl80211_iftype type)
1133 {
1134         struct rtl_priv *rtlpriv = rtl_priv(hw);
1135         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1136         u8 filterout_non_associated_bssid = false;
1137
1138         switch (type) {
1139         case NL80211_IFTYPE_ADHOC:
1140         case NL80211_IFTYPE_STATION:
1141                 filterout_non_associated_bssid = true;
1142                 break;
1143         case NL80211_IFTYPE_UNSPECIFIED:
1144         case NL80211_IFTYPE_AP:
1145         default:
1146                 break;
1147         }
1148
1149         if (filterout_non_associated_bssid == true) {
1150                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1151                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1152                                               (u8 *) (&reg_rcr));
1153                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1154         } else if (filterout_non_associated_bssid == false) {
1155                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1156                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1157                 rtlpriv->cfg->ops->set_hw_reg(hw,
1158                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1159         }
1160 }
1161
1162 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1163 {
1164         if (_rtl92ce_set_media_status(hw, type))
1165                 return -EOPNOTSUPP;
1166         _rtl92ce_set_check_bssid(hw, type);
1167         return 0;
1168 }
1169
1170 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1171 {
1172         struct rtl_priv *rtlpriv = rtl_priv(hw);
1173         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1174         u32 u4b_ac_param;
1175         u16 cw_min = le16_to_cpu(mac->ac[aci].cw_min);
1176         u16 cw_max = le16_to_cpu(mac->ac[aci].cw_max);
1177         u16 tx_op = le16_to_cpu(mac->ac[aci].tx_op);
1178
1179         rtl92c_dm_init_edca_turbo(hw);
1180         u4b_ac_param = (u32) mac->ac[aci].aifs;
1181         u4b_ac_param |= (u32) ((cw_min & 0xF) << AC_PARAM_ECW_MIN_OFFSET);
1182         u4b_ac_param |= (u32) ((cw_max & 0xF) << AC_PARAM_ECW_MAX_OFFSET);
1183         u4b_ac_param |= (u32) (tx_op << AC_PARAM_TXOP_OFFSET);
1184         RT_TRACE(rtlpriv, COMP_QOS, DBG_DMESG,
1185                  ("queue:%x, ac_param:%x aifs:%x cwmin:%x cwmax:%x txop:%x\n",
1186                   aci, u4b_ac_param, mac->ac[aci].aifs, cw_min,
1187                   cw_max, tx_op));
1188         switch (aci) {
1189         case AC1_BK:
1190                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
1191                 break;
1192         case AC0_BE:
1193                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param);
1194                 break;
1195         case AC2_VI:
1196                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, u4b_ac_param);
1197                 break;
1198         case AC3_VO:
1199                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, u4b_ac_param);
1200                 break;
1201         default:
1202                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1203                 break;
1204         }
1205 }
1206
1207 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1208 {
1209         struct rtl_priv *rtlpriv = rtl_priv(hw);
1210         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1211
1212         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1213         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1214         rtlpci->irq_enabled = true;
1215 }
1216
1217 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1218 {
1219         struct rtl_priv *rtlpriv = rtl_priv(hw);
1220         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1221
1222         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1223         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1224         rtlpci->irq_enabled = false;
1225 }
1226
1227 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1228 {
1229         struct rtl_priv *rtlpriv = rtl_priv(hw);
1230         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1231         u8 u1b_tmp;
1232
1233         rtlpriv->intf_ops->enable_aspm(hw);
1234         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1235         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1236         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1237         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1238         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1239         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1240         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1241                 rtl92c_firmware_selfreset(hw);
1242         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1243         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1244         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1245         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1246         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1247                         (u1b_tmp << 8));
1248         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1249         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1250         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1251         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1252         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1253         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1254         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1255 }
1256
1257 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1258 {
1259         struct rtl_priv *rtlpriv = rtl_priv(hw);
1260         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1261         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1262         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1263         enum nl80211_iftype opmode;
1264
1265         mac->link_state = MAC80211_NOLINK;
1266         opmode = NL80211_IFTYPE_UNSPECIFIED;
1267         _rtl92ce_set_media_status(hw, opmode);
1268         if (rtlpci->driver_is_goingto_unload ||
1269             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1270                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1271         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1272         _rtl92ce_poweroff_adapter(hw);
1273 }
1274
1275 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1276                                   u32 *p_inta, u32 *p_intb)
1277 {
1278         struct rtl_priv *rtlpriv = rtl_priv(hw);
1279         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1280
1281         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1282         rtl_write_dword(rtlpriv, ISR, *p_inta);
1283
1284         /*
1285          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1286          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1287          */
1288 }
1289
1290 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1291 {
1292
1293         struct rtl_priv *rtlpriv = rtl_priv(hw);
1294         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1295         u16 bcn_interval, atim_window;
1296
1297         bcn_interval = mac->beacon_interval;
1298         atim_window = 2;        /*FIX MERGE */
1299         rtl92ce_disable_interrupt(hw);
1300         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1301         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1302         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1303         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1304         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1305         rtl_write_byte(rtlpriv, 0x606, 0x30);
1306         rtl92ce_enable_interrupt(hw);
1307 }
1308
1309 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1310 {
1311         struct rtl_priv *rtlpriv = rtl_priv(hw);
1312         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1313         u16 bcn_interval = mac->beacon_interval;
1314
1315         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1316                  ("beacon_interval:%d\n", bcn_interval));
1317         rtl92ce_disable_interrupt(hw);
1318         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1319         rtl92ce_enable_interrupt(hw);
1320 }
1321
1322 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1323                                    u32 add_msr, u32 rm_msr)
1324 {
1325         struct rtl_priv *rtlpriv = rtl_priv(hw);
1326         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1327
1328         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1329                  ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1330         if (add_msr)
1331                 rtlpci->irq_mask[0] |= add_msr;
1332         if (rm_msr)
1333                 rtlpci->irq_mask[0] &= (~rm_msr);
1334         rtl92ce_disable_interrupt(hw);
1335         rtl92ce_enable_interrupt(hw);
1336 }
1337
1338 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1339                                                  bool autoload_fail,
1340                                                  u8 *hwinfo)
1341 {
1342         struct rtl_priv *rtlpriv = rtl_priv(hw);
1343         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1344         u8 rf_path, index, tempval;
1345         u16 i;
1346
1347         for (rf_path = 0; rf_path < 2; rf_path++) {
1348                 for (i = 0; i < 3; i++) {
1349                         if (!autoload_fail) {
1350                                 rtlefuse->
1351                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1352                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1353                                 rtlefuse->
1354                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1355                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1356                                            i];
1357                         } else {
1358                                 rtlefuse->
1359                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1360                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1361                                 rtlefuse->
1362                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1363                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1364                         }
1365                 }
1366         }
1367
1368         for (i = 0; i < 3; i++) {
1369                 if (!autoload_fail)
1370                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1371                 else
1372                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1373                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1374                     (tempval & 0xf);
1375                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1376                     ((tempval & 0xf0) >> 4);
1377         }
1378
1379         for (rf_path = 0; rf_path < 2; rf_path++)
1380                 for (i = 0; i < 3; i++)
1381                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1382                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1383                                  i,
1384                                  rtlefuse->
1385                                  eeprom_chnlarea_txpwr_cck[rf_path][i]));
1386         for (rf_path = 0; rf_path < 2; rf_path++)
1387                 for (i = 0; i < 3; i++)
1388                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1389                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1390                                  rf_path, i,
1391                                  rtlefuse->
1392                                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
1393         for (rf_path = 0; rf_path < 2; rf_path++)
1394                 for (i = 0; i < 3; i++)
1395                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1396                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1397                                  rf_path, i,
1398                                  rtlefuse->
1399                                  eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1400                                  [i]));
1401
1402         for (rf_path = 0; rf_path < 2; rf_path++) {
1403                 for (i = 0; i < 14; i++) {
1404                         index = _rtl92c_get_chnl_group((u8) i);
1405
1406                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1407                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1408                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1409                             rtlefuse->
1410                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1411
1412                         if ((rtlefuse->
1413                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1414                              rtlefuse->
1415                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1416                             > 0) {
1417                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1418                                     rtlefuse->
1419                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1420                                     [index] -
1421                                     rtlefuse->
1422                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1423                                     [index];
1424                         } else {
1425                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1426                         }
1427                 }
1428
1429                 for (i = 0; i < 14; i++) {
1430                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1431                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1432                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1433                                  rtlefuse->txpwrlevel_cck[rf_path][i],
1434                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1435                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1436                 }
1437         }
1438
1439         for (i = 0; i < 3; i++) {
1440                 if (!autoload_fail) {
1441                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1442                             hwinfo[EEPROM_TXPWR_GROUP + i];
1443                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1444                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1445                 } else {
1446                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1447                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1448                 }
1449         }
1450
1451         for (rf_path = 0; rf_path < 2; rf_path++) {
1452                 for (i = 0; i < 14; i++) {
1453                         index = _rtl92c_get_chnl_group((u8) i);
1454
1455                         if (rf_path == RF90_PATH_A) {
1456                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1457                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1458                                      & 0xf);
1459                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1460                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1461                                      & 0xf);
1462                         } else if (rf_path == RF90_PATH_B) {
1463                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1464                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1465                                       & 0xf0) >> 4);
1466                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1467                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1468                                       & 0xf0) >> 4);
1469                         }
1470
1471                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1472                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1473                                  rf_path, i,
1474                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
1475                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1476                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1477                                  rf_path, i,
1478                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
1479                 }
1480         }
1481
1482         for (i = 0; i < 14; i++) {
1483                 index = _rtl92c_get_chnl_group((u8) i);
1484
1485                 if (!autoload_fail)
1486                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1487                 else
1488                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1489
1490                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1491                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1492                     ((tempval >> 4) & 0xF);
1493
1494                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1495                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1496
1497                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1498                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1499
1500                 index = _rtl92c_get_chnl_group((u8) i);
1501
1502                 if (!autoload_fail)
1503                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1504                 else
1505                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1506
1507                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1508                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1509                     ((tempval >> 4) & 0xF);
1510         }
1511
1512         rtlefuse->legacy_ht_txpowerdiff =
1513             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1514
1515         for (i = 0; i < 14; i++)
1516                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1517                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1518                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1519         for (i = 0; i < 14; i++)
1520                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1521                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1522                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1523         for (i = 0; i < 14; i++)
1524                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1525                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1526                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1527         for (i = 0; i < 14; i++)
1528                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1529                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1530                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1531
1532         if (!autoload_fail)
1533                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1534         else
1535                 rtlefuse->eeprom_regulatory = 0;
1536         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1537                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1538
1539         if (!autoload_fail) {
1540                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1541                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1542         } else {
1543                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1544                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1545         }
1546         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1547                 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1548                  rtlefuse->eeprom_tssi[RF90_PATH_A],
1549                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
1550
1551         if (!autoload_fail)
1552                 tempval = hwinfo[EEPROM_THERMAL_METER];
1553         else
1554                 tempval = EEPROM_DEFAULT_THERMALMETER;
1555         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1556
1557         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1558                 rtlefuse->apk_thermalmeterignore = true;
1559
1560         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1561         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1562                 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1563 }
1564
1565 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1566 {
1567         struct rtl_priv *rtlpriv = rtl_priv(hw);
1568         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1569         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1570         u16 i, usvalue;
1571         u8 hwinfo[HWSET_MAX_SIZE];
1572         u16 eeprom_id;
1573
1574         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1575                 rtl_efuse_shadow_map_update(hw);
1576
1577                 memcpy((void *)hwinfo,
1578                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1579                        HWSET_MAX_SIZE);
1580         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1581                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1582                          ("RTL819X Not boot from eeprom, check it !!"));
1583         }
1584
1585         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
1586                       hwinfo, HWSET_MAX_SIZE);
1587
1588         eeprom_id = *((u16 *)&hwinfo[0]);
1589         if (eeprom_id != RTL8190_EEPROM_ID) {
1590                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1591                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1592                 rtlefuse->autoload_failflag = true;
1593         } else {
1594                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1595                 rtlefuse->autoload_failflag = false;
1596         }
1597
1598         if (rtlefuse->autoload_failflag == true)
1599                 return;
1600
1601         for (i = 0; i < 6; i += 2) {
1602                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1603                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1604         }
1605
1606         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1607                  (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1608
1609         _rtl92ce_read_txpower_info_from_hwpg(hw,
1610                                              rtlefuse->autoload_failflag,
1611                                              hwinfo);
1612
1613         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1614         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1615         rtlefuse->txpwr_fromeprom = true;
1616         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1617
1618         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1619                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1620
1621         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1622                 switch (rtlefuse->eeprom_oemid) {
1623                 case EEPROM_CID_DEFAULT:
1624                         if (rtlefuse->eeprom_did == 0x8176) {
1625                                 if ((rtlefuse->eeprom_svid == 0x103C &&
1626                                      rtlefuse->eeprom_smid == 0x1629))
1627                                         rtlhal->oem_id = RT_CID_819x_HP;
1628                                 else
1629                                         rtlhal->oem_id = RT_CID_DEFAULT;
1630                         } else {
1631                                 rtlhal->oem_id = RT_CID_DEFAULT;
1632                         }
1633                         break;
1634                 case EEPROM_CID_TOSHIBA:
1635                         rtlhal->oem_id = RT_CID_TOSHIBA;
1636                         break;
1637                 case EEPROM_CID_QMI:
1638                         rtlhal->oem_id = RT_CID_819x_QMI;
1639                         break;
1640                 case EEPROM_CID_WHQL:
1641                 default:
1642                         rtlhal->oem_id = RT_CID_DEFAULT;
1643                         break;
1644
1645                 }
1646         }
1647
1648 }
1649
1650 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1651 {
1652         struct rtl_priv *rtlpriv = rtl_priv(hw);
1653         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1654         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1655
1656         switch (rtlhal->oem_id) {
1657         case RT_CID_819x_HP:
1658                 pcipriv->ledctl.led_opendrain = true;
1659                 break;
1660         case RT_CID_819x_Lenovo:
1661         case RT_CID_DEFAULT:
1662         case RT_CID_TOSHIBA:
1663         case RT_CID_CCX:
1664         case RT_CID_819x_Acer:
1665         case RT_CID_WHQL:
1666         default:
1667                 break;
1668         }
1669         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1670                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
1671 }
1672
1673 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1674 {
1675         struct rtl_priv *rtlpriv = rtl_priv(hw);
1676         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1677         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1678         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1679         u8 tmp_u1b;
1680
1681         rtlhal->version = _rtl92ce_read_chip_version(hw);
1682         if (get_rf_type(rtlphy) == RF_1T1R)
1683                 rtlpriv->dm.rfpath_rxenable[0] = true;
1684         else
1685                 rtlpriv->dm.rfpath_rxenable[0] =
1686                     rtlpriv->dm.rfpath_rxenable[1] = true;
1687         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
1688                                                 rtlhal->version));
1689         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1690         if (tmp_u1b & BIT(4)) {
1691                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1692                 rtlefuse->epromtype = EEPROM_93C46;
1693         } else {
1694                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1695                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1696         }
1697         if (tmp_u1b & BIT(5)) {
1698                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1699                 rtlefuse->autoload_failflag = false;
1700                 _rtl92ce_read_adapter_info(hw);
1701         } else {
1702                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1703         }
1704
1705         _rtl92ce_hal_customized_behavior(hw);
1706 }
1707
1708 void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw)
1709 {
1710         struct rtl_priv *rtlpriv = rtl_priv(hw);
1711         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1712         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1713
1714         u32 ratr_value = (u32) mac->basic_rates;
1715         u8 *mcsrate = mac->mcs;
1716         u8 ratr_index = 0;
1717         u8 nmode = mac->ht_enable;
1718         u8 mimo_ps = 1;
1719         u16 shortgi_rate;
1720         u32 tmp_ratr_value;
1721         u8 curtxbw_40mhz = mac->bw_40;
1722         u8 curshortgi_40mhz = mac->sgi_40;
1723         u8 curshortgi_20mhz = mac->sgi_20;
1724         enum wireless_mode wirelessmode = mac->mode;
1725
1726         ratr_value |= ((*(u16 *) (mcsrate))) << 12;
1727
1728         switch (wirelessmode) {
1729         case WIRELESS_MODE_B:
1730                 if (ratr_value & 0x0000000c)
1731                         ratr_value &= 0x0000000d;
1732                 else
1733                         ratr_value &= 0x0000000f;
1734                 break;
1735         case WIRELESS_MODE_G:
1736                 ratr_value &= 0x00000FF5;
1737                 break;
1738         case WIRELESS_MODE_N_24G:
1739         case WIRELESS_MODE_N_5G:
1740                 nmode = 1;
1741                 if (mimo_ps == 0) {
1742                         ratr_value &= 0x0007F005;
1743                 } else {
1744                         u32 ratr_mask;
1745
1746                         if (get_rf_type(rtlphy) == RF_1T2R ||
1747                             get_rf_type(rtlphy) == RF_1T1R)
1748                                 ratr_mask = 0x000ff005;
1749                         else
1750                                 ratr_mask = 0x0f0ff005;
1751
1752                         ratr_value &= ratr_mask;
1753                 }
1754                 break;
1755         default:
1756                 if (rtlphy->rf_type == RF_1T2R)
1757                         ratr_value &= 0x000ff0ff;
1758                 else
1759                         ratr_value &= 0x0f0ff0ff;
1760
1761                 break;
1762         }
1763
1764         ratr_value &= 0x0FFFFFFF;
1765
1766         if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || (!curtxbw_40mhz &&
1767                        curshortgi_20mhz))) {
1768
1769                 ratr_value |= 0x10000000;
1770                 tmp_ratr_value = (ratr_value >> 12);
1771
1772                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1773                         if ((1 << shortgi_rate) & tmp_ratr_value)
1774                                 break;
1775                 }
1776
1777                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1778                     (shortgi_rate << 4) | (shortgi_rate);
1779         }
1780
1781         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1782
1783         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1784                  ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1785 }
1786
1787 void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
1788 {
1789         struct rtl_priv *rtlpriv = rtl_priv(hw);
1790         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1791         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1792         u32 ratr_bitmap = (u32) mac->basic_rates;
1793         u8 *p_mcsrate = mac->mcs;
1794         u8 ratr_index;
1795         u8 curtxbw_40mhz = mac->bw_40;
1796         u8 curshortgi_40mhz = mac->sgi_40;
1797         u8 curshortgi_20mhz = mac->sgi_20;
1798         enum wireless_mode wirelessmode = mac->mode;
1799         bool shortgi = false;
1800         u8 rate_mask[5];
1801         u8 macid = 0;
1802         u8 mimops = 1;
1803
1804         ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
1805         switch (wirelessmode) {
1806         case WIRELESS_MODE_B:
1807                 ratr_index = RATR_INX_WIRELESS_B;
1808                 if (ratr_bitmap & 0x0000000c)
1809                         ratr_bitmap &= 0x0000000d;
1810                 else
1811                         ratr_bitmap &= 0x0000000f;
1812                 break;
1813         case WIRELESS_MODE_G:
1814                 ratr_index = RATR_INX_WIRELESS_GB;
1815
1816                 if (rssi_level == 1)
1817                         ratr_bitmap &= 0x00000f00;
1818                 else if (rssi_level == 2)
1819                         ratr_bitmap &= 0x00000ff0;
1820                 else
1821                         ratr_bitmap &= 0x00000ff5;
1822                 break;
1823         case WIRELESS_MODE_A:
1824                 ratr_index = RATR_INX_WIRELESS_A;
1825                 ratr_bitmap &= 0x00000ff0;
1826                 break;
1827         case WIRELESS_MODE_N_24G:
1828         case WIRELESS_MODE_N_5G:
1829                 ratr_index = RATR_INX_WIRELESS_NGB;
1830
1831                 if (mimops == 0) {
1832                         if (rssi_level == 1)
1833                                 ratr_bitmap &= 0x00070000;
1834                         else if (rssi_level == 2)
1835                                 ratr_bitmap &= 0x0007f000;
1836                         else
1837                                 ratr_bitmap &= 0x0007f005;
1838                 } else {
1839                         if (rtlphy->rf_type == RF_1T2R ||
1840                             rtlphy->rf_type == RF_1T1R) {
1841                                 if (curtxbw_40mhz) {
1842                                         if (rssi_level == 1)
1843                                                 ratr_bitmap &= 0x000f0000;
1844                                         else if (rssi_level == 2)
1845                                                 ratr_bitmap &= 0x000ff000;
1846                                         else
1847                                                 ratr_bitmap &= 0x000ff015;
1848                                 } else {
1849                                         if (rssi_level == 1)
1850                                                 ratr_bitmap &= 0x000f0000;
1851                                         else if (rssi_level == 2)
1852                                                 ratr_bitmap &= 0x000ff000;
1853                                         else
1854                                                 ratr_bitmap &= 0x000ff005;
1855                                 }
1856                         } else {
1857                                 if (curtxbw_40mhz) {
1858                                         if (rssi_level == 1)
1859                                                 ratr_bitmap &= 0x0f0f0000;
1860                                         else if (rssi_level == 2)
1861                                                 ratr_bitmap &= 0x0f0ff000;
1862                                         else
1863                                                 ratr_bitmap &= 0x0f0ff015;
1864                                 } else {
1865                                         if (rssi_level == 1)
1866                                                 ratr_bitmap &= 0x0f0f0000;
1867                                         else if (rssi_level == 2)
1868                                                 ratr_bitmap &= 0x0f0ff000;
1869                                         else
1870                                                 ratr_bitmap &= 0x0f0ff005;
1871                                 }
1872                         }
1873                 }
1874
1875                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1876                     (!curtxbw_40mhz && curshortgi_20mhz)) {
1877
1878                         if (macid == 0)
1879                                 shortgi = true;
1880                         else if (macid == 1)
1881                                 shortgi = false;
1882                 }
1883                 break;
1884         default:
1885                 ratr_index = RATR_INX_WIRELESS_NGB;
1886
1887                 if (rtlphy->rf_type == RF_1T2R)
1888                         ratr_bitmap &= 0x000ff0ff;
1889                 else
1890                         ratr_bitmap &= 0x0f0ff0ff;
1891                 break;
1892         }
1893         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1894                  ("ratr_bitmap :%x\n", ratr_bitmap));
1895         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
1896                                        (ratr_index << 28);
1897         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1898         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
1899                                                  "ratr_val:%x, %x:%x:%x:%x:%x\n",
1900                                                  ratr_index, ratr_bitmap,
1901                                                  rate_mask[0], rate_mask[1],
1902                                                  rate_mask[2], rate_mask[3],
1903                                                  rate_mask[4]));
1904         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1905 }
1906
1907 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1908 {
1909         struct rtl_priv *rtlpriv = rtl_priv(hw);
1910         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1911         u16 sifs_timer;
1912
1913         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1914                                       (u8 *)&mac->slot_time);
1915         if (!mac->ht_enable)
1916                 sifs_timer = 0x0a0a;
1917         else
1918                 sifs_timer = 0x1010;
1919         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1920 }
1921
1922 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
1923 {
1924         struct rtl_priv *rtlpriv = rtl_priv(hw);
1925         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1926         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1927         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
1928         u8 u1tmp;
1929         bool actuallyset = false;
1930         unsigned long flag;
1931
1932         if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
1933                 return false;
1934
1935         if (ppsc->swrf_processing)
1936                 return false;
1937
1938         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1939         if (ppsc->rfchange_inprogress) {
1940                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1941                 return false;
1942         } else {
1943                 ppsc->rfchange_inprogress = true;
1944                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1945         }
1946
1947         cur_rfstate = ppsc->rfpwr_state;
1948
1949         if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
1950             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) {
1951                 rtlpriv->intf_ops->disable_aspm(hw);
1952                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
1953         }
1954
1955         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1956                        REG_MAC_PINMUX_CFG)&~(BIT(3)));
1957
1958         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1959         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1960
1961         if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
1962                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1963                          ("GPIOChangeRF  - HW Radio ON, RF ON\n"));
1964
1965                 e_rfpowerstate_toset = ERFON;
1966                 ppsc->hwradiooff = false;
1967                 actuallyset = true;
1968         } else if ((ppsc->hwradiooff == false)
1969                    && (e_rfpowerstate_toset == ERFOFF)) {
1970                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1971                          ("GPIOChangeRF  - HW Radio OFF, RF OFF\n"));
1972
1973                 e_rfpowerstate_toset = ERFOFF;
1974                 ppsc->hwradiooff = true;
1975                 actuallyset = true;
1976         }
1977
1978         if (actuallyset) {
1979                 if (e_rfpowerstate_toset == ERFON) {
1980                         if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
1981                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) {
1982                                 rtlpriv->intf_ops->disable_aspm(hw);
1983                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
1984                         }
1985                 }
1986
1987                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1988                 ppsc->rfchange_inprogress = false;
1989                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1990
1991                 if (e_rfpowerstate_toset == ERFOFF) {
1992                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) {
1993                                 rtlpriv->intf_ops->enable_aspm(hw);
1994                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
1995                         }
1996                 }
1997
1998         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
1999                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2000                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2001
2002                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) {
2003                         rtlpriv->intf_ops->enable_aspm(hw);
2004                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2005                 }
2006
2007                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2008                 ppsc->rfchange_inprogress = false;
2009                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2010         } else {
2011                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2012                 ppsc->rfchange_inprogress = false;
2013                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2014         }
2015
2016         *valid = 1;
2017         return !ppsc->hwradiooff;
2018
2019 }
2020
2021 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2022                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2023                      bool is_wepkey, bool clear_all)
2024 {
2025         struct rtl_priv *rtlpriv = rtl_priv(hw);
2026         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2027         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2028         u8 *macaddr = p_macaddr;
2029         u32 entry_id = 0;
2030         bool is_pairwise = false;
2031
2032         static u8 cam_const_addr[4][6] = {
2033                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2034                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2035                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2036                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2037         };
2038         static u8 cam_const_broad[] = {
2039                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2040         };
2041
2042         if (clear_all) {
2043                 u8 idx = 0;
2044                 u8 cam_offset = 0;
2045                 u8 clear_number = 5;
2046
2047                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2048
2049                 for (idx = 0; idx < clear_number; idx++) {
2050                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2051                         rtl_cam_empty_entry(hw, cam_offset + idx);
2052
2053                         if (idx < 5) {
2054                                 memset(rtlpriv->sec.key_buf[idx], 0,
2055                                        MAX_KEY_LEN);
2056                                 rtlpriv->sec.key_len[idx] = 0;
2057                         }
2058                 }
2059
2060         } else {
2061                 switch (enc_algo) {
2062                 case WEP40_ENCRYPTION:
2063                         enc_algo = CAM_WEP40;
2064                         break;
2065                 case WEP104_ENCRYPTION:
2066                         enc_algo = CAM_WEP104;
2067                         break;
2068                 case TKIP_ENCRYPTION:
2069                         enc_algo = CAM_TKIP;
2070                         break;
2071                 case AESCCMP_ENCRYPTION:
2072                         enc_algo = CAM_AES;
2073                         break;
2074                 default:
2075                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2076                                         "not process\n"));
2077                         enc_algo = CAM_TKIP;
2078                         break;
2079                 }
2080
2081                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2082                         macaddr = cam_const_addr[key_index];
2083                         entry_id = key_index;
2084                 } else {
2085                         if (is_group) {
2086                                 macaddr = cam_const_broad;
2087                                 entry_id = key_index;
2088                         } else {
2089                                 key_index = PAIRWISE_KEYIDX;
2090                                 entry_id = CAM_PAIRWISE_KEY_POSITION;
2091                                 is_pairwise = true;
2092                         }
2093                 }
2094
2095                 if (rtlpriv->sec.key_len[key_index] == 0) {
2096                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2097                                  ("delete one entry\n"));
2098                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2099                 } else {
2100                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2101                                  ("The insert KEY length is %d\n",
2102                                   rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2103                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2104                                  ("The insert KEY  is %x %x\n",
2105                                   rtlpriv->sec.key_buf[0][0],
2106                                   rtlpriv->sec.key_buf[0][1]));
2107
2108                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2109                                  ("add one entry\n"));
2110                         if (is_pairwise) {
2111                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2112                                               "Pairwiase Key content :",
2113                                               rtlpriv->sec.pairwise_key,
2114                                               rtlpriv->sec.
2115                                               key_len[PAIRWISE_KEYIDX]);
2116
2117                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2118                                          ("set Pairwiase key\n"));
2119
2120                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2121                                                       entry_id, enc_algo,
2122                                                       CAM_CONFIG_NO_USEDK,
2123                                                       rtlpriv->sec.
2124                                                       key_buf[key_index]);
2125                         } else {
2126                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2127                                          ("set group key\n"));
2128
2129                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2130                                         rtl_cam_add_one_entry(hw,
2131                                                 rtlefuse->dev_addr,
2132                                                 PAIRWISE_KEYIDX,
2133                                                 CAM_PAIRWISE_KEY_POSITION,
2134                                                 enc_algo,
2135                                                 CAM_CONFIG_NO_USEDK,
2136                                                 rtlpriv->sec.key_buf
2137                                                 [entry_id]);
2138                                 }
2139
2140                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2141                                                 entry_id, enc_algo,
2142                                                 CAM_CONFIG_NO_USEDK,
2143                                                 rtlpriv->sec.key_buf[entry_id]);
2144                         }
2145
2146                 }
2147         }
2148 }