drivers/net/wireless/rtl818x/rtl8180_dev.c

   1
   2 /*
   3  * Linux device driver for RTL8180 / RTL8185
   4  *
   5  * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
   6  * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
   7  *
   8  * Based on the r8180 driver, which is:
   9  * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
  10  *
  11  * Thanks to Realtek for their support!
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/pci.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/eeprom_93cx6.h>
  24 #include <net/mac80211.h>
  25
  26 #include "rtl8180.h"
  27 #include "rtl8180_rtl8225.h"
  28 #include "rtl8180_sa2400.h"
  29 #include "rtl8180_max2820.h"
  30 #include "rtl8180_grf5101.h"
  31
  32 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  33 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
  34 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
  35 MODULE_LICENSE("GPL");
  36
  37 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
  38         /* rtl8185 */
  39         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
  40         { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
  41         { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
  42
  43         /* rtl8180 */
  44         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
  45         { PCI_DEVICE(0x1799, 0x6001) },
  46         { PCI_DEVICE(0x1799, 0x6020) },
  47         { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
  48         { }
  49 };
  50
  51 MODULE_DEVICE_TABLE(pci, rtl8180_table);
  52
  53 static const struct ieee80211_rate rtl818x_rates[] = {
  54         { .bitrate = 10, .hw_value = 0, },
  55         { .bitrate = 20, .hw_value = 1, },
  56         { .bitrate = 55, .hw_value = 2, },
  57         { .bitrate = 110, .hw_value = 3, },
  58         { .bitrate = 60, .hw_value = 4, },
  59         { .bitrate = 90, .hw_value = 5, },
  60         { .bitrate = 120, .hw_value = 6, },
  61         { .bitrate = 180, .hw_value = 7, },
  62         { .bitrate = 240, .hw_value = 8, },
  63         { .bitrate = 360, .hw_value = 9, },
  64         { .bitrate = 480, .hw_value = 10, },
  65         { .bitrate = 540, .hw_value = 11, },
  66 };
  67
  68 static const struct ieee80211_channel rtl818x_channels[] = {
  69         { .center_freq = 2412 },
  70         { .center_freq = 2417 },
  71         { .center_freq = 2422 },
  72         { .center_freq = 2427 },
  73         { .center_freq = 2432 },
  74         { .center_freq = 2437 },
  75         { .center_freq = 2442 },
  76         { .center_freq = 2447 },
  77         { .center_freq = 2452 },
  78         { .center_freq = 2457 },
  79         { .center_freq = 2462 },
  80         { .center_freq = 2467 },
  81         { .center_freq = 2472 },
  82         { .center_freq = 2484 },
  83 };
  84
  85
  86 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
  87 {
  88         struct rtl8180_priv *priv = dev->priv;
  89         int i = 10;
  90         u32 buf;
  91
  92         buf = (data << 8) | addr;
  93
  94         rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
  95         while (i--) {
  96                 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
  97                 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
  98                         return;
  99         }
 100 }
 101
 102 static void rtl8180_handle_tx(struct ieee80211_hw *dev)
 103 {
 104         struct rtl8180_priv *priv = dev->priv;
 105         struct rtl8180_tx_ring *ring;
 106         int prio;
 107
 108         spin_lock(&priv->lock);
 109
 110         for (prio = 3; prio >= 0; prio--) {
 111                 ring = &priv->tx_ring[prio];
 112
 113                 while (skb_queue_len(&ring->queue)) {
 114                         struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
 115                         struct sk_buff *skb;
 116                         struct ieee80211_tx_info *info;
 117                         u32 flags = le32_to_cpu(entry->flags);
 118
 119                         if (flags & RTL818X_TX_DESC_FLAG_OWN)
 120                                 break;
 121
 122                         ring->idx = (ring->idx + 1) % ring->entries;
 123                         skb = __skb_dequeue(&ring->queue);
 124                         pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
 125                                          skb->len, PCI_DMA_TODEVICE);
 126
 127                         info = IEEE80211_SKB_CB(skb);
 128                         ieee80211_tx_info_clear_status(info);
 129
 130                         if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
 131                             (flags & RTL818X_TX_DESC_FLAG_TX_OK))
 132                                 info->flags |= IEEE80211_TX_STAT_ACK;
 133
 134                         info->status.rates[0].count = (flags & 0xFF) + 1;
 135                         info->status.rates[1].idx = -1;
 136
 137                         ieee80211_tx_status(dev, skb);
 138                         if (ring->entries - skb_queue_len(&ring->queue) == 2)
 139                                 ieee80211_wake_queue(dev, prio);
 140                 }
 141         }
 142
 143         spin_unlock(&priv->lock);
 144 }
 145
 146 static int rtl8180_poll(struct ieee80211_hw *dev, int budget)
 147 {
 148         struct rtl8180_priv *priv = dev->priv;
 149         unsigned int count = 0;
 150         u8 signal, agc, sq;
 151
 152         /* handle pending Tx queue cleanup */
 153         rtl8180_handle_tx(dev);
 154
 155         while (count++ < budget) {
 156                 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
 157                 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
 158                 u32 flags = le32_to_cpu(entry->flags);
 159
 160                 if (flags & RTL818X_RX_DESC_FLAG_OWN)
 161                         break;
 162
 163                 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
 164                                       RTL818X_RX_DESC_FLAG_FOF |
 165                                       RTL818X_RX_DESC_FLAG_RX_ERR)))
 166                         goto done;
 167                 else {
 168                         u32 flags2 = le32_to_cpu(entry->flags2);
 169                         struct ieee80211_rx_status rx_status = {0};
 170                         struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
 171
 172                         if (unlikely(!new_skb))
 173                                 goto done;
 174
 175                         pci_unmap_single(priv->pdev,
 176                                          *((dma_addr_t *)skb->cb),
 177                                          MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 178                         skb_put(skb, flags & 0xFFF);
 179
 180                         rx_status.antenna = (flags2 >> 15) & 1;
 181                         rx_status.rate_idx = (flags >> 20) & 0xF;
 182                         agc = (flags2 >> 17) & 0x7F;
 183                         if (priv->r8185) {
 184                                 if (rx_status.rate_idx > 3)
 185                                         signal = 90 - clamp_t(u8, agc, 25, 90);
 186                                 else
 187                                         signal = 95 - clamp_t(u8, agc, 30, 95);
 188                         } else {
 189                                 sq = flags2 & 0xff;
 190                                 signal = priv->rf->calc_rssi(agc, sq);
 191                         }
 192                         rx_status.signal = signal;
 193                         rx_status.freq = dev->conf.channel->center_freq;
 194                         rx_status.band = dev->conf.channel->band;
 195                         rx_status.mactime = le64_to_cpu(entry->tsft);
 196                         rx_status.flag |= RX_FLAG_TSFT;
 197                         if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
 198                                 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
 199
 200                         memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
 201                         ieee80211_rx(dev, skb);
 202
 203                         skb = new_skb;
 204                         priv->rx_buf[priv->rx_idx] = skb;
 205                         *((dma_addr_t *) skb->cb) =
 206                                 pci_map_single(priv->pdev, skb_tail_pointer(skb),
 207                                                MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 208                 }
 209
 210         done:
 211                 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
 212                 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
 213                                            MAX_RX_SIZE);
 214                 if (priv->rx_idx == 31)
 215                         entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
 216                 priv->rx_idx = (priv->rx_idx + 1) % 32;
 217         }
 218
 219         if (count < budget) {
 220                 /* disable polling */
 221                 ieee80211_napi_complete(dev);
 222
 223                 /* enable interrupts */
 224                 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
 225         }
 226
 227         return count;
 228 }
 229
 230 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
 231 {
 232         struct ieee80211_hw *dev = dev_id;
 233         struct rtl8180_priv *priv = dev->priv;
 234         u16 reg;
 235
 236         reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
 237         if (unlikely(reg == 0xFFFF))
 238                 return IRQ_HANDLED;
 239
 240         rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
 241
 242         /* disable interrupts */
 243         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
 244
 245         /* enable polling */
 246         ieee80211_napi_schedule(dev);
 247
 248         return IRQ_HANDLED;
 249 }
 250
 251 static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
 252 {
 253         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 254         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
 255         struct rtl8180_priv *priv = dev->priv;
 256         struct rtl8180_tx_ring *ring;
 257         struct rtl8180_tx_desc *entry;
 258         unsigned int idx, prio;
 259         dma_addr_t mapping;
 260         u32 tx_flags;
 261         u8 rc_flags;
 262         u16 plcp_len = 0;
 263         __le16 rts_duration = 0;
 264
 265         prio = skb_get_queue_mapping(skb);
 266         ring = &priv->tx_ring[prio];
 267
 268         mapping = pci_map_single(priv->pdev, skb->data,
 269                                  skb->len, PCI_DMA_TODEVICE);
 270
 271         tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
 272                    RTL818X_TX_DESC_FLAG_LS |
 273                    (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
 274                    skb->len;
 275
 276         if (priv->r8185)
 277                 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
 278                             RTL818X_TX_DESC_FLAG_NO_ENC;
 279
 280         rc_flags = info->control.rates[0].flags;
 281         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
 282                 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
 283                 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
 284         } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
 285                 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
 286                 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
 287         }
 288
 289         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
 290                 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
 291                                                       info);
 292
 293         if (!priv->r8185) {
 294                 unsigned int remainder;
 295
 296                 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
 297                                 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
 298                 remainder = (16 * (skb->len + 4)) %
 299                             ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
 300                 if (remainder <= 6)
 301                         plcp_len |= 1 << 15;
 302         }
 303
 304         spin_lock(&priv->lock);
 305
 306         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
 307                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
 308                         priv->seqno += 0x10;
 309                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
 310                 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
 311         }
 312
 313         idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
 314         entry = &ring->desc[idx];
 315
 316         entry->rts_duration = rts_duration;
 317         entry->plcp_len = cpu_to_le16(plcp_len);
 318         entry->tx_buf = cpu_to_le32(mapping);
 319         entry->frame_len = cpu_to_le32(skb->len);
 320         entry->flags2 = info->control.rates[1].idx >= 0 ?
 321                 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
 322         entry->retry_limit = info->control.rates[0].count;
 323         entry->flags = cpu_to_le32(tx_flags);
 324         __skb_queue_tail(&ring->queue, skb);
 325         if (ring->entries - skb_queue_len(&ring->queue) < 2)
 326                 ieee80211_stop_queue(dev, prio);
 327
 328         spin_unlock(&priv->lock);
 329
 330         rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
 331
 332         return 0;
 333 }
 334
 335 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
 336 {
 337         u8 reg;
 338
 339         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 340         reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
 341         rtl818x_iowrite8(priv, &priv->map->CONFIG3,
 342                  reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
 343         rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
 344         rtl818x_iowrite8(priv, &priv->map->CONFIG3,
 345                  reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
 346         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 347 }
 348
 349 static int rtl8180_init_hw(struct ieee80211_hw *dev)
 350 {
 351         struct rtl8180_priv *priv = dev->priv;
 352         u16 reg;
 353
 354         rtl818x_iowrite8(priv, &priv->map->CMD, 0);
 355         rtl818x_ioread8(priv, &priv->map->CMD);
 356         msleep(10);
 357
 358         /* reset */
 359         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
 360         rtl818x_ioread8(priv, &priv->map->CMD);
 361
 362         reg = rtl818x_ioread8(priv, &priv->map->CMD);
 363         reg &= (1 << 1);
 364         reg |= RTL818X_CMD_RESET;
 365         rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
 366         rtl818x_ioread8(priv, &priv->map->CMD);
 367         msleep(200);
 368
 369         /* check success of reset */
 370         if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
 371                 wiphy_err(dev->wiphy, "reset timeout!\n");
 372                 return -ETIMEDOUT;
 373         }
 374
 375         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
 376         rtl818x_ioread8(priv, &priv->map->CMD);
 377         msleep(200);
 378
 379         if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
 380                 /* For cardbus */
 381                 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
 382                 reg |= 1 << 1;
 383                 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
 384                 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
 385                 reg |= (1 << 15) | (1 << 14) | (1 << 4);
 386                 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
 387         }
 388
 389         rtl818x_iowrite8(priv, &priv->map->MSR, 0);
 390
 391         if (!priv->r8185)
 392                 rtl8180_set_anaparam(priv, priv->anaparam);
 393
 394         rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
 395         rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
 396         rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
 397         rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
 398         rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
 399
 400         /* TODO: necessary? specs indicate not */
 401         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 402         reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
 403         rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
 404         if (priv->r8185) {
 405                 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
 406                 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
 407         }
 408         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 409
 410         /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
 411
 412         /* TODO: turn off hw wep on rtl8180 */
 413
 414         rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
 415
 416         if (priv->r8185) {
 417                 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
 418                 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
 419                 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
 420
 421                 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
 422
 423                 /* TODO: set ClkRun enable? necessary? */
 424                 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
 425                 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
 426                 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 427                 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
 428                 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
 429                 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 430         } else {
 431                 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
 432                 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
 433
 434                 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
 435                 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
 436         }
 437
 438         priv->rf->init(dev);
 439         if (priv->r8185)
 440                 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
 441         return 0;
 442 }
 443
 444 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
 445 {
 446         struct rtl8180_priv *priv = dev->priv;
 447         struct rtl8180_rx_desc *entry;
 448         int i;
 449
 450         priv->rx_ring = pci_alloc_consistent(priv->pdev,
 451                                              sizeof(*priv->rx_ring) * 32,
 452                                              &priv->rx_ring_dma);
 453
 454         if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
 455                 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
 456                 return -ENOMEM;
 457         }
 458
 459         memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
 460         priv->rx_idx = 0;
 461
 462         for (i = 0; i < 32; i++) {
 463                 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
 464                 dma_addr_t *mapping;
 465                 entry = &priv->rx_ring[i];
 466                 if (!skb)
 467                         return 0;
 468
 469                 priv->rx_buf[i] = skb;
 470                 mapping = (dma_addr_t *)skb->cb;
 471                 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
 472                                           MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 473                 entry->rx_buf = cpu_to_le32(*mapping);
 474                 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
 475                                            MAX_RX_SIZE);
 476         }
 477         entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
 478         return 0;
 479 }
 480
 481 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
 482 {
 483         struct rtl8180_priv *priv = dev->priv;
 484         int i;
 485
 486         for (i = 0; i < 32; i++) {
 487                 struct sk_buff *skb = priv->rx_buf[i];
 488                 if (!skb)
 489                         continue;
 490
 491                 pci_unmap_single(priv->pdev,
 492                                  *((dma_addr_t *)skb->cb),
 493                                  MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 494                 kfree_skb(skb);
 495         }
 496
 497         pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
 498                             priv->rx_ring, priv->rx_ring_dma);
 499         priv->rx_ring = NULL;
 500 }
 501
 502 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
 503                                 unsigned int prio, unsigned int entries)
 504 {
 505         struct rtl8180_priv *priv = dev->priv;
 506         struct rtl8180_tx_desc *ring;
 507         dma_addr_t dma;
 508         int i;
 509
 510         ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
 511         if (!ring || (unsigned long)ring & 0xFF) {
 512                 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
 513                           prio);
 514                 return -ENOMEM;
 515         }
 516
 517         memset(ring, 0, sizeof(*ring)*entries);
 518         priv->tx_ring[prio].desc = ring;
 519         priv->tx_ring[prio].dma = dma;
 520         priv->tx_ring[prio].idx = 0;
 521         priv->tx_ring[prio].entries = entries;
 522         skb_queue_head_init(&priv->tx_ring[prio].queue);
 523
 524         for (i = 0; i < entries; i++)
 525                 ring[i].next_tx_desc =
 526                         cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
 527
 528         return 0;
 529 }
 530
 531 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
 532 {
 533         struct rtl8180_priv *priv = dev->priv;
 534         struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
 535
 536         while (skb_queue_len(&ring->queue)) {
 537                 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
 538                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
 539
 540                 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
 541                                  skb->len, PCI_DMA_TODEVICE);
 542                 kfree_skb(skb);
 543                 ring->idx = (ring->idx + 1) % ring->entries;
 544         }
 545
 546         pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
 547                             ring->desc, ring->dma);
 548         ring->desc = NULL;
 549 }
 550
 551 static int rtl8180_start(struct ieee80211_hw *dev)
 552 {
 553         struct rtl8180_priv *priv = dev->priv;
 554         int ret, i;
 555         u32 reg;
 556
 557         ret = rtl8180_init_rx_ring(dev);
 558         if (ret)
 559                 return ret;
 560
 561         for (i = 0; i < 4; i++)
 562                 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
 563                         goto err_free_rings;
 564
 565         ret = rtl8180_init_hw(dev);
 566         if (ret)
 567                 goto err_free_rings;
 568
 569         rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
 570         rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
 571         rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
 572         rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
 573         rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
 574
 575         ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
 576                           IRQF_SHARED, KBUILD_MODNAME, dev);
 577         if (ret) {
 578                 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
 579                 goto err_free_rings;
 580         }
 581
 582         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
 583
 584         rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
 585         rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
 586
 587         reg = RTL818X_RX_CONF_ONLYERLPKT |
 588               RTL818X_RX_CONF_RX_AUTORESETPHY |
 589               RTL818X_RX_CONF_MGMT |
 590               RTL818X_RX_CONF_DATA |
 591               (7 << 8 /* MAX RX DMA */) |
 592               RTL818X_RX_CONF_BROADCAST |
 593               RTL818X_RX_CONF_NICMAC;
 594
 595         if (priv->r8185)
 596                 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
 597         else {
 598                 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
 599                         ? RTL818X_RX_CONF_CSDM1 : 0;
 600                 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
 601                         ? RTL818X_RX_CONF_CSDM2 : 0;
 602         }
 603
 604         priv->rx_conf = reg;
 605         rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
 606
 607         if (priv->r8185) {
 608                 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
 609                 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
 610                 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
 611                 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
 612
 613                 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
 614                 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
 615                 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
 616                 reg |=  RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
 617                 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
 618
 619                 /* disable early TX */
 620                 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
 621         }
 622
 623         reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
 624         reg |= (6 << 21 /* MAX TX DMA */) |
 625                RTL818X_TX_CONF_NO_ICV;
 626
 627         if (priv->r8185)
 628                 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
 629         else
 630                 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
 631
 632         /* different meaning, same value on both rtl8185 and rtl8180 */
 633         reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
 634
 635         rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
 636
 637         reg = rtl818x_ioread8(priv, &priv->map->CMD);
 638         reg |= RTL818X_CMD_RX_ENABLE;
 639         reg |= RTL818X_CMD_TX_ENABLE;
 640         rtl818x_iowrite8(priv, &priv->map->CMD, reg);
 641
 642         return 0;
 643
 644  err_free_rings:
 645         rtl8180_free_rx_ring(dev);
 646         for (i = 0; i < 4; i++)
 647                 if (priv->tx_ring[i].desc)
 648                         rtl8180_free_tx_ring(dev, i);
 649
 650         return ret;
 651 }
 652
 653 static void rtl8180_stop(struct ieee80211_hw *dev)
 654 {
 655         struct rtl8180_priv *priv = dev->priv;
 656         u8 reg;
 657         int i;
 658
 659         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
 660
 661         reg = rtl818x_ioread8(priv, &priv->map->CMD);
 662         reg &= ~RTL818X_CMD_TX_ENABLE;
 663         reg &= ~RTL818X_CMD_RX_ENABLE;
 664         rtl818x_iowrite8(priv, &priv->map->CMD, reg);
 665
 666         priv->rf->stop(dev);
 667
 668         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 669         reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
 670         rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
 671         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 672
 673         free_irq(priv->pdev->irq, dev);
 674
 675         rtl8180_free_rx_ring(dev);
 676         for (i = 0; i < 4; i++)
 677                 rtl8180_free_tx_ring(dev, i);
 678 }
 679
 680 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev)
 681 {
 682         struct rtl8180_priv *priv = dev->priv;
 683
 684         return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
 685                (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
 686 }
 687
 688 static void rtl8180_beacon_work(struct work_struct *work)
 689 {
 690         struct rtl8180_vif *vif_priv =
 691                 container_of(work, struct rtl8180_vif, beacon_work.work);
 692         struct ieee80211_vif *vif =
 693                 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
 694         struct ieee80211_hw *dev = vif_priv->dev;
 695         struct ieee80211_mgmt *mgmt;
 696         struct sk_buff *skb;
 697         int err = 0;
 698
 699         /* don't overflow the tx ring */
 700         if (ieee80211_queue_stopped(dev, 0))
 701                 goto resched;
 702
 703         /* grab a fresh beacon */
 704         skb = ieee80211_beacon_get(dev, vif);
 705         if (!skb)
 706                 goto resched;
 707
 708         /*
 709          * update beacon timestamp w/ TSF value
 710          * TODO: make hardware update beacon timestamp
 711          */
 712         mgmt = (struct ieee80211_mgmt *)skb->data;
 713         mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev));
 714
 715         /* TODO: use actual beacon queue */
 716         skb_set_queue_mapping(skb, 0);
 717
 718         err = rtl8180_tx(dev, skb);
 719         WARN_ON(err);
 720
 721 resched:
 722         /*
 723          * schedule next beacon
 724          * TODO: use hardware support for beacon timing
 725          */
 726         schedule_delayed_work(&vif_priv->beacon_work,
 727                         usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
 728 }
 729
 730 static int rtl8180_add_interface(struct ieee80211_hw *dev,
 731                                  struct ieee80211_vif *vif)
 732 {
 733         struct rtl8180_priv *priv = dev->priv;
 734         struct rtl8180_vif *vif_priv;
 735
 736         /*
 737          * We only support one active interface at a time.
 738          */
 739         if (priv->vif)
 740                 return -EBUSY;
 741
 742         switch (vif->type) {
 743         case NL80211_IFTYPE_STATION:
 744         case NL80211_IFTYPE_ADHOC:
 745                 break;
 746         default:
 747                 return -EOPNOTSUPP;
 748         }
 749
 750         priv->vif = vif;
 751
 752         /* Initialize driver private area */
 753         vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
 754         vif_priv->dev = dev;
 755         INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
 756         vif_priv->enable_beacon = false;
 757
 758         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 759         rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
 760                           le32_to_cpu(*(__le32 *)vif->addr));
 761         rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
 762                           le16_to_cpu(*(__le16 *)(vif->addr + 4)));
 763         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 764
 765         return 0;
 766 }
 767
 768 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
 769                                      struct ieee80211_vif *vif)
 770 {
 771         struct rtl8180_priv *priv = dev->priv;
 772         priv->vif = NULL;
 773 }
 774
 775 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
 776 {
 777         struct rtl8180_priv *priv = dev->priv;
 778         struct ieee80211_conf *conf = &dev->conf;
 779
 780         priv->rf->set_chan(dev, conf);
 781
 782         return 0;
 783 }
 784
 785 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
 786                                      struct ieee80211_vif *vif,
 787                                      struct ieee80211_bss_conf *info,
 788                                      u32 changed)
 789 {
 790         struct rtl8180_priv *priv = dev->priv;
 791         struct rtl8180_vif *vif_priv;
 792         int i;
 793         u8 reg;
 794
 795         vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
 796
 797         if (changed & BSS_CHANGED_BSSID) {
 798                 for (i = 0; i < ETH_ALEN; i++)
 799                         rtl818x_iowrite8(priv, &priv->map->BSSID[i],
 800                                          info->bssid[i]);
 801
 802                 if (is_valid_ether_addr(info->bssid)) {
 803                         if (vif->type == NL80211_IFTYPE_ADHOC)
 804                                 reg = RTL818X_MSR_ADHOC;
 805                         else
 806                                 reg = RTL818X_MSR_INFRA;
 807                 } else
 808                         reg = RTL818X_MSR_NO_LINK;
 809                 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
 810         }
 811
 812         if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
 813                 priv->rf->conf_erp(dev, info);
 814
 815         if (changed & BSS_CHANGED_BEACON_ENABLED)
 816                 vif_priv->enable_beacon = info->enable_beacon;
 817
 818         if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
 819                 cancel_delayed_work_sync(&vif_priv->beacon_work);
 820                 if (vif_priv->enable_beacon)
 821                         schedule_work(&vif_priv->beacon_work.work);
 822         }
 823 }
 824
 825 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
 826                                      struct netdev_hw_addr_list *mc_list)
 827 {
 828         return netdev_hw_addr_list_count(mc_list);
 829 }
 830
 831 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
 832                                      unsigned int changed_flags,
 833                                      unsigned int *total_flags,
 834                                      u64 multicast)
 835 {
 836         struct rtl8180_priv *priv = dev->priv;
 837
 838         if (changed_flags & FIF_FCSFAIL)
 839                 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
 840         if (changed_flags & FIF_CONTROL)
 841                 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
 842         if (changed_flags & FIF_OTHER_BSS)
 843                 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
 844         if (*total_flags & FIF_ALLMULTI || multicast > 0)
 845                 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
 846         else
 847                 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
 848
 849         *total_flags = 0;
 850
 851         if (priv->rx_conf & RTL818X_RX_CONF_FCS)
 852                 *total_flags |= FIF_FCSFAIL;
 853         if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
 854                 *total_flags |= FIF_CONTROL;
 855         if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
 856                 *total_flags |= FIF_OTHER_BSS;
 857         if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
 858                 *total_flags |= FIF_ALLMULTI;
 859
 860         rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
 861 }
 862
 863 static const struct ieee80211_ops rtl8180_ops = {
 864         .tx                     = rtl8180_tx,
 865         .start                  = rtl8180_start,
 866         .stop                   = rtl8180_stop,
 867         .add_interface          = rtl8180_add_interface,
 868         .remove_interface       = rtl8180_remove_interface,
 869         .config                 = rtl8180_config,
 870         .bss_info_changed       = rtl8180_bss_info_changed,
 871         .prepare_multicast      = rtl8180_prepare_multicast,
 872         .configure_filter       = rtl8180_configure_filter,
 873         .get_tsf                = rtl8180_get_tsf,
 874         .napi_poll              = rtl8180_poll,
 875 };
 876
 877 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
 878 {
 879         struct ieee80211_hw *dev = eeprom->data;
 880         struct rtl8180_priv *priv = dev->priv;
 881         u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
 882
 883         eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
 884         eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
 885         eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
 886         eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
 887 }
 888
 889 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
 890 {
 891         struct ieee80211_hw *dev = eeprom->data;
 892         struct rtl8180_priv *priv = dev->priv;
 893         u8 reg = 2 << 6;
 894
 895         if (eeprom->reg_data_in)
 896                 reg |= RTL818X_EEPROM_CMD_WRITE;
 897         if (eeprom->reg_data_out)
 898                 reg |= RTL818X_EEPROM_CMD_READ;
 899         if (eeprom->reg_data_clock)
 900                 reg |= RTL818X_EEPROM_CMD_CK;
 901         if (eeprom->reg_chip_select)
 902                 reg |= RTL818X_EEPROM_CMD_CS;
 903
 904         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
 905         rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
 906         udelay(10);
 907 }
 908
 909 static int __devinit rtl8180_probe(struct pci_dev *pdev,
 910                                    const struct pci_device_id *id)
 911 {
 912         struct ieee80211_hw *dev;
 913         struct rtl8180_priv *priv;
 914         unsigned long mem_addr, mem_len;
 915         unsigned int io_addr, io_len;
 916         int err, i;
 917         struct eeprom_93cx6 eeprom;
 918         const char *chip_name, *rf_name = NULL;
 919         u32 reg;
 920         u16 eeprom_val;
 921         u8 mac_addr[ETH_ALEN];
 922
 923         err = pci_enable_device(pdev);
 924         if (err) {
 925                 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
 926                        pci_name(pdev));
 927                 return err;
 928         }
 929
 930         err = pci_request_regions(pdev, KBUILD_MODNAME);
 931         if (err) {
 932                 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
 933                        pci_name(pdev));
 934                 return err;
 935         }
 936
 937         io_addr = pci_resource_start(pdev, 0);
 938         io_len = pci_resource_len(pdev, 0);
 939         mem_addr = pci_resource_start(pdev, 1);
 940         mem_len = pci_resource_len(pdev, 1);
 941
 942         if (mem_len < sizeof(struct rtl818x_csr) ||
 943             io_len < sizeof(struct rtl818x_csr)) {
 944                 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
 945                        pci_name(pdev));
 946                 err = -ENOMEM;
 947                 goto err_free_reg;
 948         }
 949
 950         if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
 951             (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
 952                 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
 953                        pci_name(pdev));
 954                 goto err_free_reg;
 955         }
 956
 957         pci_set_master(pdev);
 958
 959         dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
 960         if (!dev) {
 961                 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
 962                        pci_name(pdev));
 963                 err = -ENOMEM;
 964                 goto err_free_reg;
 965         }
 966
 967         priv = dev->priv;
 968         priv->pdev = pdev;
 969
 970         dev->max_rates = 2;
 971         SET_IEEE80211_DEV(dev, &pdev->dev);
 972         pci_set_drvdata(pdev, dev);
 973
 974         priv->map = pci_iomap(pdev, 1, mem_len);
 975         if (!priv->map)
 976                 priv->map = pci_iomap(pdev, 0, io_len);
 977
 978         if (!priv->map) {
 979                 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
 980                        pci_name(pdev));
 981                 goto err_free_dev;
 982         }
 983
 984         BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
 985         BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
 986
 987         memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
 988         memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
 989
 990         priv->band.band = IEEE80211_BAND_2GHZ;
 991         priv->band.channels = priv->channels;
 992         priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
 993         priv->band.bitrates = priv->rates;
 994         priv->band.n_bitrates = 4;
 995         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
 996
 997         dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
 998                      IEEE80211_HW_RX_INCLUDES_FCS |
 999                      IEEE80211_HW_SIGNAL_UNSPEC;
1000         dev->vif_data_size = sizeof(struct rtl8180_vif);
1001         dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1002                                         BIT(NL80211_IFTYPE_ADHOC);
1003         dev->queues = 1;
1004         dev->max_signal = 65;
1005
1006         dev->napi_weight = 64;
1007
1008         reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1009         reg &= RTL818X_TX_CONF_HWVER_MASK;
1010         switch (reg) {
1011         case RTL818X_TX_CONF_R8180_ABCD:
1012                 chip_name = "RTL8180";
1013                 break;
1014         case RTL818X_TX_CONF_R8180_F:
1015                 chip_name = "RTL8180vF";
1016                 break;
1017         case RTL818X_TX_CONF_R8185_ABC:
1018                 chip_name = "RTL8185";
1019                 break;
1020         case RTL818X_TX_CONF_R8185_D:
1021                 chip_name = "RTL8185vD";
1022                 break;
1023         default:
1024                 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1025                        pci_name(pdev), reg >> 25);
1026                 goto err_iounmap;
1027         }
1028
1029         priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1030         if (priv->r8185) {
1031                 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1032                 pci_try_set_mwi(pdev);
1033         }
1034
1035         eeprom.data = dev;
1036         eeprom.register_read = rtl8180_eeprom_register_read;
1037         eeprom.register_write = rtl8180_eeprom_register_write;
1038         if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1039                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1040         else
1041                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1042
1043         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1044         rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1045         udelay(10);
1046
1047         eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1048         eeprom_val &= 0xFF;
1049         switch (eeprom_val) {
1050         case 1: rf_name = "Intersil";
1051                 break;
1052         case 2: rf_name = "RFMD";
1053                 break;
1054         case 3: priv->rf = &sa2400_rf_ops;
1055                 break;
1056         case 4: priv->rf = &max2820_rf_ops;
1057                 break;
1058         case 5: priv->rf = &grf5101_rf_ops;
1059                 break;
1060         case 9: priv->rf = rtl8180_detect_rf(dev);
1061                 break;
1062         case 10:
1063                 rf_name = "RTL8255";
1064                 break;
1065         default:
1066                 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1067                        pci_name(pdev), eeprom_val);
1068                 goto err_iounmap;
1069         }
1070
1071         if (!priv->rf) {
1072                 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1073                        pci_name(pdev), rf_name);
1074                 goto err_iounmap;
1075         }
1076
1077         eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1078         priv->csthreshold = eeprom_val >> 8;
1079         if (!priv->r8185) {
1080                 __le32 anaparam;
1081                 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1082                 priv->anaparam = le32_to_cpu(anaparam);
1083                 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1084         }
1085
1086         eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1087         if (!is_valid_ether_addr(mac_addr)) {
1088                 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1089                        " randomly generated MAC addr\n", pci_name(pdev));
1090                 random_ether_addr(mac_addr);
1091         }
1092         SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1093
1094         /* CCK TX power */
1095         for (i = 0; i < 14; i += 2) {
1096                 u16 txpwr;
1097                 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
1098                 priv->channels[i].hw_value = txpwr & 0xFF;
1099                 priv->channels[i + 1].hw_value = txpwr >> 8;
1100         }
1101
1102         /* OFDM TX power */
1103         if (priv->r8185) {
1104                 for (i = 0; i < 14; i += 2) {
1105                         u16 txpwr;
1106                         eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1107                         priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1108                         priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1109                 }
1110         }
1111
1112         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1113
1114         spin_lock_init(&priv->lock);
1115
1116         err = ieee80211_register_hw(dev);
1117         if (err) {
1118                 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1119                        pci_name(pdev));
1120                 goto err_iounmap;
1121         }
1122
1123         wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1124                    mac_addr, chip_name, priv->rf->name);
1125
1126         return 0;
1127
1128  err_iounmap:
1129         iounmap(priv->map);
1130
1131  err_free_dev:
1132         pci_set_drvdata(pdev, NULL);
1133         ieee80211_free_hw(dev);
1134
1135  err_free_reg:
1136         pci_release_regions(pdev);
1137         pci_disable_device(pdev);
1138         return err;
1139 }
1140
1141 static void __devexit rtl8180_remove(struct pci_dev *pdev)
1142 {
1143         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1144         struct rtl8180_priv *priv;
1145
1146         if (!dev)
1147                 return;
1148
1149         ieee80211_unregister_hw(dev);
1150
1151         priv = dev->priv;
1152
1153         pci_iounmap(pdev, priv->map);
1154         pci_release_regions(pdev);
1155         pci_disable_device(pdev);
1156         ieee80211_free_hw(dev);
1157 }
1158
1159 #ifdef CONFIG_PM
1160 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1161 {
1162         pci_save_state(pdev);
1163         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1164         return 0;
1165 }
1166
1167 static int rtl8180_resume(struct pci_dev *pdev)
1168 {
1169         pci_set_power_state(pdev, PCI_D0);
1170         pci_restore_state(pdev);
1171         return 0;
1172 }
1173
1174 #endif /* CONFIG_PM */
1175
1176 static struct pci_driver rtl8180_driver = {
1177         .name           = KBUILD_MODNAME,
1178         .id_table       = rtl8180_table,
1179         .probe          = rtl8180_probe,
1180         .remove         = __devexit_p(rtl8180_remove),
1181 #ifdef CONFIG_PM
1182         .suspend        = rtl8180_suspend,
1183         .resume         = rtl8180_resume,
1184 #endif /* CONFIG_PM */
1185 };
1186
1187 static int __init rtl8180_init(void)
1188 {
1189         return pci_register_driver(&rtl8180_driver);
1190 }
1191
1192 static void __exit rtl8180_exit(void)
1193 {
1194         pci_unregister_driver(&rtl8180_driver);
1195 }
1196
1197 module_init(rtl8180_init);
1198 module_exit(rtl8180_exit);