3 * Linux device driver for RTL8180 / RTL8185
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
11 * Thanks to Realtek for their support!
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <linux/module.h>
25 #include <net/mac80211.h>
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
35 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36 MODULE_LICENSE("GPL");
38 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
49 { PCI_DEVICE(0x1186, 0x3301) },
50 { PCI_DEVICE(0x1432, 0x7106) },
54 MODULE_DEVICE_TABLE(pci, rtl8180_table);
56 static const struct ieee80211_rate rtl818x_rates[] = {
57 { .bitrate = 10, .hw_value = 0, },
58 { .bitrate = 20, .hw_value = 1, },
59 { .bitrate = 55, .hw_value = 2, },
60 { .bitrate = 110, .hw_value = 3, },
61 { .bitrate = 60, .hw_value = 4, },
62 { .bitrate = 90, .hw_value = 5, },
63 { .bitrate = 120, .hw_value = 6, },
64 { .bitrate = 180, .hw_value = 7, },
65 { .bitrate = 240, .hw_value = 8, },
66 { .bitrate = 360, .hw_value = 9, },
67 { .bitrate = 480, .hw_value = 10, },
68 { .bitrate = 540, .hw_value = 11, },
71 static const struct ieee80211_channel rtl818x_channels[] = {
72 { .center_freq = 2412 },
73 { .center_freq = 2417 },
74 { .center_freq = 2422 },
75 { .center_freq = 2427 },
76 { .center_freq = 2432 },
77 { .center_freq = 2437 },
78 { .center_freq = 2442 },
79 { .center_freq = 2447 },
80 { .center_freq = 2452 },
81 { .center_freq = 2457 },
82 { .center_freq = 2462 },
83 { .center_freq = 2467 },
84 { .center_freq = 2472 },
85 { .center_freq = 2484 },
88 /* Queues for rtl8187se card
99 * The complete map for DMA kick reg using use all queue is:
100 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
101 * {1, 6, 5, 4, 3, 2, 7};
103 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
106 * BC | 7 | 4 <- currently not used yet
107 * MG | 1 | x <- Not used
108 * HI | 6 | x <- Not used
114 * Beacon queue could be used, but this is not finished yet.
116 * I thougth about using the other two queues but I decided not to do this:
118 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
121 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
122 * queue but since mac80211 will do not know about it, I will probably gain
123 * some HW priority whenever the VO queue is not empty, but this gain is
124 * limited by the fact that I had to stop the mac80211 queue whenever one of
125 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
128 * - I don't know how to set in the HW the contention window params for MGMT
129 * and HI-prio queues.
132 static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] = {5, 4, 3, 2, 7};
134 /* Queues for rtl8180/rtl8185 cards
142 * The complete map for DMA kick reg using all queue is:
143 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
145 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
146 * otherwise QoS can't be done, we use just one.
147 * Beacon queue could be used, but this is not finished yet.
151 * BC | 7 | 1 <- currently not used yet.
152 * HI | 6 | x <- not used
153 * NO | 5 | x <- not used
157 static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {4, 7};
159 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
161 struct rtl8180_priv *priv = dev->priv;
165 buf = (data << 8) | addr;
167 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
169 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
170 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
175 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
177 struct rtl8180_priv *priv = dev->priv;
178 struct rtl818x_rx_cmd_desc *cmd_desc;
179 unsigned int count = 32;
184 void *entry = priv->rx_ring + priv->rx_idx * priv->rx_ring_sz;
185 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
189 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
190 struct rtl8187se_rx_desc *desc = entry;
192 flags = le32_to_cpu(desc->flags);
193 flags2 = le32_to_cpu(desc->flags2);
194 tsft = le64_to_cpu(desc->tsft);
196 struct rtl8180_rx_desc *desc = entry;
198 flags = le32_to_cpu(desc->flags);
199 flags2 = le32_to_cpu(desc->flags2);
200 tsft = le64_to_cpu(desc->tsft);
203 if (flags & RTL818X_RX_DESC_FLAG_OWN)
206 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
207 RTL818X_RX_DESC_FLAG_FOF |
208 RTL818X_RX_DESC_FLAG_RX_ERR)))
211 struct ieee80211_rx_status rx_status = {0};
212 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
214 if (unlikely(!new_skb))
217 mapping = pci_map_single(priv->pdev,
218 skb_tail_pointer(new_skb),
219 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
221 if (pci_dma_mapping_error(priv->pdev, mapping)) {
223 dev_err(&priv->pdev->dev, "RX DMA map error\n");
228 pci_unmap_single(priv->pdev,
229 *((dma_addr_t *)skb->cb),
230 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
231 skb_put(skb, flags & 0xFFF);
233 rx_status.antenna = (flags2 >> 15) & 1;
234 rx_status.rate_idx = (flags >> 20) & 0xF;
235 agc = (flags2 >> 17) & 0x7F;
237 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
238 if (rx_status.rate_idx > 3)
239 signal = 90 - clamp_t(u8, agc, 25, 90);
241 signal = 95 - clamp_t(u8, agc, 30, 95);
242 } else if (priv->chip_family ==
243 RTL818X_CHIP_FAMILY_RTL8180) {
245 signal = priv->rf->calc_rssi(agc, sq);
247 /* TODO: rtl8187se rssi */
250 rx_status.signal = signal;
251 rx_status.freq = dev->conf.chandef.chan->center_freq;
252 rx_status.band = dev->conf.chandef.chan->band;
253 rx_status.mactime = tsft;
254 rx_status.flag |= RX_FLAG_MACTIME_START;
255 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
256 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
258 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
259 ieee80211_rx_irqsafe(dev, skb);
262 priv->rx_buf[priv->rx_idx] = skb;
263 *((dma_addr_t *) skb->cb) = mapping;
268 cmd_desc->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
269 cmd_desc->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
271 if (priv->rx_idx == 31)
273 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
274 priv->rx_idx = (priv->rx_idx + 1) % 32;
278 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
280 struct rtl8180_priv *priv = dev->priv;
281 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
283 while (skb_queue_len(&ring->queue)) {
284 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
286 struct ieee80211_tx_info *info;
287 u32 flags = le32_to_cpu(entry->flags);
289 if (flags & RTL818X_TX_DESC_FLAG_OWN)
292 ring->idx = (ring->idx + 1) % ring->entries;
293 skb = __skb_dequeue(&ring->queue);
294 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
295 skb->len, PCI_DMA_TODEVICE);
297 info = IEEE80211_SKB_CB(skb);
298 ieee80211_tx_info_clear_status(info);
300 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
301 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
302 info->flags |= IEEE80211_TX_STAT_ACK;
304 info->status.rates[0].count = (flags & 0xFF) + 1;
305 info->status.rates[1].idx = -1;
307 ieee80211_tx_status_irqsafe(dev, skb);
308 if (ring->entries - skb_queue_len(&ring->queue) == 2)
309 ieee80211_wake_queue(dev, prio);
313 static irqreturn_t rtl8187se_interrupt(int irq, void *dev_id)
315 struct ieee80211_hw *dev = dev_id;
316 struct rtl8180_priv *priv = dev->priv;
321 spin_lock_irqsave(&priv->lock, flags);
322 /* Note: 32-bit interrupt status */
323 reg = rtl818x_ioread32(priv, &priv->map->INT_STATUS_SE);
324 if (unlikely(reg == 0xFFFFFFFF)) {
325 spin_unlock_irqrestore(&priv->lock, flags);
329 rtl818x_iowrite32(priv, &priv->map->INT_STATUS_SE, reg);
331 if (reg & IMR_TIMEOUT1)
332 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
334 if (reg & (IMR_TBDOK | IMR_TBDER))
335 rtl8180_handle_tx(dev, 4);
337 if (reg & (IMR_TVODOK | IMR_TVODER))
338 rtl8180_handle_tx(dev, 0);
340 if (reg & (IMR_TVIDOK | IMR_TVIDER))
341 rtl8180_handle_tx(dev, 1);
343 if (reg & (IMR_TBEDOK | IMR_TBEDER))
344 rtl8180_handle_tx(dev, 2);
346 if (reg & (IMR_TBKDOK | IMR_TBKDER))
347 rtl8180_handle_tx(dev, 3);
349 if (reg & (IMR_ROK | IMR_RER | RTL818X_INT_SE_RX_DU | IMR_RQOSOK))
350 rtl8180_handle_rx(dev);
351 /* The interface sometimes generates several RX DMA descriptor errors
352 * at startup. Do not report these.
354 if ((reg & RTL818X_INT_SE_RX_DU) && desc_err++ > 2)
356 wiphy_err(dev->wiphy, "No RX DMA Descriptor avail\n");
358 spin_unlock_irqrestore(&priv->lock, flags);
362 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
364 struct ieee80211_hw *dev = dev_id;
365 struct rtl8180_priv *priv = dev->priv;
368 spin_lock(&priv->lock);
369 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
370 if (unlikely(reg == 0xFFFF)) {
371 spin_unlock(&priv->lock);
375 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
377 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
378 rtl8180_handle_tx(dev, 1);
380 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
381 rtl8180_handle_tx(dev, 0);
383 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
384 rtl8180_handle_rx(dev);
386 spin_unlock(&priv->lock);
391 static void rtl8180_tx(struct ieee80211_hw *dev,
392 struct ieee80211_tx_control *control,
395 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
396 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
397 struct rtl8180_priv *priv = dev->priv;
398 struct rtl8180_tx_ring *ring;
399 struct rtl8180_tx_desc *entry;
401 unsigned int idx, prio, hw_prio;
406 __le16 rts_duration = 0;
407 /* do arithmetic and then convert to le16 */
408 u16 frame_duration = 0;
410 prio = skb_get_queue_mapping(skb);
411 ring = &priv->tx_ring[prio];
413 mapping = pci_map_single(priv->pdev, skb->data,
414 skb->len, PCI_DMA_TODEVICE);
416 if (pci_dma_mapping_error(priv->pdev, mapping)) {
418 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
422 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
423 RTL818X_TX_DESC_FLAG_LS |
424 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
427 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
428 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
429 RTL818X_TX_DESC_FLAG_NO_ENC;
431 rc_flags = info->control.rates[0].flags;
432 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
433 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
434 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
435 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
436 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
437 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
440 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
441 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
444 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
445 unsigned int remainder;
447 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
448 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
449 remainder = (16 * (skb->len + 4)) %
450 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
455 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
457 /* SIFS time (required by HW) is already included by
458 * ieee80211_generic_frame_duration
460 duration = ieee80211_generic_frame_duration(dev, priv->vif,
461 IEEE80211_BAND_2GHZ, skb->len,
462 ieee80211_get_tx_rate(dev, info));
464 frame_duration = priv->ack_time + le16_to_cpu(duration);
467 spin_lock_irqsave(&priv->lock, flags);
469 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
470 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
472 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
473 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
476 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
477 entry = &ring->desc[idx];
479 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
480 entry->frame_duration = cpu_to_le16(frame_duration);
481 entry->frame_len_se = cpu_to_le16(skb->len);
484 entry->flags3 = cpu_to_le16(1<<4);
486 entry->frame_len = cpu_to_le32(skb->len);
488 entry->rts_duration = rts_duration;
489 entry->plcp_len = cpu_to_le16(plcp_len);
490 entry->tx_buf = cpu_to_le32(mapping);
492 entry->flags2 = info->control.rates[1].idx >= 0 ?
493 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
494 entry->retry_limit = info->control.rates[0].count;
496 /* We must be sure that tx_flags is written last because the HW
497 * looks at it to check if the rest of data is valid or not
500 entry->flags = cpu_to_le32(tx_flags);
501 /* We must be sure this has been written before followings HW
502 * register write, because this write will made the HW attempts
503 * to DMA the just-written data
507 __skb_queue_tail(&ring->queue, skb);
508 if (ring->entries - skb_queue_len(&ring->queue) < 2)
509 ieee80211_stop_queue(dev, prio);
511 spin_unlock_irqrestore(&priv->lock, flags);
513 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
514 /* just poll: rings are stopped with TPPollStop reg */
515 hw_prio = rtl8187se_queues_map[prio];
516 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
519 hw_prio = rtl8180_queues_map[prio];
520 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
521 (1 << hw_prio) | /* ring to poll */
522 (1<<1) | (1<<2));/* stopped rings */
526 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
530 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
531 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
532 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
533 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
534 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
535 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
536 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
537 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
540 static void rtl8180_int_enable(struct ieee80211_hw *dev)
542 struct rtl8180_priv *priv = dev->priv;
544 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
545 rtl818x_iowrite32(priv, &priv->map->IMR, IMR_TMGDOK |
546 IMR_TBDER | IMR_THPDER |
547 IMR_THPDER | IMR_THPDOK |
548 IMR_TVODER | IMR_TVODOK |
549 IMR_TVIDER | IMR_TVIDOK |
550 IMR_TBEDER | IMR_TBEDOK |
551 IMR_TBKDER | IMR_TBKDOK |
553 IMR_ROK | IMR_RQOSOK);
555 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
559 static void rtl8180_int_disable(struct ieee80211_hw *dev)
561 struct rtl8180_priv *priv = dev->priv;
563 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
564 rtl818x_iowrite32(priv, &priv->map->IMR, 0);
566 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
570 static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev,
573 struct rtl8180_priv *priv = dev->priv;
578 max = fls(rates_mask) - 1;
579 min = ffs(rates_mask) - 1;
581 switch (priv->chip_family) {
583 case RTL818X_CHIP_FAMILY_RTL8180:
584 /* in 8180 this is NOT a BITMAP */
585 reg = rtl818x_ioread16(priv, &priv->map->BRSR);
588 rtl818x_iowrite16(priv, &priv->map->BRSR, reg);
591 case RTL818X_CHIP_FAMILY_RTL8185:
592 /* in 8185 this is a BITMAP */
593 rtl818x_iowrite16(priv, &priv->map->BRSR, rates_mask);
594 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (max << 4) | min);
597 case RTL818X_CHIP_FAMILY_RTL8187SE:
598 /* in 8187se this is a BITMAP */
599 rtl818x_iowrite16(priv, &priv->map->BRSR_8187SE, rates_mask);
604 static int rtl8180_init_hw(struct ieee80211_hw *dev)
606 struct rtl8180_priv *priv = dev->priv;
609 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
610 rtl818x_ioread8(priv, &priv->map->CMD);
614 rtl8180_int_disable(dev);
615 rtl818x_ioread8(priv, &priv->map->CMD);
617 reg = rtl818x_ioread8(priv, &priv->map->CMD);
619 reg |= RTL818X_CMD_RESET;
620 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
621 rtl818x_ioread8(priv, &priv->map->CMD);
624 /* check success of reset */
625 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
626 wiphy_err(dev->wiphy, "reset timeout!\n");
630 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
631 rtl818x_ioread8(priv, &priv->map->CMD);
634 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
636 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
638 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
639 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
640 reg |= (1 << 15) | (1 << 14) | (1 << 4);
641 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
644 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
646 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
647 rtl8180_set_anaparam(priv, priv->anaparam);
649 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
650 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[1].dma);
651 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
653 /* TODO: necessary? specs indicate not */
654 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
655 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
656 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
657 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
658 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
659 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
661 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
663 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
665 /* TODO: turn off hw wep on rtl8180 */
667 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
669 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
670 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
671 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
673 /* TODO: set ClkRun enable? necessary? */
674 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
675 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
676 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
677 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
678 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
679 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
681 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
683 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
684 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
689 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
690 * otherwise. bitmask 0x3 and 0x01f3 respectively.
691 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
692 * this after rf init.
693 * TODO: try to find out whether RF code really needs to do this..
695 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
696 rtl8180_conf_basic_rates(dev, 0x3);
698 rtl8180_conf_basic_rates(dev, 0x1f3);
703 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
705 struct rtl8180_priv *priv = dev->priv;
706 struct rtl818x_rx_cmd_desc *entry;
709 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
710 priv->rx_ring_sz = sizeof(struct rtl8187se_rx_desc);
712 priv->rx_ring_sz = sizeof(struct rtl8180_rx_desc);
714 priv->rx_ring = pci_alloc_consistent(priv->pdev,
715 priv->rx_ring_sz * 32,
718 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
719 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
723 memset(priv->rx_ring, 0, priv->rx_ring_sz * 32);
726 for (i = 0; i < 32; i++) {
727 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
729 entry = priv->rx_ring + priv->rx_ring_sz*i;
731 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
734 priv->rx_buf[i] = skb;
735 mapping = (dma_addr_t *)skb->cb;
736 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
737 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
739 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
741 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
745 entry->rx_buf = cpu_to_le32(*mapping);
746 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
749 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
753 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
755 struct rtl8180_priv *priv = dev->priv;
758 for (i = 0; i < 32; i++) {
759 struct sk_buff *skb = priv->rx_buf[i];
763 pci_unmap_single(priv->pdev,
764 *((dma_addr_t *)skb->cb),
765 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
769 pci_free_consistent(priv->pdev, priv->rx_ring_sz * 32,
770 priv->rx_ring, priv->rx_ring_dma);
771 priv->rx_ring = NULL;
774 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
775 unsigned int prio, unsigned int entries)
777 struct rtl8180_priv *priv = dev->priv;
778 struct rtl8180_tx_desc *ring;
782 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
783 if (!ring || (unsigned long)ring & 0xFF) {
784 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
789 memset(ring, 0, sizeof(*ring)*entries);
790 priv->tx_ring[prio].desc = ring;
791 priv->tx_ring[prio].dma = dma;
792 priv->tx_ring[prio].idx = 0;
793 priv->tx_ring[prio].entries = entries;
794 skb_queue_head_init(&priv->tx_ring[prio].queue);
796 for (i = 0; i < entries; i++)
797 ring[i].next_tx_desc =
798 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
803 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
805 struct rtl8180_priv *priv = dev->priv;
806 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
808 while (skb_queue_len(&ring->queue)) {
809 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
810 struct sk_buff *skb = __skb_dequeue(&ring->queue);
812 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
813 skb->len, PCI_DMA_TODEVICE);
815 ring->idx = (ring->idx + 1) % ring->entries;
818 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
819 ring->desc, ring->dma);
823 static int rtl8180_start(struct ieee80211_hw *dev)
825 struct rtl8180_priv *priv = dev->priv;
829 ret = rtl8180_init_rx_ring(dev);
833 for (i = 0; i < (dev->queues + 1); i++)
834 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
837 ret = rtl8180_init_hw(dev);
841 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
842 ret = request_irq(priv->pdev->irq, rtl8187se_interrupt,
843 IRQF_SHARED, KBUILD_MODNAME, dev);
845 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
846 IRQF_SHARED, KBUILD_MODNAME, dev);
850 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
854 rtl8180_int_enable(dev);
856 /* in rtl8187se at MAR regs offset there is the management
857 * TX descriptor DMA addres..
859 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
860 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
861 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
864 reg = RTL818X_RX_CONF_ONLYERLPKT |
865 RTL818X_RX_CONF_RX_AUTORESETPHY |
866 RTL818X_RX_CONF_MGMT |
867 RTL818X_RX_CONF_DATA |
868 (7 << 8 /* MAX RX DMA */) |
869 RTL818X_RX_CONF_BROADCAST |
870 RTL818X_RX_CONF_NICMAC;
872 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
873 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
875 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
876 ? RTL818X_RX_CONF_CSDM1 : 0;
877 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
878 ? RTL818X_RX_CONF_CSDM2 : 0;
882 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
884 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
885 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
887 /* CW is not on per-packet basis.
888 * in rtl8185 the CW_VALUE reg is used.
890 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
891 /* retry limit IS on per-packet basis.
892 * the short and long retry limit in TX_CONF
895 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
896 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
898 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
899 /* TX antenna and TX gain are not on per-packet basis.
900 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
901 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
903 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
904 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
905 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
906 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
908 /* disable early TX */
909 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
912 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
913 reg |= (6 << 21 /* MAX TX DMA */) |
914 RTL818X_TX_CONF_NO_ICV;
918 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
919 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
921 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
923 reg &= ~RTL818X_TX_CONF_DISCW;
925 /* different meaning, same value on both rtl8185 and rtl8180 */
926 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
928 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
930 reg = rtl818x_ioread8(priv, &priv->map->CMD);
931 reg |= RTL818X_CMD_RX_ENABLE;
932 reg |= RTL818X_CMD_TX_ENABLE;
933 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
938 rtl8180_free_rx_ring(dev);
939 for (i = 0; i < (dev->queues + 1); i++)
940 if (priv->tx_ring[i].desc)
941 rtl8180_free_tx_ring(dev, i);
946 static void rtl8180_stop(struct ieee80211_hw *dev)
948 struct rtl8180_priv *priv = dev->priv;
952 rtl8180_int_disable(dev);
954 reg = rtl818x_ioread8(priv, &priv->map->CMD);
955 reg &= ~RTL818X_CMD_TX_ENABLE;
956 reg &= ~RTL818X_CMD_RX_ENABLE;
957 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
961 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
962 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
963 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
964 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
966 free_irq(priv->pdev->irq, dev);
968 rtl8180_free_rx_ring(dev);
969 for (i = 0; i < (dev->queues + 1); i++)
970 rtl8180_free_tx_ring(dev, i);
973 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
974 struct ieee80211_vif *vif)
976 struct rtl8180_priv *priv = dev->priv;
978 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
979 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
982 static void rtl8180_beacon_work(struct work_struct *work)
984 struct rtl8180_vif *vif_priv =
985 container_of(work, struct rtl8180_vif, beacon_work.work);
986 struct ieee80211_vif *vif =
987 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
988 struct ieee80211_hw *dev = vif_priv->dev;
989 struct ieee80211_mgmt *mgmt;
992 /* don't overflow the tx ring */
993 if (ieee80211_queue_stopped(dev, 0))
996 /* grab a fresh beacon */
997 skb = ieee80211_beacon_get(dev, vif);
1002 * update beacon timestamp w/ TSF value
1003 * TODO: make hardware update beacon timestamp
1005 mgmt = (struct ieee80211_mgmt *)skb->data;
1006 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
1008 /* TODO: use actual beacon queue */
1009 skb_set_queue_mapping(skb, 0);
1011 rtl8180_tx(dev, NULL, skb);
1015 * schedule next beacon
1016 * TODO: use hardware support for beacon timing
1018 schedule_delayed_work(&vif_priv->beacon_work,
1019 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
1022 static int rtl8180_add_interface(struct ieee80211_hw *dev,
1023 struct ieee80211_vif *vif)
1025 struct rtl8180_priv *priv = dev->priv;
1026 struct rtl8180_vif *vif_priv;
1029 * We only support one active interface at a time.
1034 switch (vif->type) {
1035 case NL80211_IFTYPE_STATION:
1036 case NL80211_IFTYPE_ADHOC:
1044 /* Initialize driver private area */
1045 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1046 vif_priv->dev = dev;
1047 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
1048 vif_priv->enable_beacon = false;
1050 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1051 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
1052 le32_to_cpu(*(__le32 *)vif->addr));
1053 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
1054 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1055 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1060 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
1061 struct ieee80211_vif *vif)
1063 struct rtl8180_priv *priv = dev->priv;
1067 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
1069 struct rtl8180_priv *priv = dev->priv;
1070 struct ieee80211_conf *conf = &dev->conf;
1072 priv->rf->set_chan(dev, conf);
1077 static int rtl8180_conf_tx(struct ieee80211_hw *dev,
1078 struct ieee80211_vif *vif, u16 queue,
1079 const struct ieee80211_tx_queue_params *params)
1081 struct rtl8180_priv *priv = dev->priv;
1084 /* nothing to do ? */
1085 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1088 cw_min = fls(params->cw_min);
1089 cw_max = fls(params->cw_max);
1091 rtl818x_iowrite8(priv, &priv->map->CW_VAL, (cw_max << 4) | cw_min);
1096 static void rtl8180_conf_erp(struct ieee80211_hw *dev,
1097 struct ieee80211_bss_conf *info)
1099 struct rtl8180_priv *priv = dev->priv;
1104 /* TODO: should we do something ? */
1105 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1108 /* I _hope_ this means 10uS for the HW.
1109 * In reference code it is 0x22 for
1110 * both rtl8187L and rtl8187SE
1114 if (info->use_short_slot)
1115 priv->slot_time = 9;
1117 priv->slot_time = 20;
1119 /* 10 is SIFS time in uS */
1120 difs = 10 + 2 * priv->slot_time;
1121 eifs = 10 + difs + priv->ack_time;
1123 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1124 hw_eifs = DIV_ROUND_UP(eifs, 4);
1127 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1128 rtl818x_iowrite8(priv, &priv->map->SIFS, sifs);
1129 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1131 /* from reference code. set ack timeout reg = eifs reg */
1132 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs);
1134 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1135 * the HW still wait for DIFS.
1136 * HW uses 4uS units for EIFS.
1138 hw_eifs = DIV_ROUND_UP(eifs - difs, 4);
1140 rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs);
1143 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
1144 struct ieee80211_vif *vif,
1145 struct ieee80211_bss_conf *info,
1148 struct rtl8180_priv *priv = dev->priv;
1149 struct rtl8180_vif *vif_priv;
1153 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1155 if (changed & BSS_CHANGED_BSSID) {
1156 for (i = 0; i < ETH_ALEN; i++)
1157 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1160 if (is_valid_ether_addr(info->bssid)) {
1161 if (vif->type == NL80211_IFTYPE_ADHOC)
1162 reg = RTL818X_MSR_ADHOC;
1164 reg = RTL818X_MSR_INFRA;
1166 reg = RTL818X_MSR_NO_LINK;
1167 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1170 if (changed & BSS_CHANGED_BASIC_RATES)
1171 rtl8180_conf_basic_rates(dev, info->basic_rates);
1173 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
1175 /* when preamble changes, acktime duration changes, and erp must
1176 * be recalculated. ACK time is calculated at lowest rate.
1177 * Since mac80211 include SIFS time we remove it (-10)
1180 le16_to_cpu(ieee80211_generic_frame_duration(dev,
1182 IEEE80211_BAND_2GHZ, 10,
1183 &priv->rates[0])) - 10;
1185 rtl8180_conf_erp(dev, info);
1188 if (changed & BSS_CHANGED_BEACON_ENABLED)
1189 vif_priv->enable_beacon = info->enable_beacon;
1191 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1192 cancel_delayed_work_sync(&vif_priv->beacon_work);
1193 if (vif_priv->enable_beacon)
1194 schedule_work(&vif_priv->beacon_work.work);
1198 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
1199 struct netdev_hw_addr_list *mc_list)
1201 return netdev_hw_addr_list_count(mc_list);
1204 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
1205 unsigned int changed_flags,
1206 unsigned int *total_flags,
1209 struct rtl8180_priv *priv = dev->priv;
1211 if (changed_flags & FIF_FCSFAIL)
1212 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1213 if (changed_flags & FIF_CONTROL)
1214 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1215 if (changed_flags & FIF_OTHER_BSS)
1216 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1217 if (*total_flags & FIF_ALLMULTI || multicast > 0)
1218 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1220 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1224 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1225 *total_flags |= FIF_FCSFAIL;
1226 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1227 *total_flags |= FIF_CONTROL;
1228 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1229 *total_flags |= FIF_OTHER_BSS;
1230 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1231 *total_flags |= FIF_ALLMULTI;
1233 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
1236 static const struct ieee80211_ops rtl8180_ops = {
1238 .start = rtl8180_start,
1239 .stop = rtl8180_stop,
1240 .add_interface = rtl8180_add_interface,
1241 .remove_interface = rtl8180_remove_interface,
1242 .config = rtl8180_config,
1243 .bss_info_changed = rtl8180_bss_info_changed,
1244 .conf_tx = rtl8180_conf_tx,
1245 .prepare_multicast = rtl8180_prepare_multicast,
1246 .configure_filter = rtl8180_configure_filter,
1247 .get_tsf = rtl8180_get_tsf,
1250 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1252 struct rtl8180_priv *priv = eeprom->data;
1253 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1255 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1256 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1257 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1258 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1261 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1263 struct rtl8180_priv *priv = eeprom->data;
1266 if (eeprom->reg_data_in)
1267 reg |= RTL818X_EEPROM_CMD_WRITE;
1268 if (eeprom->reg_data_out)
1269 reg |= RTL818X_EEPROM_CMD_READ;
1270 if (eeprom->reg_data_clock)
1271 reg |= RTL818X_EEPROM_CMD_CK;
1272 if (eeprom->reg_chip_select)
1273 reg |= RTL818X_EEPROM_CMD_CS;
1275 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1276 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1280 static void rtl8180_eeprom_read(struct rtl8180_priv *priv)
1282 struct eeprom_93cx6 eeprom;
1283 int eeprom_cck_table_adr;
1288 eeprom.register_read = rtl8180_eeprom_register_read;
1289 eeprom.register_write = rtl8180_eeprom_register_write;
1290 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1291 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1293 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1295 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1296 RTL818X_EEPROM_CMD_PROGRAM);
1297 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1300 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1302 priv->rf_type = eeprom_val;
1304 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1305 priv->csthreshold = eeprom_val >> 8;
1307 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3);
1309 eeprom_cck_table_adr = 0x10;
1312 for (i = 0; i < 14; i += 2) {
1314 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1),
1316 priv->channels[i].hw_value = txpwr & 0xFF;
1317 priv->channels[i + 1].hw_value = txpwr >> 8;
1321 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1322 for (i = 0; i < 14; i += 2) {
1324 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1325 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1326 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1330 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1332 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1333 priv->anaparam = le32_to_cpu(anaparam);
1334 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1337 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1338 RTL818X_EEPROM_CMD_NORMAL);
1341 static int rtl8180_probe(struct pci_dev *pdev,
1342 const struct pci_device_id *id)
1344 struct ieee80211_hw *dev;
1345 struct rtl8180_priv *priv;
1346 unsigned long mem_addr, mem_len;
1347 unsigned int io_addr, io_len;
1349 const char *chip_name, *rf_name = NULL;
1352 err = pci_enable_device(pdev);
1354 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
1359 err = pci_request_regions(pdev, KBUILD_MODNAME);
1361 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
1366 io_addr = pci_resource_start(pdev, 0);
1367 io_len = pci_resource_len(pdev, 0);
1368 mem_addr = pci_resource_start(pdev, 1);
1369 mem_len = pci_resource_len(pdev, 1);
1371 if (mem_len < sizeof(struct rtl818x_csr) ||
1372 io_len < sizeof(struct rtl818x_csr)) {
1373 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
1379 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1380 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1381 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
1386 pci_set_master(pdev);
1388 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1390 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1400 SET_IEEE80211_DEV(dev, &pdev->dev);
1401 pci_set_drvdata(pdev, dev);
1403 priv->map = pci_iomap(pdev, 1, mem_len);
1405 priv->map = pci_iomap(pdev, 0, io_len);
1408 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
1413 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1414 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1416 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1417 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1419 priv->band.band = IEEE80211_BAND_2GHZ;
1420 priv->band.channels = priv->channels;
1421 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1422 priv->band.bitrates = priv->rates;
1423 priv->band.n_bitrates = 4;
1424 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1426 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1427 IEEE80211_HW_RX_INCLUDES_FCS |
1428 IEEE80211_HW_SIGNAL_UNSPEC;
1429 dev->vif_data_size = sizeof(struct rtl8180_vif);
1430 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1431 BIT(NL80211_IFTYPE_ADHOC);
1432 dev->max_signal = 65;
1434 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1435 reg &= RTL818X_TX_CONF_HWVER_MASK;
1437 case RTL818X_TX_CONF_R8180_ABCD:
1438 chip_name = "RTL8180";
1439 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1442 case RTL818X_TX_CONF_R8180_F:
1443 chip_name = "RTL8180vF";
1444 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1447 case RTL818X_TX_CONF_R8185_ABC:
1448 chip_name = "RTL8185";
1449 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1452 case RTL818X_TX_CONF_R8185_D:
1453 chip_name = "RTL8185vD";
1454 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1457 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1458 pci_name(pdev), reg >> 25);
1462 /* we declare to MAC80211 all the queues except for beacon queue
1463 * that will be eventually handled by DRV.
1464 * TX rings are arranged in such a way that lower is the IDX,
1465 * higher is the priority, in order to achieve direct mapping
1466 * with mac80211, however the beacon queue is an exception and it
1467 * is mapped on the highst tx ring IDX.
1469 dev->queues = RTL8180_NR_TX_QUEUES - 1;
1471 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1472 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1473 pci_try_set_mwi(pdev);
1476 rtl8180_eeprom_read(priv);
1478 switch (priv->rf_type) {
1479 case 1: rf_name = "Intersil";
1481 case 2: rf_name = "RFMD";
1483 case 3: priv->rf = &sa2400_rf_ops;
1485 case 4: priv->rf = &max2820_rf_ops;
1487 case 5: priv->rf = &grf5101_rf_ops;
1489 case 9: priv->rf = rtl8180_detect_rf(dev);
1492 rf_name = "RTL8255";
1495 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1496 pci_name(pdev), priv->rf_type);
1501 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1502 pci_name(pdev), rf_name);
1506 if (!is_valid_ether_addr(priv->mac_addr)) {
1507 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1508 " randomly generated MAC addr\n", pci_name(pdev));
1509 eth_random_addr(priv->mac_addr);
1511 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
1513 spin_lock_init(&priv->lock);
1515 err = ieee80211_register_hw(dev);
1517 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1522 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1523 priv->mac_addr, chip_name, priv->rf->name);
1528 pci_iounmap(pdev, priv->map);
1531 ieee80211_free_hw(dev);
1534 pci_release_regions(pdev);
1535 pci_disable_device(pdev);
1539 static void rtl8180_remove(struct pci_dev *pdev)
1541 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1542 struct rtl8180_priv *priv;
1547 ieee80211_unregister_hw(dev);
1551 pci_iounmap(pdev, priv->map);
1552 pci_release_regions(pdev);
1553 pci_disable_device(pdev);
1554 ieee80211_free_hw(dev);
1558 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1560 pci_save_state(pdev);
1561 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1565 static int rtl8180_resume(struct pci_dev *pdev)
1567 pci_set_power_state(pdev, PCI_D0);
1568 pci_restore_state(pdev);
1572 #endif /* CONFIG_PM */
1574 static struct pci_driver rtl8180_driver = {
1575 .name = KBUILD_MODNAME,
1576 .id_table = rtl8180_table,
1577 .probe = rtl8180_probe,
1578 .remove = rtl8180_remove,
1580 .suspend = rtl8180_suspend,
1581 .resume = rtl8180_resume,
1582 #endif /* CONFIG_PM */
1585 module_pci_driver(rtl8180_driver);