drivers/net/wireless/rt2x00/rt73usb.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: rt73usb device specific routines.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt73usb.h"
  38
  39 /*
  40  * Allow hardware encryption to be disabled.
  41  */
  42 static int modparam_nohwcrypt = 0;
  43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt73usb_register_read and rt73usb_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the usb_cache_mutex
  59  */
  60 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
  61                                          const unsigned int offset, u32 *value)
  62 {
  63         __le32 reg;
  64         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  65                                       USB_VENDOR_REQUEST_IN, offset,
  66                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  67         *value = le32_to_cpu(reg);
  68 }
  69
  70 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
  71                                               const unsigned int offset, u32 *value)
  72 {
  73         __le32 reg;
  74         rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
  75                                        USB_VENDOR_REQUEST_IN, offset,
  76                                        &reg, sizeof(u32), REGISTER_TIMEOUT);
  77         *value = le32_to_cpu(reg);
  78 }
  79
  80 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
  81                                               const unsigned int offset,
  82                                               void *value, const u32 length)
  83 {
  84         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  85                                       USB_VENDOR_REQUEST_IN, offset,
  86                                       value, length,
  87                                       REGISTER_TIMEOUT32(length));
  88 }
  89
  90 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
  91                                           const unsigned int offset, u32 value)
  92 {
  93         __le32 reg = cpu_to_le32(value);
  94         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
  95                                       USB_VENDOR_REQUEST_OUT, offset,
  96                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  97 }
  98
  99 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
 100                                                const unsigned int offset, u32 value)
 101 {
 102         __le32 reg = cpu_to_le32(value);
 103         rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
 104                                        USB_VENDOR_REQUEST_OUT, offset,
 105                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
 106 }
 107
 108 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
 109                                                const unsigned int offset,
 110                                                void *value, const u32 length)
 111 {
 112         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
 113                                       USB_VENDOR_REQUEST_OUT, offset,
 114                                       value, length,
 115                                       REGISTER_TIMEOUT32(length));
 116 }
 117
 118 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
 119 {
 120         u32 reg;
 121         unsigned int i;
 122
 123         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 124                 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
 125                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 126                         break;
 127                 udelay(REGISTER_BUSY_DELAY);
 128         }
 129
 130         return reg;
 131 }
 132
 133 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
 134                               const unsigned int word, const u8 value)
 135 {
 136         u32 reg;
 137
 138         mutex_lock(&rt2x00dev->usb_cache_mutex);
 139
 140         /*
 141          * Wait until the BBP becomes ready.
 142          */
 143         reg = rt73usb_bbp_check(rt2x00dev);
 144         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 145                 goto exit_fail;
 146
 147         /*
 148          * Write the data into the BBP.
 149          */
 150         reg = 0;
 151         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
 152         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 153         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 154         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
 155
 156         rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 157         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 158
 159         return;
 160
 161 exit_fail:
 162         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 163
 164         ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
 165 }
 166
 167 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
 168                              const unsigned int word, u8 *value)
 169 {
 170         u32 reg;
 171
 172         mutex_lock(&rt2x00dev->usb_cache_mutex);
 173
 174         /*
 175          * Wait until the BBP becomes ready.
 176          */
 177         reg = rt73usb_bbp_check(rt2x00dev);
 178         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 179                 goto exit_fail;
 180
 181         /*
 182          * Write the request into the BBP.
 183          */
 184         reg = 0;
 185         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 186         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 187         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 188
 189         rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 190
 191         /*
 192          * Wait until the BBP becomes ready.
 193          */
 194         reg = rt73usb_bbp_check(rt2x00dev);
 195         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 196                 goto exit_fail;
 197
 198         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 199         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 200
 201         return;
 202
 203 exit_fail:
 204         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 205
 206         ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 207         *value = 0xff;
 208 }
 209
 210 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
 211                              const unsigned int word, const u32 value)
 212 {
 213         u32 reg;
 214         unsigned int i;
 215
 216         if (!word)
 217                 return;
 218
 219         mutex_lock(&rt2x00dev->usb_cache_mutex);
 220
 221         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 222                 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
 223                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 224                         goto rf_write;
 225                 udelay(REGISTER_BUSY_DELAY);
 226         }
 227
 228         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 229         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 230         return;
 231
 232 rf_write:
 233         reg = 0;
 234         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 235
 236         /*
 237          * RF5225 and RF2527 contain 21 bits per RF register value,
 238          * all others contain 20 bits.
 239          */
 240         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
 241                            20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 242                                  rt2x00_rf(&rt2x00dev->chip, RF2527)));
 243         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 244         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 245
 246         rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
 247         rt2x00_rf_write(rt2x00dev, word, value);
 248         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 249 }
 250
 251 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 252 static const struct rt2x00debug rt73usb_rt2x00debug = {
 253         .owner  = THIS_MODULE,
 254         .csr    = {
 255                 .read           = rt73usb_register_read,
 256                 .write          = rt73usb_register_write,
 257                 .flags          = RT2X00DEBUGFS_OFFSET,
 258                 .word_base      = CSR_REG_BASE,
 259                 .word_size      = sizeof(u32),
 260                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 261         },
 262         .eeprom = {
 263                 .read           = rt2x00_eeprom_read,
 264                 .write          = rt2x00_eeprom_write,
 265                 .word_base      = EEPROM_BASE,
 266                 .word_size      = sizeof(u16),
 267                 .word_count     = EEPROM_SIZE / sizeof(u16),
 268         },
 269         .bbp    = {
 270                 .read           = rt73usb_bbp_read,
 271                 .write          = rt73usb_bbp_write,
 272                 .word_base      = BBP_BASE,
 273                 .word_size      = sizeof(u8),
 274                 .word_count     = BBP_SIZE / sizeof(u8),
 275         },
 276         .rf     = {
 277                 .read           = rt2x00_rf_read,
 278                 .write          = rt73usb_rf_write,
 279                 .word_base      = RF_BASE,
 280                 .word_size      = sizeof(u32),
 281                 .word_count     = RF_SIZE / sizeof(u32),
 282         },
 283 };
 284 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 285
 286 #ifdef CONFIG_RT2X00_LIB_LEDS
 287 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
 288                                    enum led_brightness brightness)
 289 {
 290         struct rt2x00_led *led =
 291            container_of(led_cdev, struct rt2x00_led, led_dev);
 292         unsigned int enabled = brightness != LED_OFF;
 293         unsigned int a_mode =
 294             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 295         unsigned int bg_mode =
 296             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 297
 298         if (led->type == LED_TYPE_RADIO) {
 299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 300                                    MCU_LEDCS_RADIO_STATUS, enabled);
 301
 302                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 303                                             0, led->rt2x00dev->led_mcu_reg,
 304                                             REGISTER_TIMEOUT);
 305         } else if (led->type == LED_TYPE_ASSOC) {
 306                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 307                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 308                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 309                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 310
 311                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 312                                             0, led->rt2x00dev->led_mcu_reg,
 313                                             REGISTER_TIMEOUT);
 314         } else if (led->type == LED_TYPE_QUALITY) {
 315                 /*
 316                  * The brightness is divided into 6 levels (0 - 5),
 317                  * this means we need to convert the brightness
 318                  * argument into the matching level within that range.
 319                  */
 320                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 321                                             brightness / (LED_FULL / 6),
 322                                             led->rt2x00dev->led_mcu_reg,
 323                                             REGISTER_TIMEOUT);
 324         }
 325 }
 326
 327 static int rt73usb_blink_set(struct led_classdev *led_cdev,
 328                              unsigned long *delay_on,
 329                              unsigned long *delay_off)
 330 {
 331         struct rt2x00_led *led =
 332             container_of(led_cdev, struct rt2x00_led, led_dev);
 333         u32 reg;
 334
 335         rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 336         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 337         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 338         rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
 339
 340         return 0;
 341 }
 342
 343 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
 344                              struct rt2x00_led *led,
 345                              enum led_type type)
 346 {
 347         led->rt2x00dev = rt2x00dev;
 348         led->type = type;
 349         led->led_dev.brightness_set = rt73usb_brightness_set;
 350         led->led_dev.blink_set = rt73usb_blink_set;
 351         led->flags = LED_INITIALIZED;
 352 }
 353 #endif /* CONFIG_RT2X00_LIB_LEDS */
 354
 355 /*
 356  * Configuration handlers.
 357  */
 358 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 359                                      struct rt2x00lib_crypto *crypto,
 360                                      struct ieee80211_key_conf *key)
 361 {
 362         struct hw_key_entry key_entry;
 363         struct rt2x00_field32 field;
 364         int timeout;
 365         u32 mask;
 366         u32 reg;
 367
 368         if (crypto->cmd == SET_KEY) {
 369                 /*
 370                  * rt2x00lib can't determine the correct free
 371                  * key_idx for shared keys. We have 1 register
 372                  * with key valid bits. The goal is simple, read
 373                  * the register, if that is full we have no slots
 374                  * left.
 375                  * Note that each BSS is allowed to have up to 4
 376                  * shared keys, so put a mask over the allowed
 377                  * entries.
 378                  */
 379                 mask = (0xf << crypto->bssidx);
 380
 381                 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 382                 reg &= mask;
 383
 384                 if (reg && reg == mask)
 385                         return -ENOSPC;
 386
 387                 key->hw_key_idx += reg ? ffz(reg) : 0;
 388
 389                 /*
 390                  * Upload key to hardware
 391                  */
 392                 memcpy(key_entry.key, crypto->key,
 393                        sizeof(key_entry.key));
 394                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 395                        sizeof(key_entry.tx_mic));
 396                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 397                        sizeof(key_entry.rx_mic));
 398
 399                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 400                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 401                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 402                                                     USB_VENDOR_REQUEST_OUT, reg,
 403                                                     &key_entry,
 404                                                     sizeof(key_entry),
 405                                                     timeout);
 406
 407                 /*
 408                  * The cipher types are stored over 2 registers.
 409                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 410                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 411                  * Using the correct defines correctly will cause overhead,
 412                  * so just calculate the correct offset.
 413                  */
 414                 if (key->hw_key_idx < 8) {
 415                         field.bit_offset = (3 * key->hw_key_idx);
 416                         field.bit_mask = 0x7 << field.bit_offset;
 417
 418                         rt73usb_register_read(rt2x00dev, SEC_CSR1, &reg);
 419                         rt2x00_set_field32(&reg, field, crypto->cipher);
 420                         rt73usb_register_write(rt2x00dev, SEC_CSR1, reg);
 421                 } else {
 422                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 423                         field.bit_mask = 0x7 << field.bit_offset;
 424
 425                         rt73usb_register_read(rt2x00dev, SEC_CSR5, &reg);
 426                         rt2x00_set_field32(&reg, field, crypto->cipher);
 427                         rt73usb_register_write(rt2x00dev, SEC_CSR5, reg);
 428                 }
 429
 430                 /*
 431                  * The driver does not support the IV/EIV generation
 432                  * in hardware. However it doesn't support the IV/EIV
 433                  * inside the ieee80211 frame either, but requires it
 434                  * to be provided seperately for the descriptor.
 435                  * rt2x00lib will cut the IV/EIV data out of all frames
 436                  * given to us by mac80211, but we must tell mac80211
 437                  * to generate the IV/EIV data.
 438                  */
 439                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 440         }
 441
 442         /*
 443          * SEC_CSR0 contains only single-bit fields to indicate
 444          * a particular key is valid. Because using the FIELD32()
 445          * defines directly will cause a lot of overhead we use
 446          * a calculation to determine the correct bit directly.
 447          */
 448         mask = 1 << key->hw_key_idx;
 449
 450         rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 451         if (crypto->cmd == SET_KEY)
 452                 reg |= mask;
 453         else if (crypto->cmd == DISABLE_KEY)
 454                 reg &= ~mask;
 455         rt73usb_register_write(rt2x00dev, SEC_CSR0, reg);
 456
 457         return 0;
 458 }
 459
 460 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 461                                        struct rt2x00lib_crypto *crypto,
 462                                        struct ieee80211_key_conf *key)
 463 {
 464         struct hw_pairwise_ta_entry addr_entry;
 465         struct hw_key_entry key_entry;
 466         int timeout;
 467         u32 mask;
 468         u32 reg;
 469
 470         if (crypto->cmd == SET_KEY) {
 471                 /*
 472                  * rt2x00lib can't determine the correct free
 473                  * key_idx for pairwise keys. We have 2 registers
 474                  * with key valid bits. The goal is simple, read
 475                  * the first register, if that is full move to
 476                  * the next register.
 477                  * When both registers are full, we drop the key,
 478                  * otherwise we use the first invalid entry.
 479                  */
 480                 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 481                 if (reg && reg == ~0) {
 482                         key->hw_key_idx = 32;
 483                         rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 484                         if (reg && reg == ~0)
 485                                 return -ENOSPC;
 486                 }
 487
 488                 key->hw_key_idx += reg ? ffz(reg) : 0;
 489
 490                 /*
 491                  * Upload key to hardware
 492                  */
 493                 memcpy(key_entry.key, crypto->key,
 494                        sizeof(key_entry.key));
 495                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 496                        sizeof(key_entry.tx_mic));
 497                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 498                        sizeof(key_entry.rx_mic));
 499
 500                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 501                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 502                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 503                                                     USB_VENDOR_REQUEST_OUT, reg,
 504                                                     &key_entry,
 505                                                     sizeof(key_entry),
 506                                                     timeout);
 507
 508                 /*
 509                  * Send the address and cipher type to the hardware register.
 510                  * This data fits within the CSR cache size, so we can use
 511                  * rt73usb_register_multiwrite() directly.
 512                  */
 513                 memset(&addr_entry, 0, sizeof(addr_entry));
 514                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 515                 addr_entry.cipher = crypto->cipher;
 516
 517                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 518                 rt73usb_register_multiwrite(rt2x00dev, reg,
 519                                             &addr_entry, sizeof(addr_entry));
 520
 521                 /*
 522                  * Enable pairwise lookup table for given BSS idx,
 523                  * without this received frames will not be decrypted
 524                  * by the hardware.
 525                  */
 526                 rt73usb_register_read(rt2x00dev, SEC_CSR4, &reg);
 527                 reg |= (1 << crypto->bssidx);
 528                 rt73usb_register_write(rt2x00dev, SEC_CSR4, reg);
 529
 530                 /*
 531                  * The driver does not support the IV/EIV generation
 532                  * in hardware. However it doesn't support the IV/EIV
 533                  * inside the ieee80211 frame either, but requires it
 534                  * to be provided seperately for the descriptor.
 535                  * rt2x00lib will cut the IV/EIV data out of all frames
 536                  * given to us by mac80211, but we must tell mac80211
 537                  * to generate the IV/EIV data.
 538                  */
 539                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 540         }
 541
 542         /*
 543          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 544          * a particular key is valid. Because using the FIELD32()
 545          * defines directly will cause a lot of overhead we use
 546          * a calculation to determine the correct bit directly.
 547          */
 548         if (key->hw_key_idx < 32) {
 549                 mask = 1 << key->hw_key_idx;
 550
 551                 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 552                 if (crypto->cmd == SET_KEY)
 553                         reg |= mask;
 554                 else if (crypto->cmd == DISABLE_KEY)
 555                         reg &= ~mask;
 556                 rt73usb_register_write(rt2x00dev, SEC_CSR2, reg);
 557         } else {
 558                 mask = 1 << (key->hw_key_idx - 32);
 559
 560                 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 561                 if (crypto->cmd == SET_KEY)
 562                         reg |= mask;
 563                 else if (crypto->cmd == DISABLE_KEY)
 564                         reg &= ~mask;
 565                 rt73usb_register_write(rt2x00dev, SEC_CSR3, reg);
 566         }
 567
 568         return 0;
 569 }
 570
 571 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
 572                                   const unsigned int filter_flags)
 573 {
 574         u32 reg;
 575
 576         /*
 577          * Start configuration steps.
 578          * Note that the version error will always be dropped
 579          * and broadcast frames will always be accepted since
 580          * there is no filter for it at this time.
 581          */
 582         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 583         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 584                            !(filter_flags & FIF_FCSFAIL));
 585         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 586                            !(filter_flags & FIF_PLCPFAIL));
 587         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 588                            !(filter_flags & FIF_CONTROL));
 589         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 590                            !(filter_flags & FIF_PROMISC_IN_BSS));
 591         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 592                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 593                            !rt2x00dev->intf_ap_count);
 594         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 595         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 596                            !(filter_flags & FIF_ALLMULTI));
 597         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 598         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 599                            !(filter_flags & FIF_CONTROL));
 600         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 601 }
 602
 603 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
 604                                 struct rt2x00_intf *intf,
 605                                 struct rt2x00intf_conf *conf,
 606                                 const unsigned int flags)
 607 {
 608         unsigned int beacon_base;
 609         u32 reg;
 610
 611         if (flags & CONFIG_UPDATE_TYPE) {
 612                 /*
 613                  * Clear current synchronisation setup.
 614                  * For the Beacon base registers we only need to clear
 615                  * the first byte since that byte contains the VALID and OWNER
 616                  * bits which (when set to 0) will invalidate the entire beacon.
 617                  */
 618                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 619                 rt73usb_register_write(rt2x00dev, beacon_base, 0);
 620
 621                 /*
 622                  * Enable synchronisation.
 623                  */
 624                 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 625                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 626                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 627                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 628                 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 629         }
 630
 631         if (flags & CONFIG_UPDATE_MAC) {
 632                 reg = le32_to_cpu(conf->mac[1]);
 633                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 634                 conf->mac[1] = cpu_to_le32(reg);
 635
 636                 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
 637                                             conf->mac, sizeof(conf->mac));
 638         }
 639
 640         if (flags & CONFIG_UPDATE_BSSID) {
 641                 reg = le32_to_cpu(conf->bssid[1]);
 642                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 643                 conf->bssid[1] = cpu_to_le32(reg);
 644
 645                 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
 646                                             conf->bssid, sizeof(conf->bssid));
 647         }
 648 }
 649
 650 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
 651                                struct rt2x00lib_erp *erp)
 652 {
 653         u32 reg;
 654
 655         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 656         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 657         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 658
 659         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 660         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 661                            !!erp->short_preamble);
 662         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 663
 664         rt73usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
 665
 666         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
 667         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 668         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
 669
 670         rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
 671         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 672         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 673         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 674         rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
 675 }
 676
 677 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 678                                       struct antenna_setup *ant)
 679 {
 680         u8 r3;
 681         u8 r4;
 682         u8 r77;
 683         u8 temp;
 684
 685         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 686         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 687         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 688
 689         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 690
 691         /*
 692          * Configure the RX antenna.
 693          */
 694         switch (ant->rx) {
 695         case ANTENNA_HW_DIVERSITY:
 696                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 697                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
 698                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
 699                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
 700                 break;
 701         case ANTENNA_A:
 702                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 703                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 704                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 705                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 706                 else
 707                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 708                 break;
 709         case ANTENNA_B:
 710         default:
 711                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 712                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 713                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 714                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 715                 else
 716                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 717                 break;
 718         }
 719
 720         rt73usb_bbp_write(rt2x00dev, 77, r77);
 721         rt73usb_bbp_write(rt2x00dev, 3, r3);
 722         rt73usb_bbp_write(rt2x00dev, 4, r4);
 723 }
 724
 725 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 726                                       struct antenna_setup *ant)
 727 {
 728         u8 r3;
 729         u8 r4;
 730         u8 r77;
 731
 732         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 733         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 734         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 735
 736         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 737         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 738                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 739
 740         /*
 741          * Configure the RX antenna.
 742          */
 743         switch (ant->rx) {
 744         case ANTENNA_HW_DIVERSITY:
 745                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 746                 break;
 747         case ANTENNA_A:
 748                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 749                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 750                 break;
 751         case ANTENNA_B:
 752         default:
 753                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 754                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 755                 break;
 756         }
 757
 758         rt73usb_bbp_write(rt2x00dev, 77, r77);
 759         rt73usb_bbp_write(rt2x00dev, 3, r3);
 760         rt73usb_bbp_write(rt2x00dev, 4, r4);
 761 }
 762
 763 struct antenna_sel {
 764         u8 word;
 765         /*
 766          * value[0] -> non-LNA
 767          * value[1] -> LNA
 768          */
 769         u8 value[2];
 770 };
 771
 772 static const struct antenna_sel antenna_sel_a[] = {
 773         { 96,  { 0x58, 0x78 } },
 774         { 104, { 0x38, 0x48 } },
 775         { 75,  { 0xfe, 0x80 } },
 776         { 86,  { 0xfe, 0x80 } },
 777         { 88,  { 0xfe, 0x80 } },
 778         { 35,  { 0x60, 0x60 } },
 779         { 97,  { 0x58, 0x58 } },
 780         { 98,  { 0x58, 0x58 } },
 781 };
 782
 783 static const struct antenna_sel antenna_sel_bg[] = {
 784         { 96,  { 0x48, 0x68 } },
 785         { 104, { 0x2c, 0x3c } },
 786         { 75,  { 0xfe, 0x80 } },
 787         { 86,  { 0xfe, 0x80 } },
 788         { 88,  { 0xfe, 0x80 } },
 789         { 35,  { 0x50, 0x50 } },
 790         { 97,  { 0x48, 0x48 } },
 791         { 98,  { 0x48, 0x48 } },
 792 };
 793
 794 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
 795                                struct antenna_setup *ant)
 796 {
 797         const struct antenna_sel *sel;
 798         unsigned int lna;
 799         unsigned int i;
 800         u32 reg;
 801
 802         /*
 803          * We should never come here because rt2x00lib is supposed
 804          * to catch this and send us the correct antenna explicitely.
 805          */
 806         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 807                ant->tx == ANTENNA_SW_DIVERSITY);
 808
 809         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 810                 sel = antenna_sel_a;
 811                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 812         } else {
 813                 sel = antenna_sel_bg;
 814                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 815         }
 816
 817         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 818                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 819
 820         rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
 821
 822         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 823                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
 824         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 825                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
 826
 827         rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
 828
 829         if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
 830             rt2x00_rf(&rt2x00dev->chip, RF5225))
 831                 rt73usb_config_antenna_5x(rt2x00dev, ant);
 832         else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
 833                  rt2x00_rf(&rt2x00dev->chip, RF2527))
 834                 rt73usb_config_antenna_2x(rt2x00dev, ant);
 835 }
 836
 837 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 838                                     struct rt2x00lib_conf *libconf)
 839 {
 840         u16 eeprom;
 841         short lna_gain = 0;
 842
 843         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 844                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 845                         lna_gain += 14;
 846
 847                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 848                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 849         } else {
 850                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 851                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 852         }
 853
 854         rt2x00dev->lna_gain = lna_gain;
 855 }
 856
 857 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
 858                                    struct rf_channel *rf, const int txpower)
 859 {
 860         u8 r3;
 861         u8 r94;
 862         u8 smart;
 863
 864         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 865         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 866
 867         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 868                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 869
 870         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 871         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 872         rt73usb_bbp_write(rt2x00dev, 3, r3);
 873
 874         r94 = 6;
 875         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 876                 r94 += txpower - MAX_TXPOWER;
 877         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 878                 r94 += txpower;
 879         rt73usb_bbp_write(rt2x00dev, 94, r94);
 880
 881         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 882         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 883         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 884         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 885
 886         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 887         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 888         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 889         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 890
 891         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 892         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 893         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 894         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 895
 896         udelay(10);
 897 }
 898
 899 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 900                                    const int txpower)
 901 {
 902         struct rf_channel rf;
 903
 904         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 905         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 906         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 907         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 908
 909         rt73usb_config_channel(rt2x00dev, &rf, txpower);
 910 }
 911
 912 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 913                                        struct rt2x00lib_conf *libconf)
 914 {
 915         u32 reg;
 916
 917         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 918         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 919                            libconf->conf->long_frame_max_tx_count);
 920         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 921                            libconf->conf->short_frame_max_tx_count);
 922         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 923 }
 924
 925 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
 926                                     struct rt2x00lib_conf *libconf)
 927 {
 928         u32 reg;
 929
 930         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 931         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 932         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 933
 934         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 935         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 936         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 937
 938         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 939         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 940                            libconf->conf->beacon_int * 16);
 941         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 942 }
 943
 944 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
 945                            struct rt2x00lib_conf *libconf,
 946                            const unsigned int flags)
 947 {
 948         /* Always recalculate LNA gain before changing configuration */
 949         rt73usb_config_lna_gain(rt2x00dev, libconf);
 950
 951         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 952                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
 953                                        libconf->conf->power_level);
 954         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 955             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 956                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 957         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 958                 rt73usb_config_retry_limit(rt2x00dev, libconf);
 959         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
 960                 rt73usb_config_duration(rt2x00dev, libconf);
 961 }
 962
 963 /*
 964  * Link tuning
 965  */
 966 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
 967                                struct link_qual *qual)
 968 {
 969         u32 reg;
 970
 971         /*
 972          * Update FCS error count from register.
 973          */
 974         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
 975         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 976
 977         /*
 978          * Update False CCA count from register.
 979          */
 980         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
 981         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 982 }
 983
 984 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
 985 {
 986         rt73usb_bbp_write(rt2x00dev, 17, 0x20);
 987         rt2x00dev->link.vgc_level = 0x20;
 988 }
 989
 990 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
 991 {
 992         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 993         u8 r17;
 994         u8 up_bound;
 995         u8 low_bound;
 996
 997         rt73usb_bbp_read(rt2x00dev, 17, &r17);
 998
 999         /*
1000          * Determine r17 bounds.
1001          */
1002         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1003                 low_bound = 0x28;
1004                 up_bound = 0x48;
1005
1006                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1007                         low_bound += 0x10;
1008                         up_bound += 0x10;
1009                 }
1010         } else {
1011                 if (rssi > -82) {
1012                         low_bound = 0x1c;
1013                         up_bound = 0x40;
1014                 } else if (rssi > -84) {
1015                         low_bound = 0x1c;
1016                         up_bound = 0x20;
1017                 } else {
1018                         low_bound = 0x1c;
1019                         up_bound = 0x1c;
1020                 }
1021
1022                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1023                         low_bound += 0x14;
1024                         up_bound += 0x10;
1025                 }
1026         }
1027
1028         /*
1029          * If we are not associated, we should go straight to the
1030          * dynamic CCA tuning.
1031          */
1032         if (!rt2x00dev->intf_associated)
1033                 goto dynamic_cca_tune;
1034
1035         /*
1036          * Special big-R17 for very short distance
1037          */
1038         if (rssi > -35) {
1039                 if (r17 != 0x60)
1040                         rt73usb_bbp_write(rt2x00dev, 17, 0x60);
1041                 return;
1042         }
1043
1044         /*
1045          * Special big-R17 for short distance
1046          */
1047         if (rssi >= -58) {
1048                 if (r17 != up_bound)
1049                         rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1050                 return;
1051         }
1052
1053         /*
1054          * Special big-R17 for middle-short distance
1055          */
1056         if (rssi >= -66) {
1057                 low_bound += 0x10;
1058                 if (r17 != low_bound)
1059                         rt73usb_bbp_write(rt2x00dev, 17, low_bound);
1060                 return;
1061         }
1062
1063         /*
1064          * Special mid-R17 for middle distance
1065          */
1066         if (rssi >= -74) {
1067                 if (r17 != (low_bound + 0x10))
1068                         rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
1069                 return;
1070         }
1071
1072         /*
1073          * Special case: Change up_bound based on the rssi.
1074          * Lower up_bound when rssi is weaker then -74 dBm.
1075          */
1076         up_bound -= 2 * (-74 - rssi);
1077         if (low_bound > up_bound)
1078                 up_bound = low_bound;
1079
1080         if (r17 > up_bound) {
1081                 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1082                 return;
1083         }
1084
1085 dynamic_cca_tune:
1086
1087         /*
1088          * r17 does not yet exceed upper limit, continue and base
1089          * the r17 tuning on the false CCA count.
1090          */
1091         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1092                 r17 += 4;
1093                 if (r17 > up_bound)
1094                         r17 = up_bound;
1095                 rt73usb_bbp_write(rt2x00dev, 17, r17);
1096         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1097                 r17 -= 4;
1098                 if (r17 < low_bound)
1099                         r17 = low_bound;
1100                 rt73usb_bbp_write(rt2x00dev, 17, r17);
1101         }
1102 }
1103
1104 /*
1105  * Firmware functions
1106  */
1107 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1108 {
1109         return FIRMWARE_RT2571;
1110 }
1111
1112 static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
1113 {
1114         u16 crc;
1115
1116         /*
1117          * Use the crc itu-t algorithm.
1118          * The last 2 bytes in the firmware array are the crc checksum itself,
1119          * this means that we should never pass those 2 bytes to the crc
1120          * algorithm.
1121          */
1122         crc = crc_itu_t(0, data, len - 2);
1123         crc = crc_itu_t_byte(crc, 0);
1124         crc = crc_itu_t_byte(crc, 0);
1125
1126         return crc;
1127 }
1128
1129 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1130                                  const size_t len)
1131 {
1132         unsigned int i;
1133         int status;
1134         u32 reg;
1135
1136         /*
1137          * Wait for stable hardware.
1138          */
1139         for (i = 0; i < 100; i++) {
1140                 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1141                 if (reg)
1142                         break;
1143                 msleep(1);
1144         }
1145
1146         if (!reg) {
1147                 ERROR(rt2x00dev, "Unstable hardware.\n");
1148                 return -EBUSY;
1149         }
1150
1151         /*
1152          * Write firmware to device.
1153          */
1154         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1155                                             USB_VENDOR_REQUEST_OUT,
1156                                             FIRMWARE_IMAGE_BASE,
1157                                             data, len,
1158                                             REGISTER_TIMEOUT32(len));
1159
1160         /*
1161          * Send firmware request to device to load firmware,
1162          * we need to specify a long timeout time.
1163          */
1164         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1165                                              0, USB_MODE_FIRMWARE,
1166                                              REGISTER_TIMEOUT_FIRMWARE);
1167         if (status < 0) {
1168                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1169                 return status;
1170         }
1171
1172         return 0;
1173 }
1174
1175 /*
1176  * Initialization functions.
1177  */
1178 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1179 {
1180         u32 reg;
1181
1182         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1183         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1184         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1185         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1186         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1187
1188         rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1189         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1190         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1191         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1192         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1193         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1194         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1195         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1196         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1197         rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1198
1199         /*
1200          * CCK TXD BBP registers
1201          */
1202         rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1203         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1204         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1205         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1206         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1207         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1208         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1209         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1210         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1211         rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1212
1213         /*
1214          * OFDM TXD BBP registers
1215          */
1216         rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1217         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1218         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1219         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1220         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1221         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1222         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1223         rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1224
1225         rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1226         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1227         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1228         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1229         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1230         rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1231
1232         rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1233         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1234         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1235         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1236         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1237         rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1238
1239         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1240         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1241         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1242         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1243         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1244         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1245         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1246         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1247
1248         rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1249
1250         rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1251         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1252         rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1253
1254         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1255
1256         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1257                 return -EBUSY;
1258
1259         rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1260
1261         /*
1262          * Invalidate all Shared Keys (SEC_CSR0),
1263          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1264          */
1265         rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1266         rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1267         rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1268
1269         reg = 0x000023b0;
1270         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1271             rt2x00_rf(&rt2x00dev->chip, RF2527))
1272                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1273         rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1274
1275         rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1276         rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1277         rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1278
1279         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1280         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1281         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1282
1283         /*
1284          * Clear all beacons
1285          * For the Beacon base registers we only need to clear
1286          * the first byte since that byte contains the VALID and OWNER
1287          * bits which (when set to 0) will invalidate the entire beacon.
1288          */
1289         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1290         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1291         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1292         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1293
1294         /*
1295          * We must clear the error counters.
1296          * These registers are cleared on read,
1297          * so we may pass a useless variable to store the value.
1298          */
1299         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1300         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1301         rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1302
1303         /*
1304          * Reset MAC and BBP registers.
1305          */
1306         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1307         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1308         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1309         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1310
1311         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1312         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1313         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1314         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1315
1316         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1317         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1318         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1319
1320         return 0;
1321 }
1322
1323 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1324 {
1325         unsigned int i;
1326         u8 value;
1327
1328         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1329                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1330                 if ((value != 0xff) && (value != 0x00))
1331                         return 0;
1332                 udelay(REGISTER_BUSY_DELAY);
1333         }
1334
1335         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1336         return -EACCES;
1337 }
1338
1339 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1340 {
1341         unsigned int i;
1342         u16 eeprom;
1343         u8 reg_id;
1344         u8 value;
1345
1346         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1347                 return -EACCES;
1348
1349         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1350         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1351         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1352         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1353         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1354         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1355         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1356         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1357         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1358         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1359         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1360         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1361         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1362         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1363         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1364         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1365         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1366         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1367         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1368         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1369         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1370         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1371         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1372         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1373         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1374
1375         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1376                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1377
1378                 if (eeprom != 0xffff && eeprom != 0x0000) {
1379                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1380                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1381                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1382                 }
1383         }
1384
1385         return 0;
1386 }
1387
1388 /*
1389  * Device state switch handlers.
1390  */
1391 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1392                               enum dev_state state)
1393 {
1394         u32 reg;
1395
1396         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1397         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1398                            (state == STATE_RADIO_RX_OFF) ||
1399                            (state == STATE_RADIO_RX_OFF_LINK));
1400         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1401 }
1402
1403 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1404 {
1405         /*
1406          * Initialize all registers.
1407          */
1408         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1409                      rt73usb_init_bbp(rt2x00dev)))
1410                 return -EIO;
1411
1412         return 0;
1413 }
1414
1415 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1416 {
1417         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1418
1419         /*
1420          * Disable synchronisation.
1421          */
1422         rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1423
1424         rt2x00usb_disable_radio(rt2x00dev);
1425 }
1426
1427 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1428 {
1429         u32 reg;
1430         unsigned int i;
1431         char put_to_sleep;
1432
1433         put_to_sleep = (state != STATE_AWAKE);
1434
1435         rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1436         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1437         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1438         rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1439
1440         /*
1441          * Device is not guaranteed to be in the requested state yet.
1442          * We must wait until the register indicates that the
1443          * device has entered the correct state.
1444          */
1445         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1446                 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1447                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1448                 if (state == !put_to_sleep)
1449                         return 0;
1450                 msleep(10);
1451         }
1452
1453         return -EBUSY;
1454 }
1455
1456 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1457                                     enum dev_state state)
1458 {
1459         int retval = 0;
1460
1461         switch (state) {
1462         case STATE_RADIO_ON:
1463                 retval = rt73usb_enable_radio(rt2x00dev);
1464                 break;
1465         case STATE_RADIO_OFF:
1466                 rt73usb_disable_radio(rt2x00dev);
1467                 break;
1468         case STATE_RADIO_RX_ON:
1469         case STATE_RADIO_RX_ON_LINK:
1470         case STATE_RADIO_RX_OFF:
1471         case STATE_RADIO_RX_OFF_LINK:
1472                 rt73usb_toggle_rx(rt2x00dev, state);
1473                 break;
1474         case STATE_RADIO_IRQ_ON:
1475         case STATE_RADIO_IRQ_OFF:
1476                 /* No support, but no error either */
1477                 break;
1478         case STATE_DEEP_SLEEP:
1479         case STATE_SLEEP:
1480         case STATE_STANDBY:
1481         case STATE_AWAKE:
1482                 retval = rt73usb_set_state(rt2x00dev, state);
1483                 break;
1484         default:
1485                 retval = -ENOTSUPP;
1486                 break;
1487         }
1488
1489         if (unlikely(retval))
1490                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1491                       state, retval);
1492
1493         return retval;
1494 }
1495
1496 /*
1497  * TX descriptor initialization
1498  */
1499 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1500                                   struct sk_buff *skb,
1501                                   struct txentry_desc *txdesc)
1502 {
1503         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1504         __le32 *txd = skbdesc->desc;
1505         u32 word;
1506
1507         /*
1508          * Start writing the descriptor words.
1509          */
1510         rt2x00_desc_read(txd, 1, &word);
1511         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1512         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1513         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1514         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1515         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1516         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1517                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1518         rt2x00_desc_write(txd, 1, word);
1519
1520         rt2x00_desc_read(txd, 2, &word);
1521         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1522         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1523         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1524         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1525         rt2x00_desc_write(txd, 2, word);
1526
1527         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1528                 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1529                 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1530         }
1531
1532         rt2x00_desc_read(txd, 5, &word);
1533         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1534                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1535         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1536         rt2x00_desc_write(txd, 5, word);
1537
1538         rt2x00_desc_read(txd, 0, &word);
1539         rt2x00_set_field32(&word, TXD_W0_BURST,
1540                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1541         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1542         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1543                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1544         rt2x00_set_field32(&word, TXD_W0_ACK,
1545                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1546         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1547                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1548         rt2x00_set_field32(&word, TXD_W0_OFDM,
1549                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1550         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1551         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1552                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1553         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1554                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1555         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1556                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1557         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1558         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1559         rt2x00_set_field32(&word, TXD_W0_BURST2,
1560                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1561         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1562         rt2x00_desc_write(txd, 0, word);
1563 }
1564
1565 /*
1566  * TX data initialization
1567  */
1568 static void rt73usb_write_beacon(struct queue_entry *entry)
1569 {
1570         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1571         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1572         unsigned int beacon_base;
1573         u32 reg;
1574
1575         /*
1576          * Add the descriptor in front of the skb.
1577          */
1578         skb_push(entry->skb, entry->queue->desc_size);
1579         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1580         skbdesc->desc = entry->skb->data;
1581
1582         /*
1583          * Disable beaconing while we are reloading the beacon data,
1584          * otherwise we might be sending out invalid data.
1585          */
1586         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1587         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1588         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1589         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1590         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1591
1592         /*
1593          * Write entire beacon with descriptor to register.
1594          */
1595         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1596         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1597                                             USB_VENDOR_REQUEST_OUT, beacon_base,
1598                                             entry->skb->data, entry->skb->len,
1599                                             REGISTER_TIMEOUT32(entry->skb->len));
1600
1601         /*
1602          * Clean up the beacon skb.
1603          */
1604         dev_kfree_skb(entry->skb);
1605         entry->skb = NULL;
1606 }
1607
1608 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1609                                    struct sk_buff *skb)
1610 {
1611         int length;
1612
1613         /*
1614          * The length _must_ be a multiple of 4,
1615          * but it must _not_ be a multiple of the USB packet size.
1616          */
1617         length = roundup(skb->len, 4);
1618         length += (4 * !(length % rt2x00dev->usb_maxpacket));
1619
1620         return length;
1621 }
1622
1623 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1624                                   const enum data_queue_qid queue)
1625 {
1626         u32 reg;
1627
1628         if (queue != QID_BEACON) {
1629                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1630                 return;
1631         }
1632
1633         /*
1634          * For Wi-Fi faily generated beacons between participating stations.
1635          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1636          */
1637         rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1638
1639         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1640         if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1641                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1642                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1643                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1644                 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1645         }
1646 }
1647
1648 /*
1649  * RX control handlers
1650  */
1651 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1652 {
1653         u8 offset = rt2x00dev->lna_gain;
1654         u8 lna;
1655
1656         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1657         switch (lna) {
1658         case 3:
1659                 offset += 90;
1660                 break;
1661         case 2:
1662                 offset += 74;
1663                 break;
1664         case 1:
1665                 offset += 64;
1666                 break;
1667         default:
1668                 return 0;
1669         }
1670
1671         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1672                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1673                         if (lna == 3 || lna == 2)
1674                                 offset += 10;
1675                 } else {
1676                         if (lna == 3)
1677                                 offset += 6;
1678                         else if (lna == 2)
1679                                 offset += 8;
1680                 }
1681         }
1682
1683         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1684 }
1685
1686 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1687                                 struct rxdone_entry_desc *rxdesc)
1688 {
1689         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1690         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1691         __le32 *rxd = (__le32 *)entry->skb->data;
1692         u32 word0;
1693         u32 word1;
1694
1695         /*
1696          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1697          * frame data in rt2x00usb.
1698          */
1699         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1700         rxd = (__le32 *)skbdesc->desc;
1701
1702         /*
1703          * It is now safe to read the descriptor on all architectures.
1704          */
1705         rt2x00_desc_read(rxd, 0, &word0);
1706         rt2x00_desc_read(rxd, 1, &word1);
1707
1708         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1709                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1710
1711         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1712                 rxdesc->cipher =
1713                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1714                 rxdesc->cipher_status =
1715                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1716         }
1717
1718         if (rxdesc->cipher != CIPHER_NONE) {
1719                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv);
1720                 _rt2x00_desc_read(rxd, 3, &rxdesc->eiv);
1721                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1722
1723                 /*
1724                  * Hardware has stripped IV/EIV data from 802.11 frame during
1725                  * decryption. It has provided the data seperately but rt2x00lib
1726                  * should decide if it should be reinserted.
1727                  */
1728                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1729
1730                 /*
1731                  * FIXME: Legacy driver indicates that the frame does
1732                  * contain the Michael Mic. Unfortunately, in rt2x00
1733                  * the MIC seems to be missing completely...
1734                  */
1735                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1736
1737                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1738                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1739                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1740                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1741         }
1742
1743         /*
1744          * Obtain the status about this packet.
1745          * When frame was received with an OFDM bitrate,
1746          * the signal is the PLCP value. If it was received with
1747          * a CCK bitrate the signal is the rate in 100kbit/s.
1748          */
1749         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1750         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1751         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1752
1753         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1754                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1755         else
1756                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1757         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1758                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1759
1760         /*
1761          * Set skb pointers, and update frame information.
1762          */
1763         skb_pull(entry->skb, entry->queue->desc_size);
1764         skb_trim(entry->skb, rxdesc->size);
1765 }
1766
1767 /*
1768  * Device probe functions.
1769  */
1770 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1771 {
1772         u16 word;
1773         u8 *mac;
1774         s8 value;
1775
1776         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1777
1778         /*
1779          * Start validation of the data that has been read.
1780          */
1781         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1782         if (!is_valid_ether_addr(mac)) {
1783                 random_ether_addr(mac);
1784                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1785         }
1786
1787         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1788         if (word == 0xffff) {
1789                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1790                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1791                                    ANTENNA_B);
1792                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1793                                    ANTENNA_B);
1794                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1795                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1796                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1797                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1798                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1799                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1800         }
1801
1802         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1803         if (word == 0xffff) {
1804                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1805                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1806                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1807         }
1808
1809         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1810         if (word == 0xffff) {
1811                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1812                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1813                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1814                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1815                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1816                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1817                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1818                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1819                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1820                                    LED_MODE_DEFAULT);
1821                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1822                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1823         }
1824
1825         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1826         if (word == 0xffff) {
1827                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1828                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1829                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1830                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1831         }
1832
1833         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1834         if (word == 0xffff) {
1835                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1836                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1837                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1838                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1839         } else {
1840                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1841                 if (value < -10 || value > 10)
1842                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1843                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1844                 if (value < -10 || value > 10)
1845                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1846                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1847         }
1848
1849         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1850         if (word == 0xffff) {
1851                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1852                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1853                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1854                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1855         } else {
1856                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1857                 if (value < -10 || value > 10)
1858                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1859                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1860                 if (value < -10 || value > 10)
1861                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1862                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1863         }
1864
1865         return 0;
1866 }
1867
1868 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1869 {
1870         u32 reg;
1871         u16 value;
1872         u16 eeprom;
1873
1874         /*
1875          * Read EEPROM word for configuration.
1876          */
1877         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1878
1879         /*
1880          * Identify RF chipset.
1881          */
1882         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1883         rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1884         rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1885
1886         if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1887                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1888                 return -ENODEV;
1889         }
1890
1891         if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1892             !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1893             !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1894             !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1895                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1896                 return -ENODEV;
1897         }
1898
1899         /*
1900          * Identify default antenna configuration.
1901          */
1902         rt2x00dev->default_ant.tx =
1903             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1904         rt2x00dev->default_ant.rx =
1905             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1906
1907         /*
1908          * Read the Frame type.
1909          */
1910         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1911                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1912
1913         /*
1914          * Read frequency offset.
1915          */
1916         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1917         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1918
1919         /*
1920          * Read external LNA informations.
1921          */
1922         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1923
1924         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1925                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1926                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1927         }
1928
1929         /*
1930          * Store led settings, for correct led behaviour.
1931          */
1932 #ifdef CONFIG_RT2X00_LIB_LEDS
1933         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1934
1935         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1936         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1937         if (value == LED_MODE_SIGNAL_STRENGTH)
1938                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1939                                  LED_TYPE_QUALITY);
1940
1941         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1942         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1943                            rt2x00_get_field16(eeprom,
1944                                               EEPROM_LED_POLARITY_GPIO_0));
1945         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1946                            rt2x00_get_field16(eeprom,
1947                                               EEPROM_LED_POLARITY_GPIO_1));
1948         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1949                            rt2x00_get_field16(eeprom,
1950                                               EEPROM_LED_POLARITY_GPIO_2));
1951         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1952                            rt2x00_get_field16(eeprom,
1953                                               EEPROM_LED_POLARITY_GPIO_3));
1954         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1955                            rt2x00_get_field16(eeprom,
1956                                               EEPROM_LED_POLARITY_GPIO_4));
1957         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1958                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1959         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1960                            rt2x00_get_field16(eeprom,
1961                                               EEPROM_LED_POLARITY_RDY_G));
1962         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1963                            rt2x00_get_field16(eeprom,
1964                                               EEPROM_LED_POLARITY_RDY_A));
1965 #endif /* CONFIG_RT2X00_LIB_LEDS */
1966
1967         return 0;
1968 }
1969
1970 /*
1971  * RF value list for RF2528
1972  * Supports: 2.4 GHz
1973  */
1974 static const struct rf_channel rf_vals_bg_2528[] = {
1975         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1976         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1977         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1978         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1979         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1980         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1981         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1982         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1983         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1984         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1985         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1986         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1987         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1988         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1989 };
1990
1991 /*
1992  * RF value list for RF5226
1993  * Supports: 2.4 GHz & 5.2 GHz
1994  */
1995 static const struct rf_channel rf_vals_5226[] = {
1996         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1997         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1998         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1999         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
2000         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
2001         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
2002         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
2003         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
2004         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
2005         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
2006         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
2007         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
2008         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
2009         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
2010
2011         /* 802.11 UNI / HyperLan 2 */
2012         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
2013         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
2014         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
2015         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
2016         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2017         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2018         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2019         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2020
2021         /* 802.11 HyperLan 2 */
2022         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2023         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2024         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2025         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2026         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2027         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2028         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2029         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2030         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2031         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2032
2033         /* 802.11 UNII */
2034         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2035         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2036         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2037         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2038         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2039         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2040
2041         /* MMAC(Japan)J52 ch 34,38,42,46 */
2042         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2043         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2044         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2045         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2046 };
2047
2048 /*
2049  * RF value list for RF5225 & RF2527
2050  * Supports: 2.4 GHz & 5.2 GHz
2051  */
2052 static const struct rf_channel rf_vals_5225_2527[] = {
2053         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2054         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2055         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2056         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2057         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2058         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2059         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2060         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2061         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2062         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2063         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2064         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2065         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2066         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2067
2068         /* 802.11 UNI / HyperLan 2 */
2069         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2070         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2071         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2072         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2073         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2074         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2075         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2076         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2077
2078         /* 802.11 HyperLan 2 */
2079         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2080         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2081         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2082         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2083         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2084         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2085         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2086         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2087         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2088         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2089
2090         /* 802.11 UNII */
2091         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2092         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2093         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2094         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2095         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2096         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2097
2098         /* MMAC(Japan)J52 ch 34,38,42,46 */
2099         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2100         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2101         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2102         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2103 };
2104
2105
2106 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2107 {
2108         struct hw_mode_spec *spec = &rt2x00dev->spec;
2109         struct channel_info *info;
2110         char *tx_power;
2111         unsigned int i;
2112
2113         /*
2114          * Initialize all hw fields.
2115          */
2116         rt2x00dev->hw->flags =
2117             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2118             IEEE80211_HW_SIGNAL_DBM;
2119         rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
2120
2121         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2122         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2123                                 rt2x00_eeprom_addr(rt2x00dev,
2124                                                    EEPROM_MAC_ADDR_0));
2125
2126         /*
2127          * Initialize hw_mode information.
2128          */
2129         spec->supported_bands = SUPPORT_BAND_2GHZ;
2130         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2131
2132         if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2133                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2134                 spec->channels = rf_vals_bg_2528;
2135         } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
2136                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2137                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2138                 spec->channels = rf_vals_5226;
2139         } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2140                 spec->num_channels = 14;
2141                 spec->channels = rf_vals_5225_2527;
2142         } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
2143                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2144                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2145                 spec->channels = rf_vals_5225_2527;
2146         }
2147
2148         /*
2149          * Create channel information array
2150          */
2151         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2152         if (!info)
2153                 return -ENOMEM;
2154
2155         spec->channels_info = info;
2156
2157         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2158         for (i = 0; i < 14; i++)
2159                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2160
2161         if (spec->num_channels > 14) {
2162                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2163                 for (i = 14; i < spec->num_channels; i++)
2164                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2165         }
2166
2167         return 0;
2168 }
2169
2170 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2171 {
2172         int retval;
2173
2174         /*
2175          * Allocate eeprom data.
2176          */
2177         retval = rt73usb_validate_eeprom(rt2x00dev);
2178         if (retval)
2179                 return retval;
2180
2181         retval = rt73usb_init_eeprom(rt2x00dev);
2182         if (retval)
2183                 return retval;
2184
2185         /*
2186          * Initialize hw specifications.
2187          */
2188         retval = rt73usb_probe_hw_mode(rt2x00dev);
2189         if (retval)
2190                 return retval;
2191
2192         /*
2193          * This device requires firmware.
2194          */
2195         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2196         __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2197         if (!modparam_nohwcrypt)
2198                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2199
2200         /*
2201          * Set the rssi offset.
2202          */
2203         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2204
2205         return 0;
2206 }
2207
2208 /*
2209  * IEEE80211 stack callback functions.
2210  */
2211 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2212                            const struct ieee80211_tx_queue_params *params)
2213 {
2214         struct rt2x00_dev *rt2x00dev = hw->priv;
2215         struct data_queue *queue;
2216         struct rt2x00_field32 field;
2217         int retval;
2218         u32 reg;
2219
2220         /*
2221          * First pass the configuration through rt2x00lib, that will
2222          * update the queue settings and validate the input. After that
2223          * we are free to update the registers based on the value
2224          * in the queue parameter.
2225          */
2226         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2227         if (retval)
2228                 return retval;
2229
2230         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2231
2232         /* Update WMM TXOP register */
2233         if (queue_idx < 2) {
2234                 field.bit_offset = queue_idx * 16;
2235                 field.bit_mask = 0xffff << field.bit_offset;
2236
2237                 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2238                 rt2x00_set_field32(&reg, field, queue->txop);
2239                 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2240         } else if (queue_idx < 4) {
2241                 field.bit_offset = (queue_idx - 2) * 16;
2242                 field.bit_mask = 0xffff << field.bit_offset;
2243
2244                 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2245                 rt2x00_set_field32(&reg, field, queue->txop);
2246                 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2247         }
2248
2249         /* Update WMM registers */
2250         field.bit_offset = queue_idx * 4;
2251         field.bit_mask = 0xf << field.bit_offset;
2252
2253         rt73usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2254         rt2x00_set_field32(&reg, field, queue->aifs);
2255         rt73usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2256
2257         rt73usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2258         rt2x00_set_field32(&reg, field, queue->cw_min);
2259         rt73usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2260
2261         rt73usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2262         rt2x00_set_field32(&reg, field, queue->cw_max);
2263         rt73usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2264
2265         return 0;
2266 }
2267
2268 #if 0
2269 /*
2270  * Mac80211 demands get_tsf must be atomic.
2271  * This is not possible for rt73usb since all register access
2272  * functions require sleeping. Untill mac80211 no longer needs
2273  * get_tsf to be atomic, this function should be disabled.
2274  */
2275 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2276 {
2277         struct rt2x00_dev *rt2x00dev = hw->priv;
2278         u64 tsf;
2279         u32 reg;
2280
2281         rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2282         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2283         rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2284         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2285
2286         return tsf;
2287 }
2288 #else
2289 #define rt73usb_get_tsf NULL
2290 #endif
2291
2292 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2293         .tx                     = rt2x00mac_tx,
2294         .start                  = rt2x00mac_start,
2295         .stop                   = rt2x00mac_stop,
2296         .add_interface          = rt2x00mac_add_interface,
2297         .remove_interface       = rt2x00mac_remove_interface,
2298         .config                 = rt2x00mac_config,
2299         .config_interface       = rt2x00mac_config_interface,
2300         .configure_filter       = rt2x00mac_configure_filter,
2301         .set_key                = rt2x00mac_set_key,
2302         .get_stats              = rt2x00mac_get_stats,
2303         .bss_info_changed       = rt2x00mac_bss_info_changed,
2304         .conf_tx                = rt73usb_conf_tx,
2305         .get_tx_stats           = rt2x00mac_get_tx_stats,
2306         .get_tsf                = rt73usb_get_tsf,
2307 };
2308
2309 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2310         .probe_hw               = rt73usb_probe_hw,
2311         .get_firmware_name      = rt73usb_get_firmware_name,
2312         .get_firmware_crc       = rt73usb_get_firmware_crc,
2313         .load_firmware          = rt73usb_load_firmware,
2314         .initialize             = rt2x00usb_initialize,
2315         .uninitialize           = rt2x00usb_uninitialize,
2316         .init_rxentry           = rt2x00usb_init_rxentry,
2317         .init_txentry           = rt2x00usb_init_txentry,
2318         .set_device_state       = rt73usb_set_device_state,
2319         .link_stats             = rt73usb_link_stats,
2320         .reset_tuner            = rt73usb_reset_tuner,
2321         .link_tuner             = rt73usb_link_tuner,
2322         .write_tx_desc          = rt73usb_write_tx_desc,
2323         .write_tx_data          = rt2x00usb_write_tx_data,
2324         .write_beacon           = rt73usb_write_beacon,
2325         .get_tx_data_len        = rt73usb_get_tx_data_len,
2326         .kick_tx_queue          = rt73usb_kick_tx_queue,
2327         .fill_rxdone            = rt73usb_fill_rxdone,
2328         .config_shared_key      = rt73usb_config_shared_key,
2329         .config_pairwise_key    = rt73usb_config_pairwise_key,
2330         .config_filter          = rt73usb_config_filter,
2331         .config_intf            = rt73usb_config_intf,
2332         .config_erp             = rt73usb_config_erp,
2333         .config_ant             = rt73usb_config_ant,
2334         .config                 = rt73usb_config,
2335 };
2336
2337 static const struct data_queue_desc rt73usb_queue_rx = {
2338         .entry_num              = RX_ENTRIES,
2339         .data_size              = DATA_FRAME_SIZE,
2340         .desc_size              = RXD_DESC_SIZE,
2341         .priv_size              = sizeof(struct queue_entry_priv_usb),
2342 };
2343
2344 static const struct data_queue_desc rt73usb_queue_tx = {
2345         .entry_num              = TX_ENTRIES,
2346         .data_size              = DATA_FRAME_SIZE,
2347         .desc_size              = TXD_DESC_SIZE,
2348         .priv_size              = sizeof(struct queue_entry_priv_usb),
2349 };
2350
2351 static const struct data_queue_desc rt73usb_queue_bcn = {
2352         .entry_num              = 4 * BEACON_ENTRIES,
2353         .data_size              = MGMT_FRAME_SIZE,
2354         .desc_size              = TXINFO_SIZE,
2355         .priv_size              = sizeof(struct queue_entry_priv_usb),
2356 };
2357
2358 static const struct rt2x00_ops rt73usb_ops = {
2359         .name           = KBUILD_MODNAME,
2360         .max_sta_intf   = 1,
2361         .max_ap_intf    = 4,
2362         .eeprom_size    = EEPROM_SIZE,
2363         .rf_size        = RF_SIZE,
2364         .tx_queues      = NUM_TX_QUEUES,
2365         .rx             = &rt73usb_queue_rx,
2366         .tx             = &rt73usb_queue_tx,
2367         .bcn            = &rt73usb_queue_bcn,
2368         .lib            = &rt73usb_rt2x00_ops,
2369         .hw             = &rt73usb_mac80211_ops,
2370 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2371         .debugfs        = &rt73usb_rt2x00debug,
2372 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2373 };
2374
2375 /*
2376  * rt73usb module information.
2377  */
2378 static struct usb_device_id rt73usb_device_table[] = {
2379         /* AboCom */
2380         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2381         /* Askey */
2382         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2383         /* ASUS */
2384         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2385         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2386         /* Belkin */
2387         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2388         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2389         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2390         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2391         /* Billionton */
2392         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2393         /* Buffalo */
2394         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2395         /* CNet */
2396         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2397         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2398         /* Conceptronic */
2399         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2400         /* Corega */
2401         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2402         /* D-Link */
2403         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2404         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2405         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2406         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2407         /* Gemtek */
2408         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2409         /* Gigabyte */
2410         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2411         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2412         /* Huawei-3Com */
2413         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2414         /* Hercules */
2415         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2416         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2417         /* Linksys */
2418         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2419         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2420         /* MSI */
2421         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2422         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2423         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2424         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2425         /* Ralink */
2426         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2427         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2428         /* Qcom */
2429         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2430         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2431         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2432         /* Senao */
2433         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2434         /* Sitecom */
2435         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2436         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2437         /* Surecom */
2438         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2439         /* Planex */
2440         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2441         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2442         { 0, }
2443 };
2444
2445 MODULE_AUTHOR(DRV_PROJECT);
2446 MODULE_VERSION(DRV_VERSION);
2447 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2448 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2449 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2450 MODULE_FIRMWARE(FIRMWARE_RT2571);
2451 MODULE_LICENSE("GPL");
2452
2453 static struct usb_driver rt73usb_driver = {
2454         .name           = KBUILD_MODNAME,
2455         .id_table       = rt73usb_device_table,
2456         .probe          = rt2x00usb_probe,
2457         .disconnect     = rt2x00usb_disconnect,
2458         .suspend        = rt2x00usb_suspend,
2459         .resume         = rt2x00usb_resume,
2460 };
2461
2462 static int __init rt73usb_init(void)
2463 {
2464         return usb_register(&rt73usb_driver);
2465 }
2466
2467 static void __exit rt73usb_exit(void)
2468 {
2469         usb_deregister(&rt73usb_driver);
2470 }
2471
2472 module_init(rt73usb_init);
2473 module_exit(rt73usb_exit);