2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
48 #include "rt2800pci.h"
51 * Allow hardware encryption to be disabled.
53 static int modparam_nohwcrypt = 0;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
63 * SOC devices don't support MCU requests.
65 if (rt2x00_is_soc(rt2x00dev))
68 for (i = 0; i < 200; i++) {
69 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
77 udelay(REGISTER_BUSY_DELAY);
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
83 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
105 struct rt2x00_dev *rt2x00dev = eeprom->data;
108 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®);
110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112 eeprom->reg_data_clock =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114 eeprom->reg_chip_select =
115 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
120 struct rt2x00_dev *rt2x00dev = eeprom->data;
123 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
126 !!eeprom->reg_data_clock);
127 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
128 !!eeprom->reg_chip_select);
130 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
135 struct eeprom_93cx6 eeprom;
138 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®);
140 eeprom.data = rt2x00dev;
141 eeprom.register_read = rt2800pci_eepromregister_read;
142 eeprom.register_write = rt2800pci_eepromregister_write;
143 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
146 eeprom.width = PCI_EEPROM_WIDTH_93C46;
149 eeprom.width = PCI_EEPROM_WIDTH_93C66;
152 eeprom.width = PCI_EEPROM_WIDTH_93C86;
155 eeprom.reg_data_in = 0;
156 eeprom.reg_data_out = 0;
157 eeprom.reg_data_clock = 0;
158 eeprom.reg_chip_select = 0;
160 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161 EEPROM_SIZE / sizeof(u16));
164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
166 return rt2800_efuse_detect(rt2x00dev);
169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
171 rt2800_read_eeprom_efuse(rt2x00dev);
174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
186 #endif /* CONFIG_PCI */
191 static void rt2800pci_start_queue(struct data_queue *queue)
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
196 switch (queue->qid) {
198 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
199 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
200 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
204 * Allow beacon tasklets to be scheduled for periodic
207 tasklet_enable(&rt2x00dev->tbtt_tasklet);
208 tasklet_enable(&rt2x00dev->pretbtt_tasklet);
210 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
211 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
212 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
213 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
214 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
216 rt2800_register_read(rt2x00dev, INT_TIMER_EN, ®);
217 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
218 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
225 static void rt2800pci_kick_queue(struct data_queue *queue)
227 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
228 struct queue_entry *entry;
230 switch (queue->qid) {
235 entry = rt2x00queue_get_entry(queue, Q_INDEX);
236 rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
239 entry = rt2x00queue_get_entry(queue, Q_INDEX);
240 rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
247 static void rt2800pci_stop_queue(struct data_queue *queue)
249 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
252 switch (queue->qid) {
254 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
255 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
256 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
259 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
260 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
261 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
262 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
263 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
265 rt2800_register_read(rt2x00dev, INT_TIMER_EN, ®);
266 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
267 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
270 * Wait for tbtt tasklets to finish.
272 tasklet_disable(&rt2x00dev->tbtt_tasklet);
273 tasklet_disable(&rt2x00dev->pretbtt_tasklet);
283 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
285 return FIRMWARE_RT2860;
288 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
289 const u8 *data, const size_t len)
294 * enable Host program ram write selection
297 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
298 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
301 * Write firmware to device.
303 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
306 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
307 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
309 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
310 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
316 * Initialization functions.
318 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
320 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
323 if (entry->queue->qid == QID_RX) {
324 rt2x00_desc_read(entry_priv->desc, 1, &word);
326 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
328 rt2x00_desc_read(entry_priv->desc, 1, &word);
330 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
334 static void rt2800pci_clear_entry(struct queue_entry *entry)
336 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
337 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
338 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
341 if (entry->queue->qid == QID_RX) {
342 rt2x00_desc_read(entry_priv->desc, 0, &word);
343 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
344 rt2x00_desc_write(entry_priv->desc, 0, word);
346 rt2x00_desc_read(entry_priv->desc, 1, &word);
347 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
348 rt2x00_desc_write(entry_priv->desc, 1, word);
351 * Set RX IDX in register to inform hardware that we have
352 * handled this entry and it is available for reuse again.
354 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
357 rt2x00_desc_read(entry_priv->desc, 1, &word);
358 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
359 rt2x00_desc_write(entry_priv->desc, 1, word);
363 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
365 struct queue_entry_priv_pci *entry_priv;
369 * Initialize registers.
371 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
372 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
373 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
374 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
375 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
377 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
378 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
379 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
380 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
381 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
383 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
384 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
385 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
386 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
387 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
389 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
390 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
391 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
392 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
393 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
395 entry_priv = rt2x00dev->rx->entries[0].priv_data;
396 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
397 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
398 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
399 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
402 * Enable global DMA configuration
404 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
405 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
406 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
407 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
408 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
410 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
416 * Device state switch handlers.
418 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
419 enum dev_state state)
421 int mask = (state == STATE_RADIO_IRQ_ON);
426 * When interrupts are being enabled, the interrupt registers
427 * should clear the register to assure a clean state.
429 if (state == STATE_RADIO_IRQ_ON) {
430 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
431 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
434 * Enable tasklets. The beacon related tasklets are
435 * enabled when the beacon queue is started.
437 tasklet_enable(&rt2x00dev->txstatus_tasklet);
438 tasklet_enable(&rt2x00dev->rxdone_tasklet);
439 tasklet_enable(&rt2x00dev->autowake_tasklet);
442 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
443 rt2800_register_read(rt2x00dev, INT_MASK_CSR, ®);
444 rt2x00_set_field32(®, INT_MASK_CSR_RXDELAYINT, 0);
445 rt2x00_set_field32(®, INT_MASK_CSR_TXDELAYINT, 0);
446 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, mask);
447 rt2x00_set_field32(®, INT_MASK_CSR_AC0_DMA_DONE, 0);
448 rt2x00_set_field32(®, INT_MASK_CSR_AC1_DMA_DONE, 0);
449 rt2x00_set_field32(®, INT_MASK_CSR_AC2_DMA_DONE, 0);
450 rt2x00_set_field32(®, INT_MASK_CSR_AC3_DMA_DONE, 0);
451 rt2x00_set_field32(®, INT_MASK_CSR_HCCA_DMA_DONE, 0);
452 rt2x00_set_field32(®, INT_MASK_CSR_MGMT_DMA_DONE, 0);
453 rt2x00_set_field32(®, INT_MASK_CSR_MCU_COMMAND, 0);
454 rt2x00_set_field32(®, INT_MASK_CSR_RXTX_COHERENT, 0);
455 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, mask);
456 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, mask);
457 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, mask);
458 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, mask);
459 rt2x00_set_field32(®, INT_MASK_CSR_GPTIMER, 0);
460 rt2x00_set_field32(®, INT_MASK_CSR_RX_COHERENT, 0);
461 rt2x00_set_field32(®, INT_MASK_CSR_TX_COHERENT, 0);
462 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
463 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
465 if (state == STATE_RADIO_IRQ_OFF) {
467 * Ensure that all tasklets are finished before
468 * disabling the interrupts.
470 tasklet_disable(&rt2x00dev->txstatus_tasklet);
471 tasklet_disable(&rt2x00dev->rxdone_tasklet);
472 tasklet_disable(&rt2x00dev->autowake_tasklet);
476 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
483 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
484 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
485 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
486 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
487 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
488 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
489 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
490 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
491 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
493 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
494 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
496 if (rt2x00_rt(rt2x00dev, RT5390)) {
497 rt2800_register_read(rt2x00dev, AUX_CTRL, ®);
498 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
499 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
500 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
503 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
505 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
506 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
507 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
508 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
510 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
515 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
517 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
518 rt2800pci_init_queues(rt2x00dev)))
521 return rt2800_enable_radio(rt2x00dev);
524 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
526 if (rt2x00_is_soc(rt2x00dev)) {
527 rt2800_disable_radio(rt2x00dev);
528 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
529 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
533 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
534 enum dev_state state)
536 if (state == STATE_AWAKE) {
537 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
538 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
539 } else if (state == STATE_SLEEP) {
540 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 0xffffffff);
541 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, 0xffffffff);
542 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
548 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
549 enum dev_state state)
556 * Before the radio can be enabled, the device first has
557 * to be woken up. After that it needs a bit of time
558 * to be fully awake and then the radio can be enabled.
560 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
562 retval = rt2800pci_enable_radio(rt2x00dev);
564 case STATE_RADIO_OFF:
566 * After the radio has been disabled, the device should
567 * be put to sleep for powersaving.
569 rt2800pci_disable_radio(rt2x00dev);
570 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
572 case STATE_RADIO_IRQ_ON:
573 case STATE_RADIO_IRQ_OFF:
574 rt2800pci_toggle_irq(rt2x00dev, state);
576 case STATE_DEEP_SLEEP:
580 retval = rt2800pci_set_state(rt2x00dev, state);
587 if (unlikely(retval))
588 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
595 * TX descriptor initialization
597 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
599 return (__le32 *) entry->skb->data;
602 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
603 struct txentry_desc *txdesc)
605 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
606 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
607 __le32 *txd = entry_priv->desc;
611 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
612 * must contains a TXWI structure + 802.11 header + padding + 802.11
613 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
614 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
615 * data. It means that LAST_SEC0 is always 0.
619 * Initialize TX descriptor
621 rt2x00_desc_read(txd, 0, &word);
622 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
623 rt2x00_desc_write(txd, 0, word);
625 rt2x00_desc_read(txd, 1, &word);
626 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
627 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
628 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
629 rt2x00_set_field32(&word, TXD_W1_BURST,
630 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
631 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
632 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
633 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
634 rt2x00_desc_write(txd, 1, word);
636 rt2x00_desc_read(txd, 2, &word);
637 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
638 skbdesc->skb_dma + TXWI_DESC_SIZE);
639 rt2x00_desc_write(txd, 2, word);
641 rt2x00_desc_read(txd, 3, &word);
642 rt2x00_set_field32(&word, TXD_W3_WIV,
643 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
644 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
645 rt2x00_desc_write(txd, 3, word);
648 * Register descriptor details in skb frame descriptor.
651 skbdesc->desc_len = TXD_DESC_SIZE;
655 * RX control handlers
657 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
658 struct rxdone_entry_desc *rxdesc)
660 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
661 __le32 *rxd = entry_priv->desc;
664 rt2x00_desc_read(rxd, 3, &word);
666 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
667 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
670 * Unfortunately we don't know the cipher type used during
671 * decryption. This prevents us from correct providing
672 * correct statistics through debugfs.
674 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
676 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
678 * Hardware has stripped IV/EIV data from 802.11 frame during
679 * decryption. Unfortunately the descriptor doesn't contain
680 * any fields with the EIV/IV data either, so they can't
681 * be restored by rt2x00lib.
683 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
686 * The hardware has already checked the Michael Mic and has
687 * stripped it from the frame. Signal this to mac80211.
689 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
691 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
692 rxdesc->flags |= RX_FLAG_DECRYPTED;
693 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
694 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
697 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
698 rxdesc->dev_flags |= RXDONE_MY_BSS;
700 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
701 rxdesc->dev_flags |= RXDONE_L2PAD;
704 * Process the RXWI structure that is at the start of the buffer.
706 rt2800_process_rxwi(entry, rxdesc);
710 * Interrupt functions.
712 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
714 struct ieee80211_conf conf = { .flags = 0 };
715 struct rt2x00lib_conf libconf = { .conf = &conf };
717 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
720 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
722 struct data_queue *queue;
723 struct queue_entry *entry;
727 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
728 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
729 if (unlikely(qid >= QID_RX)) {
731 * Unknown queue, this shouldn't happen. Just drop
734 WARNING(rt2x00dev, "Got TX status report with "
735 "unexpected pid %u, dropping\n", qid);
739 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
740 if (unlikely(queue == NULL)) {
742 * The queue is NULL, this shouldn't happen. Stop
743 * processing here and drop the tx status
745 WARNING(rt2x00dev, "Got TX status for an unavailable "
746 "queue %u, dropping\n", qid);
750 if (unlikely(rt2x00queue_empty(queue))) {
752 * The queue is empty. Stop processing here
753 * and drop the tx status.
755 WARNING(rt2x00dev, "Got TX status for an empty "
756 "queue %u, dropping\n", qid);
760 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
761 rt2800_txdone_entry(entry, status);
765 static void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
766 struct rt2x00_field32 irq_field)
772 * Enable a single interrupt. The interrupt mask register
773 * access needs locking.
775 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
776 rt2800_register_read(rt2x00dev, INT_MASK_CSR, ®);
777 rt2x00_set_field32(®, irq_field, 1);
778 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
779 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
782 static void rt2800pci_txstatus_tasklet(unsigned long data)
784 rt2800pci_txdone((struct rt2x00_dev *)data);
787 * No need to enable the tx status interrupt here as we always
788 * leave it enabled to minimize the possibility of a tx status
789 * register overflow. See comment in interrupt handler.
793 static void rt2800pci_pretbtt_tasklet(unsigned long data)
795 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
796 rt2x00lib_pretbtt(rt2x00dev);
797 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
800 static void rt2800pci_tbtt_tasklet(unsigned long data)
802 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
803 rt2x00lib_beacondone(rt2x00dev);
804 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
807 static void rt2800pci_rxdone_tasklet(unsigned long data)
809 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
810 rt2x00pci_rxdone(rt2x00dev);
811 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
814 static void rt2800pci_autowake_tasklet(unsigned long data)
816 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
817 rt2800pci_wakeup(rt2x00dev);
818 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
821 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
827 * The TX_FIFO_STATUS interrupt needs special care. We should
828 * read TX_STA_FIFO but we should do it immediately as otherwise
829 * the register can overflow and we would lose status reports.
831 * Hence, read the TX_STA_FIFO register and copy all tx status
832 * reports into a kernel FIFO which is handled in the txstatus
833 * tasklet. We use a tasklet to process the tx status reports
834 * because we can schedule the tasklet multiple times (when the
835 * interrupt fires again during tx status processing).
837 * Furthermore we don't disable the TX_FIFO_STATUS
838 * interrupt here but leave it enabled so that the TX_STA_FIFO
839 * can also be read while the interrupt thread gets executed.
841 * Since we have only one producer and one consumer we don't
842 * need to lock the kfifo.
844 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
845 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
847 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
850 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
851 WARNING(rt2x00dev, "TX status FIFO overrun,"
852 "drop tx status report.\n");
857 /* Schedule the tasklet for processing the tx status. */
858 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
861 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
863 struct rt2x00_dev *rt2x00dev = dev_instance;
867 /* Read status and ACK all interrupts */
868 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
869 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
874 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
878 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
879 * for interrupts and interrupt masks we can just use the value of
880 * INT_SOURCE_CSR to create the interrupt mask.
884 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
885 rt2800pci_txstatus_interrupt(rt2x00dev);
887 * Never disable the TX_FIFO_STATUS interrupt.
889 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
892 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
893 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
895 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
896 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
898 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
899 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
901 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
902 tasklet_schedule(&rt2x00dev->autowake_tasklet);
905 * Disable all interrupts for which a tasklet was scheduled right now,
906 * the tasklet will reenable the appropriate interrupts.
908 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
909 rt2800_register_read(rt2x00dev, INT_MASK_CSR, ®);
911 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
912 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
918 * Device probe functions.
920 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
923 * Read EEPROM into buffer
925 if (rt2x00_is_soc(rt2x00dev))
926 rt2800pci_read_eeprom_soc(rt2x00dev);
927 else if (rt2800pci_efuse_detect(rt2x00dev))
928 rt2800pci_read_eeprom_efuse(rt2x00dev);
930 rt2800pci_read_eeprom_pci(rt2x00dev);
932 return rt2800_validate_eeprom(rt2x00dev);
935 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
940 * Allocate eeprom data.
942 retval = rt2800pci_validate_eeprom(rt2x00dev);
946 retval = rt2800_init_eeprom(rt2x00dev);
951 * Initialize hw specifications.
953 retval = rt2800_probe_hw_mode(rt2x00dev);
958 * This device has multiple filters for control frames
959 * and has a separate filter for PS Poll frames.
961 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
962 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
965 * This device has a pre tbtt interrupt and thus fetches
966 * a new beacon directly prior to transmission.
968 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
971 * This device requires firmware.
973 if (!rt2x00_is_soc(rt2x00dev))
974 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
975 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
976 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
977 __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
978 __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
979 if (!modparam_nohwcrypt)
980 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
981 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
982 __set_bit(DRIVER_REQUIRE_HT_TX_DESC, &rt2x00dev->flags);
985 * Set the rssi offset.
987 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
992 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
994 .start = rt2x00mac_start,
995 .stop = rt2x00mac_stop,
996 .add_interface = rt2x00mac_add_interface,
997 .remove_interface = rt2x00mac_remove_interface,
998 .config = rt2x00mac_config,
999 .configure_filter = rt2x00mac_configure_filter,
1000 .set_key = rt2x00mac_set_key,
1001 .sw_scan_start = rt2x00mac_sw_scan_start,
1002 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1003 .get_stats = rt2x00mac_get_stats,
1004 .get_tkip_seq = rt2800_get_tkip_seq,
1005 .set_rts_threshold = rt2800_set_rts_threshold,
1006 .bss_info_changed = rt2x00mac_bss_info_changed,
1007 .conf_tx = rt2800_conf_tx,
1008 .get_tsf = rt2800_get_tsf,
1009 .rfkill_poll = rt2x00mac_rfkill_poll,
1010 .ampdu_action = rt2800_ampdu_action,
1011 .flush = rt2x00mac_flush,
1012 .get_survey = rt2800_get_survey,
1015 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1016 .register_read = rt2x00pci_register_read,
1017 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1018 .register_write = rt2x00pci_register_write,
1019 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1020 .register_multiread = rt2x00pci_register_multiread,
1021 .register_multiwrite = rt2x00pci_register_multiwrite,
1022 .regbusy_read = rt2x00pci_regbusy_read,
1023 .drv_write_firmware = rt2800pci_write_firmware,
1024 .drv_init_registers = rt2800pci_init_registers,
1025 .drv_get_txwi = rt2800pci_get_txwi,
1028 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1029 .irq_handler = rt2800pci_interrupt,
1030 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1031 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1032 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1033 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1034 .autowake_tasklet = rt2800pci_autowake_tasklet,
1035 .probe_hw = rt2800pci_probe_hw,
1036 .get_firmware_name = rt2800pci_get_firmware_name,
1037 .check_firmware = rt2800_check_firmware,
1038 .load_firmware = rt2800_load_firmware,
1039 .initialize = rt2x00pci_initialize,
1040 .uninitialize = rt2x00pci_uninitialize,
1041 .get_entry_state = rt2800pci_get_entry_state,
1042 .clear_entry = rt2800pci_clear_entry,
1043 .set_device_state = rt2800pci_set_device_state,
1044 .rfkill_poll = rt2800_rfkill_poll,
1045 .link_stats = rt2800_link_stats,
1046 .reset_tuner = rt2800_reset_tuner,
1047 .link_tuner = rt2800_link_tuner,
1048 .start_queue = rt2800pci_start_queue,
1049 .kick_queue = rt2800pci_kick_queue,
1050 .stop_queue = rt2800pci_stop_queue,
1051 .write_tx_desc = rt2800pci_write_tx_desc,
1052 .write_tx_data = rt2800_write_tx_data,
1053 .write_beacon = rt2800_write_beacon,
1054 .clear_beacon = rt2800_clear_beacon,
1055 .fill_rxdone = rt2800pci_fill_rxdone,
1056 .config_shared_key = rt2800_config_shared_key,
1057 .config_pairwise_key = rt2800_config_pairwise_key,
1058 .config_filter = rt2800_config_filter,
1059 .config_intf = rt2800_config_intf,
1060 .config_erp = rt2800_config_erp,
1061 .config_ant = rt2800_config_ant,
1062 .config = rt2800_config,
1065 static const struct data_queue_desc rt2800pci_queue_rx = {
1067 .data_size = AGGREGATION_SIZE,
1068 .desc_size = RXD_DESC_SIZE,
1069 .priv_size = sizeof(struct queue_entry_priv_pci),
1072 static const struct data_queue_desc rt2800pci_queue_tx = {
1074 .data_size = AGGREGATION_SIZE,
1075 .desc_size = TXD_DESC_SIZE,
1076 .priv_size = sizeof(struct queue_entry_priv_pci),
1079 static const struct data_queue_desc rt2800pci_queue_bcn = {
1081 .data_size = 0, /* No DMA required for beacons */
1082 .desc_size = TXWI_DESC_SIZE,
1083 .priv_size = sizeof(struct queue_entry_priv_pci),
1086 static const struct rt2x00_ops rt2800pci_ops = {
1087 .name = KBUILD_MODNAME,
1090 .eeprom_size = EEPROM_SIZE,
1092 .tx_queues = NUM_TX_QUEUES,
1093 .extra_tx_headroom = TXWI_DESC_SIZE,
1094 .rx = &rt2800pci_queue_rx,
1095 .tx = &rt2800pci_queue_tx,
1096 .bcn = &rt2800pci_queue_bcn,
1097 .lib = &rt2800pci_rt2x00_ops,
1098 .drv = &rt2800pci_rt2800_ops,
1099 .hw = &rt2800pci_mac80211_ops,
1100 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1101 .debugfs = &rt2800_rt2x00debug,
1102 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1106 * RT2800pci module information.
1109 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1110 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1111 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1112 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1113 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1114 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1115 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1116 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1117 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1118 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1119 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1120 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1121 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1122 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1123 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1124 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1125 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1126 #ifdef CONFIG_RT2800PCI_RT33XX
1127 { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1129 #ifdef CONFIG_RT2800PCI_RT35XX
1130 { PCI_DEVICE(0x1432, 0x7711), PCI_DEVICE_DATA(&rt2800pci_ops) },
1131 { PCI_DEVICE(0x1432, 0x7722), PCI_DEVICE_DATA(&rt2800pci_ops) },
1132 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1133 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1134 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1135 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1136 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1138 #ifdef CONFIG_RT2800PCI_RT53XX
1139 { PCI_DEVICE(0x1814, 0x5390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1143 #endif /* CONFIG_PCI */
1145 MODULE_AUTHOR(DRV_PROJECT);
1146 MODULE_VERSION(DRV_VERSION);
1147 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1148 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1150 MODULE_FIRMWARE(FIRMWARE_RT2860);
1151 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1152 #endif /* CONFIG_PCI */
1153 MODULE_LICENSE("GPL");
1155 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1156 static int rt2800soc_probe(struct platform_device *pdev)
1158 return rt2x00soc_probe(pdev, &rt2800pci_ops);
1161 static struct platform_driver rt2800soc_driver = {
1163 .name = "rt2800_wmac",
1164 .owner = THIS_MODULE,
1165 .mod_name = KBUILD_MODNAME,
1167 .probe = rt2800soc_probe,
1168 .remove = __devexit_p(rt2x00soc_remove),
1169 .suspend = rt2x00soc_suspend,
1170 .resume = rt2x00soc_resume,
1172 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1175 static struct pci_driver rt2800pci_driver = {
1176 .name = KBUILD_MODNAME,
1177 .id_table = rt2800pci_device_table,
1178 .probe = rt2x00pci_probe,
1179 .remove = __devexit_p(rt2x00pci_remove),
1180 .suspend = rt2x00pci_suspend,
1181 .resume = rt2x00pci_resume,
1183 #endif /* CONFIG_PCI */
1185 static int __init rt2800pci_init(void)
1189 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1190 ret = platform_driver_register(&rt2800soc_driver);
1195 ret = pci_register_driver(&rt2800pci_driver);
1197 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1198 platform_driver_unregister(&rt2800soc_driver);
1207 static void __exit rt2800pci_exit(void)
1210 pci_unregister_driver(&rt2800pci_driver);
1212 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1213 platform_driver_unregister(&rt2800soc_driver);
1217 module_init(rt2800pci_init);
1218 module_exit(rt2800pci_exit);