drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/eeprom_93cx6.h>
  42
  43 #include "rt2x00.h"
  44 #include "rt2x00pci.h"
  45 #include "rt2x00soc.h"
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800pci.h"
  49
  50 /*
  51  * Allow hardware encryption to be disabled.
  52  */
  53 static int modparam_nohwcrypt = 0;
  54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  56
  57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  58 {
  59         unsigned int i;
  60         u32 reg;
  61
  62         /*
  63          * SOC devices don't support MCU requests.
  64          */
  65         if (rt2x00_is_soc(rt2x00dev))
  66                 return;
  67
  68         for (i = 0; i < 200; i++) {
  69                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  70
  71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  75                         break;
  76
  77                 udelay(REGISTER_BUSY_DELAY);
  78         }
  79
  80         if (i == 200)
  81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  82
  83         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  85 }
  86
  87 #ifdef CONFIG_RT2800PCI_SOC
  88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  89 {
  90         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
  91
  92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  93 }
  94 #else
  95 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  96 {
  97 }
  98 #endif /* CONFIG_RT2800PCI_SOC */
  99
 100 #ifdef CONFIG_RT2800PCI_PCI
 101 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 102 {
 103         struct rt2x00_dev *rt2x00dev = eeprom->data;
 104         u32 reg;
 105
 106         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 107
 108         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 109         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 110         eeprom->reg_data_clock =
 111             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 112         eeprom->reg_chip_select =
 113             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 114 }
 115
 116 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 117 {
 118         struct rt2x00_dev *rt2x00dev = eeprom->data;
 119         u32 reg = 0;
 120
 121         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 122         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 124                            !!eeprom->reg_data_clock);
 125         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 126                            !!eeprom->reg_chip_select);
 127
 128         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 129 }
 130
 131 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 132 {
 133         struct eeprom_93cx6 eeprom;
 134         u32 reg;
 135
 136         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 137
 138         eeprom.data = rt2x00dev;
 139         eeprom.register_read = rt2800pci_eepromregister_read;
 140         eeprom.register_write = rt2800pci_eepromregister_write;
 141         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
 142         {
 143         case 0:
 144                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 145                 break;
 146         case 1:
 147                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 148                 break;
 149         default:
 150                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
 151                 break;
 152         }
 153         eeprom.reg_data_in = 0;
 154         eeprom.reg_data_out = 0;
 155         eeprom.reg_data_clock = 0;
 156         eeprom.reg_chip_select = 0;
 157
 158         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 159                                EEPROM_SIZE / sizeof(u16));
 160 }
 161
 162 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 163 {
 164         return rt2800_efuse_detect(rt2x00dev);
 165 }
 166
 167 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 168 {
 169         rt2800_read_eeprom_efuse(rt2x00dev);
 170 }
 171 #else
 172 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 173 {
 174 }
 175
 176 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 177 {
 178         return 0;
 179 }
 180
 181 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 182 {
 183 }
 184 #endif /* CONFIG_RT2800PCI_PCI */
 185
 186 /*
 187  * Firmware functions
 188  */
 189 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 190 {
 191         return FIRMWARE_RT2860;
 192 }
 193
 194 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
 195                                     const u8 *data, const size_t len)
 196 {
 197         u32 reg;
 198
 199         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 200
 201         /*
 202          * enable Host program ram write selection
 203          */
 204         reg = 0;
 205         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 206         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 207
 208         /*
 209          * Write firmware to device.
 210          */
 211         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 212                                    data, len);
 213
 214         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 215         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 216
 217         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 218         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 219
 220         return 0;
 221 }
 222
 223 /*
 224  * Initialization functions.
 225  */
 226 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 227 {
 228         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 229         u32 word;
 230
 231         if (entry->queue->qid == QID_RX) {
 232                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 233
 234                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 235         } else {
 236                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 237
 238                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 239         }
 240 }
 241
 242 static void rt2800pci_clear_entry(struct queue_entry *entry)
 243 {
 244         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 245         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 246         u32 word;
 247
 248         if (entry->queue->qid == QID_RX) {
 249                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 250                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 251                 rt2x00_desc_write(entry_priv->desc, 0, word);
 252
 253                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 254                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 255                 rt2x00_desc_write(entry_priv->desc, 1, word);
 256         } else {
 257                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 258                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 259                 rt2x00_desc_write(entry_priv->desc, 1, word);
 260         }
 261 }
 262
 263 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 264 {
 265         struct queue_entry_priv_pci *entry_priv;
 266         u32 reg;
 267
 268         /*
 269          * Initialize registers.
 270          */
 271         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 272         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 273         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 274         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 275         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 276
 277         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 278         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 279         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 280         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 281         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 282
 283         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 284         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 285         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 286         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 287         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 288
 289         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 290         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 291         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 292         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 293         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 294
 295         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 296         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 297         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 298         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 299         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 300
 301         /*
 302          * Enable global DMA configuration
 303          */
 304         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 305         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 306         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 307         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 308         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 309
 310         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * Device state switch handlers.
 317  */
 318 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 319                                 enum dev_state state)
 320 {
 321         u32 reg;
 322
 323         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 324         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
 325                            (state == STATE_RADIO_RX_ON) ||
 326                            (state == STATE_RADIO_RX_ON_LINK));
 327         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 328 }
 329
 330 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 331                                  enum dev_state state)
 332 {
 333         int mask = (state == STATE_RADIO_IRQ_ON) ||
 334                    (state == STATE_RADIO_IRQ_ON_ISR);
 335         u32 reg;
 336
 337         /*
 338          * When interrupts are being enabled, the interrupt registers
 339          * should clear the register to assure a clean state.
 340          */
 341         if (state == STATE_RADIO_IRQ_ON) {
 342                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 343                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 344         }
 345
 346         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 347         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
 348         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
 349         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 350         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
 351         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
 352         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
 353         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
 354         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
 355         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
 356         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
 357         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
 358         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 359         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 360         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 361         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 362         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
 363         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
 364         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
 365         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 366 }
 367
 368 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
 369 {
 370         u32 reg;
 371
 372         /*
 373          * Reset DMA indexes
 374          */
 375         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 376         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 377         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 378         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 379         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 380         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 381         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 382         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 383         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 384
 385         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 386         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 387
 388         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 389
 390         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 391         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 392         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 393         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 394
 395         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 396
 397         return 0;
 398 }
 399
 400 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 401 {
 402         u32 reg;
 403         u16 word;
 404
 405         /*
 406          * Initialize all registers.
 407          */
 408         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 409                      rt2800pci_init_queues(rt2x00dev) ||
 410                      rt2800_init_registers(rt2x00dev) ||
 411                      rt2800_wait_wpdma_ready(rt2x00dev) ||
 412                      rt2800_init_bbp(rt2x00dev) ||
 413                      rt2800_init_rfcsr(rt2x00dev)))
 414                 return -EIO;
 415
 416         /*
 417          * Send signal to firmware during boot time.
 418          */
 419         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 420
 421         /*
 422          * Enable RX.
 423          */
 424         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 425         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 426         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 427         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 428
 429         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 430         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
 431         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
 432         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
 433         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 434         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 435
 436         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 437         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 438         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 439         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 440
 441         /*
 442          * Initialize LED control
 443          */
 444         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
 445         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
 446                               word & 0xff, (word >> 8) & 0xff);
 447
 448         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
 449         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
 450                               word & 0xff, (word >> 8) & 0xff);
 451
 452         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
 453         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
 454                               word & 0xff, (word >> 8) & 0xff);
 455
 456         return 0;
 457 }
 458
 459 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 460 {
 461         u32 reg;
 462
 463         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 464         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 465         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 466         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 467         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 468         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 469         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 470
 471         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 472         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 473         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
 474
 475         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 476
 477         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 478         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 479         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 480         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 481         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 482         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 483         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 484         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 485         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 486
 487         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 488         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 489
 490         /* Wait for DMA, ignore error */
 491         rt2800_wait_wpdma_ready(rt2x00dev);
 492 }
 493
 494 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 495                                enum dev_state state)
 496 {
 497         /*
 498          * Always put the device to sleep (even when we intend to wakeup!)
 499          * if the device is booting and wasn't asleep it will return
 500          * failure when attempting to wakeup.
 501          */
 502         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
 503
 504         if (state == STATE_AWAKE) {
 505                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 506                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 513                                       enum dev_state state)
 514 {
 515         int retval = 0;
 516
 517         switch (state) {
 518         case STATE_RADIO_ON:
 519                 /*
 520                  * Before the radio can be enabled, the device first has
 521                  * to be woken up. After that it needs a bit of time
 522                  * to be fully awake and then the radio can be enabled.
 523                  */
 524                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 525                 msleep(1);
 526                 retval = rt2800pci_enable_radio(rt2x00dev);
 527                 break;
 528         case STATE_RADIO_OFF:
 529                 /*
 530                  * After the radio has been disabled, the device should
 531                  * be put to sleep for powersaving.
 532                  */
 533                 rt2800pci_disable_radio(rt2x00dev);
 534                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 535                 break;
 536         case STATE_RADIO_RX_ON:
 537         case STATE_RADIO_RX_ON_LINK:
 538         case STATE_RADIO_RX_OFF:
 539         case STATE_RADIO_RX_OFF_LINK:
 540                 rt2800pci_toggle_rx(rt2x00dev, state);
 541                 break;
 542         case STATE_RADIO_IRQ_ON:
 543         case STATE_RADIO_IRQ_ON_ISR:
 544         case STATE_RADIO_IRQ_OFF:
 545         case STATE_RADIO_IRQ_OFF_ISR:
 546                 rt2800pci_toggle_irq(rt2x00dev, state);
 547                 break;
 548         case STATE_DEEP_SLEEP:
 549         case STATE_SLEEP:
 550         case STATE_STANDBY:
 551         case STATE_AWAKE:
 552                 retval = rt2800pci_set_state(rt2x00dev, state);
 553                 break;
 554         default:
 555                 retval = -ENOTSUPP;
 556                 break;
 557         }
 558
 559         if (unlikely(retval))
 560                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 561                       state, retval);
 562
 563         return retval;
 564 }
 565
 566 /*
 567  * TX descriptor initialization
 568  */
 569 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
 570 {
 571         return (__le32 *) entry->skb->data;
 572 }
 573
 574 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 575                                     struct sk_buff *skb,
 576                                     struct txentry_desc *txdesc)
 577 {
 578         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 579         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
 580         __le32 *txd = entry_priv->desc;
 581         u32 word;
 582
 583         /*
 584          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 585          * must contains a TXWI structure + 802.11 header + padding + 802.11
 586          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 587          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 588          * data. It means that LAST_SEC0 is always 0.
 589          */
 590
 591         /*
 592          * Initialize TX descriptor
 593          */
 594         rt2x00_desc_read(txd, 0, &word);
 595         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 596         rt2x00_desc_write(txd, 0, word);
 597
 598         rt2x00_desc_read(txd, 1, &word);
 599         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
 600         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 601                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 602         rt2x00_set_field32(&word, TXD_W1_BURST,
 603                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 604         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
 605         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 606         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 607         rt2x00_desc_write(txd, 1, word);
 608
 609         rt2x00_desc_read(txd, 2, &word);
 610         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 611                            skbdesc->skb_dma + TXWI_DESC_SIZE);
 612         rt2x00_desc_write(txd, 2, word);
 613
 614         rt2x00_desc_read(txd, 3, &word);
 615         rt2x00_set_field32(&word, TXD_W3_WIV,
 616                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 617         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 618         rt2x00_desc_write(txd, 3, word);
 619
 620         /*
 621          * Register descriptor details in skb frame descriptor.
 622          */
 623         skbdesc->desc = txd;
 624         skbdesc->desc_len = TXD_DESC_SIZE;
 625 }
 626
 627 /*
 628  * TX data initialization
 629  */
 630 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
 631                                     const enum data_queue_qid queue_idx)
 632 {
 633         struct data_queue *queue;
 634         unsigned int idx, qidx = 0;
 635
 636         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
 637                 return;
 638
 639         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
 640         idx = queue->index[Q_INDEX];
 641
 642         if (queue_idx == QID_MGMT)
 643                 qidx = 5;
 644         else
 645                 qidx = queue_idx;
 646
 647         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
 648 }
 649
 650 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
 651                                     const enum data_queue_qid qid)
 652 {
 653         u32 reg;
 654
 655         if (qid == QID_BEACON) {
 656                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
 657                 return;
 658         }
 659
 660         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 661         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
 662         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
 663         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
 664         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
 665         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 666 }
 667
 668 /*
 669  * RX control handlers
 670  */
 671 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 672                                   struct rxdone_entry_desc *rxdesc)
 673 {
 674         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 675         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 676         __le32 *rxd = entry_priv->desc;
 677         u32 word;
 678
 679         rt2x00_desc_read(rxd, 3, &word);
 680
 681         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 682                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 683
 684         /*
 685          * Unfortunately we don't know the cipher type used during
 686          * decryption. This prevents us from correct providing
 687          * correct statistics through debugfs.
 688          */
 689         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 690
 691         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 692                 /*
 693                  * Hardware has stripped IV/EIV data from 802.11 frame during
 694                  * decryption. Unfortunately the descriptor doesn't contain
 695                  * any fields with the EIV/IV data either, so they can't
 696                  * be restored by rt2x00lib.
 697                  */
 698                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 699
 700                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 701                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 702                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 703                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 704         }
 705
 706         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 707                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 708
 709         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 710                 rxdesc->dev_flags |= RXDONE_L2PAD;
 711
 712         /*
 713          * Process the RXWI structure that is at the start of the buffer.
 714          */
 715         rt2800_process_rxwi(entry, rxdesc);
 716
 717         /*
 718          * Set RX IDX in register to inform hardware that we have handled
 719          * this entry and it is available for reuse again.
 720          */
 721         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
 722 }
 723
 724 /*
 725  * Interrupt functions.
 726  */
 727 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
 728 {
 729         struct ieee80211_conf conf = { .flags = 0 };
 730         struct rt2x00lib_conf libconf = { .conf = &conf };
 731
 732         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 733 }
 734
 735 static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
 736 {
 737         struct rt2x00_dev *rt2x00dev = dev_instance;
 738         u32 reg = rt2x00dev->irqvalue[0];
 739
 740         /*
 741          * 1 - Pre TBTT interrupt.
 742          */
 743         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
 744                 rt2x00lib_pretbtt(rt2x00dev);
 745
 746         /*
 747          * 2 - Beacondone interrupt.
 748          */
 749         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
 750                 rt2x00lib_beacondone(rt2x00dev);
 751
 752         /*
 753          * 3 - Rx ring done interrupt.
 754          */
 755         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 756                 rt2x00pci_rxdone(rt2x00dev);
 757
 758         /*
 759          * 4 - Tx done interrupt.
 760          */
 761         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
 762                 rt2800_txdone(rt2x00dev);
 763
 764         /*
 765          * 5 - Auto wakeup interrupt.
 766          */
 767         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 768                 rt2800pci_wakeup(rt2x00dev);
 769
 770         /* Enable interrupts again. */
 771         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
 772                                               STATE_RADIO_IRQ_ON_ISR);
 773
 774         return IRQ_HANDLED;
 775 }
 776
 777 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
 778 {
 779         struct rt2x00_dev *rt2x00dev = dev_instance;
 780         u32 reg;
 781
 782         /* Read status and ACK all interrupts */
 783         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 784         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 785
 786         if (!reg)
 787                 return IRQ_NONE;
 788
 789         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 790                 return IRQ_HANDLED;
 791
 792         /* Store irqvalue for use in the interrupt thread. */
 793         rt2x00dev->irqvalue[0] = reg;
 794
 795         /* Disable interrupts, will be enabled again in the interrupt thread. */
 796         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
 797                                               STATE_RADIO_IRQ_OFF_ISR);
 798
 799
 800         return IRQ_WAKE_THREAD;
 801 }
 802
 803 /*
 804  * Device probe functions.
 805  */
 806 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
 807 {
 808         /*
 809          * Read EEPROM into buffer
 810          */
 811         if (rt2x00_is_soc(rt2x00dev))
 812                 rt2800pci_read_eeprom_soc(rt2x00dev);
 813         else if (rt2800pci_efuse_detect(rt2x00dev))
 814                 rt2800pci_read_eeprom_efuse(rt2x00dev);
 815         else
 816                 rt2800pci_read_eeprom_pci(rt2x00dev);
 817
 818         return rt2800_validate_eeprom(rt2x00dev);
 819 }
 820
 821 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
 822 {
 823         int retval;
 824
 825         /*
 826          * Allocate eeprom data.
 827          */
 828         retval = rt2800pci_validate_eeprom(rt2x00dev);
 829         if (retval)
 830                 return retval;
 831
 832         retval = rt2800_init_eeprom(rt2x00dev);
 833         if (retval)
 834                 return retval;
 835
 836         /*
 837          * Initialize hw specifications.
 838          */
 839         retval = rt2800_probe_hw_mode(rt2x00dev);
 840         if (retval)
 841                 return retval;
 842
 843         /*
 844          * This device has multiple filters for control frames
 845          * and has a separate filter for PS Poll frames.
 846          */
 847         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
 848         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
 849
 850         /*
 851          * This device has a pre tbtt interrupt and thus fetches
 852          * a new beacon directly prior to transmission.
 853          */
 854         __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
 855
 856         /*
 857          * This device requires firmware.
 858          */
 859         if (!rt2x00_is_soc(rt2x00dev))
 860                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
 861         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
 862         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
 863         if (!modparam_nohwcrypt)
 864                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
 865         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
 866
 867         /*
 868          * Set the rssi offset.
 869          */
 870         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
 871
 872         return 0;
 873 }
 874
 875 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
 876         .tx                     = rt2x00mac_tx,
 877         .start                  = rt2x00mac_start,
 878         .stop                   = rt2x00mac_stop,
 879         .add_interface          = rt2x00mac_add_interface,
 880         .remove_interface       = rt2x00mac_remove_interface,
 881         .config                 = rt2x00mac_config,
 882         .configure_filter       = rt2x00mac_configure_filter,
 883         .set_key                = rt2x00mac_set_key,
 884         .sw_scan_start          = rt2x00mac_sw_scan_start,
 885         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
 886         .get_stats              = rt2x00mac_get_stats,
 887         .get_tkip_seq           = rt2800_get_tkip_seq,
 888         .set_rts_threshold      = rt2800_set_rts_threshold,
 889         .bss_info_changed       = rt2x00mac_bss_info_changed,
 890         .conf_tx                = rt2800_conf_tx,
 891         .get_tsf                = rt2800_get_tsf,
 892         .rfkill_poll            = rt2x00mac_rfkill_poll,
 893         .ampdu_action           = rt2800_ampdu_action,
 894 };
 895
 896 static const struct rt2800_ops rt2800pci_rt2800_ops = {
 897         .register_read          = rt2x00pci_register_read,
 898         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
 899         .register_write         = rt2x00pci_register_write,
 900         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
 901         .register_multiread     = rt2x00pci_register_multiread,
 902         .register_multiwrite    = rt2x00pci_register_multiwrite,
 903         .regbusy_read           = rt2x00pci_regbusy_read,
 904         .drv_write_firmware     = rt2800pci_write_firmware,
 905         .drv_init_registers     = rt2800pci_init_registers,
 906         .drv_get_txwi           = rt2800pci_get_txwi,
 907 };
 908
 909 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
 910         .irq_handler            = rt2800pci_interrupt,
 911         .irq_handler_thread     = rt2800pci_interrupt_thread,
 912         .probe_hw               = rt2800pci_probe_hw,
 913         .get_firmware_name      = rt2800pci_get_firmware_name,
 914         .check_firmware         = rt2800_check_firmware,
 915         .load_firmware          = rt2800_load_firmware,
 916         .initialize             = rt2x00pci_initialize,
 917         .uninitialize           = rt2x00pci_uninitialize,
 918         .get_entry_state        = rt2800pci_get_entry_state,
 919         .clear_entry            = rt2800pci_clear_entry,
 920         .set_device_state       = rt2800pci_set_device_state,
 921         .rfkill_poll            = rt2800_rfkill_poll,
 922         .link_stats             = rt2800_link_stats,
 923         .reset_tuner            = rt2800_reset_tuner,
 924         .link_tuner             = rt2800_link_tuner,
 925         .write_tx_desc          = rt2800pci_write_tx_desc,
 926         .write_tx_data          = rt2800_write_tx_data,
 927         .write_beacon           = rt2800_write_beacon,
 928         .kick_tx_queue          = rt2800pci_kick_tx_queue,
 929         .kill_tx_queue          = rt2800pci_kill_tx_queue,
 930         .fill_rxdone            = rt2800pci_fill_rxdone,
 931         .config_shared_key      = rt2800_config_shared_key,
 932         .config_pairwise_key    = rt2800_config_pairwise_key,
 933         .config_filter          = rt2800_config_filter,
 934         .config_intf            = rt2800_config_intf,
 935         .config_erp             = rt2800_config_erp,
 936         .config_ant             = rt2800_config_ant,
 937         .config                 = rt2800_config,
 938 };
 939
 940 static const struct data_queue_desc rt2800pci_queue_rx = {
 941         .entry_num              = RX_ENTRIES,
 942         .data_size              = AGGREGATION_SIZE,
 943         .desc_size              = RXD_DESC_SIZE,
 944         .priv_size              = sizeof(struct queue_entry_priv_pci),
 945 };
 946
 947 static const struct data_queue_desc rt2800pci_queue_tx = {
 948         .entry_num              = TX_ENTRIES,
 949         .data_size              = AGGREGATION_SIZE,
 950         .desc_size              = TXD_DESC_SIZE,
 951         .priv_size              = sizeof(struct queue_entry_priv_pci),
 952 };
 953
 954 static const struct data_queue_desc rt2800pci_queue_bcn = {
 955         .entry_num              = 8 * BEACON_ENTRIES,
 956         .data_size              = 0, /* No DMA required for beacons */
 957         .desc_size              = TXWI_DESC_SIZE,
 958         .priv_size              = sizeof(struct queue_entry_priv_pci),
 959 };
 960
 961 static const struct rt2x00_ops rt2800pci_ops = {
 962         .name                   = KBUILD_MODNAME,
 963         .max_sta_intf           = 1,
 964         .max_ap_intf            = 8,
 965         .eeprom_size            = EEPROM_SIZE,
 966         .rf_size                = RF_SIZE,
 967         .tx_queues              = NUM_TX_QUEUES,
 968         .extra_tx_headroom      = TXWI_DESC_SIZE,
 969         .rx                     = &rt2800pci_queue_rx,
 970         .tx                     = &rt2800pci_queue_tx,
 971         .bcn                    = &rt2800pci_queue_bcn,
 972         .lib                    = &rt2800pci_rt2x00_ops,
 973         .drv                    = &rt2800pci_rt2800_ops,
 974         .hw                     = &rt2800pci_mac80211_ops,
 975 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 976         .debugfs                = &rt2800_rt2x00debug,
 977 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 978 };
 979
 980 /*
 981  * RT2800pci module information.
 982  */
 983 #ifdef CONFIG_RT2800PCI_PCI
 984 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
 985         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
 986         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
 987         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
 988         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
 989         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
 990         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
 991         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
 992         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
 993         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
 994         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
 995         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
 996         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
 997 #ifdef CONFIG_RT2800PCI_RT30XX
 998         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
 999         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1000         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1001         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1002 #endif
1003 #ifdef CONFIG_RT2800PCI_RT35XX
1004         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1005         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1006         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1007         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1008         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1009 #endif
1010         { 0, }
1011 };
1012 #endif /* CONFIG_RT2800PCI_PCI */
1013
1014 MODULE_AUTHOR(DRV_PROJECT);
1015 MODULE_VERSION(DRV_VERSION);
1016 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1017 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1018 #ifdef CONFIG_RT2800PCI_PCI
1019 MODULE_FIRMWARE(FIRMWARE_RT2860);
1020 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1021 #endif /* CONFIG_RT2800PCI_PCI */
1022 MODULE_LICENSE("GPL");
1023
1024 #ifdef CONFIG_RT2800PCI_SOC
1025 static int rt2800soc_probe(struct platform_device *pdev)
1026 {
1027         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1028 }
1029
1030 static struct platform_driver rt2800soc_driver = {
1031         .driver         = {
1032                 .name           = "rt2800_wmac",
1033                 .owner          = THIS_MODULE,
1034                 .mod_name       = KBUILD_MODNAME,
1035         },
1036         .probe          = rt2800soc_probe,
1037         .remove         = __devexit_p(rt2x00soc_remove),
1038         .suspend        = rt2x00soc_suspend,
1039         .resume         = rt2x00soc_resume,
1040 };
1041 #endif /* CONFIG_RT2800PCI_SOC */
1042
1043 #ifdef CONFIG_RT2800PCI_PCI
1044 static struct pci_driver rt2800pci_driver = {
1045         .name           = KBUILD_MODNAME,
1046         .id_table       = rt2800pci_device_table,
1047         .probe          = rt2x00pci_probe,
1048         .remove         = __devexit_p(rt2x00pci_remove),
1049         .suspend        = rt2x00pci_suspend,
1050         .resume         = rt2x00pci_resume,
1051 };
1052 #endif /* CONFIG_RT2800PCI_PCI */
1053
1054 static int __init rt2800pci_init(void)
1055 {
1056         int ret = 0;
1057
1058 #ifdef CONFIG_RT2800PCI_SOC
1059         ret = platform_driver_register(&rt2800soc_driver);
1060         if (ret)
1061                 return ret;
1062 #endif
1063 #ifdef CONFIG_RT2800PCI_PCI
1064         ret = pci_register_driver(&rt2800pci_driver);
1065         if (ret) {
1066 #ifdef CONFIG_RT2800PCI_SOC
1067                 platform_driver_unregister(&rt2800soc_driver);
1068 #endif
1069                 return ret;
1070         }
1071 #endif
1072
1073         return ret;
1074 }
1075
1076 static void __exit rt2800pci_exit(void)
1077 {
1078 #ifdef CONFIG_RT2800PCI_PCI
1079         pci_unregister_driver(&rt2800pci_driver);
1080 #endif
1081 #ifdef CONFIG_RT2800PCI_SOC
1082         platform_driver_unregister(&rt2800soc_driver);
1083 #endif
1084 }
1085
1086 module_init(rt2800pci_init);
1087 module_exit(rt2800pci_exit);