2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
48 #include "rt2800pci.h"
51 * Allow hardware encryption to be disabled.
53 static int modparam_nohwcrypt = 0;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
63 * SOC devices don't support MCU requests.
65 if (rt2x00_is_soc(rt2x00dev))
68 for (i = 0; i < 200; i++) {
69 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
77 udelay(REGISTER_BUSY_DELAY);
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
83 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
105 struct rt2x00_dev *rt2x00dev = eeprom->data;
108 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®);
110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112 eeprom->reg_data_clock =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114 eeprom->reg_chip_select =
115 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
120 struct rt2x00_dev *rt2x00dev = eeprom->data;
123 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
126 !!eeprom->reg_data_clock);
127 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
128 !!eeprom->reg_chip_select);
130 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
135 struct eeprom_93cx6 eeprom;
138 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®);
140 eeprom.data = rt2x00dev;
141 eeprom.register_read = rt2800pci_eepromregister_read;
142 eeprom.register_write = rt2800pci_eepromregister_write;
143 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
146 eeprom.width = PCI_EEPROM_WIDTH_93C46;
149 eeprom.width = PCI_EEPROM_WIDTH_93C66;
152 eeprom.width = PCI_EEPROM_WIDTH_93C86;
155 eeprom.reg_data_in = 0;
156 eeprom.reg_data_out = 0;
157 eeprom.reg_data_clock = 0;
158 eeprom.reg_chip_select = 0;
160 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161 EEPROM_SIZE / sizeof(u16));
164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
166 return rt2800_efuse_detect(rt2x00dev);
169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
171 rt2800_read_eeprom_efuse(rt2x00dev);
174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
186 #endif /* CONFIG_PCI */
191 static void rt2800pci_start_queue(struct data_queue *queue)
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
196 switch (queue->qid) {
198 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
199 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
200 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
203 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
204 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
205 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
206 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
207 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
214 static void rt2800pci_kick_queue(struct data_queue *queue)
216 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
217 struct queue_entry *entry;
219 switch (queue->qid) {
224 entry = rt2x00queue_get_entry(queue, Q_INDEX);
225 rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
228 entry = rt2x00queue_get_entry(queue, Q_INDEX);
229 rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
236 static void rt2800pci_stop_queue(struct data_queue *queue)
238 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
241 switch (queue->qid) {
243 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
244 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
245 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
248 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
249 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
250 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
251 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
252 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
262 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
264 return FIRMWARE_RT2860;
267 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
268 const u8 *data, const size_t len)
273 * enable Host program ram write selection
276 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
277 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
280 * Write firmware to device.
282 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
285 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
286 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
288 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
289 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
295 * Initialization functions.
297 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
299 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
302 if (entry->queue->qid == QID_RX) {
303 rt2x00_desc_read(entry_priv->desc, 1, &word);
305 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
307 rt2x00_desc_read(entry_priv->desc, 1, &word);
309 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
313 static void rt2800pci_clear_entry(struct queue_entry *entry)
315 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
316 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
317 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
320 if (entry->queue->qid == QID_RX) {
321 rt2x00_desc_read(entry_priv->desc, 0, &word);
322 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
323 rt2x00_desc_write(entry_priv->desc, 0, word);
325 rt2x00_desc_read(entry_priv->desc, 1, &word);
326 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
327 rt2x00_desc_write(entry_priv->desc, 1, word);
330 * Set RX IDX in register to inform hardware that we have
331 * handled this entry and it is available for reuse again.
333 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
336 rt2x00_desc_read(entry_priv->desc, 1, &word);
337 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
338 rt2x00_desc_write(entry_priv->desc, 1, word);
342 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
344 struct queue_entry_priv_pci *entry_priv;
348 * Initialize registers.
350 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
351 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
352 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
353 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
354 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
356 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
357 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
358 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
359 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
360 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
362 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
363 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
364 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
365 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
366 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
368 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
369 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
370 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
371 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
372 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
374 entry_priv = rt2x00dev->rx->entries[0].priv_data;
375 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
376 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
377 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
378 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
381 * Enable global DMA configuration
383 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
384 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
385 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
386 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
387 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
389 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
395 * Device state switch handlers.
397 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
398 enum dev_state state)
400 int mask = (state == STATE_RADIO_IRQ_ON) ||
401 (state == STATE_RADIO_IRQ_ON_ISR);
405 * When interrupts are being enabled, the interrupt registers
406 * should clear the register to assure a clean state.
408 if (state == STATE_RADIO_IRQ_ON) {
409 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
410 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
413 rt2800_register_read(rt2x00dev, INT_MASK_CSR, ®);
414 rt2x00_set_field32(®, INT_MASK_CSR_RXDELAYINT, 0);
415 rt2x00_set_field32(®, INT_MASK_CSR_TXDELAYINT, 0);
416 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, mask);
417 rt2x00_set_field32(®, INT_MASK_CSR_AC0_DMA_DONE, 0);
418 rt2x00_set_field32(®, INT_MASK_CSR_AC1_DMA_DONE, 0);
419 rt2x00_set_field32(®, INT_MASK_CSR_AC2_DMA_DONE, 0);
420 rt2x00_set_field32(®, INT_MASK_CSR_AC3_DMA_DONE, 0);
421 rt2x00_set_field32(®, INT_MASK_CSR_HCCA_DMA_DONE, 0);
422 rt2x00_set_field32(®, INT_MASK_CSR_MGMT_DMA_DONE, 0);
423 rt2x00_set_field32(®, INT_MASK_CSR_MCU_COMMAND, 0);
424 rt2x00_set_field32(®, INT_MASK_CSR_RXTX_COHERENT, 0);
425 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, mask);
426 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, mask);
427 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, mask);
428 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, mask);
429 rt2x00_set_field32(®, INT_MASK_CSR_GPTIMER, 0);
430 rt2x00_set_field32(®, INT_MASK_CSR_RX_COHERENT, 0);
431 rt2x00_set_field32(®, INT_MASK_CSR_TX_COHERENT, 0);
432 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
435 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
442 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
443 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
444 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
445 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
446 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
447 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
448 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
449 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
450 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
452 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
453 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
455 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
457 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
458 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
459 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
460 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
462 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
467 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
469 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
470 rt2800pci_init_queues(rt2x00dev)))
473 return rt2800_enable_radio(rt2x00dev);
476 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
480 rt2800_disable_radio(rt2x00dev);
482 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
484 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
485 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
486 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
487 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
488 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
489 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
490 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
491 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
492 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
494 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
495 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
498 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
499 enum dev_state state)
502 * Always put the device to sleep (even when we intend to wakeup!)
503 * if the device is booting and wasn't asleep it will return
504 * failure when attempting to wakeup.
506 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0xff, 2);
508 if (state == STATE_AWAKE) {
509 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
510 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
516 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
517 enum dev_state state)
524 * Before the radio can be enabled, the device first has
525 * to be woken up. After that it needs a bit of time
526 * to be fully awake and then the radio can be enabled.
528 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
530 retval = rt2800pci_enable_radio(rt2x00dev);
532 case STATE_RADIO_OFF:
534 * After the radio has been disabled, the device should
535 * be put to sleep for powersaving.
537 rt2800pci_disable_radio(rt2x00dev);
538 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
540 case STATE_RADIO_IRQ_ON:
541 case STATE_RADIO_IRQ_ON_ISR:
542 case STATE_RADIO_IRQ_OFF:
543 case STATE_RADIO_IRQ_OFF_ISR:
544 rt2800pci_toggle_irq(rt2x00dev, state);
546 case STATE_DEEP_SLEEP:
550 retval = rt2800pci_set_state(rt2x00dev, state);
557 if (unlikely(retval))
558 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
565 * TX descriptor initialization
567 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
569 return (__le32 *) entry->skb->data;
572 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
573 struct txentry_desc *txdesc)
575 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
576 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
577 __le32 *txd = entry_priv->desc;
581 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
582 * must contains a TXWI structure + 802.11 header + padding + 802.11
583 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
584 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
585 * data. It means that LAST_SEC0 is always 0.
589 * Initialize TX descriptor
591 rt2x00_desc_read(txd, 0, &word);
592 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
593 rt2x00_desc_write(txd, 0, word);
595 rt2x00_desc_read(txd, 1, &word);
596 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
597 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
598 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
599 rt2x00_set_field32(&word, TXD_W1_BURST,
600 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
601 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
602 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
603 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
604 rt2x00_desc_write(txd, 1, word);
606 rt2x00_desc_read(txd, 2, &word);
607 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
608 skbdesc->skb_dma + TXWI_DESC_SIZE);
609 rt2x00_desc_write(txd, 2, word);
611 rt2x00_desc_read(txd, 3, &word);
612 rt2x00_set_field32(&word, TXD_W3_WIV,
613 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
614 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
615 rt2x00_desc_write(txd, 3, word);
618 * Register descriptor details in skb frame descriptor.
621 skbdesc->desc_len = TXD_DESC_SIZE;
625 * RX control handlers
627 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
628 struct rxdone_entry_desc *rxdesc)
630 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
631 __le32 *rxd = entry_priv->desc;
634 rt2x00_desc_read(rxd, 3, &word);
636 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
637 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
640 * Unfortunately we don't know the cipher type used during
641 * decryption. This prevents us from correct providing
642 * correct statistics through debugfs.
644 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
646 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
648 * Hardware has stripped IV/EIV data from 802.11 frame during
649 * decryption. Unfortunately the descriptor doesn't contain
650 * any fields with the EIV/IV data either, so they can't
651 * be restored by rt2x00lib.
653 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
655 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
656 rxdesc->flags |= RX_FLAG_DECRYPTED;
657 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
658 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
661 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
662 rxdesc->dev_flags |= RXDONE_MY_BSS;
664 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
665 rxdesc->dev_flags |= RXDONE_L2PAD;
668 * Process the RXWI structure that is at the start of the buffer.
670 rt2800_process_rxwi(entry, rxdesc);
674 * Interrupt functions.
676 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
678 struct ieee80211_conf conf = { .flags = 0 };
679 struct rt2x00lib_conf libconf = { .conf = &conf };
681 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
684 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
686 struct data_queue *queue;
687 struct queue_entry *entry;
691 while (!kfifo_is_empty(&rt2x00dev->txstatus_fifo)) {
692 /* Now remove the tx status from the FIFO */
693 if (kfifo_out(&rt2x00dev->txstatus_fifo, &status,
694 sizeof(status)) != sizeof(status)) {
699 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
702 * Unknown queue, this shouldn't happen. Just drop
705 WARNING(rt2x00dev, "Got TX status report with "
706 "unexpected pid %u, dropping\n", qid);
710 queue = rt2x00queue_get_queue(rt2x00dev, qid);
711 if (unlikely(queue == NULL)) {
713 * The queue is NULL, this shouldn't happen. Stop
714 * processing here and drop the tx status
716 WARNING(rt2x00dev, "Got TX status for an unavailable "
717 "queue %u, dropping\n", qid);
721 if (rt2x00queue_empty(queue)) {
723 * The queue is empty. Stop processing here
724 * and drop the tx status.
726 WARNING(rt2x00dev, "Got TX status for an empty "
727 "queue %u, dropping\n", qid);
731 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
732 rt2800_txdone_entry(entry, status);
736 static void rt2800pci_txstatus_tasklet(unsigned long data)
738 rt2800pci_txdone((struct rt2x00_dev *)data);
741 static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
743 struct rt2x00_dev *rt2x00dev = dev_instance;
744 u32 reg = rt2x00dev->irqvalue[0];
747 * 1 - Pre TBTT interrupt.
749 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
750 rt2x00lib_pretbtt(rt2x00dev);
753 * 2 - Beacondone interrupt.
755 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
756 rt2x00lib_beacondone(rt2x00dev);
759 * 3 - Rx ring done interrupt.
761 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
762 rt2x00pci_rxdone(rt2x00dev);
765 * 4 - Auto wakeup interrupt.
767 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
768 rt2800pci_wakeup(rt2x00dev);
770 /* Enable interrupts again. */
771 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
772 STATE_RADIO_IRQ_ON_ISR);
777 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
783 * The TX_FIFO_STATUS interrupt needs special care. We should
784 * read TX_STA_FIFO but we should do it immediately as otherwise
785 * the register can overflow and we would lose status reports.
787 * Hence, read the TX_STA_FIFO register and copy all tx status
788 * reports into a kernel FIFO which is handled in the txstatus
789 * tasklet. We use a tasklet to process the tx status reports
790 * because we can schedule the tasklet multiple times (when the
791 * interrupt fires again during tx status processing).
793 * Furthermore we don't disable the TX_FIFO_STATUS
794 * interrupt here but leave it enabled so that the TX_STA_FIFO
795 * can also be read while the interrupt thread gets executed.
797 * Since we have only one producer and one consumer we don't
798 * need to lock the kfifo.
800 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
801 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
803 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
806 if (kfifo_is_full(&rt2x00dev->txstatus_fifo)) {
807 WARNING(rt2x00dev, "TX status FIFO overrun,"
808 " drop tx status report.\n");
812 if (kfifo_in(&rt2x00dev->txstatus_fifo, &status,
813 sizeof(status)) != sizeof(status)) {
814 WARNING(rt2x00dev, "TX status FIFO overrun,"
815 "drop tx status report.\n");
820 /* Schedule the tasklet for processing the tx status. */
821 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
824 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
826 struct rt2x00_dev *rt2x00dev = dev_instance;
828 irqreturn_t ret = IRQ_HANDLED;
830 /* Read status and ACK all interrupts */
831 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
832 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
837 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
840 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
841 rt2800pci_txstatus_interrupt(rt2x00dev);
843 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) ||
844 rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) ||
845 rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
846 rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
848 * All other interrupts are handled in the interrupt thread.
849 * Store irqvalue for use in the interrupt thread.
851 rt2x00dev->irqvalue[0] = reg;
854 * Disable interrupts, will be enabled again in the
857 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
858 STATE_RADIO_IRQ_OFF_ISR);
861 * Leave the TX_FIFO_STATUS interrupt enabled to not lose any
864 rt2800_register_read(rt2x00dev, INT_MASK_CSR, ®);
865 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
866 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
868 ret = IRQ_WAKE_THREAD;
875 * Device probe functions.
877 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
880 * Read EEPROM into buffer
882 if (rt2x00_is_soc(rt2x00dev))
883 rt2800pci_read_eeprom_soc(rt2x00dev);
884 else if (rt2800pci_efuse_detect(rt2x00dev))
885 rt2800pci_read_eeprom_efuse(rt2x00dev);
887 rt2800pci_read_eeprom_pci(rt2x00dev);
889 return rt2800_validate_eeprom(rt2x00dev);
892 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
897 * Allocate eeprom data.
899 retval = rt2800pci_validate_eeprom(rt2x00dev);
903 retval = rt2800_init_eeprom(rt2x00dev);
908 * Initialize hw specifications.
910 retval = rt2800_probe_hw_mode(rt2x00dev);
915 * This device has multiple filters for control frames
916 * and has a separate filter for PS Poll frames.
918 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
919 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
922 * This device has a pre tbtt interrupt and thus fetches
923 * a new beacon directly prior to transmission.
925 __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
928 * This device requires firmware.
930 if (!rt2x00_is_soc(rt2x00dev))
931 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
932 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
933 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
934 __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
935 __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
936 if (!modparam_nohwcrypt)
937 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
938 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
941 * Set the rssi offset.
943 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
948 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
950 .start = rt2x00mac_start,
951 .stop = rt2x00mac_stop,
952 .add_interface = rt2x00mac_add_interface,
953 .remove_interface = rt2x00mac_remove_interface,
954 .config = rt2x00mac_config,
955 .configure_filter = rt2x00mac_configure_filter,
956 .set_key = rt2x00mac_set_key,
957 .sw_scan_start = rt2x00mac_sw_scan_start,
958 .sw_scan_complete = rt2x00mac_sw_scan_complete,
959 .get_stats = rt2x00mac_get_stats,
960 .get_tkip_seq = rt2800_get_tkip_seq,
961 .set_rts_threshold = rt2800_set_rts_threshold,
962 .bss_info_changed = rt2x00mac_bss_info_changed,
963 .conf_tx = rt2800_conf_tx,
964 .get_tsf = rt2800_get_tsf,
965 .rfkill_poll = rt2x00mac_rfkill_poll,
966 .ampdu_action = rt2800_ampdu_action,
967 .flush = rt2x00mac_flush,
968 .get_survey = rt2800_get_survey,
971 static const struct rt2800_ops rt2800pci_rt2800_ops = {
972 .register_read = rt2x00pci_register_read,
973 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
974 .register_write = rt2x00pci_register_write,
975 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
976 .register_multiread = rt2x00pci_register_multiread,
977 .register_multiwrite = rt2x00pci_register_multiwrite,
978 .regbusy_read = rt2x00pci_regbusy_read,
979 .drv_write_firmware = rt2800pci_write_firmware,
980 .drv_init_registers = rt2800pci_init_registers,
981 .drv_get_txwi = rt2800pci_get_txwi,
984 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
985 .irq_handler = rt2800pci_interrupt,
986 .irq_handler_thread = rt2800pci_interrupt_thread,
987 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
988 .probe_hw = rt2800pci_probe_hw,
989 .get_firmware_name = rt2800pci_get_firmware_name,
990 .check_firmware = rt2800_check_firmware,
991 .load_firmware = rt2800_load_firmware,
992 .initialize = rt2x00pci_initialize,
993 .uninitialize = rt2x00pci_uninitialize,
994 .get_entry_state = rt2800pci_get_entry_state,
995 .clear_entry = rt2800pci_clear_entry,
996 .set_device_state = rt2800pci_set_device_state,
997 .rfkill_poll = rt2800_rfkill_poll,
998 .link_stats = rt2800_link_stats,
999 .reset_tuner = rt2800_reset_tuner,
1000 .link_tuner = rt2800_link_tuner,
1001 .start_queue = rt2800pci_start_queue,
1002 .kick_queue = rt2800pci_kick_queue,
1003 .stop_queue = rt2800pci_stop_queue,
1004 .write_tx_desc = rt2800pci_write_tx_desc,
1005 .write_tx_data = rt2800_write_tx_data,
1006 .write_beacon = rt2800_write_beacon,
1007 .fill_rxdone = rt2800pci_fill_rxdone,
1008 .config_shared_key = rt2800_config_shared_key,
1009 .config_pairwise_key = rt2800_config_pairwise_key,
1010 .config_filter = rt2800_config_filter,
1011 .config_intf = rt2800_config_intf,
1012 .config_erp = rt2800_config_erp,
1013 .config_ant = rt2800_config_ant,
1014 .config = rt2800_config,
1017 static const struct data_queue_desc rt2800pci_queue_rx = {
1019 .data_size = AGGREGATION_SIZE,
1020 .desc_size = RXD_DESC_SIZE,
1021 .priv_size = sizeof(struct queue_entry_priv_pci),
1024 static const struct data_queue_desc rt2800pci_queue_tx = {
1026 .data_size = AGGREGATION_SIZE,
1027 .desc_size = TXD_DESC_SIZE,
1028 .priv_size = sizeof(struct queue_entry_priv_pci),
1031 static const struct data_queue_desc rt2800pci_queue_bcn = {
1033 .data_size = 0, /* No DMA required for beacons */
1034 .desc_size = TXWI_DESC_SIZE,
1035 .priv_size = sizeof(struct queue_entry_priv_pci),
1038 static const struct rt2x00_ops rt2800pci_ops = {
1039 .name = KBUILD_MODNAME,
1042 .eeprom_size = EEPROM_SIZE,
1044 .tx_queues = NUM_TX_QUEUES,
1045 .extra_tx_headroom = TXWI_DESC_SIZE,
1046 .rx = &rt2800pci_queue_rx,
1047 .tx = &rt2800pci_queue_tx,
1048 .bcn = &rt2800pci_queue_bcn,
1049 .lib = &rt2800pci_rt2x00_ops,
1050 .drv = &rt2800pci_rt2800_ops,
1051 .hw = &rt2800pci_mac80211_ops,
1052 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1053 .debugfs = &rt2800_rt2x00debug,
1054 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1058 * RT2800pci module information.
1061 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1062 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1063 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1064 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1065 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1066 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1067 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1068 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1069 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1070 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1071 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1072 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1073 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1074 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1075 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1076 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1077 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1078 #ifdef CONFIG_RT2800PCI_RT33XX
1079 { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1081 #ifdef CONFIG_RT2800PCI_RT35XX
1082 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1083 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1084 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1085 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1086 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1090 #endif /* CONFIG_PCI */
1092 MODULE_AUTHOR(DRV_PROJECT);
1093 MODULE_VERSION(DRV_VERSION);
1094 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1095 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1097 MODULE_FIRMWARE(FIRMWARE_RT2860);
1098 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1099 #endif /* CONFIG_PCI */
1100 MODULE_LICENSE("GPL");
1102 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1103 static int rt2800soc_probe(struct platform_device *pdev)
1105 return rt2x00soc_probe(pdev, &rt2800pci_ops);
1108 static struct platform_driver rt2800soc_driver = {
1110 .name = "rt2800_wmac",
1111 .owner = THIS_MODULE,
1112 .mod_name = KBUILD_MODNAME,
1114 .probe = rt2800soc_probe,
1115 .remove = __devexit_p(rt2x00soc_remove),
1116 .suspend = rt2x00soc_suspend,
1117 .resume = rt2x00soc_resume,
1119 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1122 static struct pci_driver rt2800pci_driver = {
1123 .name = KBUILD_MODNAME,
1124 .id_table = rt2800pci_device_table,
1125 .probe = rt2x00pci_probe,
1126 .remove = __devexit_p(rt2x00pci_remove),
1127 .suspend = rt2x00pci_suspend,
1128 .resume = rt2x00pci_resume,
1130 #endif /* CONFIG_PCI */
1132 static int __init rt2800pci_init(void)
1136 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1137 ret = platform_driver_register(&rt2800soc_driver);
1142 ret = pci_register_driver(&rt2800pci_driver);
1144 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1145 platform_driver_unregister(&rt2800soc_driver);
1154 static void __exit rt2800pci_exit(void)
1157 pci_unregister_driver(&rt2800pci_driver);
1159 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1160 platform_driver_unregister(&rt2800soc_driver);
1164 module_init(rt2800pci_init);
1165 module_exit(rt2800pci_exit);