2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
92 mutex_lock(&rt2x00dev->csr_mutex);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
100 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
109 mutex_unlock(&rt2x00dev->csr_mutex);
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
117 mutex_lock(&rt2x00dev->csr_mutex);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
129 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
136 WAIT_FOR_BBP(rt2x00dev, ®);
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
141 mutex_unlock(&rt2x00dev->csr_mutex);
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
149 mutex_lock(&rt2x00dev->csr_mutex);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
157 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
165 mutex_unlock(&rt2x00dev->csr_mutex);
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
173 mutex_lock(&rt2x00dev->csr_mutex);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
185 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
191 WAIT_FOR_RFCSR(rt2x00dev, ®);
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
196 mutex_unlock(&rt2x00dev->csr_mutex);
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
204 mutex_lock(&rt2x00dev->csr_mutex);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev, ®)) {
212 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1);
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
221 mutex_unlock(&rt2x00dev->csr_mutex);
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev))
236 mutex_lock(&rt2x00dev->csr_mutex);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
243 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
250 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
254 mutex_unlock(&rt2x00dev->csr_mutex);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
265 if (reg && reg != ~0)
270 ERROR(rt2x00dev, "Unstable hardware.\n");
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
281 * Some devices are really slow to respond here. Wait a whole second
284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
317 crc = crc_ccitt(~0, data, len - 2);
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
327 return fw_crc == crc;
330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
345 if (rt2x00_is_usb(rt2x00dev)) {
354 * Validate the firmware length
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
360 * Check if the chipset requires one of the upper parts
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
398 * Wait for stable hardware.
400 if (rt2800_wait_csr_ready(rt2x00dev))
403 if (rt2x00_is_pci(rt2x00dev)) {
404 if (rt2x00_rt(rt2x00dev, RT3572) ||
405 rt2x00_rt(rt2x00dev, RT5390)) {
406 rt2800_register_read(rt2x00dev, AUX_CTRL, ®);
407 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
408 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
409 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
411 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
415 * Write firmware to the device.
417 rt2800_drv_write_firmware(rt2x00dev, data, len);
420 * Wait for device to stabilize.
422 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
423 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®);
424 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
429 if (i == REGISTER_BUSY_COUNT) {
430 ERROR(rt2x00dev, "PBF system register not ready.\n");
435 * Disable DMA, will be reenabled later when enabling
438 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
439 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
440 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
441 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
444 * Initialize firmware.
446 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
447 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
448 if (rt2x00_is_usb(rt2x00dev))
449 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
454 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
456 void rt2800_write_tx_data(struct queue_entry *entry,
457 struct txentry_desc *txdesc)
459 __le32 *txwi = rt2800_drv_get_txwi(entry);
463 * Initialize TX Info descriptor
465 rt2x00_desc_read(txwi, 0, &word);
466 rt2x00_set_field32(&word, TXWI_W0_FRAG,
467 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
468 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
470 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
471 rt2x00_set_field32(&word, TXWI_W0_TS,
472 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
474 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
475 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
476 txdesc->u.ht.mpdu_density);
477 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
478 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
479 rt2x00_set_field32(&word, TXWI_W0_BW,
480 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
481 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
482 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
483 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
484 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
485 rt2x00_desc_write(txwi, 0, word);
487 rt2x00_desc_read(txwi, 1, &word);
488 rt2x00_set_field32(&word, TXWI_W1_ACK,
489 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
490 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
491 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
492 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
493 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
494 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
495 txdesc->key_idx : txdesc->u.ht.wcid);
496 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
498 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
499 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
500 rt2x00_desc_write(txwi, 1, word);
503 * Always write 0 to IV/EIV fields, hardware will insert the IV
504 * from the IVEIV register when TXD_W3_WIV is set to 0.
505 * When TXD_W3_WIV is set to 1 it will use the IV data
506 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
507 * crypto entry in the registers should be used to encrypt the frame.
509 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
510 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
512 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
514 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
516 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
517 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
518 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
524 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
525 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
526 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
527 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
528 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
529 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
531 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
532 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
533 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
534 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
535 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
539 * Convert the value from the descriptor into the RSSI value
540 * If the value in the descriptor is 0, it is considered invalid
541 * and the default (extremely low) rssi value is assumed
543 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
544 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
545 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
548 * mac80211 only accepts a single RSSI value. Calculating the
549 * average doesn't deliver a fair answer either since -60:-60 would
550 * be considered equally good as -50:-70 while the second is the one
551 * which gives less energy...
553 rssi0 = max(rssi0, rssi1);
554 return (int)max(rssi0, rssi2);
557 void rt2800_process_rxwi(struct queue_entry *entry,
558 struct rxdone_entry_desc *rxdesc)
560 __le32 *rxwi = (__le32 *) entry->skb->data;
563 rt2x00_desc_read(rxwi, 0, &word);
565 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
566 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
568 rt2x00_desc_read(rxwi, 1, &word);
570 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
571 rxdesc->flags |= RX_FLAG_SHORT_GI;
573 if (rt2x00_get_field32(word, RXWI_W1_BW))
574 rxdesc->flags |= RX_FLAG_40MHZ;
577 * Detect RX rate, always use MCS as signal type.
579 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
580 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
581 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
584 * Mask of 0x8 bit to remove the short preamble flag.
586 if (rxdesc->rate_mode == RATE_MODE_CCK)
587 rxdesc->signal &= ~0x8;
589 rt2x00_desc_read(rxwi, 2, &word);
592 * Convert descriptor AGC value to RSSI value.
594 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
597 * Remove RXWI descriptor from start of buffer.
599 skb_pull(entry->skb, RXWI_DESC_SIZE);
601 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
603 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
605 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
606 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
607 struct txdone_entry_desc txdesc;
613 * Obtain the status about this packet.
616 rt2x00_desc_read(txwi, 0, &word);
618 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
619 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
621 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
622 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
625 * If a frame was meant to be sent as a single non-aggregated MPDU
626 * but ended up in an aggregate the used tx rate doesn't correlate
627 * with the one specified in the TXWI as the whole aggregate is sent
628 * with the same rate.
630 * For example: two frames are sent to rt2x00, the first one sets
631 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
632 * and requests MCS15. If the hw aggregates both frames into one
633 * AMDPU the tx status for both frames will contain MCS7 although
634 * the frame was sent successfully.
636 * Hence, replace the requested rate with the real tx rate to not
637 * confuse the rate control algortihm by providing clearly wrong
640 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
641 skbdesc->tx_rate_idx = real_mcs;
645 if (aggr == 1 || ampdu == 1)
646 __set_bit(TXDONE_AMPDU, &txdesc.flags);
649 * Ralink has a retry mechanism using a global fallback
650 * table. We setup this fallback table to try the immediate
651 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
652 * always contains the MCS used for the last transmission, be
653 * it successful or not.
655 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
657 * Transmission succeeded. The number of retries is
660 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
661 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
664 * Transmission failed. The number of retries is
665 * always 7 in this case (for a total number of 8
668 __set_bit(TXDONE_FAILURE, &txdesc.flags);
669 txdesc.retry = rt2x00dev->long_retry;
673 * the frame was retried at least once
674 * -> hw used fallback rates
677 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
679 rt2x00lib_txdone(entry, &txdesc);
681 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
683 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
685 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
686 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
687 unsigned int beacon_base;
688 unsigned int padding_len;
692 * Disable beaconing while we are reloading the beacon data,
693 * otherwise we might be sending out invalid data.
695 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
697 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
698 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
701 * Add space for the TXWI in front of the skb.
703 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
706 * Register descriptor details in skb frame descriptor.
708 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
709 skbdesc->desc = entry->skb->data;
710 skbdesc->desc_len = TXWI_DESC_SIZE;
713 * Add the TXWI for the beacon to the skb.
715 rt2800_write_tx_data(entry, txdesc);
718 * Dump beacon to userspace through debugfs.
720 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
723 * Write entire beacon with TXWI and padding to register.
725 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
726 if (padding_len && skb_pad(entry->skb, padding_len)) {
727 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
728 /* skb freed by skb_pad() on failure */
730 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
734 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
735 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
736 entry->skb->len + padding_len);
739 * Enable beaconing again.
741 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
742 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
745 * Clean up beacon skb.
747 dev_kfree_skb_any(entry->skb);
750 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
752 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
753 unsigned int beacon_base)
758 * For the Beacon base registers we only need to clear
759 * the whole TXWI which (when set to 0) will invalidate
762 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
763 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
766 void rt2800_clear_beacon(struct queue_entry *entry)
768 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
772 * Disable beaconing while we are reloading the beacon data,
773 * otherwise we might be sending out invalid data.
775 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
776 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
777 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
782 rt2800_clear_beacon_register(rt2x00dev,
783 HW_BEACON_OFFSET(entry->entry_idx));
786 * Enabled beaconing again.
788 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
789 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
791 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
793 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
794 const struct rt2x00debug rt2800_rt2x00debug = {
795 .owner = THIS_MODULE,
797 .read = rt2800_register_read,
798 .write = rt2800_register_write,
799 .flags = RT2X00DEBUGFS_OFFSET,
800 .word_base = CSR_REG_BASE,
801 .word_size = sizeof(u32),
802 .word_count = CSR_REG_SIZE / sizeof(u32),
805 .read = rt2x00_eeprom_read,
806 .write = rt2x00_eeprom_write,
807 .word_base = EEPROM_BASE,
808 .word_size = sizeof(u16),
809 .word_count = EEPROM_SIZE / sizeof(u16),
812 .read = rt2800_bbp_read,
813 .write = rt2800_bbp_write,
814 .word_base = BBP_BASE,
815 .word_size = sizeof(u8),
816 .word_count = BBP_SIZE / sizeof(u8),
819 .read = rt2x00_rf_read,
820 .write = rt2800_rf_write,
821 .word_base = RF_BASE,
822 .word_size = sizeof(u32),
823 .word_count = RF_SIZE / sizeof(u32),
826 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
827 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
829 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
833 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
834 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
836 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
838 #ifdef CONFIG_RT2X00_LIB_LEDS
839 static void rt2800_brightness_set(struct led_classdev *led_cdev,
840 enum led_brightness brightness)
842 struct rt2x00_led *led =
843 container_of(led_cdev, struct rt2x00_led, led_dev);
844 unsigned int enabled = brightness != LED_OFF;
845 unsigned int bg_mode =
846 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
847 unsigned int polarity =
848 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
849 EEPROM_FREQ_LED_POLARITY);
850 unsigned int ledmode =
851 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
852 EEPROM_FREQ_LED_MODE);
855 /* Check for SoC (SOC devices don't support MCU requests) */
856 if (rt2x00_is_soc(led->rt2x00dev)) {
857 rt2800_register_read(led->rt2x00dev, LED_CFG, ®);
859 /* Set LED Polarity */
860 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity);
863 if (led->type == LED_TYPE_RADIO) {
864 rt2x00_set_field32(®, LED_CFG_G_LED_MODE,
866 } else if (led->type == LED_TYPE_ASSOC) {
867 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE,
869 } else if (led->type == LED_TYPE_QUALITY) {
870 rt2x00_set_field32(®, LED_CFG_R_LED_MODE,
874 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
877 if (led->type == LED_TYPE_RADIO) {
878 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
880 } else if (led->type == LED_TYPE_ASSOC) {
881 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
882 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
883 } else if (led->type == LED_TYPE_QUALITY) {
885 * The brightness is divided into 6 levels (0 - 5),
886 * The specs tell us the following levels:
888 * to determine the level in a simple way we can simply
889 * work with bitshifting:
892 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
893 (1 << brightness / (LED_FULL / 6)) - 1,
899 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
900 struct rt2x00_led *led, enum led_type type)
902 led->rt2x00dev = rt2x00dev;
904 led->led_dev.brightness_set = rt2800_brightness_set;
905 led->flags = LED_INITIALIZED;
907 #endif /* CONFIG_RT2X00_LIB_LEDS */
910 * Configuration handlers.
912 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
916 struct mac_wcid_entry wcid_entry;
919 offset = MAC_WCID_ENTRY(wcid);
921 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
923 memcpy(wcid_entry.mac, address, ETH_ALEN);
925 rt2800_register_multiwrite(rt2x00dev, offset,
926 &wcid_entry, sizeof(wcid_entry));
929 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
932 offset = MAC_WCID_ATTR_ENTRY(wcid);
933 rt2800_register_write(rt2x00dev, offset, 0);
936 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
937 int wcid, u32 bssidx)
939 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
943 * The BSS Idx numbers is split in a main value of 3 bits,
944 * and a extended field for adding one additional bit to the value.
946 rt2800_register_read(rt2x00dev, offset, ®);
947 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
948 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
949 (bssidx & 0x8) >> 3);
950 rt2800_register_write(rt2x00dev, offset, reg);
953 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
954 struct rt2x00lib_crypto *crypto,
955 struct ieee80211_key_conf *key)
957 struct mac_iveiv_entry iveiv_entry;
961 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
963 if (crypto->cmd == SET_KEY) {
964 rt2800_register_read(rt2x00dev, offset, ®);
965 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
966 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
968 * Both the cipher as the BSS Idx numbers are split in a main
969 * value of 3 bits, and a extended field for adding one additional
972 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER,
973 (crypto->cipher & 0x7));
974 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
975 (crypto->cipher & 0x8) >> 3);
976 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
977 rt2800_register_write(rt2x00dev, offset, reg);
979 /* Delete the cipher without touching the bssidx */
980 rt2800_register_read(rt2x00dev, offset, ®);
981 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
982 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0);
983 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
984 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
985 rt2800_register_write(rt2x00dev, offset, reg);
988 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
990 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
991 if ((crypto->cipher == CIPHER_TKIP) ||
992 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
993 (crypto->cipher == CIPHER_AES))
994 iveiv_entry.iv[3] |= 0x20;
995 iveiv_entry.iv[3] |= key->keyidx << 6;
996 rt2800_register_multiwrite(rt2x00dev, offset,
997 &iveiv_entry, sizeof(iveiv_entry));
1000 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1001 struct rt2x00lib_crypto *crypto,
1002 struct ieee80211_key_conf *key)
1004 struct hw_key_entry key_entry;
1005 struct rt2x00_field32 field;
1009 if (crypto->cmd == SET_KEY) {
1010 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1012 memcpy(key_entry.key, crypto->key,
1013 sizeof(key_entry.key));
1014 memcpy(key_entry.tx_mic, crypto->tx_mic,
1015 sizeof(key_entry.tx_mic));
1016 memcpy(key_entry.rx_mic, crypto->rx_mic,
1017 sizeof(key_entry.rx_mic));
1019 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1020 rt2800_register_multiwrite(rt2x00dev, offset,
1021 &key_entry, sizeof(key_entry));
1025 * The cipher types are stored over multiple registers
1026 * starting with SHARED_KEY_MODE_BASE each word will have
1027 * 32 bits and contains the cipher types for 2 bssidx each.
1028 * Using the correct defines correctly will cause overhead,
1029 * so just calculate the correct offset.
1031 field.bit_offset = 4 * (key->hw_key_idx % 8);
1032 field.bit_mask = 0x7 << field.bit_offset;
1034 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1036 rt2800_register_read(rt2x00dev, offset, ®);
1037 rt2x00_set_field32(®, field,
1038 (crypto->cmd == SET_KEY) * crypto->cipher);
1039 rt2800_register_write(rt2x00dev, offset, reg);
1042 * Update WCID information
1044 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1045 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1047 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1051 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1053 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1055 struct mac_wcid_entry wcid_entry;
1060 * Search for the first free WCID entry and return the corresponding
1063 * Make sure the WCID starts _after_ the last possible shared key
1066 * Since parts of the pairwise key table might be shared with
1067 * the beacon frame buffers 6 & 7 we should only write into the
1068 * first 222 entries.
1070 for (idx = 33; idx <= 222; idx++) {
1071 offset = MAC_WCID_ENTRY(idx);
1072 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1073 sizeof(wcid_entry));
1074 if (is_broadcast_ether_addr(wcid_entry.mac))
1079 * Use -1 to indicate that we don't have any more space in the WCID
1085 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1086 struct rt2x00lib_crypto *crypto,
1087 struct ieee80211_key_conf *key)
1089 struct hw_key_entry key_entry;
1092 if (crypto->cmd == SET_KEY) {
1094 * Allow key configuration only for STAs that are
1097 if (crypto->wcid < 0)
1099 key->hw_key_idx = crypto->wcid;
1101 memcpy(key_entry.key, crypto->key,
1102 sizeof(key_entry.key));
1103 memcpy(key_entry.tx_mic, crypto->tx_mic,
1104 sizeof(key_entry.tx_mic));
1105 memcpy(key_entry.rx_mic, crypto->rx_mic,
1106 sizeof(key_entry.rx_mic));
1108 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1109 rt2800_register_multiwrite(rt2x00dev, offset,
1110 &key_entry, sizeof(key_entry));
1114 * Update WCID information
1116 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1120 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1122 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1123 struct ieee80211_sta *sta)
1126 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1129 * Find next free WCID.
1131 wcid = rt2800_find_wcid(rt2x00dev);
1134 * Store selected wcid even if it is invalid so that we can
1135 * later decide if the STA is uploaded into the hw.
1137 sta_priv->wcid = wcid;
1140 * No space left in the device, however, we can still communicate
1141 * with the STA -> No error.
1147 * Clean up WCID attributes and write STA address to the device.
1149 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1150 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1151 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1152 rt2x00lib_get_bssidx(rt2x00dev, vif));
1155 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1157 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1160 * Remove WCID entry, no need to clean the attributes as they will
1161 * get renewed when the WCID is reused.
1163 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1167 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1169 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1170 const unsigned int filter_flags)
1175 * Start configuration steps.
1176 * Note that the version error will always be dropped
1177 * and broadcast frames will always be accepted since
1178 * there is no filter for it at this time.
1180 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®);
1181 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR,
1182 !(filter_flags & FIF_FCSFAIL));
1183 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR,
1184 !(filter_flags & FIF_PLCPFAIL));
1185 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME,
1186 !(filter_flags & FIF_PROMISC_IN_BSS));
1187 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1188 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1189 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST,
1190 !(filter_flags & FIF_ALLMULTI));
1191 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0);
1192 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1193 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK,
1194 !(filter_flags & FIF_CONTROL));
1195 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END,
1196 !(filter_flags & FIF_CONTROL));
1197 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK,
1198 !(filter_flags & FIF_CONTROL));
1199 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS,
1200 !(filter_flags & FIF_CONTROL));
1201 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS,
1202 !(filter_flags & FIF_CONTROL));
1203 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL,
1204 !(filter_flags & FIF_PSPOLL));
1205 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA,
1206 !(filter_flags & FIF_CONTROL));
1207 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR,
1208 !(filter_flags & FIF_CONTROL));
1209 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL,
1210 !(filter_flags & FIF_CONTROL));
1211 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1213 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1215 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1216 struct rt2x00intf_conf *conf, const unsigned int flags)
1219 bool update_bssid = false;
1221 if (flags & CONFIG_UPDATE_TYPE) {
1223 * Enable synchronisation.
1225 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1226 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1227 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1229 if (conf->sync == TSF_SYNC_AP_NONE) {
1231 * Tune beacon queue transmit parameters for AP mode
1233 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®);
1234 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1235 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1236 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1237 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1238 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1240 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®);
1241 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1242 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1243 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1244 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1245 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1249 if (flags & CONFIG_UPDATE_MAC) {
1250 if (flags & CONFIG_UPDATE_TYPE &&
1251 conf->sync == TSF_SYNC_AP_NONE) {
1253 * The BSSID register has to be set to our own mac
1254 * address in AP mode.
1256 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1257 update_bssid = true;
1260 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1261 reg = le32_to_cpu(conf->mac[1]);
1262 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1263 conf->mac[1] = cpu_to_le32(reg);
1266 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1267 conf->mac, sizeof(conf->mac));
1270 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1271 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1272 reg = le32_to_cpu(conf->bssid[1]);
1273 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1274 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1275 conf->bssid[1] = cpu_to_le32(reg);
1278 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1279 conf->bssid, sizeof(conf->bssid));
1282 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1284 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1285 struct rt2x00lib_erp *erp)
1287 bool any_sta_nongf = !!(erp->ht_opmode &
1288 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1289 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1290 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1291 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1294 /* default protection rate for HT20: OFDM 24M */
1295 mm20_rate = gf20_rate = 0x4004;
1297 /* default protection rate for HT40: duplicate OFDM 24M */
1298 mm40_rate = gf40_rate = 0x4084;
1300 switch (protection) {
1301 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1303 * All STAs in this BSS are HT20/40 but there might be
1304 * STAs not supporting greenfield mode.
1305 * => Disable protection for HT transmissions.
1307 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1310 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1312 * All STAs in this BSS are HT20 or HT20/40 but there
1313 * might be STAs not supporting greenfield mode.
1314 * => Protect all HT40 transmissions.
1316 mm20_mode = gf20_mode = 0;
1317 mm40_mode = gf40_mode = 2;
1320 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1322 * Nonmember protection:
1323 * According to 802.11n we _should_ protect all
1324 * HT transmissions (but we don't have to).
1326 * But if cts_protection is enabled we _shall_ protect
1327 * all HT transmissions using a CCK rate.
1329 * And if any station is non GF we _shall_ protect
1332 * We decide to protect everything
1333 * -> fall through to mixed mode.
1335 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1337 * Legacy STAs are present
1338 * => Protect all HT transmissions.
1340 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1343 * If erp protection is needed we have to protect HT
1344 * transmissions with CCK 11M long preamble.
1346 if (erp->cts_protection) {
1347 /* don't duplicate RTS/CTS in CCK mode */
1348 mm20_rate = mm40_rate = 0x0003;
1349 gf20_rate = gf40_rate = 0x0003;
1354 /* check for STAs not supporting greenfield mode */
1356 gf20_mode = gf40_mode = 2;
1358 /* Update HT protection config */
1359 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
1360 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1361 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1362 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1364 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
1365 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1366 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1367 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1369 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
1370 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1371 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1372 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1374 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
1375 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1376 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1377 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1380 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1385 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1386 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
1387 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY,
1388 !!erp->short_preamble);
1389 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE,
1390 !!erp->short_preamble);
1391 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1394 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1395 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
1396 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL,
1397 erp->cts_protection ? 2 : 0);
1398 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1401 if (changed & BSS_CHANGED_BASIC_RATES) {
1402 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1404 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1407 if (changed & BSS_CHANGED_ERP_SLOT) {
1408 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
1409 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME,
1411 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1413 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
1414 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs);
1415 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1418 if (changed & BSS_CHANGED_BEACON_INT) {
1419 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1420 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
1421 erp->beacon_int * 16);
1422 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1425 if (changed & BSS_CHANGED_HT)
1426 rt2800_config_ht_opmode(rt2x00dev, erp);
1428 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1430 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1434 u8 led_ctrl, led_g_mode, led_r_mode;
1436 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
1437 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1438 rt2x00_set_field32(®, GPIO_SWITCH_0, 1);
1439 rt2x00_set_field32(®, GPIO_SWITCH_1, 1);
1441 rt2x00_set_field32(®, GPIO_SWITCH_0, 0);
1442 rt2x00_set_field32(®, GPIO_SWITCH_1, 0);
1444 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1446 rt2800_register_read(rt2x00dev, LED_CFG, ®);
1447 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1448 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1449 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1450 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1451 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1452 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1453 if (led_ctrl == 0 || led_ctrl > 0x40) {
1454 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode);
1455 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode);
1456 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1458 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1459 (led_g_mode << 2) | led_r_mode, 1);
1464 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1468 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1469 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1471 if (rt2x00_is_pci(rt2x00dev)) {
1472 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®);
1473 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1474 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1475 } else if (rt2x00_is_usb(rt2x00dev))
1476 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1479 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
1480 rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1481 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1482 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1485 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1491 rt2800_bbp_read(rt2x00dev, 1, &r1);
1492 rt2800_bbp_read(rt2x00dev, 3, &r3);
1494 if (rt2x00_rt(rt2x00dev, RT3572) &&
1495 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1496 rt2800_config_3572bt_ant(rt2x00dev);
1499 * Configure the TX antenna.
1501 switch (ant->tx_chain_num) {
1503 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1506 if (rt2x00_rt(rt2x00dev, RT3572) &&
1507 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1508 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1510 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1513 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1518 * Configure the RX antenna.
1520 switch (ant->rx_chain_num) {
1522 if (rt2x00_rt(rt2x00dev, RT3070) ||
1523 rt2x00_rt(rt2x00dev, RT3090) ||
1524 rt2x00_rt(rt2x00dev, RT3390)) {
1525 rt2x00_eeprom_read(rt2x00dev,
1526 EEPROM_NIC_CONF1, &eeprom);
1527 if (rt2x00_get_field16(eeprom,
1528 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1529 rt2800_set_ant_diversity(rt2x00dev,
1530 rt2x00dev->default_ant.rx);
1532 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1535 if (rt2x00_rt(rt2x00dev, RT3572) &&
1536 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1537 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1538 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1539 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1540 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1542 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1546 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1550 rt2800_bbp_write(rt2x00dev, 3, r3);
1551 rt2800_bbp_write(rt2x00dev, 1, r1);
1553 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1555 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1556 struct rt2x00lib_conf *libconf)
1561 if (libconf->rf.channel <= 14) {
1562 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1563 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1564 } else if (libconf->rf.channel <= 64) {
1565 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1566 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1567 } else if (libconf->rf.channel <= 128) {
1568 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1569 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1571 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1572 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1575 rt2x00dev->lna_gain = lna_gain;
1578 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1579 struct ieee80211_conf *conf,
1580 struct rf_channel *rf,
1581 struct channel_info *info)
1583 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1585 if (rt2x00dev->default_ant.tx_chain_num == 1)
1586 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1588 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1589 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1590 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1591 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1592 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1594 if (rf->channel > 14) {
1596 * When TX power is below 0, we should increase it by 7 to
1597 * make it a positive value (Minimum value is -7).
1598 * However this means that values between 0 and 7 have
1599 * double meaning, and we should set a 7DBm boost flag.
1601 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1602 (info->default_power1 >= 0));
1604 if (info->default_power1 < 0)
1605 info->default_power1 += 7;
1607 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1609 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1610 (info->default_power2 >= 0));
1612 if (info->default_power2 < 0)
1613 info->default_power2 += 7;
1615 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1617 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1618 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1621 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1623 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1624 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1625 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1626 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1630 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1631 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1632 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1633 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1637 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1638 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1639 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1640 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1643 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1644 struct ieee80211_conf *conf,
1645 struct rf_channel *rf,
1646 struct channel_info *info)
1648 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1649 u8 rfcsr, calib_tx, calib_rx;
1651 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1653 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1654 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1655 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1657 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1658 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1659 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1661 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1662 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1663 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1665 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1666 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1667 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1669 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1670 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1671 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1672 if (rt2x00_rt(rt2x00dev, RT3390)) {
1673 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1674 rt2x00dev->default_ant.rx_chain_num == 1);
1675 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1676 rt2x00dev->default_ant.tx_chain_num == 1);
1678 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1679 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1680 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1681 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1683 switch (rt2x00dev->default_ant.tx_chain_num) {
1685 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1688 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1692 switch (rt2x00dev->default_ant.rx_chain_num) {
1694 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1697 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1701 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1703 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1704 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1705 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1707 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1708 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1710 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1711 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1712 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1714 if (rt2x00_rt(rt2x00dev, RT3390)) {
1715 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1716 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1718 if (conf_is_ht40(conf)) {
1719 calib_tx = drv_data->calibration_bw40;
1720 calib_rx = drv_data->calibration_bw40;
1722 calib_tx = drv_data->calibration_bw20;
1723 calib_rx = drv_data->calibration_bw20;
1727 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1728 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1729 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1731 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1732 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1733 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1735 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1736 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1737 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1739 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1740 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1741 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1743 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1744 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1747 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1748 struct ieee80211_conf *conf,
1749 struct rf_channel *rf,
1750 struct channel_info *info)
1752 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1756 if (rf->channel <= 14) {
1757 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1758 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1760 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1761 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1764 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1765 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1767 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1768 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1769 if (rf->channel <= 14)
1770 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1772 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1773 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1775 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1776 if (rf->channel <= 14)
1777 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1779 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1780 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1782 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1783 if (rf->channel <= 14) {
1784 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1785 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1786 info->default_power1);
1788 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1789 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1790 (info->default_power1 & 0x3) |
1791 ((info->default_power1 & 0xC) << 1));
1793 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1795 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1796 if (rf->channel <= 14) {
1797 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1798 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1799 info->default_power2);
1801 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1802 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1803 (info->default_power2 & 0x3) |
1804 ((info->default_power2 & 0xC) << 1));
1806 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1808 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1809 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1810 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1811 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1812 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1813 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1814 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1815 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1816 if (rf->channel <= 14) {
1817 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1818 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1820 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1821 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1823 switch (rt2x00dev->default_ant.tx_chain_num) {
1825 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1827 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1831 switch (rt2x00dev->default_ant.rx_chain_num) {
1833 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1835 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1839 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1841 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1842 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1843 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1845 if (conf_is_ht40(conf)) {
1846 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1847 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1849 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1850 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1853 if (rf->channel <= 14) {
1854 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1855 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1856 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1857 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1858 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1860 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1861 drv_data->txmixer_gain_24g);
1862 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1863 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1864 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1865 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1866 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1867 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1868 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1869 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1871 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1872 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1873 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1874 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1875 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1876 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1877 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1878 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1879 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1880 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1882 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1883 drv_data->txmixer_gain_5g);
1884 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1885 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1886 if (rf->channel <= 64) {
1887 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1888 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1889 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1890 } else if (rf->channel <= 128) {
1891 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1892 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1893 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1895 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1896 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1897 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1899 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1900 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1901 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1904 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
1905 rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1906 if (rf->channel <= 14)
1907 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT7, 1);
1909 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT7, 0);
1910 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1912 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1913 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1914 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1917 #define RT5390_POWER_BOUND 0x27
1918 #define RT5390_FREQ_OFFSET_BOUND 0x5f
1920 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1921 struct ieee80211_conf *conf,
1922 struct rf_channel *rf,
1923 struct channel_info *info)
1927 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1928 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1929 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1930 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1931 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1933 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1934 if (info->default_power1 > RT5390_POWER_BOUND)
1935 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1937 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1938 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1940 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1941 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1942 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1943 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1944 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1945 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1947 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1948 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1949 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1950 RT5390_FREQ_OFFSET_BOUND);
1952 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1953 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1955 if (rf->channel <= 14) {
1956 int idx = rf->channel-1;
1958 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1959 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1960 /* r55/r59 value array of channel 1~14 */
1961 static const char r55_bt_rev[] = {0x83, 0x83,
1962 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1963 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1964 static const char r59_bt_rev[] = {0x0e, 0x0e,
1965 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1966 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1968 rt2800_rfcsr_write(rt2x00dev, 55,
1970 rt2800_rfcsr_write(rt2x00dev, 59,
1973 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1974 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1975 0x88, 0x88, 0x86, 0x85, 0x84};
1977 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1980 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1981 static const char r55_nonbt_rev[] = {0x23, 0x23,
1982 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1983 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1984 static const char r59_nonbt_rev[] = {0x07, 0x07,
1985 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1986 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1988 rt2800_rfcsr_write(rt2x00dev, 55,
1989 r55_nonbt_rev[idx]);
1990 rt2800_rfcsr_write(rt2x00dev, 59,
1991 r59_nonbt_rev[idx]);
1992 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1993 static const char r59_non_bt[] = {0x8f, 0x8f,
1994 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1995 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1997 rt2800_rfcsr_write(rt2x00dev, 59,
2003 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2004 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2005 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2006 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2008 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2009 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2010 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2013 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2014 struct ieee80211_conf *conf,
2015 struct rf_channel *rf,
2016 struct channel_info *info)
2019 unsigned int tx_pin;
2022 if (rf->channel <= 14) {
2023 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2024 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2026 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2027 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2030 switch (rt2x00dev->chip.rf) {
2036 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2039 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2043 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2046 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2050 * Change BBP settings
2052 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2053 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2054 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2055 rt2800_bbp_write(rt2x00dev, 86, 0);
2057 if (rf->channel <= 14) {
2058 if (!rt2x00_rt(rt2x00dev, RT5390)) {
2059 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2060 &rt2x00dev->cap_flags)) {
2061 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2062 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2064 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2065 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2069 if (rt2x00_rt(rt2x00dev, RT3572))
2070 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2072 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2074 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2075 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2077 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2080 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®);
2081 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2082 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
2083 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
2084 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2086 if (rt2x00_rt(rt2x00dev, RT3572))
2087 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2091 /* Turn on unused PA or LNA when not using 1T or 1R */
2092 if (rt2x00dev->default_ant.tx_chain_num == 2) {
2093 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2095 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2099 /* Turn on unused PA or LNA when not using 1T or 1R */
2100 if (rt2x00dev->default_ant.rx_chain_num == 2) {
2101 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2102 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2105 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2106 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2107 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2108 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2109 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2110 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2112 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2114 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2116 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2118 if (rt2x00_rt(rt2x00dev, RT3572))
2119 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2121 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2122 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2123 rt2800_bbp_write(rt2x00dev, 4, bbp);
2125 rt2800_bbp_read(rt2x00dev, 3, &bbp);
2126 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2127 rt2800_bbp_write(rt2x00dev, 3, bbp);
2129 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2130 if (conf_is_ht40(conf)) {
2131 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2132 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2133 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2135 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2136 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2137 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2144 * Clear channel statistic counters
2146 rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®);
2147 rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®);
2148 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®);
2151 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2160 * Read TSSI boundaries for temperature compensation from
2163 * Array idx 0 1 2 3 4 5 6 7 8
2164 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2165 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2167 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2168 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2169 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2170 EEPROM_TSSI_BOUND_BG1_MINUS4);
2171 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2172 EEPROM_TSSI_BOUND_BG1_MINUS3);
2174 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2175 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2176 EEPROM_TSSI_BOUND_BG2_MINUS2);
2177 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2178 EEPROM_TSSI_BOUND_BG2_MINUS1);
2180 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2181 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2182 EEPROM_TSSI_BOUND_BG3_REF);
2183 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2184 EEPROM_TSSI_BOUND_BG3_PLUS1);
2186 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2187 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2188 EEPROM_TSSI_BOUND_BG4_PLUS2);
2189 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2190 EEPROM_TSSI_BOUND_BG4_PLUS3);
2192 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2193 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2194 EEPROM_TSSI_BOUND_BG5_PLUS4);
2196 step = rt2x00_get_field16(eeprom,
2197 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2199 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2200 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2201 EEPROM_TSSI_BOUND_A1_MINUS4);
2202 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2203 EEPROM_TSSI_BOUND_A1_MINUS3);
2205 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2206 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2207 EEPROM_TSSI_BOUND_A2_MINUS2);
2208 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2209 EEPROM_TSSI_BOUND_A2_MINUS1);
2211 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2212 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2213 EEPROM_TSSI_BOUND_A3_REF);
2214 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2215 EEPROM_TSSI_BOUND_A3_PLUS1);
2217 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2218 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2219 EEPROM_TSSI_BOUND_A4_PLUS2);
2220 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2221 EEPROM_TSSI_BOUND_A4_PLUS3);
2223 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2224 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2225 EEPROM_TSSI_BOUND_A5_PLUS4);
2227 step = rt2x00_get_field16(eeprom,
2228 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2232 * Check if temperature compensation is supported.
2234 if (tssi_bounds[4] == 0xff)
2238 * Read current TSSI (BBP 49).
2240 rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi);
2243 * Compare TSSI value (BBP49) with the compensation boundaries
2244 * from the EEPROM and increase or decrease tx power.
2246 for (i = 0; i <= 3; i++) {
2247 if (current_tssi > tssi_bounds[i])
2252 for (i = 8; i >= 5; i--) {
2253 if (current_tssi < tssi_bounds[i])
2258 return (i - 4) * step;
2261 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2262 enum ieee80211_band band)
2269 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2272 * HT40 compensation not required.
2274 if (eeprom == 0xffff ||
2275 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2278 if (band == IEEE80211_BAND_2GHZ) {
2279 comp_en = rt2x00_get_field16(eeprom,
2280 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2282 comp_type = rt2x00_get_field16(eeprom,
2283 EEPROM_TXPOWER_DELTA_TYPE_2G);
2284 comp_value = rt2x00_get_field16(eeprom,
2285 EEPROM_TXPOWER_DELTA_VALUE_2G);
2287 comp_value = -comp_value;
2290 comp_en = rt2x00_get_field16(eeprom,
2291 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2293 comp_type = rt2x00_get_field16(eeprom,
2294 EEPROM_TXPOWER_DELTA_TYPE_5G);
2295 comp_value = rt2x00_get_field16(eeprom,
2296 EEPROM_TXPOWER_DELTA_VALUE_5G);
2298 comp_value = -comp_value;
2305 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2306 enum ieee80211_band band, int power_level,
2307 u8 txpower, int delta)
2313 u8 eirp_txpower_criterion;
2316 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2319 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2321 * Check if eirp txpower exceed txpower_limit.
2322 * We use OFDM 6M as criterion and its eirp txpower
2323 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2324 * .11b data rate need add additional 4dbm
2325 * when calculating eirp txpower.
2327 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, ®);
2328 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2330 rt2x00_eeprom_read(rt2x00dev,
2331 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2333 if (band == IEEE80211_BAND_2GHZ)
2334 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2335 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2337 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2338 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2340 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2341 (is_rate_b ? 4 : 0) + delta;
2343 reg_limit = (eirp_txpower > power_level) ?
2344 (eirp_txpower - power_level) : 0;
2348 return txpower + delta - reg_limit;
2351 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2352 enum ieee80211_band band,
2364 * Calculate HT40 compensation delta
2366 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2369 * calculate temperature compensation delta
2371 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2374 * set to normal bbp tx power control mode: +/- 0dBm
2376 rt2800_bbp_read(rt2x00dev, 1, &r1);
2377 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2378 rt2800_bbp_write(rt2x00dev, 1, r1);
2379 offset = TX_PWR_CFG_0;
2381 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2382 /* just to be safe */
2383 if (offset > TX_PWR_CFG_4)
2386 rt2800_register_read(rt2x00dev, offset, ®);
2388 /* read the next four txpower values */
2389 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2392 is_rate_b = i ? 0 : 1;
2394 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2395 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2396 * TX_PWR_CFG_4: unknown
2398 txpower = rt2x00_get_field16(eeprom,
2399 EEPROM_TXPOWER_BYRATE_RATE0);
2400 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2401 power_level, txpower, delta);
2402 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower);
2405 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2406 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2407 * TX_PWR_CFG_4: unknown
2409 txpower = rt2x00_get_field16(eeprom,
2410 EEPROM_TXPOWER_BYRATE_RATE1);
2411 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2412 power_level, txpower, delta);
2413 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower);
2416 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2417 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2418 * TX_PWR_CFG_4: unknown
2420 txpower = rt2x00_get_field16(eeprom,
2421 EEPROM_TXPOWER_BYRATE_RATE2);
2422 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2423 power_level, txpower, delta);
2424 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower);
2427 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2428 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2429 * TX_PWR_CFG_4: unknown
2431 txpower = rt2x00_get_field16(eeprom,
2432 EEPROM_TXPOWER_BYRATE_RATE3);
2433 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2434 power_level, txpower, delta);
2435 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower);
2437 /* read the next four txpower values */
2438 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2443 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2444 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2445 * TX_PWR_CFG_4: unknown
2447 txpower = rt2x00_get_field16(eeprom,
2448 EEPROM_TXPOWER_BYRATE_RATE0);
2449 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2450 power_level, txpower, delta);
2451 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower);
2454 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2455 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2456 * TX_PWR_CFG_4: unknown
2458 txpower = rt2x00_get_field16(eeprom,
2459 EEPROM_TXPOWER_BYRATE_RATE1);
2460 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2461 power_level, txpower, delta);
2462 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower);
2465 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2466 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2467 * TX_PWR_CFG_4: unknown
2469 txpower = rt2x00_get_field16(eeprom,
2470 EEPROM_TXPOWER_BYRATE_RATE2);
2471 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2472 power_level, txpower, delta);
2473 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower);
2476 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2477 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2478 * TX_PWR_CFG_4: unknown
2480 txpower = rt2x00_get_field16(eeprom,
2481 EEPROM_TXPOWER_BYRATE_RATE3);
2482 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2483 power_level, txpower, delta);
2484 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower);
2486 rt2800_register_write(rt2x00dev, offset, reg);
2488 /* next TX_PWR_CFG register */
2493 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2495 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2496 rt2x00dev->tx_power);
2498 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2500 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2501 struct rt2x00lib_conf *libconf)
2505 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
2506 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT,
2507 libconf->conf->short_frame_max_tx_count);
2508 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT,
2509 libconf->conf->long_frame_max_tx_count);
2510 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2513 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2514 struct rt2x00lib_conf *libconf)
2516 enum dev_state state =
2517 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2518 STATE_SLEEP : STATE_AWAKE;
2521 if (state == STATE_SLEEP) {
2522 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2524 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
2525 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2526 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2527 libconf->conf->listen_interval - 1);
2528 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2529 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2531 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2533 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
2534 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2535 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2536 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2537 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2539 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2543 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2544 struct rt2x00lib_conf *libconf,
2545 const unsigned int flags)
2547 /* Always recalculate LNA gain before changing configuration */
2548 rt2800_config_lna_gain(rt2x00dev, libconf);
2550 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2551 rt2800_config_channel(rt2x00dev, libconf->conf,
2552 &libconf->rf, &libconf->channel);
2553 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2554 libconf->conf->power_level);
2556 if (flags & IEEE80211_CONF_CHANGE_POWER)
2557 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2558 libconf->conf->power_level);
2559 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2560 rt2800_config_retry_limit(rt2x00dev, libconf);
2561 if (flags & IEEE80211_CONF_CHANGE_PS)
2562 rt2800_config_ps(rt2x00dev, libconf);
2564 EXPORT_SYMBOL_GPL(rt2800_config);
2569 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2574 * Update FCS error count from register.
2576 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
2577 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2579 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2581 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2583 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2584 if (rt2x00_rt(rt2x00dev, RT3070) ||
2585 rt2x00_rt(rt2x00dev, RT3071) ||
2586 rt2x00_rt(rt2x00dev, RT3090) ||
2587 rt2x00_rt(rt2x00dev, RT3390) ||
2588 rt2x00_rt(rt2x00dev, RT5390))
2589 return 0x1c + (2 * rt2x00dev->lna_gain);
2591 return 0x2e + rt2x00dev->lna_gain;
2594 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2595 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2597 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2600 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2601 struct link_qual *qual, u8 vgc_level)
2603 if (qual->vgc_level != vgc_level) {
2604 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2605 qual->vgc_level = vgc_level;
2606 qual->vgc_level_reg = vgc_level;
2610 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2612 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2614 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2616 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2619 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2623 * When RSSI is better then -80 increase VGC level with 0x10
2625 rt2800_set_vgc(rt2x00dev, qual,
2626 rt2800_get_default_vgc(rt2x00dev) +
2627 ((qual->rssi > -80) * 0x10));
2629 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2632 * Initialization functions.
2634 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2641 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
2642 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2643 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2644 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2645 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2646 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2647 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2649 ret = rt2800_drv_init_registers(rt2x00dev);
2653 rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®);
2654 rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2655 rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2656 rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2657 rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2658 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2660 rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®);
2661 rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2662 rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2663 rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2664 rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2665 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2667 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2668 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2670 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2672 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
2673 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2674 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
2675 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0);
2676 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
2677 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
2678 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2679 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2681 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2683 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
2684 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2685 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2686 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2688 if (rt2x00_rt(rt2x00dev, RT3071) ||
2689 rt2x00_rt(rt2x00dev, RT3090) ||
2690 rt2x00_rt(rt2x00dev, RT3390)) {
2691 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2692 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2693 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2694 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2695 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2696 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2697 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2698 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2701 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2704 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2706 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2707 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2709 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2710 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2711 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2713 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2714 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2716 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2717 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2718 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2719 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2720 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2721 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2722 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2723 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2724 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2725 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2726 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2728 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2729 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2732 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®);
2733 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2734 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0);
2735 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2736 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0);
2737 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0);
2738 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2739 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0);
2740 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0);
2741 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2743 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®);
2744 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2745 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2746 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2747 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2749 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®);
2750 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2751 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2752 rt2x00_rt(rt2x00dev, RT2883) ||
2753 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2754 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2);
2756 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1);
2757 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0);
2758 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0);
2759 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2761 rt2800_register_read(rt2x00dev, LED_CFG, ®);
2762 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70);
2763 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30);
2764 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3);
2765 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3);
2766 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3);
2767 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3);
2768 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1);
2769 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2771 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2773 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
2774 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2775 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2776 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2777 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2778 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0);
2779 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2780 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2782 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
2783 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1);
2784 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2785 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2786 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0);
2787 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2788 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2789 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2790 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2792 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
2793 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3);
2794 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0);
2795 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2796 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2797 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2798 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2799 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2800 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2801 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2802 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1);
2803 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2805 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
2806 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3);
2807 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2808 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2809 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2810 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2811 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2812 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2813 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2814 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2815 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1);
2816 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2818 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
2819 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2820 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0);
2821 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2822 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2823 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2824 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2825 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2826 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2827 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2828 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0);
2829 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2831 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
2832 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2833 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0);
2834 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2835 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2836 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2837 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2838 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2839 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2840 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2841 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0);
2842 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2844 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
2845 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2846 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0);
2847 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2848 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2849 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2850 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2851 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2852 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2853 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2854 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0);
2855 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2857 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
2858 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2859 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0);
2860 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2861 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2862 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2863 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2864 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2865 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2866 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2867 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0);
2868 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2870 if (rt2x00_is_usb(rt2x00dev)) {
2871 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2873 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
2874 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2875 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2876 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2877 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2878 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2879 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2880 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2881 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2882 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2883 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2887 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2888 * although it is reserved.
2890 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®);
2891 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2892 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2893 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2894 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2895 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2896 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2897 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2898 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2899 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2900 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2901 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2903 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2905 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
2906 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2907 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
2908 IEEE80211_MAX_RTS_THRESHOLD);
2909 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0);
2910 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2912 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2915 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2916 * time should be set to 16. However, the original Ralink driver uses
2917 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2918 * connection problems with 11g + CTS protection. Hence, use the same
2919 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2921 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
2922 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2923 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2924 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2925 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314);
2926 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2927 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2929 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2932 * ASIC will keep garbage value after boot, clear encryption keys.
2934 for (i = 0; i < 4; i++)
2935 rt2800_register_write(rt2x00dev,
2936 SHARED_KEY_MODE_ENTRY(i), 0);
2938 for (i = 0; i < 256; i++) {
2939 rt2800_config_wcid(rt2x00dev, NULL, i);
2940 rt2800_delete_wcid_attr(rt2x00dev, i);
2941 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2947 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2948 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2949 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2950 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2951 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2952 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2953 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2954 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2956 if (rt2x00_is_usb(rt2x00dev)) {
2957 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®);
2958 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30);
2959 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2960 } else if (rt2x00_is_pcie(rt2x00dev)) {
2961 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®);
2962 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125);
2963 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2966 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®);
2967 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0);
2968 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0);
2969 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1);
2970 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2);
2971 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3);
2972 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4);
2973 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5);
2974 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6);
2975 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2977 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®);
2978 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8);
2979 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8);
2980 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9);
2981 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10);
2982 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11);
2983 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12);
2984 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13);
2985 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14);
2986 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2988 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®);
2989 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2990 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2991 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2992 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2993 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2994 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2995 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2996 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2997 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2999 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®);
3000 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0);
3001 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0);
3002 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1);
3003 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2);
3004 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3007 * Do not force the BA window size, we use the TXWI to set it
3009 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®);
3010 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3011 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3012 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3015 * We must clear the error counters.
3016 * These registers are cleared on read,
3017 * so we may pass a useless variable to store the value.
3019 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
3020 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®);
3021 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®);
3022 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®);
3023 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®);
3024 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®);
3027 * Setup leadtime for pre tbtt interrupt to 6ms
3029 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®);
3030 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3031 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3034 * Set up channel statistics timer
3036 rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®);
3037 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1);
3038 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1);
3039 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1);
3040 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1);
3041 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1);
3042 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3047 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3052 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3053 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®);
3054 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3057 udelay(REGISTER_BUSY_DELAY);
3060 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3064 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3070 * BBP was enabled after firmware was loaded,
3071 * but we need to reactivate it now.
3073 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3074 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3077 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3078 rt2800_bbp_read(rt2x00dev, 0, &value);
3079 if ((value != 0xff) && (value != 0x00))
3081 udelay(REGISTER_BUSY_DELAY);
3084 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3088 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3095 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3096 rt2800_wait_bbp_ready(rt2x00dev)))
3099 if (rt2x00_rt(rt2x00dev, RT5390)) {
3100 rt2800_bbp_read(rt2x00dev, 4, &value);
3101 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3102 rt2800_bbp_write(rt2x00dev, 4, value);
3105 if (rt2800_is_305x_soc(rt2x00dev) ||
3106 rt2x00_rt(rt2x00dev, RT3572) ||
3107 rt2x00_rt(rt2x00dev, RT5390))
3108 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3110 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3111 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3113 if (rt2x00_rt(rt2x00dev, RT5390))
3114 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3116 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3117 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3118 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3119 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3120 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3121 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3122 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3123 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3124 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3126 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3127 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3130 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3132 if (rt2x00_rt(rt2x00dev, RT3070) ||
3133 rt2x00_rt(rt2x00dev, RT3071) ||
3134 rt2x00_rt(rt2x00dev, RT3090) ||
3135 rt2x00_rt(rt2x00dev, RT3390) ||
3136 rt2x00_rt(rt2x00dev, RT3572) ||
3137 rt2x00_rt(rt2x00dev, RT5390)) {
3138 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3139 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3140 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3141 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3142 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3143 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3145 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3148 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3149 if (rt2x00_rt(rt2x00dev, RT5390))
3150 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3152 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3154 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3155 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3156 else if (rt2x00_rt(rt2x00dev, RT5390))
3157 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3159 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3161 if (rt2x00_rt(rt2x00dev, RT5390))
3162 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3164 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3166 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3168 if (rt2x00_rt(rt2x00dev, RT5390))
3169 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3171 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3173 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3174 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3175 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3176 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3177 rt2x00_rt(rt2x00dev, RT3572) ||
3178 rt2x00_rt(rt2x00dev, RT5390) ||
3179 rt2800_is_305x_soc(rt2x00dev))
3180 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3182 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3184 if (rt2x00_rt(rt2x00dev, RT5390))
3185 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3187 if (rt2800_is_305x_soc(rt2x00dev))
3188 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3189 else if (rt2x00_rt(rt2x00dev, RT5390))
3190 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3192 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3194 if (rt2x00_rt(rt2x00dev, RT5390))
3195 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3197 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3199 if (rt2x00_rt(rt2x00dev, RT5390))
3200 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3202 if (rt2x00_rt(rt2x00dev, RT3071) ||
3203 rt2x00_rt(rt2x00dev, RT3090) ||
3204 rt2x00_rt(rt2x00dev, RT3390) ||
3205 rt2x00_rt(rt2x00dev, RT3572) ||
3206 rt2x00_rt(rt2x00dev, RT5390)) {
3207 rt2800_bbp_read(rt2x00dev, 138, &value);
3209 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3210 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3212 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3215 rt2800_bbp_write(rt2x00dev, 138, value);
3218 if (rt2x00_rt(rt2x00dev, RT5390)) {
3221 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3222 div_mode = rt2x00_get_field16(eeprom,
3223 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3224 ant = (div_mode == 3) ? 1 : 0;
3226 /* check if this is a Bluetooth combo card */
3227 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3230 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
3231 rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3232 rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3233 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, 0);
3234 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT6, 0);
3236 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, 1);
3238 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT6, 1);
3239 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3242 rt2800_bbp_read(rt2x00dev, 152, &value);
3244 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3246 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3247 rt2800_bbp_write(rt2x00dev, 152, value);
3249 /* Init frequency calibration */
3250 rt2800_bbp_write(rt2x00dev, 142, 1);
3251 rt2800_bbp_write(rt2x00dev, 143, 57);
3254 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3255 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3257 if (eeprom != 0xffff && eeprom != 0x0000) {
3258 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3259 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3260 rt2800_bbp_write(rt2x00dev, reg_id, value);
3267 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3268 bool bw40, u8 rfcsr24, u8 filter_target)
3277 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3279 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3280 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3281 rt2800_bbp_write(rt2x00dev, 4, bbp);
3283 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3284 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3285 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3287 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3288 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3289 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3292 * Set power & frequency of passband test tone
3294 rt2800_bbp_write(rt2x00dev, 24, 0);
3296 for (i = 0; i < 100; i++) {
3297 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3300 rt2800_bbp_read(rt2x00dev, 55, &passband);
3306 * Set power & frequency of stopband test tone
3308 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3310 for (i = 0; i < 100; i++) {
3311 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3314 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3316 if ((passband - stopband) <= filter_target) {
3318 overtuned += ((passband - stopband) == filter_target);
3322 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3325 rfcsr24 -= !!overtuned;
3327 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3331 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3333 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3339 if (!rt2x00_rt(rt2x00dev, RT3070) &&
3340 !rt2x00_rt(rt2x00dev, RT3071) &&
3341 !rt2x00_rt(rt2x00dev, RT3090) &&
3342 !rt2x00_rt(rt2x00dev, RT3390) &&
3343 !rt2x00_rt(rt2x00dev, RT3572) &&
3344 !rt2x00_rt(rt2x00dev, RT5390) &&
3345 !rt2800_is_305x_soc(rt2x00dev))
3349 * Init RF calibration.
3351 if (rt2x00_rt(rt2x00dev, RT5390)) {
3352 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3353 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3354 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3356 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3357 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3359 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3360 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3361 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3363 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3364 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3367 if (rt2x00_rt(rt2x00dev, RT3070) ||
3368 rt2x00_rt(rt2x00dev, RT3071) ||
3369 rt2x00_rt(rt2x00dev, RT3090)) {
3370 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3371 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3372 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3373 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3374 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3375 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3376 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3377 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3378 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3379 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3380 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3381 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3382 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3383 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3384 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3385 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3386 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3387 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3388 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3389 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3390 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3391 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3392 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3393 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3394 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3395 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3396 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3397 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3398 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3399 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3400 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3401 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3402 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3403 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3404 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3405 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3406 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3407 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3408 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3409 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3410 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3411 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3412 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3413 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3414 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3415 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3416 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3417 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3418 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3419 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3420 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3421 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3422 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3423 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3424 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3425 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3426 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3427 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3428 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3429 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3430 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3431 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3432 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3433 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3434 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3435 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3436 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3437 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3438 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3439 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3440 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3441 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3442 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3443 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3444 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3445 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3446 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3447 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3448 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3449 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3450 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3451 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3452 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3453 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3454 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3455 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3456 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3457 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3458 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3459 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3460 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3461 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3462 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3463 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3464 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3465 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3466 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3467 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3468 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3469 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3470 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3471 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3472 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3473 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3474 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3475 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3476 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3477 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3478 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3479 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3480 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3481 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3482 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3483 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3484 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3485 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3486 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3488 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3489 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3490 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3491 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3492 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3493 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3494 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3496 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3497 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3498 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3499 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3500 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3501 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3502 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3503 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3504 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3505 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3506 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3508 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3509 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3510 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3511 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3512 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3513 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3514 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3516 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3517 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3518 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3519 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3520 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3522 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3523 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3524 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3525 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3526 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3527 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3528 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3529 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3530 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3531 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3533 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3534 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3536 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3537 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3538 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3539 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3540 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3541 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3542 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3543 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3545 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3546 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3547 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3548 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3550 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3551 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3552 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3554 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3555 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3556 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3557 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3558 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3559 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3560 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3562 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3563 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3564 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3566 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3567 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3568 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3571 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3572 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
3573 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
3574 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3575 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3576 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3577 rt2x00_rt(rt2x00dev, RT3090)) {
3578 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3580 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3581 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3582 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3584 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
3585 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
3586 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3587 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3588 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3589 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3590 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3592 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3594 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3596 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
3597 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
3598 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3599 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3600 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
3601 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
3602 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3603 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3604 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3605 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3606 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3608 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
3609 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3610 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
3611 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3613 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
3614 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
3615 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3619 * Set RX Filter calibration for 20MHz and 40MHz
3621 if (rt2x00_rt(rt2x00dev, RT3070)) {
3622 drv_data->calibration_bw20 =
3623 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3624 drv_data->calibration_bw40 =
3625 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3626 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3627 rt2x00_rt(rt2x00dev, RT3090) ||
3628 rt2x00_rt(rt2x00dev, RT3390) ||
3629 rt2x00_rt(rt2x00dev, RT3572)) {
3630 drv_data->calibration_bw20 =
3631 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3632 drv_data->calibration_bw40 =
3633 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3637 * Save BBP 25 & 26 values for later use in channel switching
3639 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
3640 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
3642 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3644 * Set back to initial state
3646 rt2800_bbp_write(rt2x00dev, 24, 0);
3648 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3649 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3650 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3653 * Set BBP back to BW20
3655 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3656 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3657 rt2800_bbp_write(rt2x00dev, 4, bbp);
3660 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3661 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3662 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3663 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3664 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3666 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®);
3667 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1);
3668 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3670 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3671 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3672 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3673 if (rt2x00_rt(rt2x00dev, RT3070) ||
3674 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3675 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3676 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3677 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3678 &rt2x00dev->cap_flags))
3679 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3681 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3682 drv_data->txmixer_gain_24g);
3683 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3686 if (rt2x00_rt(rt2x00dev, RT3090)) {
3687 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3689 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
3690 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3691 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3692 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3693 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3694 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3696 rt2800_bbp_write(rt2x00dev, 138, bbp);
3699 if (rt2x00_rt(rt2x00dev, RT3071) ||
3700 rt2x00_rt(rt2x00dev, RT3090) ||
3701 rt2x00_rt(rt2x00dev, RT3390)) {
3702 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3703 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3704 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3705 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3706 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3707 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3708 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3710 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3711 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3712 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3714 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3715 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3716 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3718 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3719 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3720 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3723 if (rt2x00_rt(rt2x00dev, RT3070)) {
3724 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3725 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3726 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3728 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3729 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3730 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3731 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3732 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3735 if (rt2x00_rt(rt2x00dev, RT5390)) {
3736 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3737 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3738 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3740 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3741 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3742 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3744 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3745 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3746 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3752 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3758 * Initialize all registers.
3760 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3761 rt2800_init_registers(rt2x00dev) ||
3762 rt2800_init_bbp(rt2x00dev) ||
3763 rt2800_init_rfcsr(rt2x00dev)))
3767 * Send signal to firmware during boot time.
3769 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3771 if (rt2x00_is_usb(rt2x00dev) &&
3772 (rt2x00_rt(rt2x00dev, RT3070) ||
3773 rt2x00_rt(rt2x00dev, RT3071) ||
3774 rt2x00_rt(rt2x00dev, RT3572))) {
3776 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3783 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
3784 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
3785 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
3786 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3790 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
3791 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3792 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3793 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3794 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3795 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3797 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
3798 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
3799 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
3800 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3803 * Initialize LED control
3805 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3806 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3807 word & 0xff, (word >> 8) & 0xff);
3809 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3810 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3811 word & 0xff, (word >> 8) & 0xff);
3813 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3814 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3815 word & 0xff, (word >> 8) & 0xff);
3819 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3821 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3825 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
3826 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3827 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3828 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3830 /* Wait for DMA, ignore error */
3831 rt2800_wait_wpdma_ready(rt2x00dev);
3833 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
3834 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0);
3835 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
3836 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3838 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3840 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3844 rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®);
3846 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3848 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3850 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3854 mutex_lock(&rt2x00dev->csr_mutex);
3856 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, ®);
3857 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i);
3858 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0);
3859 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1);
3860 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3862 /* Wait until the EEPROM has been loaded */
3863 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®);
3865 /* Apparently the data is read from end to start */
3866 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, ®);
3867 /* The returned value is in CPU order, but eeprom is le */
3868 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
3869 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, ®);
3870 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
3871 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, ®);
3872 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
3873 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, ®);
3874 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
3876 mutex_unlock(&rt2x00dev->csr_mutex);
3879 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3883 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3884 rt2800_efuse_read(rt2x00dev, i);
3886 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3888 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3890 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3893 u8 default_lna_gain;
3896 * Start validation of the data that has been read.
3898 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3899 if (!is_valid_ether_addr(mac)) {
3900 random_ether_addr(mac);
3901 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3904 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3905 if (word == 0xffff) {
3906 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3907 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3908 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3909 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3910 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3911 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3912 rt2x00_rt(rt2x00dev, RT2872)) {
3914 * There is a max of 2 RX streams for RT28x0 series
3916 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3917 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3918 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3921 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3922 if (word == 0xffff) {
3923 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3924 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3925 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3926 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3927 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3928 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3929 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3930 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3931 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3932 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3933 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3934 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3935 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3936 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3937 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3938 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3939 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3942 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3943 if ((word & 0x00ff) == 0x00ff) {
3944 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3945 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3946 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3948 if ((word & 0xff00) == 0xff00) {
3949 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3950 LED_MODE_TXRX_ACTIVITY);
3951 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3952 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3953 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3954 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3955 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3956 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3960 * During the LNA validation we are going to use
3961 * lna0 as correct value. Note that EEPROM_LNA
3962 * is never validated.
3964 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3965 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3967 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3968 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3969 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3970 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3971 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3972 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3974 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
3975 if ((word & 0x00ff) != 0x00ff) {
3976 drv_data->txmixer_gain_24g =
3977 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
3979 drv_data->txmixer_gain_24g = 0;
3982 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3983 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3984 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3985 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3986 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3987 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3989 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3991 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
3992 if ((word & 0x00ff) != 0x00ff) {
3993 drv_data->txmixer_gain_5g =
3994 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
3996 drv_data->txmixer_gain_5g = 0;
3999 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4000 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4001 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4002 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4003 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4004 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4006 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4007 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4008 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4009 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4010 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4011 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4013 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4017 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4019 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4026 * Read EEPROM word for configuration.
4028 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4031 * Identify RF chipset by EEPROM value
4032 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4033 * RT53xx: defined in "EEPROM_CHIP_ID" field
4035 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
4036 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
4037 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4039 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4041 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4042 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4044 switch (rt2x00dev->chip.rt) {
4056 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
4060 switch (rt2x00dev->chip.rf) {
4075 ERROR(rt2x00dev, "Invalid RF chipset 0x%x detected.\n",
4076 rt2x00dev->chip.rf);
4081 * Identify default antenna configuration.
4083 rt2x00dev->default_ant.tx_chain_num =
4084 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
4085 rt2x00dev->default_ant.rx_chain_num =
4086 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
4088 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4090 if (rt2x00_rt(rt2x00dev, RT3070) ||
4091 rt2x00_rt(rt2x00dev, RT3090) ||
4092 rt2x00_rt(rt2x00dev, RT3390)) {
4093 value = rt2x00_get_field16(eeprom,
4094 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4099 rt2x00dev->default_ant.tx = ANTENNA_A;
4100 rt2x00dev->default_ant.rx = ANTENNA_A;
4103 rt2x00dev->default_ant.tx = ANTENNA_A;
4104 rt2x00dev->default_ant.rx = ANTENNA_B;
4108 rt2x00dev->default_ant.tx = ANTENNA_A;
4109 rt2x00dev->default_ant.rx = ANTENNA_A;
4113 * Determine external LNA informations.
4115 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4116 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4117 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4118 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4121 * Detect if this device has an hardware controlled radio.
4123 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4124 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4127 * Detect if this device has Bluetooth co-existence.
4129 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4130 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4133 * Read frequency offset and RF programming sequence.
4135 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4136 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4139 * Store led settings, for correct led behaviour.
4141 #ifdef CONFIG_RT2X00_LIB_LEDS
4142 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4143 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4144 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4146 rt2x00dev->led_mcu_reg = eeprom;
4147 #endif /* CONFIG_RT2X00_LIB_LEDS */
4150 * Check if support EIRP tx power limit feature.
4152 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4154 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4155 EIRP_MAX_TX_POWER_LIMIT)
4156 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4160 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4163 * RF value list for rt28xx
4164 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4166 static const struct rf_channel rf_vals[] = {
4167 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4168 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4169 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4170 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4171 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4172 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4173 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4174 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4175 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4176 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4177 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4178 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4179 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4180 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4182 /* 802.11 UNI / HyperLan 2 */
4183 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4184 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4185 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4186 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4187 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4188 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4189 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4190 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4191 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4192 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4193 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4194 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4196 /* 802.11 HyperLan 2 */
4197 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4198 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4199 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4200 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4201 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4202 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4203 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4204 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4205 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4206 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4207 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4208 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4209 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4210 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4211 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4212 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4215 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4216 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4217 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4218 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4219 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4220 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4221 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4222 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4223 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4224 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4225 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4228 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4229 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4230 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4231 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4232 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4233 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4234 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4238 * RF value list for rt3xxx
4239 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4241 static const struct rf_channel rf_vals_3x[] = {
4257 /* 802.11 UNI / HyperLan 2 */
4271 /* 802.11 HyperLan 2 */
4303 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4305 struct hw_mode_spec *spec = &rt2x00dev->spec;
4306 struct channel_info *info;
4307 char *default_power1;
4308 char *default_power2;
4313 * Disable powersaving as default on PCI devices.
4315 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4316 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4319 * Initialize all hw fields.
4321 rt2x00dev->hw->flags =
4322 IEEE80211_HW_SIGNAL_DBM |
4323 IEEE80211_HW_SUPPORTS_PS |
4324 IEEE80211_HW_PS_NULLFUNC_STACK |
4325 IEEE80211_HW_AMPDU_AGGREGATION;
4327 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4328 * unless we are capable of sending the buffered frames out after the
4329 * DTIM transmission using rt2x00lib_beacondone. This will send out
4330 * multicast and broadcast traffic immediately instead of buffering it
4331 * infinitly and thus dropping it after some time.
4333 if (!rt2x00_is_usb(rt2x00dev))
4334 rt2x00dev->hw->flags |=
4335 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4337 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4338 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4339 rt2x00_eeprom_addr(rt2x00dev,
4340 EEPROM_MAC_ADDR_0));
4343 * As rt2800 has a global fallback table we cannot specify
4344 * more then one tx rate per frame but since the hw will
4345 * try several rates (based on the fallback table) we should
4346 * initialize max_report_rates to the maximum number of rates
4347 * we are going to try. Otherwise mac80211 will truncate our
4348 * reported tx rates and the rc algortihm will end up with
4351 rt2x00dev->hw->max_rates = 1;
4352 rt2x00dev->hw->max_report_rates = 7;
4353 rt2x00dev->hw->max_rate_tries = 1;
4355 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4358 * Initialize hw_mode information.
4360 spec->supported_bands = SUPPORT_BAND_2GHZ;
4361 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4363 if (rt2x00_rf(rt2x00dev, RF2820) ||
4364 rt2x00_rf(rt2x00dev, RF2720)) {
4365 spec->num_channels = 14;
4366 spec->channels = rf_vals;
4367 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4368 rt2x00_rf(rt2x00dev, RF2750)) {
4369 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4370 spec->num_channels = ARRAY_SIZE(rf_vals);
4371 spec->channels = rf_vals;
4372 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4373 rt2x00_rf(rt2x00dev, RF2020) ||
4374 rt2x00_rf(rt2x00dev, RF3021) ||
4375 rt2x00_rf(rt2x00dev, RF3022) ||
4376 rt2x00_rf(rt2x00dev, RF3320) ||
4377 rt2x00_rf(rt2x00dev, RF5370) ||
4378 rt2x00_rf(rt2x00dev, RF5390)) {
4379 spec->num_channels = 14;
4380 spec->channels = rf_vals_3x;
4381 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4382 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4383 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4384 spec->channels = rf_vals_3x;
4388 * Initialize HT information.
4390 if (!rt2x00_rf(rt2x00dev, RF2020))
4391 spec->ht.ht_supported = true;
4393 spec->ht.ht_supported = false;
4396 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4397 IEEE80211_HT_CAP_GRN_FLD |
4398 IEEE80211_HT_CAP_SGI_20 |
4399 IEEE80211_HT_CAP_SGI_40;
4401 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4402 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4405 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4406 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4408 spec->ht.ampdu_factor = 3;
4409 spec->ht.ampdu_density = 4;
4410 spec->ht.mcs.tx_params =
4411 IEEE80211_HT_MCS_TX_DEFINED |
4412 IEEE80211_HT_MCS_TX_RX_DIFF |
4413 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4414 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4416 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4418 spec->ht.mcs.rx_mask[2] = 0xff;
4420 spec->ht.mcs.rx_mask[1] = 0xff;
4422 spec->ht.mcs.rx_mask[0] = 0xff;
4423 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4428 * Create channel information array
4430 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4434 spec->channels_info = info;
4436 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4437 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4439 for (i = 0; i < 14; i++) {
4440 info[i].default_power1 = default_power1[i];
4441 info[i].default_power2 = default_power2[i];
4444 if (spec->num_channels > 14) {
4445 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4446 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4448 for (i = 14; i < spec->num_channels; i++) {
4449 info[i].default_power1 = default_power1[i];
4450 info[i].default_power2 = default_power2[i];
4456 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4459 * IEEE80211 stack callback functions.
4461 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4464 struct rt2x00_dev *rt2x00dev = hw->priv;
4465 struct mac_iveiv_entry iveiv_entry;
4468 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4469 rt2800_register_multiread(rt2x00dev, offset,
4470 &iveiv_entry, sizeof(iveiv_entry));
4472 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4473 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4475 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4477 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4479 struct rt2x00_dev *rt2x00dev = hw->priv;
4481 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4483 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
4484 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
4485 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4487 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
4488 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
4489 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4491 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
4492 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4493 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4495 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
4496 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
4497 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4499 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
4500 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
4501 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4503 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
4504 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
4505 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4507 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
4508 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
4509 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4513 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4515 int rt2800_conf_tx(struct ieee80211_hw *hw,
4516 struct ieee80211_vif *vif, u16 queue_idx,
4517 const struct ieee80211_tx_queue_params *params)
4519 struct rt2x00_dev *rt2x00dev = hw->priv;
4520 struct data_queue *queue;
4521 struct rt2x00_field32 field;
4527 * First pass the configuration through rt2x00lib, that will
4528 * update the queue settings and validate the input. After that
4529 * we are free to update the registers based on the value
4530 * in the queue parameter.
4532 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
4537 * We only need to perform additional register initialization
4543 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4545 /* Update WMM TXOP register */
4546 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4547 field.bit_offset = (queue_idx & 1) * 16;
4548 field.bit_mask = 0xffff << field.bit_offset;
4550 rt2800_register_read(rt2x00dev, offset, ®);
4551 rt2x00_set_field32(®, field, queue->txop);
4552 rt2800_register_write(rt2x00dev, offset, reg);
4554 /* Update WMM registers */
4555 field.bit_offset = queue_idx * 4;
4556 field.bit_mask = 0xf << field.bit_offset;
4558 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®);
4559 rt2x00_set_field32(®, field, queue->aifs);
4560 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4562 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®);
4563 rt2x00_set_field32(®, field, queue->cw_min);
4564 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4566 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®);
4567 rt2x00_set_field32(®, field, queue->cw_max);
4568 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4570 /* Update EDCA registers */
4571 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4573 rt2800_register_read(rt2x00dev, offset, ®);
4574 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
4575 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
4576 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4577 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4578 rt2800_register_write(rt2x00dev, offset, reg);
4582 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4584 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
4586 struct rt2x00_dev *rt2x00dev = hw->priv;
4590 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®);
4591 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4592 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®);
4593 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4597 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4599 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4600 enum ieee80211_ampdu_mlme_action action,
4601 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4604 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
4608 * Don't allow aggregation for stations the hardware isn't aware
4609 * of because tx status reports for frames to an unknown station
4610 * always contain wcid=255 and thus we can't distinguish between
4611 * multiple stations which leads to unwanted situations when the
4612 * hw reorders frames due to aggregation.
4614 if (sta_priv->wcid < 0)
4618 case IEEE80211_AMPDU_RX_START:
4619 case IEEE80211_AMPDU_RX_STOP:
4621 * The hw itself takes care of setting up BlockAck mechanisms.
4622 * So, we only have to allow mac80211 to nagotiate a BlockAck
4623 * agreement. Once that is done, the hw will BlockAck incoming
4624 * AMPDUs without further setup.
4627 case IEEE80211_AMPDU_TX_START:
4628 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4630 case IEEE80211_AMPDU_TX_STOP:
4631 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4633 case IEEE80211_AMPDU_TX_OPERATIONAL:
4636 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4641 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4643 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4644 struct survey_info *survey)
4646 struct rt2x00_dev *rt2x00dev = hw->priv;
4647 struct ieee80211_conf *conf = &hw->conf;
4648 u32 idle, busy, busy_ext;
4653 survey->channel = conf->channel;
4655 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4656 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4657 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4660 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4661 SURVEY_INFO_CHANNEL_TIME_BUSY |
4662 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4664 survey->channel_time = (idle + busy) / 1000;
4665 survey->channel_time_busy = busy / 1000;
4666 survey->channel_time_ext_busy = busy_ext / 1000;
4669 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4670 survey->filled |= SURVEY_INFO_IN_USE;
4675 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4677 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4678 MODULE_VERSION(DRV_VERSION);
4679 MODULE_DESCRIPTION("Ralink RT2800 library");
4680 MODULE_LICENSE("GPL");