drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 225         [EEPROM_CHIP_ID]                = 0x0000,
 226         [EEPROM_VERSION]                = 0x0001,
 227         [EEPROM_MAC_ADDR_0]             = 0x0002,
 228         [EEPROM_MAC_ADDR_1]             = 0x0003,
 229         [EEPROM_MAC_ADDR_2]             = 0x0004,
 230         [EEPROM_NIC_CONF0]              = 0x001a,
 231         [EEPROM_NIC_CONF1]              = 0x001b,
 232         [EEPROM_FREQ]                   = 0x001d,
 233         [EEPROM_LED_AG_CONF]            = 0x001e,
 234         [EEPROM_LED_ACT_CONF]           = 0x001f,
 235         [EEPROM_LED_POLARITY]           = 0x0020,
 236         [EEPROM_NIC_CONF2]              = 0x0021,
 237         [EEPROM_LNA]                    = 0x0022,
 238         [EEPROM_RSSI_BG]                = 0x0023,
 239         [EEPROM_RSSI_BG2]               = 0x0024,
 240         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 241         [EEPROM_RSSI_A]                 = 0x0025,
 242         [EEPROM_RSSI_A2]                = 0x0026,
 243         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 244         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 245         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 246         [EEPROM_TXPOWER_BG1]            = 0x0029,
 247         [EEPROM_TXPOWER_BG2]            = 0x0030,
 248         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 249         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 250         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 251         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 252         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 253         [EEPROM_TXPOWER_A1]             = 0x003c,
 254         [EEPROM_TXPOWER_A2]             = 0x0053,
 255         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 256         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 257         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 258         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 259         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 260         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 261         [EEPROM_BBP_START]              = 0x0078,
 262 };
 263
 264 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 265         [EEPROM_CHIP_ID]                = 0x0000,
 266         [EEPROM_VERSION]                = 0x0001,
 267         [EEPROM_MAC_ADDR_0]             = 0x0002,
 268         [EEPROM_MAC_ADDR_1]             = 0x0003,
 269         [EEPROM_MAC_ADDR_2]             = 0x0004,
 270         [EEPROM_NIC_CONF0]              = 0x001a,
 271         [EEPROM_NIC_CONF1]              = 0x001b,
 272         [EEPROM_NIC_CONF2]              = 0x001c,
 273         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 274         [EEPROM_FREQ]                   = 0x0022,
 275         [EEPROM_LED_AG_CONF]            = 0x0023,
 276         [EEPROM_LED_ACT_CONF]           = 0x0024,
 277         [EEPROM_LED_POLARITY]           = 0x0025,
 278         [EEPROM_LNA]                    = 0x0026,
 279         [EEPROM_EXT_LNA2]               = 0x0027,
 280         [EEPROM_RSSI_BG]                = 0x0028,
 281         [EEPROM_TXPOWER_DELTA]          = 0x0028, /* Overlaps with RSSI_BG */
 282         [EEPROM_RSSI_BG2]               = 0x0029,
 283         [EEPROM_TXMIXER_GAIN_BG]        = 0x0029, /* Overlaps with RSSI_BG2 */
 284         [EEPROM_RSSI_A]                 = 0x002a,
 285         [EEPROM_RSSI_A2]                = 0x002b,
 286         [EEPROM_TXMIXER_GAIN_A]         = 0x002b, /* Overlaps with RSSI_A2 */
 287         [EEPROM_TXPOWER_BG1]            = 0x0030,
 288         [EEPROM_TXPOWER_BG2]            = 0x0037,
 289         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 290         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 291         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 292         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 293         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 294         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 295         [EEPROM_TXPOWER_A1]             = 0x004b,
 296         [EEPROM_TXPOWER_A2]             = 0x0065,
 297         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 298         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 299         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 300         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 301         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 302         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 303         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 304 };
 305
 306 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 307                                              const enum rt2800_eeprom_word word)
 308 {
 309         const unsigned int *map;
 310         unsigned int index;
 311
 312         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 313                       "%s: invalid EEPROM word %d\n",
 314                       wiphy_name(rt2x00dev->hw->wiphy), word))
 315                 return 0;
 316
 317         if (rt2x00_rt(rt2x00dev, RT3593))
 318                 map = rt2800_eeprom_map_ext;
 319         else
 320                 map = rt2800_eeprom_map;
 321
 322         index = map[word];
 323
 324         /* Index 0 is valid only for EEPROM_CHIP_ID.
 325          * Otherwise it means that the offset of the
 326          * given word is not initialized in the map,
 327          * or that the field is not usable on the
 328          * actual chipset.
 329          */
 330         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 331                   "%s: invalid access of EEPROM word %d\n",
 332                   wiphy_name(rt2x00dev->hw->wiphy), word);
 333
 334         return index;
 335 }
 336
 337 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 338                                 const enum rt2800_eeprom_word word)
 339 {
 340         unsigned int index;
 341
 342         index = rt2800_eeprom_word_index(rt2x00dev, word);
 343         return rt2x00_eeprom_addr(rt2x00dev, index);
 344 }
 345
 346 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 347                                const enum rt2800_eeprom_word word, u16 *data)
 348 {
 349         unsigned int index;
 350
 351         index = rt2800_eeprom_word_index(rt2x00dev, word);
 352         rt2x00_eeprom_read(rt2x00dev, index, data);
 353 }
 354
 355 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 356                                 const enum rt2800_eeprom_word word, u16 data)
 357 {
 358         unsigned int index;
 359
 360         index = rt2800_eeprom_word_index(rt2x00dev, word);
 361         rt2x00_eeprom_write(rt2x00dev, index, data);
 362 }
 363
 364 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 365                                           const enum rt2800_eeprom_word array,
 366                                           unsigned int offset,
 367                                           u16 *data)
 368 {
 369         unsigned int index;
 370
 371         index = rt2800_eeprom_word_index(rt2x00dev, array);
 372         rt2x00_eeprom_read(rt2x00dev, index + offset, data);
 373 }
 374
 375 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 376 {
 377         u32 reg;
 378         int i, count;
 379
 380         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 381         if (rt2x00_get_field32(reg, WLAN_EN))
 382                 return 0;
 383
 384         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 385         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 386         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 387         rt2x00_set_field32(&reg, WLAN_EN, 1);
 388         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 389
 390         udelay(REGISTER_BUSY_DELAY);
 391
 392         count = 0;
 393         do {
 394                 /*
 395                  * Check PLL_LD & XTAL_RDY.
 396                  */
 397                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 398                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 399                         if (rt2x00_get_field32(reg, PLL_LD) &&
 400                             rt2x00_get_field32(reg, XTAL_RDY))
 401                                 break;
 402                         udelay(REGISTER_BUSY_DELAY);
 403                 }
 404
 405                 if (i >= REGISTER_BUSY_COUNT) {
 406
 407                         if (count >= 10)
 408                                 return -EIO;
 409
 410                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 411                         udelay(REGISTER_BUSY_DELAY);
 412                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 413                         udelay(REGISTER_BUSY_DELAY);
 414                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 415                         udelay(REGISTER_BUSY_DELAY);
 416                         count++;
 417                 } else {
 418                         count = 0;
 419                 }
 420
 421                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 422                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 423                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 424                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 425                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 426                 udelay(10);
 427                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 428                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 429                 udelay(10);
 430                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 431         } while (count != 0);
 432
 433         return 0;
 434 }
 435
 436 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 437                         const u8 command, const u8 token,
 438                         const u8 arg0, const u8 arg1)
 439 {
 440         u32 reg;
 441
 442         /*
 443          * SOC devices don't support MCU requests.
 444          */
 445         if (rt2x00_is_soc(rt2x00dev))
 446                 return;
 447
 448         mutex_lock(&rt2x00dev->csr_mutex);
 449
 450         /*
 451          * Wait until the MCU becomes available, afterwards we
 452          * can safely write the new data into the register.
 453          */
 454         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 455                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 456                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 457                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 458                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 459                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 460
 461                 reg = 0;
 462                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 463                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 464         }
 465
 466         mutex_unlock(&rt2x00dev->csr_mutex);
 467 }
 468 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 469
 470 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 471 {
 472         unsigned int i = 0;
 473         u32 reg;
 474
 475         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 476                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 477                 if (reg && reg != ~0)
 478                         return 0;
 479                 msleep(1);
 480         }
 481
 482         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 483         return -EBUSY;
 484 }
 485 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 486
 487 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 488 {
 489         unsigned int i;
 490         u32 reg;
 491
 492         /*
 493          * Some devices are really slow to respond here. Wait a whole second
 494          * before timing out.
 495          */
 496         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 497                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 498                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 499                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 500                         return 0;
 501
 502                 msleep(10);
 503         }
 504
 505         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 506         return -EACCES;
 507 }
 508 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 509
 510 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 511 {
 512         u32 reg;
 513
 514         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 515         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 516         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 517         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 518         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 519         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 520         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 521 }
 522 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 523
 524 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 525                                unsigned short *txwi_size,
 526                                unsigned short *rxwi_size)
 527 {
 528         switch (rt2x00dev->chip.rt) {
 529         case RT3593:
 530                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 531                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 532                 break;
 533
 534         case RT5592:
 535                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 536                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 537                 break;
 538
 539         default:
 540                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 541                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 542                 break;
 543         }
 544 }
 545 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 546
 547 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 548 {
 549         u16 fw_crc;
 550         u16 crc;
 551
 552         /*
 553          * The last 2 bytes in the firmware array are the crc checksum itself,
 554          * this means that we should never pass those 2 bytes to the crc
 555          * algorithm.
 556          */
 557         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 558
 559         /*
 560          * Use the crc ccitt algorithm.
 561          * This will return the same value as the legacy driver which
 562          * used bit ordering reversion on the both the firmware bytes
 563          * before input input as well as on the final output.
 564          * Obviously using crc ccitt directly is much more efficient.
 565          */
 566         crc = crc_ccitt(~0, data, len - 2);
 567
 568         /*
 569          * There is a small difference between the crc-itu-t + bitrev and
 570          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 571          * will be swapped, use swab16 to convert the crc to the correct
 572          * value.
 573          */
 574         crc = swab16(crc);
 575
 576         return fw_crc == crc;
 577 }
 578
 579 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 580                           const u8 *data, const size_t len)
 581 {
 582         size_t offset = 0;
 583         size_t fw_len;
 584         bool multiple;
 585
 586         /*
 587          * PCI(e) & SOC devices require firmware with a length
 588          * of 8kb. USB devices require firmware files with a length
 589          * of 4kb. Certain USB chipsets however require different firmware,
 590          * which Ralink only provides attached to the original firmware
 591          * file. Thus for USB devices, firmware files have a length
 592          * which is a multiple of 4kb. The firmware for rt3290 chip also
 593          * have a length which is a multiple of 4kb.
 594          */
 595         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 596                 fw_len = 4096;
 597         else
 598                 fw_len = 8192;
 599
 600         multiple = true;
 601         /*
 602          * Validate the firmware length
 603          */
 604         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 605                 return FW_BAD_LENGTH;
 606
 607         /*
 608          * Check if the chipset requires one of the upper parts
 609          * of the firmware.
 610          */
 611         if (rt2x00_is_usb(rt2x00dev) &&
 612             !rt2x00_rt(rt2x00dev, RT2860) &&
 613             !rt2x00_rt(rt2x00dev, RT2872) &&
 614             !rt2x00_rt(rt2x00dev, RT3070) &&
 615             ((len / fw_len) == 1))
 616                 return FW_BAD_VERSION;
 617
 618         /*
 619          * 8kb firmware files must be checked as if it were
 620          * 2 separate firmware files.
 621          */
 622         while (offset < len) {
 623                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 624                         return FW_BAD_CRC;
 625
 626                 offset += fw_len;
 627         }
 628
 629         return FW_OK;
 630 }
 631 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 632
 633 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 634                          const u8 *data, const size_t len)
 635 {
 636         unsigned int i;
 637         u32 reg;
 638         int retval;
 639
 640         if (rt2x00_rt(rt2x00dev, RT3290)) {
 641                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 642                 if (retval)
 643                         return -EBUSY;
 644         }
 645
 646         /*
 647          * If driver doesn't wake up firmware here,
 648          * rt2800_load_firmware will hang forever when interface is up again.
 649          */
 650         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 651
 652         /*
 653          * Wait for stable hardware.
 654          */
 655         if (rt2800_wait_csr_ready(rt2x00dev))
 656                 return -EBUSY;
 657
 658         if (rt2x00_is_pci(rt2x00dev)) {
 659                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 660                     rt2x00_rt(rt2x00dev, RT3572) ||
 661                     rt2x00_rt(rt2x00dev, RT5390) ||
 662                     rt2x00_rt(rt2x00dev, RT5392)) {
 663                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 664                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 665                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 666                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 667                 }
 668                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 669         }
 670
 671         rt2800_disable_wpdma(rt2x00dev);
 672
 673         /*
 674          * Write firmware to the device.
 675          */
 676         rt2800_drv_write_firmware(rt2x00dev, data, len);
 677
 678         /*
 679          * Wait for device to stabilize.
 680          */
 681         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 682                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 683                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 684                         break;
 685                 msleep(1);
 686         }
 687
 688         if (i == REGISTER_BUSY_COUNT) {
 689                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 690                 return -EBUSY;
 691         }
 692
 693         /*
 694          * Disable DMA, will be reenabled later when enabling
 695          * the radio.
 696          */
 697         rt2800_disable_wpdma(rt2x00dev);
 698
 699         /*
 700          * Initialize firmware.
 701          */
 702         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 703         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 704         if (rt2x00_is_usb(rt2x00dev)) {
 705                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 706                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 707         }
 708         msleep(1);
 709
 710         return 0;
 711 }
 712 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 713
 714 void rt2800_write_tx_data(struct queue_entry *entry,
 715                           struct txentry_desc *txdesc)
 716 {
 717         __le32 *txwi = rt2800_drv_get_txwi(entry);
 718         u32 word;
 719         int i;
 720
 721         /*
 722          * Initialize TX Info descriptor
 723          */
 724         rt2x00_desc_read(txwi, 0, &word);
 725         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 726                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 727         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 728                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 729         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 730         rt2x00_set_field32(&word, TXWI_W0_TS,
 731                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 732         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 733                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 734         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 735                            txdesc->u.ht.mpdu_density);
 736         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 737         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 738         rt2x00_set_field32(&word, TXWI_W0_BW,
 739                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 740         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 741                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 742         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 743         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 744         rt2x00_desc_write(txwi, 0, word);
 745
 746         rt2x00_desc_read(txwi, 1, &word);
 747         rt2x00_set_field32(&word, TXWI_W1_ACK,
 748                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 749         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 750                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 751         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 752         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 753                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 754                            txdesc->key_idx : txdesc->u.ht.wcid);
 755         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 756                            txdesc->length);
 757         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 758         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 759         rt2x00_desc_write(txwi, 1, word);
 760
 761         /*
 762          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 763          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 764          * When TXD_W3_WIV is set to 1 it will use the IV data
 765          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 766          * crypto entry in the registers should be used to encrypt the frame.
 767          *
 768          * Nulify all remaining words as well, we don't know how to program them.
 769          */
 770         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 771                 _rt2x00_desc_write(txwi, i, 0);
 772 }
 773 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 774
 775 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 776 {
 777         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 778         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 779         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 780         u16 eeprom;
 781         u8 offset0;
 782         u8 offset1;
 783         u8 offset2;
 784
 785         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 786                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 787                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 788                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 789                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 790                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 791         } else {
 792                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 793                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 794                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 795                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 796                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 797         }
 798
 799         /*
 800          * Convert the value from the descriptor into the RSSI value
 801          * If the value in the descriptor is 0, it is considered invalid
 802          * and the default (extremely low) rssi value is assumed
 803          */
 804         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 805         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 806         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 807
 808         /*
 809          * mac80211 only accepts a single RSSI value. Calculating the
 810          * average doesn't deliver a fair answer either since -60:-60 would
 811          * be considered equally good as -50:-70 while the second is the one
 812          * which gives less energy...
 813          */
 814         rssi0 = max(rssi0, rssi1);
 815         return (int)max(rssi0, rssi2);
 816 }
 817
 818 void rt2800_process_rxwi(struct queue_entry *entry,
 819                          struct rxdone_entry_desc *rxdesc)
 820 {
 821         __le32 *rxwi = (__le32 *) entry->skb->data;
 822         u32 word;
 823
 824         rt2x00_desc_read(rxwi, 0, &word);
 825
 826         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 827         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 828
 829         rt2x00_desc_read(rxwi, 1, &word);
 830
 831         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 832                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 833
 834         if (rt2x00_get_field32(word, RXWI_W1_BW))
 835                 rxdesc->flags |= RX_FLAG_40MHZ;
 836
 837         /*
 838          * Detect RX rate, always use MCS as signal type.
 839          */
 840         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 841         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 842         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 843
 844         /*
 845          * Mask of 0x8 bit to remove the short preamble flag.
 846          */
 847         if (rxdesc->rate_mode == RATE_MODE_CCK)
 848                 rxdesc->signal &= ~0x8;
 849
 850         rt2x00_desc_read(rxwi, 2, &word);
 851
 852         /*
 853          * Convert descriptor AGC value to RSSI value.
 854          */
 855         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 856         /*
 857          * Remove RXWI descriptor from start of the buffer.
 858          */
 859         skb_pull(entry->skb, entry->queue->winfo_size);
 860 }
 861 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 862
 863 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 864 {
 865         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 866         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 867         struct txdone_entry_desc txdesc;
 868         u32 word;
 869         u16 mcs, real_mcs;
 870         int aggr, ampdu;
 871
 872         /*
 873          * Obtain the status about this packet.
 874          */
 875         txdesc.flags = 0;
 876         rt2x00_desc_read(txwi, 0, &word);
 877
 878         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 879         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 880
 881         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 882         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 883
 884         /*
 885          * If a frame was meant to be sent as a single non-aggregated MPDU
 886          * but ended up in an aggregate the used tx rate doesn't correlate
 887          * with the one specified in the TXWI as the whole aggregate is sent
 888          * with the same rate.
 889          *
 890          * For example: two frames are sent to rt2x00, the first one sets
 891          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 892          * and requests MCS15. If the hw aggregates both frames into one
 893          * AMDPU the tx status for both frames will contain MCS7 although
 894          * the frame was sent successfully.
 895          *
 896          * Hence, replace the requested rate with the real tx rate to not
 897          * confuse the rate control algortihm by providing clearly wrong
 898          * data.
 899          */
 900         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 901                 skbdesc->tx_rate_idx = real_mcs;
 902                 mcs = real_mcs;
 903         }
 904
 905         if (aggr == 1 || ampdu == 1)
 906                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 907
 908         /*
 909          * Ralink has a retry mechanism using a global fallback
 910          * table. We setup this fallback table to try the immediate
 911          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 912          * always contains the MCS used for the last transmission, be
 913          * it successful or not.
 914          */
 915         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 916                 /*
 917                  * Transmission succeeded. The number of retries is
 918                  * mcs - real_mcs
 919                  */
 920                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 921                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 922         } else {
 923                 /*
 924                  * Transmission failed. The number of retries is
 925                  * always 7 in this case (for a total number of 8
 926                  * frames sent).
 927                  */
 928                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 929                 txdesc.retry = rt2x00dev->long_retry;
 930         }
 931
 932         /*
 933          * the frame was retried at least once
 934          * -> hw used fallback rates
 935          */
 936         if (txdesc.retry)
 937                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 938
 939         rt2x00lib_txdone(entry, &txdesc);
 940 }
 941 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 942
 943 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 944 {
 945         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 946         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 947         unsigned int beacon_base;
 948         unsigned int padding_len;
 949         u32 orig_reg, reg;
 950         const int txwi_desc_size = entry->queue->winfo_size;
 951
 952         /*
 953          * Disable beaconing while we are reloading the beacon data,
 954          * otherwise we might be sending out invalid data.
 955          */
 956         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 957         orig_reg = reg;
 958         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 959         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 960
 961         /*
 962          * Add space for the TXWI in front of the skb.
 963          */
 964         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
 965
 966         /*
 967          * Register descriptor details in skb frame descriptor.
 968          */
 969         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 970         skbdesc->desc = entry->skb->data;
 971         skbdesc->desc_len = txwi_desc_size;
 972
 973         /*
 974          * Add the TXWI for the beacon to the skb.
 975          */
 976         rt2800_write_tx_data(entry, txdesc);
 977
 978         /*
 979          * Dump beacon to userspace through debugfs.
 980          */
 981         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 982
 983         /*
 984          * Write entire beacon with TXWI and padding to register.
 985          */
 986         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 987         if (padding_len && skb_pad(entry->skb, padding_len)) {
 988                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
 989                 /* skb freed by skb_pad() on failure */
 990                 entry->skb = NULL;
 991                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 992                 return;
 993         }
 994
 995         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 996         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 997                                    entry->skb->len + padding_len);
 998
 999         /*
1000          * Enable beaconing again.
1001          */
1002         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1003         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1004
1005         /*
1006          * Clean up beacon skb.
1007          */
1008         dev_kfree_skb_any(entry->skb);
1009         entry->skb = NULL;
1010 }
1011 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1012
1013 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1014                                                 unsigned int beacon_base)
1015 {
1016         int i;
1017         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1018
1019         /*
1020          * For the Beacon base registers we only need to clear
1021          * the whole TXWI which (when set to 0) will invalidate
1022          * the entire beacon.
1023          */
1024         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1025                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1026 }
1027
1028 void rt2800_clear_beacon(struct queue_entry *entry)
1029 {
1030         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1031         u32 reg;
1032
1033         /*
1034          * Disable beaconing while we are reloading the beacon data,
1035          * otherwise we might be sending out invalid data.
1036          */
1037         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1038         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1039         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1040
1041         /*
1042          * Clear beacon.
1043          */
1044         rt2800_clear_beacon_register(rt2x00dev,
1045                                      HW_BEACON_OFFSET(entry->entry_idx));
1046
1047         /*
1048          * Enabled beaconing again.
1049          */
1050         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1051         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1052 }
1053 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1054
1055 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1056 const struct rt2x00debug rt2800_rt2x00debug = {
1057         .owner  = THIS_MODULE,
1058         .csr    = {
1059                 .read           = rt2800_register_read,
1060                 .write          = rt2800_register_write,
1061                 .flags          = RT2X00DEBUGFS_OFFSET,
1062                 .word_base      = CSR_REG_BASE,
1063                 .word_size      = sizeof(u32),
1064                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1065         },
1066         .eeprom = {
1067                 /* NOTE: The local EEPROM access functions can't
1068                  * be used here, use the generic versions instead.
1069                  */
1070                 .read           = rt2x00_eeprom_read,
1071                 .write          = rt2x00_eeprom_write,
1072                 .word_base      = EEPROM_BASE,
1073                 .word_size      = sizeof(u16),
1074                 .word_count     = EEPROM_SIZE / sizeof(u16),
1075         },
1076         .bbp    = {
1077                 .read           = rt2800_bbp_read,
1078                 .write          = rt2800_bbp_write,
1079                 .word_base      = BBP_BASE,
1080                 .word_size      = sizeof(u8),
1081                 .word_count     = BBP_SIZE / sizeof(u8),
1082         },
1083         .rf     = {
1084                 .read           = rt2x00_rf_read,
1085                 .write          = rt2800_rf_write,
1086                 .word_base      = RF_BASE,
1087                 .word_size      = sizeof(u32),
1088                 .word_count     = RF_SIZE / sizeof(u32),
1089         },
1090         .rfcsr  = {
1091                 .read           = rt2800_rfcsr_read,
1092                 .write          = rt2800_rfcsr_write,
1093                 .word_base      = RFCSR_BASE,
1094                 .word_size      = sizeof(u8),
1095                 .word_count     = RFCSR_SIZE / sizeof(u8),
1096         },
1097 };
1098 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1099 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1100
1101 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1102 {
1103         u32 reg;
1104
1105         if (rt2x00_rt(rt2x00dev, RT3290)) {
1106                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1107                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1108         } else {
1109                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1110                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1111         }
1112 }
1113 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1114
1115 #ifdef CONFIG_RT2X00_LIB_LEDS
1116 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1117                                   enum led_brightness brightness)
1118 {
1119         struct rt2x00_led *led =
1120             container_of(led_cdev, struct rt2x00_led, led_dev);
1121         unsigned int enabled = brightness != LED_OFF;
1122         unsigned int bg_mode =
1123             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1124         unsigned int polarity =
1125                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1126                                    EEPROM_FREQ_LED_POLARITY);
1127         unsigned int ledmode =
1128                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1129                                    EEPROM_FREQ_LED_MODE);
1130         u32 reg;
1131
1132         /* Check for SoC (SOC devices don't support MCU requests) */
1133         if (rt2x00_is_soc(led->rt2x00dev)) {
1134                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1135
1136                 /* Set LED Polarity */
1137                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1138
1139                 /* Set LED Mode */
1140                 if (led->type == LED_TYPE_RADIO) {
1141                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1142                                            enabled ? 3 : 0);
1143                 } else if (led->type == LED_TYPE_ASSOC) {
1144                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1145                                            enabled ? 3 : 0);
1146                 } else if (led->type == LED_TYPE_QUALITY) {
1147                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1148                                            enabled ? 3 : 0);
1149                 }
1150
1151                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1152
1153         } else {
1154                 if (led->type == LED_TYPE_RADIO) {
1155                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1156                                               enabled ? 0x20 : 0);
1157                 } else if (led->type == LED_TYPE_ASSOC) {
1158                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1159                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1160                 } else if (led->type == LED_TYPE_QUALITY) {
1161                         /*
1162                          * The brightness is divided into 6 levels (0 - 5),
1163                          * The specs tell us the following levels:
1164                          *      0, 1 ,3, 7, 15, 31
1165                          * to determine the level in a simple way we can simply
1166                          * work with bitshifting:
1167                          *      (1 << level) - 1
1168                          */
1169                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1170                                               (1 << brightness / (LED_FULL / 6)) - 1,
1171                                               polarity);
1172                 }
1173         }
1174 }
1175
1176 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1177                      struct rt2x00_led *led, enum led_type type)
1178 {
1179         led->rt2x00dev = rt2x00dev;
1180         led->type = type;
1181         led->led_dev.brightness_set = rt2800_brightness_set;
1182         led->flags = LED_INITIALIZED;
1183 }
1184 #endif /* CONFIG_RT2X00_LIB_LEDS */
1185
1186 /*
1187  * Configuration handlers.
1188  */
1189 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1190                                const u8 *address,
1191                                int wcid)
1192 {
1193         struct mac_wcid_entry wcid_entry;
1194         u32 offset;
1195
1196         offset = MAC_WCID_ENTRY(wcid);
1197
1198         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1199         if (address)
1200                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1201
1202         rt2800_register_multiwrite(rt2x00dev, offset,
1203                                       &wcid_entry, sizeof(wcid_entry));
1204 }
1205
1206 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1207 {
1208         u32 offset;
1209         offset = MAC_WCID_ATTR_ENTRY(wcid);
1210         rt2800_register_write(rt2x00dev, offset, 0);
1211 }
1212
1213 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1214                                            int wcid, u32 bssidx)
1215 {
1216         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1217         u32 reg;
1218
1219         /*
1220          * The BSS Idx numbers is split in a main value of 3 bits,
1221          * and a extended field for adding one additional bit to the value.
1222          */
1223         rt2800_register_read(rt2x00dev, offset, &reg);
1224         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1225         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1226                            (bssidx & 0x8) >> 3);
1227         rt2800_register_write(rt2x00dev, offset, reg);
1228 }
1229
1230 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1231                                            struct rt2x00lib_crypto *crypto,
1232                                            struct ieee80211_key_conf *key)
1233 {
1234         struct mac_iveiv_entry iveiv_entry;
1235         u32 offset;
1236         u32 reg;
1237
1238         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1239
1240         if (crypto->cmd == SET_KEY) {
1241                 rt2800_register_read(rt2x00dev, offset, &reg);
1242                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1243                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1244                 /*
1245                  * Both the cipher as the BSS Idx numbers are split in a main
1246                  * value of 3 bits, and a extended field for adding one additional
1247                  * bit to the value.
1248                  */
1249                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1250                                    (crypto->cipher & 0x7));
1251                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1252                                    (crypto->cipher & 0x8) >> 3);
1253                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1254                 rt2800_register_write(rt2x00dev, offset, reg);
1255         } else {
1256                 /* Delete the cipher without touching the bssidx */
1257                 rt2800_register_read(rt2x00dev, offset, &reg);
1258                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1259                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1260                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1261                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1262                 rt2800_register_write(rt2x00dev, offset, reg);
1263         }
1264
1265         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1266
1267         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1268         if ((crypto->cipher == CIPHER_TKIP) ||
1269             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1270             (crypto->cipher == CIPHER_AES))
1271                 iveiv_entry.iv[3] |= 0x20;
1272         iveiv_entry.iv[3] |= key->keyidx << 6;
1273         rt2800_register_multiwrite(rt2x00dev, offset,
1274                                       &iveiv_entry, sizeof(iveiv_entry));
1275 }
1276
1277 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1278                              struct rt2x00lib_crypto *crypto,
1279                              struct ieee80211_key_conf *key)
1280 {
1281         struct hw_key_entry key_entry;
1282         struct rt2x00_field32 field;
1283         u32 offset;
1284         u32 reg;
1285
1286         if (crypto->cmd == SET_KEY) {
1287                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1288
1289                 memcpy(key_entry.key, crypto->key,
1290                        sizeof(key_entry.key));
1291                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1292                        sizeof(key_entry.tx_mic));
1293                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1294                        sizeof(key_entry.rx_mic));
1295
1296                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1297                 rt2800_register_multiwrite(rt2x00dev, offset,
1298                                               &key_entry, sizeof(key_entry));
1299         }
1300
1301         /*
1302          * The cipher types are stored over multiple registers
1303          * starting with SHARED_KEY_MODE_BASE each word will have
1304          * 32 bits and contains the cipher types for 2 bssidx each.
1305          * Using the correct defines correctly will cause overhead,
1306          * so just calculate the correct offset.
1307          */
1308         field.bit_offset = 4 * (key->hw_key_idx % 8);
1309         field.bit_mask = 0x7 << field.bit_offset;
1310
1311         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1312
1313         rt2800_register_read(rt2x00dev, offset, &reg);
1314         rt2x00_set_field32(&reg, field,
1315                            (crypto->cmd == SET_KEY) * crypto->cipher);
1316         rt2800_register_write(rt2x00dev, offset, reg);
1317
1318         /*
1319          * Update WCID information
1320          */
1321         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1322         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1323                                        crypto->bssidx);
1324         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1325
1326         return 0;
1327 }
1328 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1329
1330 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1331 {
1332         struct mac_wcid_entry wcid_entry;
1333         int idx;
1334         u32 offset;
1335
1336         /*
1337          * Search for the first free WCID entry and return the corresponding
1338          * index.
1339          *
1340          * Make sure the WCID starts _after_ the last possible shared key
1341          * entry (>32).
1342          *
1343          * Since parts of the pairwise key table might be shared with
1344          * the beacon frame buffers 6 & 7 we should only write into the
1345          * first 222 entries.
1346          */
1347         for (idx = 33; idx <= 222; idx++) {
1348                 offset = MAC_WCID_ENTRY(idx);
1349                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1350                                           sizeof(wcid_entry));
1351                 if (is_broadcast_ether_addr(wcid_entry.mac))
1352                         return idx;
1353         }
1354
1355         /*
1356          * Use -1 to indicate that we don't have any more space in the WCID
1357          * table.
1358          */
1359         return -1;
1360 }
1361
1362 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1363                                struct rt2x00lib_crypto *crypto,
1364                                struct ieee80211_key_conf *key)
1365 {
1366         struct hw_key_entry key_entry;
1367         u32 offset;
1368
1369         if (crypto->cmd == SET_KEY) {
1370                 /*
1371                  * Allow key configuration only for STAs that are
1372                  * known by the hw.
1373                  */
1374                 if (crypto->wcid < 0)
1375                         return -ENOSPC;
1376                 key->hw_key_idx = crypto->wcid;
1377
1378                 memcpy(key_entry.key, crypto->key,
1379                        sizeof(key_entry.key));
1380                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1381                        sizeof(key_entry.tx_mic));
1382                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1383                        sizeof(key_entry.rx_mic));
1384
1385                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1386                 rt2800_register_multiwrite(rt2x00dev, offset,
1387                                               &key_entry, sizeof(key_entry));
1388         }
1389
1390         /*
1391          * Update WCID information
1392          */
1393         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1394
1395         return 0;
1396 }
1397 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1398
1399 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1400                    struct ieee80211_sta *sta)
1401 {
1402         int wcid;
1403         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1404
1405         /*
1406          * Find next free WCID.
1407          */
1408         wcid = rt2800_find_wcid(rt2x00dev);
1409
1410         /*
1411          * Store selected wcid even if it is invalid so that we can
1412          * later decide if the STA is uploaded into the hw.
1413          */
1414         sta_priv->wcid = wcid;
1415
1416         /*
1417          * No space left in the device, however, we can still communicate
1418          * with the STA -> No error.
1419          */
1420         if (wcid < 0)
1421                 return 0;
1422
1423         /*
1424          * Clean up WCID attributes and write STA address to the device.
1425          */
1426         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1427         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1428         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1429                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1430         return 0;
1431 }
1432 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1433
1434 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1435 {
1436         /*
1437          * Remove WCID entry, no need to clean the attributes as they will
1438          * get renewed when the WCID is reused.
1439          */
1440         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1441
1442         return 0;
1443 }
1444 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1445
1446 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1447                           const unsigned int filter_flags)
1448 {
1449         u32 reg;
1450
1451         /*
1452          * Start configuration steps.
1453          * Note that the version error will always be dropped
1454          * and broadcast frames will always be accepted since
1455          * there is no filter for it at this time.
1456          */
1457         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1458         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1459                            !(filter_flags & FIF_FCSFAIL));
1460         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1461                            !(filter_flags & FIF_PLCPFAIL));
1462         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1463                            !(filter_flags & FIF_PROMISC_IN_BSS));
1464         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1465         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1466         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1467                            !(filter_flags & FIF_ALLMULTI));
1468         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1469         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1470         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1471                            !(filter_flags & FIF_CONTROL));
1472         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1473                            !(filter_flags & FIF_CONTROL));
1474         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1475                            !(filter_flags & FIF_CONTROL));
1476         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1477                            !(filter_flags & FIF_CONTROL));
1478         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1479                            !(filter_flags & FIF_CONTROL));
1480         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1481                            !(filter_flags & FIF_PSPOLL));
1482         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1483         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1484                            !(filter_flags & FIF_CONTROL));
1485         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1486                            !(filter_flags & FIF_CONTROL));
1487         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1488 }
1489 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1490
1491 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1492                         struct rt2x00intf_conf *conf, const unsigned int flags)
1493 {
1494         u32 reg;
1495         bool update_bssid = false;
1496
1497         if (flags & CONFIG_UPDATE_TYPE) {
1498                 /*
1499                  * Enable synchronisation.
1500                  */
1501                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1502                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1503                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1504
1505                 if (conf->sync == TSF_SYNC_AP_NONE) {
1506                         /*
1507                          * Tune beacon queue transmit parameters for AP mode
1508                          */
1509                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1510                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1511                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1512                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1513                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1514                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1515                 } else {
1516                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1517                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1518                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1519                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1520                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1521                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1522                 }
1523         }
1524
1525         if (flags & CONFIG_UPDATE_MAC) {
1526                 if (flags & CONFIG_UPDATE_TYPE &&
1527                     conf->sync == TSF_SYNC_AP_NONE) {
1528                         /*
1529                          * The BSSID register has to be set to our own mac
1530                          * address in AP mode.
1531                          */
1532                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1533                         update_bssid = true;
1534                 }
1535
1536                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1537                         reg = le32_to_cpu(conf->mac[1]);
1538                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1539                         conf->mac[1] = cpu_to_le32(reg);
1540                 }
1541
1542                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1543                                               conf->mac, sizeof(conf->mac));
1544         }
1545
1546         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1547                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1548                         reg = le32_to_cpu(conf->bssid[1]);
1549                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1550                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1551                         conf->bssid[1] = cpu_to_le32(reg);
1552                 }
1553
1554                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1555                                               conf->bssid, sizeof(conf->bssid));
1556         }
1557 }
1558 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1559
1560 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1561                                     struct rt2x00lib_erp *erp)
1562 {
1563         bool any_sta_nongf = !!(erp->ht_opmode &
1564                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1565         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1566         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1567         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1568         u32 reg;
1569
1570         /* default protection rate for HT20: OFDM 24M */
1571         mm20_rate = gf20_rate = 0x4004;
1572
1573         /* default protection rate for HT40: duplicate OFDM 24M */
1574         mm40_rate = gf40_rate = 0x4084;
1575
1576         switch (protection) {
1577         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1578                 /*
1579                  * All STAs in this BSS are HT20/40 but there might be
1580                  * STAs not supporting greenfield mode.
1581                  * => Disable protection for HT transmissions.
1582                  */
1583                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1584
1585                 break;
1586         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1587                 /*
1588                  * All STAs in this BSS are HT20 or HT20/40 but there
1589                  * might be STAs not supporting greenfield mode.
1590                  * => Protect all HT40 transmissions.
1591                  */
1592                 mm20_mode = gf20_mode = 0;
1593                 mm40_mode = gf40_mode = 2;
1594
1595                 break;
1596         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1597                 /*
1598                  * Nonmember protection:
1599                  * According to 802.11n we _should_ protect all
1600                  * HT transmissions (but we don't have to).
1601                  *
1602                  * But if cts_protection is enabled we _shall_ protect
1603                  * all HT transmissions using a CCK rate.
1604                  *
1605                  * And if any station is non GF we _shall_ protect
1606                  * GF transmissions.
1607                  *
1608                  * We decide to protect everything
1609                  * -> fall through to mixed mode.
1610                  */
1611         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1612                 /*
1613                  * Legacy STAs are present
1614                  * => Protect all HT transmissions.
1615                  */
1616                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1617
1618                 /*
1619                  * If erp protection is needed we have to protect HT
1620                  * transmissions with CCK 11M long preamble.
1621                  */
1622                 if (erp->cts_protection) {
1623                         /* don't duplicate RTS/CTS in CCK mode */
1624                         mm20_rate = mm40_rate = 0x0003;
1625                         gf20_rate = gf40_rate = 0x0003;
1626                 }
1627                 break;
1628         }
1629
1630         /* check for STAs not supporting greenfield mode */
1631         if (any_sta_nongf)
1632                 gf20_mode = gf40_mode = 2;
1633
1634         /* Update HT protection config */
1635         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1636         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1637         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1638         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1639
1640         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1641         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1642         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1643         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1644
1645         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1646         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1647         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1648         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1649
1650         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1651         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1652         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1653         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1654 }
1655
1656 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1657                        u32 changed)
1658 {
1659         u32 reg;
1660
1661         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1662                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1663                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1664                                    !!erp->short_preamble);
1665                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1666                                    !!erp->short_preamble);
1667                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1668         }
1669
1670         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1671                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1672                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1673                                    erp->cts_protection ? 2 : 0);
1674                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1675         }
1676
1677         if (changed & BSS_CHANGED_BASIC_RATES) {
1678                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1679                                          erp->basic_rates);
1680                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1681         }
1682
1683         if (changed & BSS_CHANGED_ERP_SLOT) {
1684                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1685                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1686                                    erp->slot_time);
1687                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1688
1689                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1690                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1691                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1692         }
1693
1694         if (changed & BSS_CHANGED_BEACON_INT) {
1695                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1696                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1697                                    erp->beacon_int * 16);
1698                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1699         }
1700
1701         if (changed & BSS_CHANGED_HT)
1702                 rt2800_config_ht_opmode(rt2x00dev, erp);
1703 }
1704 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1705
1706 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1707 {
1708         u32 reg;
1709         u16 eeprom;
1710         u8 led_ctrl, led_g_mode, led_r_mode;
1711
1712         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1713         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1714                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1715                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1716         } else {
1717                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1718                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1719         }
1720         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1721
1722         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1723         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1724         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1725         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1726             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1727                 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1728                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1729                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1730                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1731                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1732                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1733                 } else {
1734                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1735                                            (led_g_mode << 2) | led_r_mode, 1);
1736                 }
1737         }
1738 }
1739
1740 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1741                                      enum antenna ant)
1742 {
1743         u32 reg;
1744         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1745         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1746
1747         if (rt2x00_is_pci(rt2x00dev)) {
1748                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1749                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1750                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1751         } else if (rt2x00_is_usb(rt2x00dev))
1752                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1753                                    eesk_pin, 0);
1754
1755         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1756         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1757         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1758         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1759 }
1760
1761 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1762 {
1763         u8 r1;
1764         u8 r3;
1765         u16 eeprom;
1766
1767         rt2800_bbp_read(rt2x00dev, 1, &r1);
1768         rt2800_bbp_read(rt2x00dev, 3, &r3);
1769
1770         if (rt2x00_rt(rt2x00dev, RT3572) &&
1771             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1772                 rt2800_config_3572bt_ant(rt2x00dev);
1773
1774         /*
1775          * Configure the TX antenna.
1776          */
1777         switch (ant->tx_chain_num) {
1778         case 1:
1779                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1780                 break;
1781         case 2:
1782                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1783                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1784                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1785                 else
1786                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1787                 break;
1788         case 3:
1789                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1790                 break;
1791         }
1792
1793         /*
1794          * Configure the RX antenna.
1795          */
1796         switch (ant->rx_chain_num) {
1797         case 1:
1798                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1799                     rt2x00_rt(rt2x00dev, RT3090) ||
1800                     rt2x00_rt(rt2x00dev, RT3352) ||
1801                     rt2x00_rt(rt2x00dev, RT3390)) {
1802                         rt2800_eeprom_read(rt2x00dev,
1803                                            EEPROM_NIC_CONF1, &eeprom);
1804                         if (rt2x00_get_field16(eeprom,
1805                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1806                                 rt2800_set_ant_diversity(rt2x00dev,
1807                                                 rt2x00dev->default_ant.rx);
1808                 }
1809                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1810                 break;
1811         case 2:
1812                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1813                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1814                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1815                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1816                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1817                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1818                 } else {
1819                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1820                 }
1821                 break;
1822         case 3:
1823                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1824                 break;
1825         }
1826
1827         rt2800_bbp_write(rt2x00dev, 3, r3);
1828         rt2800_bbp_write(rt2x00dev, 1, r1);
1829
1830         if (rt2x00_rt(rt2x00dev, RT3593)) {
1831                 if (ant->rx_chain_num == 1)
1832                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1833                 else
1834                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
1835         }
1836 }
1837 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1838
1839 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1840                                    struct rt2x00lib_conf *libconf)
1841 {
1842         u16 eeprom;
1843         short lna_gain;
1844
1845         if (libconf->rf.channel <= 14) {
1846                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1847                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1848         } else if (libconf->rf.channel <= 64) {
1849                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1850                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1851         } else if (libconf->rf.channel <= 128) {
1852                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1853                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1854                         lna_gain = rt2x00_get_field16(eeprom,
1855                                                       EEPROM_EXT_LNA2_A1);
1856                 } else {
1857                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1858                         lna_gain = rt2x00_get_field16(eeprom,
1859                                                       EEPROM_RSSI_BG2_LNA_A1);
1860                 }
1861         } else {
1862                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1863                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1864                         lna_gain = rt2x00_get_field16(eeprom,
1865                                                       EEPROM_EXT_LNA2_A2);
1866                 } else {
1867                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1868                         lna_gain = rt2x00_get_field16(eeprom,
1869                                                       EEPROM_RSSI_A2_LNA_A2);
1870                 }
1871         }
1872
1873         rt2x00dev->lna_gain = lna_gain;
1874 }
1875
1876 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1877                                          struct ieee80211_conf *conf,
1878                                          struct rf_channel *rf,
1879                                          struct channel_info *info)
1880 {
1881         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1882
1883         if (rt2x00dev->default_ant.tx_chain_num == 1)
1884                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1885
1886         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1887                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1888                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1889         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1890                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1891
1892         if (rf->channel > 14) {
1893                 /*
1894                  * When TX power is below 0, we should increase it by 7 to
1895                  * make it a positive value (Minimum value is -7).
1896                  * However this means that values between 0 and 7 have
1897                  * double meaning, and we should set a 7DBm boost flag.
1898                  */
1899                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1900                                    (info->default_power1 >= 0));
1901
1902                 if (info->default_power1 < 0)
1903                         info->default_power1 += 7;
1904
1905                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1906
1907                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1908                                    (info->default_power2 >= 0));
1909
1910                 if (info->default_power2 < 0)
1911                         info->default_power2 += 7;
1912
1913                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1914         } else {
1915                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1916                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1917         }
1918
1919         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1920
1921         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1922         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1923         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1924         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1925
1926         udelay(200);
1927
1928         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1929         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1930         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1931         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1932
1933         udelay(200);
1934
1935         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1936         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1937         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1938         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1939 }
1940
1941 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1942                                          struct ieee80211_conf *conf,
1943                                          struct rf_channel *rf,
1944                                          struct channel_info *info)
1945 {
1946         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1947         u8 rfcsr, calib_tx, calib_rx;
1948
1949         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1950
1951         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1952         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1953         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1954
1955         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1956         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1957         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1958
1959         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1960         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1961         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1962
1963         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1964         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1965         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1966
1967         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1968         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1969         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1970                           rt2x00dev->default_ant.rx_chain_num <= 1);
1971         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1972                           rt2x00dev->default_ant.rx_chain_num <= 2);
1973         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1974         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1975                           rt2x00dev->default_ant.tx_chain_num <= 1);
1976         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1977                           rt2x00dev->default_ant.tx_chain_num <= 2);
1978         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1979
1980         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1981         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1982         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1983         msleep(1);
1984         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1985         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1986
1987         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1988         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1989         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1990
1991         if (rt2x00_rt(rt2x00dev, RT3390)) {
1992                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1993                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1994         } else {
1995                 if (conf_is_ht40(conf)) {
1996                         calib_tx = drv_data->calibration_bw40;
1997                         calib_rx = drv_data->calibration_bw40;
1998                 } else {
1999                         calib_tx = drv_data->calibration_bw20;
2000                         calib_rx = drv_data->calibration_bw20;
2001                 }
2002         }
2003
2004         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2005         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2006         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2007
2008         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2009         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2010         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2011
2012         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2013         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2014         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2015
2016         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2017         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2018         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2019         msleep(1);
2020         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2021         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2022 }
2023
2024 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2025                                          struct ieee80211_conf *conf,
2026                                          struct rf_channel *rf,
2027                                          struct channel_info *info)
2028 {
2029         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2030         u8 rfcsr;
2031         u32 reg;
2032
2033         if (rf->channel <= 14) {
2034                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2035                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2036         } else {
2037                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2038                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2039         }
2040
2041         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2042         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2043
2044         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2045         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2046         if (rf->channel <= 14)
2047                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2048         else
2049                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2050         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2051
2052         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2053         if (rf->channel <= 14)
2054                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2055         else
2056                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2057         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2058
2059         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2060         if (rf->channel <= 14) {
2061                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2062                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2063                                   info->default_power1);
2064         } else {
2065                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2066                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2067                                 (info->default_power1 & 0x3) |
2068                                 ((info->default_power1 & 0xC) << 1));
2069         }
2070         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2071
2072         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2073         if (rf->channel <= 14) {
2074                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2075                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2076                                   info->default_power2);
2077         } else {
2078                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2079                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2080                                 (info->default_power2 & 0x3) |
2081                                 ((info->default_power2 & 0xC) << 1));
2082         }
2083         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2084
2085         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2086         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2087         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2088         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2089         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2090         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2091         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2092         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2093                 if (rf->channel <= 14) {
2094                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2095                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2096                 }
2097                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2098                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2099         } else {
2100                 switch (rt2x00dev->default_ant.tx_chain_num) {
2101                 case 1:
2102                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2103                 case 2:
2104                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2105                         break;
2106                 }
2107
2108                 switch (rt2x00dev->default_ant.rx_chain_num) {
2109                 case 1:
2110                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2111                 case 2:
2112                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2113                         break;
2114                 }
2115         }
2116         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2117
2118         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2119         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2120         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2121
2122         if (conf_is_ht40(conf)) {
2123                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2124                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2125         } else {
2126                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2127                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2128         }
2129
2130         if (rf->channel <= 14) {
2131                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2132                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2133                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2134                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2135                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2136                 rfcsr = 0x4c;
2137                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2138                                   drv_data->txmixer_gain_24g);
2139                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2140                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2141                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2142                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2143                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2144                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2145                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2146                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2147         } else {
2148                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2149                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2150                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2151                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2152                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2153                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2154                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2155                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2156                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2157                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2158                 rfcsr = 0x7a;
2159                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2160                                   drv_data->txmixer_gain_5g);
2161                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2162                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2163                 if (rf->channel <= 64) {
2164                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2165                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2166                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2167                 } else if (rf->channel <= 128) {
2168                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2169                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2170                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2171                 } else {
2172                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2173                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2174                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2175                 }
2176                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2177                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2178                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2179         }
2180
2181         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2182         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2183         if (rf->channel <= 14)
2184                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2185         else
2186                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2187         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2188
2189         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2190         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2191         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2192 }
2193
2194 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2195                                          struct ieee80211_conf *conf,
2196                                          struct rf_channel *rf,
2197                                          struct channel_info *info)
2198 {
2199         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2200         u8 txrx_agc_fc;
2201         u8 txrx_h20m;
2202         u8 rfcsr;
2203         u8 bbp;
2204         const bool txbf_enabled = false; /* TODO */
2205
2206         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2207         rt2800_bbp_read(rt2x00dev, 109, &bbp);
2208         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2209         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2210         rt2800_bbp_write(rt2x00dev, 109, bbp);
2211
2212         rt2800_bbp_read(rt2x00dev, 110, &bbp);
2213         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2214         rt2800_bbp_write(rt2x00dev, 110, bbp);
2215
2216         if (rf->channel <= 14) {
2217                 /* Restore BBP 25 & 26 for 2.4 GHz */
2218                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2219                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2220         } else {
2221                 /* Hard code BBP 25 & 26 for 5GHz */
2222
2223                 /* Enable IQ Phase correction */
2224                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2225                 /* Setup IQ Phase correction value */
2226                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2227         }
2228
2229         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2230         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2231
2232         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2233         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2234         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2235
2236         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2237         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2238         if (rf->channel <= 14)
2239                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2240         else
2241                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2242         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2243
2244         rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2245         if (rf->channel <= 14) {
2246                 rfcsr = 0;
2247                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2248                                   info->default_power1 & 0x1f);
2249         } else {
2250                 if (rt2x00_is_usb(rt2x00dev))
2251                         rfcsr = 0x40;
2252
2253                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2254                                   ((info->default_power1 & 0x18) << 1) |
2255                                   (info->default_power1 & 7));
2256         }
2257         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2258
2259         rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2260         if (rf->channel <= 14) {
2261                 rfcsr = 0;
2262                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2263                                   info->default_power2 & 0x1f);
2264         } else {
2265                 if (rt2x00_is_usb(rt2x00dev))
2266                         rfcsr = 0x40;
2267
2268                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2269                                   ((info->default_power2 & 0x18) << 1) |
2270                                   (info->default_power2 & 7));
2271         }
2272         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2273
2274         rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2275         if (rf->channel <= 14) {
2276                 rfcsr = 0;
2277                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2278                                   info->default_power3 & 0x1f);
2279         } else {
2280                 if (rt2x00_is_usb(rt2x00dev))
2281                         rfcsr = 0x40;
2282
2283                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2284                                   ((info->default_power3 & 0x18) << 1) |
2285                                   (info->default_power3 & 7));
2286         }
2287         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2288
2289         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2290         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2291         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2292         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2293         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2294         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2295         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2296         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2297         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2298
2299         switch (rt2x00dev->default_ant.tx_chain_num) {
2300         case 3:
2301                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2302                 /* fallthrough */
2303         case 2:
2304                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2305                 /* fallthrough */
2306         case 1:
2307                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2308                 break;
2309         }
2310
2311         switch (rt2x00dev->default_ant.rx_chain_num) {
2312         case 3:
2313                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2314                 /* fallthrough */
2315         case 2:
2316                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2317                 /* fallthrough */
2318         case 1:
2319                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2320                 break;
2321         }
2322         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2323
2324         /* TODO: frequency calibration? */
2325
2326         if (conf_is_ht40(conf)) {
2327                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2328                                                 RFCSR24_TX_AGC_FC);
2329                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2330                                               RFCSR24_TX_H20M);
2331         } else {
2332                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2333                                                 RFCSR24_TX_AGC_FC);
2334                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2335                                               RFCSR24_TX_H20M);
2336         }
2337
2338         /* NOTE: the reference driver does not writes the new value
2339          * back to RFCSR 32
2340          */
2341         rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2342         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2343
2344         if (rf->channel <= 14)
2345                 rfcsr = 0xa0;
2346         else
2347                 rfcsr = 0x80;
2348         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2349
2350         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2351         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2352         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2353         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2354
2355         /* Band selection */
2356         rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2357         if (rf->channel <= 14)
2358                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2359         else
2360                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2361         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2362
2363         rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2364         if (rf->channel <= 14)
2365                 rfcsr = 0x3c;
2366         else
2367                 rfcsr = 0x20;
2368         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2369
2370         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2371         if (rf->channel <= 14)
2372                 rfcsr = 0x1a;
2373         else
2374                 rfcsr = 0x12;
2375         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2376
2377         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2378         if (rf->channel >= 1 && rf->channel <= 14)
2379                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2380         else if (rf->channel >= 36 && rf->channel <= 64)
2381                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2382         else if (rf->channel >= 100 && rf->channel <= 128)
2383                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2384         else
2385                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2386         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2387
2388         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2389         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2390         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2391
2392         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2393
2394         if (rf->channel <= 14) {
2395                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2396                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2397         } else {
2398                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2399                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2400         }
2401
2402         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2403         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2404         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2405
2406         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2407         if (rf->channel <= 14) {
2408                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2409                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2410         } else {
2411                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2412                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2413         }
2414         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2415
2416         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2417         if (rf->channel <= 14)
2418                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2419         else
2420                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2421
2422         if (txbf_enabled)
2423                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2424
2425         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2426
2427         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2428         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2429         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2430
2431         rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2432         if (rf->channel <= 14)
2433                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2434         else
2435                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2436         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2437
2438         if (rf->channel <= 14) {
2439                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2440                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2441         } else {
2442                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2443                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2444         }
2445
2446         /* Initiate VCO calibration */
2447         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2448         if (rf->channel <= 14) {
2449                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2450         } else {
2451                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2452                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2453                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2454                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2455                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2456                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2457         }
2458         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2459
2460         if (rf->channel >= 1 && rf->channel <= 14) {
2461                 rfcsr = 0x23;
2462                 if (txbf_enabled)
2463                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2464                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2465
2466                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2467         } else if (rf->channel >= 36 && rf->channel <= 64) {
2468                 rfcsr = 0x36;
2469                 if (txbf_enabled)
2470                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2471                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2472
2473                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2474         } else if (rf->channel >= 100 && rf->channel <= 128) {
2475                 rfcsr = 0x32;
2476                 if (txbf_enabled)
2477                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2478                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2479
2480                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2481         } else {
2482                 rfcsr = 0x30;
2483                 if (txbf_enabled)
2484                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2485                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2486
2487                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2488         }
2489 }
2490
2491 #define POWER_BOUND             0x27
2492 #define POWER_BOUND_5G          0x2b
2493 #define FREQ_OFFSET_BOUND       0x5f
2494
2495 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2496 {
2497         u8 rfcsr;
2498
2499         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2500         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2501                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2502         else
2503                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2504         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2505 }
2506
2507 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2508                                          struct ieee80211_conf *conf,
2509                                          struct rf_channel *rf,
2510                                          struct channel_info *info)
2511 {
2512         u8 rfcsr;
2513
2514         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2515         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2516         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2517         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2518         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2519
2520         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2521         if (info->default_power1 > POWER_BOUND)
2522                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2523         else
2524                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2525         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2526
2527         rt2800_adjust_freq_offset(rt2x00dev);
2528
2529         if (rf->channel <= 14) {
2530                 if (rf->channel == 6)
2531                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2532                 else
2533                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2534
2535                 if (rf->channel >= 1 && rf->channel <= 6)
2536                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2537                 else if (rf->channel >= 7 && rf->channel <= 11)
2538                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2539                 else if (rf->channel >= 12 && rf->channel <= 14)
2540                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2541         }
2542 }
2543
2544 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2545                                          struct ieee80211_conf *conf,
2546                                          struct rf_channel *rf,
2547                                          struct channel_info *info)
2548 {
2549         u8 rfcsr;
2550
2551         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2552         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2553
2554         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2555         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2556         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2557
2558         if (info->default_power1 > POWER_BOUND)
2559                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2560         else
2561                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2562
2563         if (info->default_power2 > POWER_BOUND)
2564                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2565         else
2566                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2567
2568         rt2800_adjust_freq_offset(rt2x00dev);
2569
2570         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2571         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2572         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2573
2574         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2575                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2576         else
2577                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2578
2579         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2580                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2581         else
2582                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2583
2584         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2585         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2586
2587         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2588
2589         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2590 }
2591
2592 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2593                                          struct ieee80211_conf *conf,
2594                                          struct rf_channel *rf,
2595                                          struct channel_info *info)
2596 {
2597         u8 rfcsr;
2598
2599         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2600         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2601         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2602         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2603         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2604
2605         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2606         if (info->default_power1 > POWER_BOUND)
2607                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2608         else
2609                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2610         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2611
2612         if (rt2x00_rt(rt2x00dev, RT5392)) {
2613                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2614                 if (info->default_power1 > POWER_BOUND)
2615                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2616                 else
2617                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2618                                           info->default_power2);
2619                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2620         }
2621
2622         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2623         if (rt2x00_rt(rt2x00dev, RT5392)) {
2624                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2625                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2626         }
2627         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2628         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2629         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2630         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2631         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2632
2633         rt2800_adjust_freq_offset(rt2x00dev);
2634
2635         if (rf->channel <= 14) {
2636                 int idx = rf->channel-1;
2637
2638                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2639                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2640                                 /* r55/r59 value array of channel 1~14 */
2641                                 static const char r55_bt_rev[] = {0x83, 0x83,
2642                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2643                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2644                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2645                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2646                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2647
2648                                 rt2800_rfcsr_write(rt2x00dev, 55,
2649                                                    r55_bt_rev[idx]);
2650                                 rt2800_rfcsr_write(rt2x00dev, 59,
2651                                                    r59_bt_rev[idx]);
2652                         } else {
2653                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2654                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2655                                         0x88, 0x88, 0x86, 0x85, 0x84};
2656
2657                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2658                         }
2659                 } else {
2660                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2661                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2662                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2663                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2664                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2665                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2666                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2667
2668                                 rt2800_rfcsr_write(rt2x00dev, 55,
2669                                                    r55_nonbt_rev[idx]);
2670                                 rt2800_rfcsr_write(rt2x00dev, 59,
2671                                                    r59_nonbt_rev[idx]);
2672                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2673                                    rt2x00_rt(rt2x00dev, RT5392)) {
2674                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2675                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2676                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2677
2678                                 rt2800_rfcsr_write(rt2x00dev, 59,
2679                                                    r59_non_bt[idx]);
2680                         }
2681                 }
2682         }
2683 }
2684
2685 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2686                                          struct ieee80211_conf *conf,
2687                                          struct rf_channel *rf,
2688                                          struct channel_info *info)
2689 {
2690         u8 rfcsr, ep_reg;
2691         u32 reg;
2692         int power_bound;
2693
2694         /* TODO */
2695         const bool is_11b = false;
2696         const bool is_type_ep = false;
2697
2698         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2699         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2700                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2701         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2702
2703         /* Order of values on rf_channel entry: N, K, mod, R */
2704         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2705
2706         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2707         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2708         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2709         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2710         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2711
2712         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2713         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2714         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2715         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2716
2717         if (rf->channel <= 14) {
2718                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2719                 /* FIXME: RF11 owerwrite ? */
2720                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2721                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2722                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2723                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2724                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2725                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2726                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2727                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2728                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2729                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2730                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2731                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2732                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2733                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2734                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2735                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2736                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2737                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2738                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2739                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2740                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2741                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2742                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2743                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2744                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2745                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2746                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2747                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2748
2749                 /* TODO RF27 <- tssi */
2750
2751                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2752                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2753                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2754
2755                 if (is_11b) {
2756                         /* CCK */
2757                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2758                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2759                         if (is_type_ep)
2760                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2761                         else
2762                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2763                 } else {
2764                         /* OFDM */
2765                         if (is_type_ep)
2766                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2767                         else
2768                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2769                 }
2770
2771                 power_bound = POWER_BOUND;
2772                 ep_reg = 0x2;
2773         } else {
2774                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2775                 /* FIMXE: RF11 overwrite */
2776                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2777                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2778                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2779                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2780                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2781                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2782                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2783                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2784                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2785                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2786                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2787                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2788                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2789                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2790
2791                 /* TODO RF27 <- tssi */
2792
2793                 if (rf->channel >= 36 && rf->channel <= 64) {
2794
2795                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2796                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2797                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2798                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2799                         if (rf->channel <= 50)
2800                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2801                         else if (rf->channel >= 52)
2802                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2803                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2804                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2805                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2806                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2807                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2808                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2809                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2810                         if (rf->channel <= 50) {
2811                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2812                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2813                         } else if (rf->channel >= 52) {
2814                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2815                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2816                         }
2817
2818                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2819                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2820                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2821
2822                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2823
2824                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2825                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2826                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2827                         if (rf->channel <= 153) {
2828                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2829                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2830                         } else if (rf->channel >= 155) {
2831                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2832                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2833                         }
2834                         if (rf->channel <= 138) {
2835                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2836                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2837                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2838                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2839                         } else if (rf->channel >= 140) {
2840                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2841                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2842                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2843                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2844                         }
2845                         if (rf->channel <= 124)
2846                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2847                         else if (rf->channel >= 126)
2848                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2849                         if (rf->channel <= 138)
2850                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2851                         else if (rf->channel >= 140)
2852                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2853                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2854                         if (rf->channel <= 138)
2855                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2856                         else if (rf->channel >= 140)
2857                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2858                         if (rf->channel <= 128)
2859                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2860                         else if (rf->channel >= 130)
2861                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2862                         if (rf->channel <= 116)
2863                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2864                         else if (rf->channel >= 118)
2865                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2866                         if (rf->channel <= 138)
2867                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2868                         else if (rf->channel >= 140)
2869                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2870                         if (rf->channel <= 116)
2871                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2872                         else if (rf->channel >= 118)
2873                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2874                 }
2875
2876                 power_bound = POWER_BOUND_5G;
2877                 ep_reg = 0x3;
2878         }
2879
2880         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2881         if (info->default_power1 > power_bound)
2882                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2883         else
2884                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2885         if (is_type_ep)
2886                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2887         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2888
2889         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2890         if (info->default_power2 > power_bound)
2891                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2892         else
2893                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2894         if (is_type_ep)
2895                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2896         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2897
2898         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2899         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2900         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2901
2902         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2903                           rt2x00dev->default_ant.tx_chain_num >= 1);
2904         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2905                           rt2x00dev->default_ant.tx_chain_num == 2);
2906         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2907
2908         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2909                           rt2x00dev->default_ant.rx_chain_num >= 1);
2910         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2911                           rt2x00dev->default_ant.rx_chain_num == 2);
2912         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2913
2914         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2915         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2916
2917         if (conf_is_ht40(conf))
2918                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2919         else
2920                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2921
2922         if (!is_11b) {
2923                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2924                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2925         }
2926
2927         /* TODO proper frequency adjustment */
2928         rt2800_adjust_freq_offset(rt2x00dev);
2929
2930         /* TODO merge with others */
2931         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2932         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2933         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2934
2935         /* BBP settings */
2936         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2937         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2938         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2939
2940         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2941         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2942         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2943         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2944
2945         /* GLRT band configuration */
2946         rt2800_bbp_write(rt2x00dev, 195, 128);
2947         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2948         rt2800_bbp_write(rt2x00dev, 195, 129);
2949         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2950         rt2800_bbp_write(rt2x00dev, 195, 130);
2951         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2952         rt2800_bbp_write(rt2x00dev, 195, 131);
2953         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2954         rt2800_bbp_write(rt2x00dev, 195, 133);
2955         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2956         rt2800_bbp_write(rt2x00dev, 195, 124);
2957         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2958 }
2959
2960 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2961                                            const unsigned int word,
2962                                            const u8 value)
2963 {
2964         u8 chain, reg;
2965
2966         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2967                 rt2800_bbp_read(rt2x00dev, 27, &reg);
2968                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
2969                 rt2800_bbp_write(rt2x00dev, 27, reg);
2970
2971                 rt2800_bbp_write(rt2x00dev, word, value);
2972         }
2973 }
2974
2975 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2976 {
2977         u8 cal;
2978
2979         /* TX0 IQ Gain */
2980         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2981         if (channel <= 14)
2982                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2983         else if (channel >= 36 && channel <= 64)
2984                 cal = rt2x00_eeprom_byte(rt2x00dev,
2985                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2986         else if (channel >= 100 && channel <= 138)
2987                 cal = rt2x00_eeprom_byte(rt2x00dev,
2988                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2989         else if (channel >= 140 && channel <= 165)
2990                 cal = rt2x00_eeprom_byte(rt2x00dev,
2991                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2992         else
2993                 cal = 0;
2994         rt2800_bbp_write(rt2x00dev, 159, cal);
2995
2996         /* TX0 IQ Phase */
2997         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
2998         if (channel <= 14)
2999                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3000         else if (channel >= 36 && channel <= 64)
3001                 cal = rt2x00_eeprom_byte(rt2x00dev,
3002                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3003         else if (channel >= 100 && channel <= 138)
3004                 cal = rt2x00_eeprom_byte(rt2x00dev,
3005                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3006         else if (channel >= 140 && channel <= 165)
3007                 cal = rt2x00_eeprom_byte(rt2x00dev,
3008                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3009         else
3010                 cal = 0;
3011         rt2800_bbp_write(rt2x00dev, 159, cal);
3012
3013         /* TX1 IQ Gain */
3014         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3015         if (channel <= 14)
3016                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3017         else if (channel >= 36 && channel <= 64)
3018                 cal = rt2x00_eeprom_byte(rt2x00dev,
3019                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3020         else if (channel >= 100 && channel <= 138)
3021                 cal = rt2x00_eeprom_byte(rt2x00dev,
3022                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3023         else if (channel >= 140 && channel <= 165)
3024                 cal = rt2x00_eeprom_byte(rt2x00dev,
3025                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3026         else
3027                 cal = 0;
3028         rt2800_bbp_write(rt2x00dev, 159, cal);
3029
3030         /* TX1 IQ Phase */
3031         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3032         if (channel <= 14)
3033                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3034         else if (channel >= 36 && channel <= 64)
3035                 cal = rt2x00_eeprom_byte(rt2x00dev,
3036                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3037         else if (channel >= 100 && channel <= 138)
3038                 cal = rt2x00_eeprom_byte(rt2x00dev,
3039                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3040         else if (channel >= 140 && channel <= 165)
3041                 cal = rt2x00_eeprom_byte(rt2x00dev,
3042                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3043         else
3044                 cal = 0;
3045         rt2800_bbp_write(rt2x00dev, 159, cal);
3046
3047         /* FIXME: possible RX0, RX1 callibration ? */
3048
3049         /* RF IQ compensation control */
3050         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3051         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3052         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3053
3054         /* RF IQ imbalance compensation control */
3055         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3056         cal = rt2x00_eeprom_byte(rt2x00dev,
3057                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3058         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3059 }
3060
3061 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3062                                   unsigned int channel,
3063                                   char txpower)
3064 {
3065         if (rt2x00_rt(rt2x00dev, RT3593))
3066                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3067
3068         if (channel <= 14)
3069                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3070
3071         if (rt2x00_rt(rt2x00dev, RT3593))
3072                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3073                                MAX_A_TXPOWER_3593);
3074         else
3075                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3076 }
3077
3078 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3079                                   struct ieee80211_conf *conf,
3080                                   struct rf_channel *rf,
3081                                   struct channel_info *info)
3082 {
3083         u32 reg;
3084         unsigned int tx_pin;
3085         u8 bbp, rfcsr;
3086
3087         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3088                                                      info->default_power1);
3089         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3090                                                      info->default_power2);
3091         if (rt2x00dev->default_ant.tx_chain_num > 2)
3092                 info->default_power3 =
3093                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3094                                               info->default_power3);
3095
3096         switch (rt2x00dev->chip.rf) {
3097         case RF2020:
3098         case RF3020:
3099         case RF3021:
3100         case RF3022:
3101         case RF3320:
3102                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3103                 break;
3104         case RF3052:
3105                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3106                 break;
3107         case RF3053:
3108                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3109                 break;
3110         case RF3290:
3111                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3112                 break;
3113         case RF3322:
3114                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3115                 break;
3116         case RF5360:
3117         case RF5370:
3118         case RF5372:
3119         case RF5390:
3120         case RF5392:
3121                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3122                 break;
3123         case RF5592:
3124                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3125                 break;
3126         default:
3127                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3128         }
3129
3130         if (rt2x00_rf(rt2x00dev, RF3290) ||
3131             rt2x00_rf(rt2x00dev, RF3322) ||
3132             rt2x00_rf(rt2x00dev, RF5360) ||
3133             rt2x00_rf(rt2x00dev, RF5370) ||
3134             rt2x00_rf(rt2x00dev, RF5372) ||
3135             rt2x00_rf(rt2x00dev, RF5390) ||
3136             rt2x00_rf(rt2x00dev, RF5392)) {
3137                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3138                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3139                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3140                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3141
3142                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3143                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3144                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3145         }
3146
3147         /*
3148          * Change BBP settings
3149          */
3150         if (rt2x00_rt(rt2x00dev, RT3352)) {
3151                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3152                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3153                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3154                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3155         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3156                 if (rf->channel > 14) {
3157                         /* Disable CCK Packet detection on 5GHz */
3158                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
3159                 } else {
3160                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3161                 }
3162
3163                 if (conf_is_ht40(conf))
3164                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
3165                 else
3166                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
3167
3168                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3169                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3170                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3171                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3172         } else {
3173                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3174                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3175                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3176                 rt2800_bbp_write(rt2x00dev, 86, 0);
3177         }
3178
3179         if (rf->channel <= 14) {
3180                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3181                     !rt2x00_rt(rt2x00dev, RT5392)) {
3182                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3183                                      &rt2x00dev->cap_flags)) {
3184                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3185                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3186                         } else {
3187                                 if (rt2x00_rt(rt2x00dev, RT3593))
3188                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3189                                 else
3190                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
3191                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3192                         }
3193                         if (rt2x00_rt(rt2x00dev, RT3593))
3194                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3195                 }
3196
3197         } else {
3198                 if (rt2x00_rt(rt2x00dev, RT3572))
3199                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
3200                 else if (rt2x00_rt(rt2x00dev, RT3593))
3201                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
3202                 else
3203                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3204
3205                 if (rt2x00_rt(rt2x00dev, RT3593))
3206                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3207
3208                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
3209                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
3210                 else
3211                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
3212         }
3213
3214         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
3215         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3216         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3217         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3218         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3219
3220         if (rt2x00_rt(rt2x00dev, RT3572))
3221                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3222
3223         tx_pin = 0;
3224
3225         switch (rt2x00dev->default_ant.tx_chain_num) {
3226         case 3:
3227                 /* Turn on tertiary PAs */
3228                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3229                                    rf->channel > 14);
3230                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3231                                    rf->channel <= 14);
3232                 /* fall-through */
3233         case 2:
3234                 /* Turn on secondary PAs */
3235                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3236                                    rf->channel > 14);
3237                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3238                                    rf->channel <= 14);
3239                 /* fall-through */
3240         case 1:
3241                 /* Turn on primary PAs */
3242                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3243                                    rf->channel > 14);
3244                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
3245                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3246                 else
3247                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3248                                            rf->channel <= 14);
3249                 break;
3250         }
3251
3252         switch (rt2x00dev->default_ant.rx_chain_num) {
3253         case 3:
3254                 /* Turn on tertiary LNAs */
3255                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3256                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3257                 /* fall-through */
3258         case 2:
3259                 /* Turn on secondary LNAs */
3260                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3261                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3262                 /* fall-through */
3263         case 1:
3264                 /* Turn on primary LNAs */
3265                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3266                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3267                 break;
3268         }
3269
3270         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3271         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3272
3273         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3274
3275         if (rt2x00_rt(rt2x00dev, RT3572))
3276                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3277
3278         if (rt2x00_rt(rt2x00dev, RT3593)) {
3279                 if (rt2x00_is_usb(rt2x00dev)) {
3280                         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3281
3282                         /* Band selection. GPIO #8 controls all paths */
3283                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3284                         if (rf->channel <= 14)
3285                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3286                         else
3287                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3288
3289                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3290                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3291
3292                         /* LNA PE control.
3293                         * GPIO #4 controls PE0 and PE1,
3294                         * GPIO #7 controls PE2
3295                         */
3296                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3297                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3298
3299                         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3300                 }
3301
3302                 /* AGC init */
3303                 if (rf->channel <= 14)
3304                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
3305                 else
3306                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3307
3308                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3309
3310                 usleep_range(1000, 1500);
3311         }
3312
3313         if (rt2x00_rt(rt2x00dev, RT5592)) {
3314                 rt2800_bbp_write(rt2x00dev, 195, 141);
3315                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3316
3317                 /* AGC init */
3318                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3319                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3320
3321                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3322         }
3323
3324         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3325         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3326         rt2800_bbp_write(rt2x00dev, 4, bbp);
3327
3328         rt2800_bbp_read(rt2x00dev, 3, &bbp);
3329         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3330         rt2800_bbp_write(rt2x00dev, 3, bbp);
3331
3332         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3333                 if (conf_is_ht40(conf)) {
3334                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3335                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3336                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
3337                 } else {
3338                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
3339                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
3340                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
3341                 }
3342         }
3343
3344         msleep(1);
3345
3346         /*
3347          * Clear channel statistic counters
3348          */
3349         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3350         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3351         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
3352
3353         /*
3354          * Clear update flag
3355          */
3356         if (rt2x00_rt(rt2x00dev, RT3352)) {
3357                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3358                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3359                 rt2800_bbp_write(rt2x00dev, 49, bbp);
3360         }
3361 }
3362
3363 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3364 {
3365         u8 tssi_bounds[9];
3366         u8 current_tssi;
3367         u16 eeprom;
3368         u8 step;
3369         int i;
3370
3371         /*
3372          * Read TSSI boundaries for temperature compensation from
3373          * the EEPROM.
3374          *
3375          * Array idx               0    1    2    3    4    5    6    7    8
3376          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
3377          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3378          */
3379         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3380                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
3381                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3382                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
3383                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3384                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
3385
3386                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
3387                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3388                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
3389                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3390                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
3391
3392                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3393                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3394                                         EEPROM_TSSI_BOUND_BG3_REF);
3395                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3396                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
3397
3398                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3399                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3400                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
3401                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3402                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
3403
3404                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3405                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3406                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
3407
3408                 step = rt2x00_get_field16(eeprom,
3409                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3410         } else {
3411                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3412                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3413                                         EEPROM_TSSI_BOUND_A1_MINUS4);
3414                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3415                                         EEPROM_TSSI_BOUND_A1_MINUS3);
3416
3417                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3418                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3419                                         EEPROM_TSSI_BOUND_A2_MINUS2);
3420                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3421                                         EEPROM_TSSI_BOUND_A2_MINUS1);
3422
3423                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3424                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3425                                         EEPROM_TSSI_BOUND_A3_REF);
3426                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3427                                         EEPROM_TSSI_BOUND_A3_PLUS1);
3428
3429                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3430                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3431                                         EEPROM_TSSI_BOUND_A4_PLUS2);
3432                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3433                                         EEPROM_TSSI_BOUND_A4_PLUS3);
3434
3435                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3436                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3437                                         EEPROM_TSSI_BOUND_A5_PLUS4);
3438
3439                 step = rt2x00_get_field16(eeprom,
3440                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
3441         }
3442
3443         /*
3444          * Check if temperature compensation is supported.
3445          */
3446         if (tssi_bounds[4] == 0xff || step == 0xff)
3447                 return 0;
3448
3449         /*
3450          * Read current TSSI (BBP 49).
3451          */
3452         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3453
3454         /*
3455          * Compare TSSI value (BBP49) with the compensation boundaries
3456          * from the EEPROM and increase or decrease tx power.
3457          */
3458         for (i = 0; i <= 3; i++) {
3459                 if (current_tssi > tssi_bounds[i])
3460                         break;
3461         }
3462
3463         if (i == 4) {
3464                 for (i = 8; i >= 5; i--) {
3465                         if (current_tssi < tssi_bounds[i])
3466                                 break;
3467                 }
3468         }
3469
3470         return (i - 4) * step;
3471 }
3472
3473 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3474                                       enum ieee80211_band band)
3475 {
3476         u16 eeprom;
3477         u8 comp_en;
3478         u8 comp_type;
3479         int comp_value = 0;
3480
3481         rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3482
3483         /*
3484          * HT40 compensation not required.
3485          */
3486         if (eeprom == 0xffff ||
3487             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3488                 return 0;
3489
3490         if (band == IEEE80211_BAND_2GHZ) {
3491                 comp_en = rt2x00_get_field16(eeprom,
3492                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
3493                 if (comp_en) {
3494                         comp_type = rt2x00_get_field16(eeprom,
3495                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
3496                         comp_value = rt2x00_get_field16(eeprom,
3497                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
3498                         if (!comp_type)
3499                                 comp_value = -comp_value;
3500                 }
3501         } else {
3502                 comp_en = rt2x00_get_field16(eeprom,
3503                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
3504                 if (comp_en) {
3505                         comp_type = rt2x00_get_field16(eeprom,
3506                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
3507                         comp_value = rt2x00_get_field16(eeprom,
3508                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
3509                         if (!comp_type)
3510                                 comp_value = -comp_value;
3511                 }
3512         }
3513
3514         return comp_value;
3515 }
3516
3517 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3518                                         int power_level, int max_power)
3519 {
3520         int delta;
3521
3522         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3523                 return 0;
3524
3525         /*
3526          * XXX: We don't know the maximum transmit power of our hardware since
3527          * the EEPROM doesn't expose it. We only know that we are calibrated
3528          * to 100% tx power.
3529          *
3530          * Hence, we assume the regulatory limit that cfg80211 calulated for
3531          * the current channel is our maximum and if we are requested to lower
3532          * the value we just reduce our tx power accordingly.
3533          */
3534         delta = power_level - max_power;
3535         return min(delta, 0);
3536 }
3537
3538 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3539                                    enum ieee80211_band band, int power_level,
3540                                    u8 txpower, int delta)
3541 {
3542         u16 eeprom;
3543         u8 criterion;
3544         u8 eirp_txpower;
3545         u8 eirp_txpower_criterion;
3546         u8 reg_limit;
3547
3548         if (rt2x00_rt(rt2x00dev, RT3593))
3549                 return min_t(u8, txpower, 0xc);
3550
3551         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
3552                 /*
3553                  * Check if eirp txpower exceed txpower_limit.
3554                  * We use OFDM 6M as criterion and its eirp txpower
3555                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
3556                  * .11b data rate need add additional 4dbm
3557                  * when calculating eirp txpower.
3558                  */
3559                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3560                                               1, &eeprom);
3561                 criterion = rt2x00_get_field16(eeprom,
3562                                                EEPROM_TXPOWER_BYRATE_RATE0);
3563
3564                 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3565                                    &eeprom);
3566
3567                 if (band == IEEE80211_BAND_2GHZ)
3568                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3569                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3570                 else
3571                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3572                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3573
3574                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3575                                (is_rate_b ? 4 : 0) + delta;
3576
3577                 reg_limit = (eirp_txpower > power_level) ?
3578                                         (eirp_txpower - power_level) : 0;
3579         } else
3580                 reg_limit = 0;
3581
3582         txpower = max(0, txpower + delta - reg_limit);
3583         return min_t(u8, txpower, 0xc);
3584 }
3585
3586
3587 enum {
3588         TX_PWR_CFG_0_IDX,
3589         TX_PWR_CFG_1_IDX,
3590         TX_PWR_CFG_2_IDX,
3591         TX_PWR_CFG_3_IDX,
3592         TX_PWR_CFG_4_IDX,
3593         TX_PWR_CFG_5_IDX,
3594         TX_PWR_CFG_6_IDX,
3595         TX_PWR_CFG_7_IDX,
3596         TX_PWR_CFG_8_IDX,
3597         TX_PWR_CFG_9_IDX,
3598         TX_PWR_CFG_0_EXT_IDX,
3599         TX_PWR_CFG_1_EXT_IDX,
3600         TX_PWR_CFG_2_EXT_IDX,
3601         TX_PWR_CFG_3_EXT_IDX,
3602         TX_PWR_CFG_4_EXT_IDX,
3603         TX_PWR_CFG_IDX_COUNT,
3604 };
3605
3606 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3607                                          struct ieee80211_channel *chan,
3608                                          int power_level)
3609 {
3610         u8 txpower;
3611         u16 eeprom;
3612         u32 regs[TX_PWR_CFG_IDX_COUNT];
3613         unsigned int offset;
3614         enum ieee80211_band band = chan->band;
3615         int delta;
3616         int i;
3617
3618         memset(regs, '\0', sizeof(regs));
3619
3620         /* TODO: adapt TX power reduction from the rt28xx code */
3621
3622         /* calculate temperature compensation delta */
3623         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3624
3625         if (band == IEEE80211_BAND_5GHZ)
3626                 offset = 16;
3627         else
3628                 offset = 0;
3629
3630         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3631                 offset += 8;
3632
3633         /* read the next four txpower values */
3634         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3635                                       offset, &eeprom);
3636
3637         /* CCK 1MBS,2MBS */
3638         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3639         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3640                                             txpower, delta);
3641         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3642                            TX_PWR_CFG_0_CCK1_CH0, txpower);
3643         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3644                            TX_PWR_CFG_0_CCK1_CH1, txpower);
3645         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3646                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3647
3648         /* CCK 5.5MBS,11MBS */
3649         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3650         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3651                                             txpower, delta);
3652         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3653                            TX_PWR_CFG_0_CCK5_CH0, txpower);
3654         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3655                            TX_PWR_CFG_0_CCK5_CH1, txpower);
3656         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3657                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3658
3659         /* OFDM 6MBS,9MBS */
3660         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3661         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3662                                             txpower, delta);
3663         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3664                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
3665         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3666                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
3667         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3668                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3669
3670         /* OFDM 12MBS,18MBS */
3671         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3672         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3673                                             txpower, delta);
3674         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3675                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
3676         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3677                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
3678         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3679                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3680
3681         /* read the next four txpower values */
3682         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3683                                       offset + 1, &eeprom);
3684
3685         /* OFDM 24MBS,36MBS */
3686         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3687         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3688                                             txpower, delta);
3689         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3690                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
3691         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3692                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
3693         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3694                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3695
3696         /* OFDM 48MBS */
3697         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3698         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3699                                             txpower, delta);
3700         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3701                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
3702         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3703                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
3704         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3705                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3706
3707         /* OFDM 54MBS */
3708         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3709         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3710                                             txpower, delta);
3711         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3712                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
3713         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3714                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
3715         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3716                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
3717
3718         /* read the next four txpower values */
3719         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3720                                       offset + 2, &eeprom);
3721
3722         /* MCS 0,1 */
3723         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3724         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3725                                             txpower, delta);
3726         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3727                            TX_PWR_CFG_1_MCS0_CH0, txpower);
3728         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3729                            TX_PWR_CFG_1_MCS0_CH1, txpower);
3730         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3731                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3732
3733         /* MCS 2,3 */
3734         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3735         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3736                                             txpower, delta);
3737         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3738                            TX_PWR_CFG_1_MCS2_CH0, txpower);
3739         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3740                            TX_PWR_CFG_1_MCS2_CH1, txpower);
3741         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3742                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3743
3744         /* MCS 4,5 */
3745         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3746         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3747                                             txpower, delta);
3748         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3749                            TX_PWR_CFG_2_MCS4_CH0, txpower);
3750         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3751                            TX_PWR_CFG_2_MCS4_CH1, txpower);
3752         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3753                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3754
3755         /* MCS 6 */
3756         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3757         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3758                                             txpower, delta);
3759         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3760                            TX_PWR_CFG_2_MCS6_CH0, txpower);
3761         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3762                            TX_PWR_CFG_2_MCS6_CH1, txpower);
3763         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3764                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3765
3766         /* read the next four txpower values */
3767         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3768                                       offset + 3, &eeprom);
3769
3770         /* MCS 7 */
3771         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3772         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3773                                             txpower, delta);
3774         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3775                            TX_PWR_CFG_7_MCS7_CH0, txpower);
3776         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3777                            TX_PWR_CFG_7_MCS7_CH1, txpower);
3778         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3779                            TX_PWR_CFG_7_MCS7_CH2, txpower);
3780
3781         /* MCS 8,9 */
3782         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3783         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3784                                             txpower, delta);
3785         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3786                            TX_PWR_CFG_2_MCS8_CH0, txpower);
3787         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3788                            TX_PWR_CFG_2_MCS8_CH1, txpower);
3789         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3790                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3791
3792         /* MCS 10,11 */
3793         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3794         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3795                                             txpower, delta);
3796         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3797                            TX_PWR_CFG_2_MCS10_CH0, txpower);
3798         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3799                            TX_PWR_CFG_2_MCS10_CH1, txpower);
3800         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3801                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3802
3803         /* MCS 12,13 */
3804         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3805         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3806                                             txpower, delta);
3807         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3808                            TX_PWR_CFG_3_MCS12_CH0, txpower);
3809         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3810                            TX_PWR_CFG_3_MCS12_CH1, txpower);
3811         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3812                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3813
3814         /* read the next four txpower values */
3815         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3816                                       offset + 4, &eeprom);
3817
3818         /* MCS 14 */
3819         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3820         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3821                                             txpower, delta);
3822         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3823                            TX_PWR_CFG_3_MCS14_CH0, txpower);
3824         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3825                            TX_PWR_CFG_3_MCS14_CH1, txpower);
3826         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3827                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3828
3829         /* MCS 15 */
3830         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3831         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3832                                             txpower, delta);
3833         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3834                            TX_PWR_CFG_8_MCS15_CH0, txpower);
3835         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3836                            TX_PWR_CFG_8_MCS15_CH1, txpower);
3837         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3838                            TX_PWR_CFG_8_MCS15_CH2, txpower);
3839
3840         /* MCS 16,17 */
3841         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3842         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3843                                             txpower, delta);
3844         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3845                            TX_PWR_CFG_5_MCS16_CH0, txpower);
3846         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3847                            TX_PWR_CFG_5_MCS16_CH1, txpower);
3848         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3849                            TX_PWR_CFG_5_MCS16_CH2, txpower);
3850
3851         /* MCS 18,19 */
3852         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3853         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3854                                             txpower, delta);
3855         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3856                            TX_PWR_CFG_5_MCS18_CH0, txpower);
3857         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3858                            TX_PWR_CFG_5_MCS18_CH1, txpower);
3859         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3860                            TX_PWR_CFG_5_MCS18_CH2, txpower);
3861
3862         /* read the next four txpower values */
3863         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3864                                       offset + 5, &eeprom);
3865
3866         /* MCS 20,21 */
3867         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3868         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3869                                             txpower, delta);
3870         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3871                            TX_PWR_CFG_6_MCS20_CH0, txpower);
3872         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3873                            TX_PWR_CFG_6_MCS20_CH1, txpower);
3874         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3875                            TX_PWR_CFG_6_MCS20_CH2, txpower);
3876
3877         /* MCS 22 */
3878         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3879         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3880                                             txpower, delta);
3881         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3882                            TX_PWR_CFG_6_MCS22_CH0, txpower);
3883         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3884                            TX_PWR_CFG_6_MCS22_CH1, txpower);
3885         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3886                            TX_PWR_CFG_6_MCS22_CH2, txpower);
3887
3888         /* MCS 23 */
3889         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3890         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3891                                             txpower, delta);
3892         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3893                            TX_PWR_CFG_8_MCS23_CH0, txpower);
3894         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3895                            TX_PWR_CFG_8_MCS23_CH1, txpower);
3896         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3897                            TX_PWR_CFG_8_MCS23_CH2, txpower);
3898
3899         /* read the next four txpower values */
3900         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3901                                       offset + 6, &eeprom);
3902
3903         /* STBC, MCS 0,1 */
3904         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3905         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3906                                             txpower, delta);
3907         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3908                            TX_PWR_CFG_3_STBC0_CH0, txpower);
3909         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3910                            TX_PWR_CFG_3_STBC0_CH1, txpower);
3911         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3912                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3913
3914         /* STBC, MCS 2,3 */
3915         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3916         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3917                                             txpower, delta);
3918         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3919                            TX_PWR_CFG_3_STBC2_CH0, txpower);
3920         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3921                            TX_PWR_CFG_3_STBC2_CH1, txpower);
3922         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3923                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3924
3925         /* STBC, MCS 4,5 */
3926         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3927         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3928                                             txpower, delta);
3929         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3930         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3931         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3932                            txpower);
3933
3934         /* STBC, MCS 6 */
3935         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3936         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3937                                             txpower, delta);
3938         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3939         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3940         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3941                            txpower);
3942
3943         /* read the next four txpower values */
3944         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3945                                       offset + 7, &eeprom);
3946
3947         /* STBC, MCS 7 */
3948         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3949         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3950                                             txpower, delta);
3951         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3952                            TX_PWR_CFG_9_STBC7_CH0, txpower);
3953         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3954                            TX_PWR_CFG_9_STBC7_CH1, txpower);
3955         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3956                            TX_PWR_CFG_9_STBC7_CH2, txpower);
3957
3958         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
3959         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
3960         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
3961         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
3962         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
3963         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
3964         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
3965         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
3966         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
3967         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
3968
3969         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
3970                               regs[TX_PWR_CFG_0_EXT_IDX]);
3971         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
3972                               regs[TX_PWR_CFG_1_EXT_IDX]);
3973         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
3974                               regs[TX_PWR_CFG_2_EXT_IDX]);
3975         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
3976                               regs[TX_PWR_CFG_3_EXT_IDX]);
3977         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
3978                               regs[TX_PWR_CFG_4_EXT_IDX]);
3979
3980         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
3981                 rt2x00_dbg(rt2x00dev,
3982                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
3983                            (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
3984                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
3985                                                                 '4' : '2',
3986                            (i > TX_PWR_CFG_9_IDX) ?
3987                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
3988                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
3989                            (unsigned long) regs[i]);
3990 }
3991
3992 /*
3993  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
3994  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
3995  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
3996  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
3997  * Reference per rate transmit power values are located in the EEPROM at
3998  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
3999  * current conditions (i.e. band, bandwidth, temperature, user settings).
4000  */
4001 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4002                                          struct ieee80211_channel *chan,
4003                                          int power_level)
4004 {
4005         u8 txpower, r1;
4006         u16 eeprom;
4007         u32 reg, offset;
4008         int i, is_rate_b, delta, power_ctrl;
4009         enum ieee80211_band band = chan->band;
4010
4011         /*
4012          * Calculate HT40 compensation. For 40MHz we need to add or subtract
4013          * value read from EEPROM (different for 2GHz and for 5GHz).
4014          */
4015         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4016
4017         /*
4018          * Calculate temperature compensation. Depends on measurement of current
4019          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4020          * to temperature or maybe other factors) is smaller or bigger than
4021          * expected. We adjust it, based on TSSI reference and boundaries values
4022          * provided in EEPROM.
4023          */
4024         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4025
4026         /*
4027          * Decrease power according to user settings, on devices with unknown
4028          * maximum tx power. For other devices we take user power_level into
4029          * consideration on rt2800_compensate_txpower().
4030          */
4031         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4032                                               chan->max_power);
4033
4034         /*
4035          * BBP_R1 controls TX power for all rates, it allow to set the following
4036          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4037          *
4038          * TODO: we do not use +6 dBm option to do not increase power beyond
4039          * regulatory limit, however this could be utilized for devices with
4040          * CAPABILITY_POWER_LIMIT.
4041          *
4042          * TODO: add different temperature compensation code for RT3290 & RT5390
4043          * to allow to use BBP_R1 for those chips.
4044          */
4045         if (!rt2x00_rt(rt2x00dev, RT3290) &&
4046             !rt2x00_rt(rt2x00dev, RT5390)) {
4047                 rt2800_bbp_read(rt2x00dev, 1, &r1);
4048                 if (delta <= -12) {
4049                         power_ctrl = 2;
4050                         delta += 12;
4051                 } else if (delta <= -6) {
4052                         power_ctrl = 1;
4053                         delta += 6;
4054                 } else {
4055                         power_ctrl = 0;
4056                 }
4057                 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4058                 rt2800_bbp_write(rt2x00dev, 1, r1);
4059         }
4060
4061         offset = TX_PWR_CFG_0;
4062
4063         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4064                 /* just to be safe */
4065                 if (offset > TX_PWR_CFG_4)
4066                         break;
4067
4068                 rt2800_register_read(rt2x00dev, offset, &reg);
4069
4070                 /* read the next four txpower values */
4071                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4072                                               i, &eeprom);
4073
4074                 is_rate_b = i ? 0 : 1;
4075                 /*
4076                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4077                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4078                  * TX_PWR_CFG_4: unknown
4079                  */
4080                 txpower = rt2x00_get_field16(eeprom,
4081                                              EEPROM_TXPOWER_BYRATE_RATE0);
4082                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4083                                              power_level, txpower, delta);
4084                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4085
4086                 /*
4087                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4088                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4089                  * TX_PWR_CFG_4: unknown
4090                  */
4091                 txpower = rt2x00_get_field16(eeprom,
4092                                              EEPROM_TXPOWER_BYRATE_RATE1);
4093                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4094                                              power_level, txpower, delta);
4095                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4096
4097                 /*
4098                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4099                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
4100                  * TX_PWR_CFG_4: unknown
4101                  */
4102                 txpower = rt2x00_get_field16(eeprom,
4103                                              EEPROM_TXPOWER_BYRATE_RATE2);
4104                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4105                                              power_level, txpower, delta);
4106                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4107
4108                 /*
4109                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4110                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
4111                  * TX_PWR_CFG_4: unknown
4112                  */
4113                 txpower = rt2x00_get_field16(eeprom,
4114                                              EEPROM_TXPOWER_BYRATE_RATE3);
4115                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4116                                              power_level, txpower, delta);
4117                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4118
4119                 /* read the next four txpower values */
4120                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4121                                               i + 1, &eeprom);
4122
4123                 is_rate_b = 0;
4124                 /*
4125                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4126                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4127                  * TX_PWR_CFG_4: unknown
4128                  */
4129                 txpower = rt2x00_get_field16(eeprom,
4130                                              EEPROM_TXPOWER_BYRATE_RATE0);
4131                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4132                                              power_level, txpower, delta);
4133                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4134
4135                 /*
4136                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4137                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4138                  * TX_PWR_CFG_4: unknown
4139                  */
4140                 txpower = rt2x00_get_field16(eeprom,
4141                                              EEPROM_TXPOWER_BYRATE_RATE1);
4142                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4143                                              power_level, txpower, delta);
4144                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4145
4146                 /*
4147                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4148                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4149                  * TX_PWR_CFG_4: unknown
4150                  */
4151                 txpower = rt2x00_get_field16(eeprom,
4152                                              EEPROM_TXPOWER_BYRATE_RATE2);
4153                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4154                                              power_level, txpower, delta);
4155                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4156
4157                 /*
4158                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4159                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4160                  * TX_PWR_CFG_4: unknown
4161                  */
4162                 txpower = rt2x00_get_field16(eeprom,
4163                                              EEPROM_TXPOWER_BYRATE_RATE3);
4164                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4165                                              power_level, txpower, delta);
4166                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4167
4168                 rt2800_register_write(rt2x00dev, offset, reg);
4169
4170                 /* next TX_PWR_CFG register */
4171                 offset += 4;
4172         }
4173 }
4174
4175 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4176                                   struct ieee80211_channel *chan,
4177                                   int power_level)
4178 {
4179         if (rt2x00_rt(rt2x00dev, RT3593))
4180                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4181         else
4182                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4183 }
4184
4185 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4186 {
4187         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4188                               rt2x00dev->tx_power);
4189 }
4190 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4191
4192 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4193 {
4194         u32     tx_pin;
4195         u8      rfcsr;
4196
4197         /*
4198          * A voltage-controlled oscillator(VCO) is an electronic oscillator
4199          * designed to be controlled in oscillation frequency by a voltage
4200          * input. Maybe the temperature will affect the frequency of
4201          * oscillation to be shifted. The VCO calibration will be called
4202          * periodically to adjust the frequency to be precision.
4203         */
4204
4205         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4206         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4207         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4208
4209         switch (rt2x00dev->chip.rf) {
4210         case RF2020:
4211         case RF3020:
4212         case RF3021:
4213         case RF3022:
4214         case RF3320:
4215         case RF3052:
4216                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4217                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4218                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4219                 break;
4220         case RF3053:
4221         case RF3290:
4222         case RF5360:
4223         case RF5370:
4224         case RF5372:
4225         case RF5390:
4226         case RF5392:
4227                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
4228                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4229                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4230                 break;
4231         default:
4232                 return;
4233         }
4234
4235         mdelay(1);
4236
4237         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4238         if (rt2x00dev->rf_channel <= 14) {
4239                 switch (rt2x00dev->default_ant.tx_chain_num) {
4240                 case 3:
4241                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4242                         /* fall through */
4243                 case 2:
4244                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4245                         /* fall through */
4246                 case 1:
4247                 default:
4248                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4249                         break;
4250                 }
4251         } else {
4252                 switch (rt2x00dev->default_ant.tx_chain_num) {
4253                 case 3:
4254                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4255                         /* fall through */
4256                 case 2:
4257                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4258                         /* fall through */
4259                 case 1:
4260                 default:
4261                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4262                         break;
4263                 }
4264         }
4265         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4266
4267 }
4268 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4269
4270 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4271                                       struct rt2x00lib_conf *libconf)
4272 {
4273         u32 reg;
4274
4275         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4276         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4277                            libconf->conf->short_frame_max_tx_count);
4278         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4279                            libconf->conf->long_frame_max_tx_count);
4280         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4281 }
4282
4283 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4284                              struct rt2x00lib_conf *libconf)
4285 {
4286         enum dev_state state =
4287             (libconf->conf->flags & IEEE80211_CONF_PS) ?
4288                 STATE_SLEEP : STATE_AWAKE;
4289         u32 reg;
4290
4291         if (state == STATE_SLEEP) {
4292                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4293
4294                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4295                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4296                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4297                                    libconf->conf->listen_interval - 1);
4298                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4299                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4300
4301                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4302         } else {
4303                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4304                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4305                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4306                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4307                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4308
4309                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4310         }
4311 }
4312
4313 void rt2800_config(struct rt2x00_dev *rt2x00dev,
4314                    struct rt2x00lib_conf *libconf,
4315                    const unsigned int flags)
4316 {
4317         /* Always recalculate LNA gain before changing configuration */
4318         rt2800_config_lna_gain(rt2x00dev, libconf);
4319
4320         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
4321                 rt2800_config_channel(rt2x00dev, libconf->conf,
4322                                       &libconf->rf, &libconf->channel);
4323                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4324                                       libconf->conf->power_level);
4325         }
4326         if (flags & IEEE80211_CONF_CHANGE_POWER)
4327                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4328                                       libconf->conf->power_level);
4329         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4330                 rt2800_config_retry_limit(rt2x00dev, libconf);
4331         if (flags & IEEE80211_CONF_CHANGE_PS)
4332                 rt2800_config_ps(rt2x00dev, libconf);
4333 }
4334 EXPORT_SYMBOL_GPL(rt2800_config);
4335
4336 /*
4337  * Link tuning
4338  */
4339 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4340 {
4341         u32 reg;
4342
4343         /*
4344          * Update FCS error count from register.
4345          */
4346         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4347         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4348 }
4349 EXPORT_SYMBOL_GPL(rt2800_link_stats);
4350
4351 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4352 {
4353         u8 vgc;
4354
4355         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
4356                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4357                     rt2x00_rt(rt2x00dev, RT3071) ||
4358                     rt2x00_rt(rt2x00dev, RT3090) ||
4359                     rt2x00_rt(rt2x00dev, RT3290) ||
4360                     rt2x00_rt(rt2x00dev, RT3390) ||
4361                     rt2x00_rt(rt2x00dev, RT3572) ||
4362                     rt2x00_rt(rt2x00dev, RT5390) ||
4363                     rt2x00_rt(rt2x00dev, RT5392) ||
4364                     rt2x00_rt(rt2x00dev, RT5592))
4365                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4366                 else
4367                         vgc = 0x2e + rt2x00dev->lna_gain;
4368         } else { /* 5GHZ band */
4369                 if (rt2x00_rt(rt2x00dev, RT3572))
4370                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
4371                 else if (rt2x00_rt(rt2x00dev, RT5592))
4372                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
4373                 else {
4374                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4375                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4376                         else
4377                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4378                 }
4379         }
4380
4381         return vgc;
4382 }
4383
4384 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4385                                   struct link_qual *qual, u8 vgc_level)
4386 {
4387         if (qual->vgc_level != vgc_level) {
4388                 if (rt2x00_rt(rt2x00dev, RT5592)) {
4389                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4390                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4391                 } else
4392                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4393                 qual->vgc_level = vgc_level;
4394                 qual->vgc_level_reg = vgc_level;
4395         }
4396 }
4397
4398 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4399 {
4400         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4401 }
4402 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4403
4404 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4405                        const u32 count)
4406 {
4407         u8 vgc;
4408
4409         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4410                 return;
4411         /*
4412          * When RSSI is better then -80 increase VGC level with 0x10, except
4413          * for rt5592 chip.
4414          */
4415
4416         vgc = rt2800_get_default_vgc(rt2x00dev);
4417
4418         if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
4419                 vgc += 0x20;
4420         else if (qual->rssi > -80)
4421                 vgc += 0x10;
4422
4423         rt2800_set_vgc(rt2x00dev, qual, vgc);
4424 }
4425 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4426
4427 /*
4428  * Initialization functions.
4429  */
4430 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4431 {
4432         u32 reg;
4433         u16 eeprom;
4434         unsigned int i;
4435         int ret;
4436
4437         rt2800_disable_wpdma(rt2x00dev);
4438
4439         ret = rt2800_drv_init_registers(rt2x00dev);
4440         if (ret)
4441                 return ret;
4442
4443         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
4444         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
4445         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
4446         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
4447         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
4448         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4449
4450         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
4451         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
4452         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
4453         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
4454         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
4455         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4456
4457         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4458         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4459
4460         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4461
4462         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4463         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4464         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4465         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4466         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4467         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4468         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4469         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4470
4471         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4472
4473         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4474         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4475         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4476         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4477
4478         if (rt2x00_rt(rt2x00dev, RT3290)) {
4479                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4480                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4481                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4482                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4483                 }
4484
4485                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4486                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4487                         rt2x00_set_field32(&reg, LDO0_EN, 1);
4488                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4489                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4490                 }
4491
4492                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4493                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4494                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4495                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4496                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4497
4498                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4499                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4500                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4501
4502                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4503                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4504                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4505                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4506                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4507                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4508
4509                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4510                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4511                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4512         }
4513
4514         if (rt2x00_rt(rt2x00dev, RT3071) ||
4515             rt2x00_rt(rt2x00dev, RT3090) ||
4516             rt2x00_rt(rt2x00dev, RT3290) ||
4517             rt2x00_rt(rt2x00dev, RT3390)) {
4518
4519                 if (rt2x00_rt(rt2x00dev, RT3290))
4520                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4521                                               0x00000404);
4522                 else
4523                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4524                                               0x00000400);
4525
4526                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4527                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4528                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4529                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4530                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4531                                            &eeprom);
4532                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4533                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4534                                                       0x0000002c);
4535                         else
4536                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4537                                                       0x0000000f);
4538                 } else {
4539                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4540                 }
4541         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4542                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4543
4544                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4545                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4546                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4547                 } else {
4548                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4549                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4550                 }
4551         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4552                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4553                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4554                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4555         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4556                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4557                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4558                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4559         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4560                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4561                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4562         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4563                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4564                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4565                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4566                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4567                                            &eeprom);
4568                         if (rt2x00_get_field16(eeprom,
4569                                                EEPROM_NIC_CONF1_DAC_TEST))
4570                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4571                                                       0x0000001f);
4572                         else
4573                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4574                                                       0x0000000f);
4575                 } else {
4576                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4577                                               0x00000000);
4578                 }
4579         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4580                    rt2x00_rt(rt2x00dev, RT5392) ||
4581                    rt2x00_rt(rt2x00dev, RT5592)) {
4582                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4583                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4584                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4585         } else {
4586                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4587                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4588         }
4589
4590         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4591         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4592         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4593         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4594         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4595         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4596         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4597         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4598         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4599         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4600
4601         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4602         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4603         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4604         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4605         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4606
4607         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4608         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4609         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4610             rt2x00_rt(rt2x00dev, RT2883) ||
4611             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4612                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4613         else
4614                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4615         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4616         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4617         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4618
4619         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4620         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4621         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4622         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4623         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4624         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4625         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4626         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4627         rt2800_register_write(rt2x00dev, LED_CFG, reg);
4628
4629         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4630
4631         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4632         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4633         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4634         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4635         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4636         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4637         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4638         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4639
4640         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4641         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4642         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4643         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4644         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4645         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4646         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4647         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4648         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4649
4650         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4651         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4652         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4653         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4654         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4655         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4656         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4657         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4658         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4659         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4660         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4661         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4662
4663         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4664         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4665         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4666         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4667         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4668         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4669         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4670         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4671         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4672         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4673         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4674         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4675
4676         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4677         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4678         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4679         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4680         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4681         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4682         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4683         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4684         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4685         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4686         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4687         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4688
4689         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4690         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4691         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4692         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4693         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4694         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4695         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4696         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4697         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4698         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4699         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4700         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4701
4702         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4703         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4704         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4705         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4706         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4707         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4708         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4709         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4710         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4711         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4712         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4713         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4714
4715         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4716         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4717         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4718         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4719         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4720         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4721         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4722         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4723         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4724         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4725         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4726         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4727
4728         if (rt2x00_is_usb(rt2x00dev)) {
4729                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4730
4731                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4732                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4733                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4734                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4735                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4736                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4737                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4738                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4739                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4740                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4741                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4742         }
4743
4744         /*
4745          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4746          * although it is reserved.
4747          */
4748         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4749         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4750         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4751         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4752         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4753         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4754         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4755         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4756         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4757         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4758         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4759         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4760
4761         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4762         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4763
4764         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4765         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4766         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4767                            IEEE80211_MAX_RTS_THRESHOLD);
4768         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4769         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4770
4771         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4772
4773         /*
4774          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4775          * time should be set to 16. However, the original Ralink driver uses
4776          * 16 for both and indeed using a value of 10 for CCK SIFS results in
4777          * connection problems with 11g + CTS protection. Hence, use the same
4778          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4779          */
4780         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4781         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4782         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4783         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4784         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4785         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4786         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4787
4788         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4789
4790         /*
4791          * ASIC will keep garbage value after boot, clear encryption keys.
4792          */
4793         for (i = 0; i < 4; i++)
4794                 rt2800_register_write(rt2x00dev,
4795                                          SHARED_KEY_MODE_ENTRY(i), 0);
4796
4797         for (i = 0; i < 256; i++) {
4798                 rt2800_config_wcid(rt2x00dev, NULL, i);
4799                 rt2800_delete_wcid_attr(rt2x00dev, i);
4800                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4801         }
4802
4803         /*
4804          * Clear all beacons
4805          */
4806         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
4807         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
4808         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
4809         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
4810         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
4811         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
4812         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
4813         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
4814
4815         if (rt2x00_is_usb(rt2x00dev)) {
4816                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4817                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4818                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4819         } else if (rt2x00_is_pcie(rt2x00dev)) {
4820                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4821                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4822                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4823         }
4824
4825         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4826         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4827         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4828         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4829         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4830         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4831         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4832         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4833         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4834         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4835
4836         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4837         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4838         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4839         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4840         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4841         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4842         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4843         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4844         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4845         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4846
4847         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4848         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4849         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4850         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4851         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4852         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4853         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4854         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4855         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4856         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4857
4858         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4859         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4860         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4861         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4862         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4863         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4864
4865         /*
4866          * Do not force the BA window size, we use the TXWI to set it
4867          */
4868         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4869         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4870         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4871         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4872
4873         /*
4874          * We must clear the error counters.
4875          * These registers are cleared on read,
4876          * so we may pass a useless variable to store the value.
4877          */
4878         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4879         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4880         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4881         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4882         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4883         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4884
4885         /*
4886          * Setup leadtime for pre tbtt interrupt to 6ms
4887          */
4888         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4889         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4890         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4891
4892         /*
4893          * Set up channel statistics timer
4894          */
4895         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4896         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4897         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4898         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4899         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4900         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4901         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4902
4903         return 0;
4904 }
4905
4906 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4907 {
4908         unsigned int i;
4909         u32 reg;
4910
4911         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4912                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4913                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4914                         return 0;
4915
4916                 udelay(REGISTER_BUSY_DELAY);
4917         }
4918
4919         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
4920         return -EACCES;
4921 }
4922
4923 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4924 {
4925         unsigned int i;
4926         u8 value;
4927
4928         /*
4929          * BBP was enabled after firmware was loaded,
4930          * but we need to reactivate it now.
4931          */
4932         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4933         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4934         msleep(1);
4935
4936         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4937                 rt2800_bbp_read(rt2x00dev, 0, &value);
4938                 if ((value != 0xff) && (value != 0x00))
4939                         return 0;
4940                 udelay(REGISTER_BUSY_DELAY);
4941         }
4942
4943         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
4944         return -EACCES;
4945 }
4946
4947 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
4948 {
4949         u8 value;
4950
4951         rt2800_bbp_read(rt2x00dev, 4, &value);
4952         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
4953         rt2800_bbp_write(rt2x00dev, 4, value);
4954 }
4955
4956 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
4957 {
4958         rt2800_bbp_write(rt2x00dev, 142, 1);
4959         rt2800_bbp_write(rt2x00dev, 143, 57);
4960 }
4961
4962 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
4963 {
4964         const u8 glrt_table[] = {
4965                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
4966                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
4967                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
4968                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
4969                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
4970                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
4971                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
4972                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
4973                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
4974         };
4975         int i;
4976
4977         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
4978                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
4979                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
4980         }
4981 };
4982
4983 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
4984 {
4985         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
4986         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4987         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
4988         rt2800_bbp_write(rt2x00dev, 69, 0x12);
4989         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4990         rt2800_bbp_write(rt2x00dev, 73, 0x10);
4991         rt2800_bbp_write(rt2x00dev, 81, 0x37);
4992         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4993         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
4994         rt2800_bbp_write(rt2x00dev, 84, 0x99);
4995         rt2800_bbp_write(rt2x00dev, 86, 0x00);
4996         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4997         rt2800_bbp_write(rt2x00dev, 92, 0x00);
4998         rt2800_bbp_write(rt2x00dev, 103, 0x00);
4999         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5000         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5001 }
5002
5003 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5004 {
5005         u16 eeprom;
5006         u8 value;
5007
5008         rt2800_bbp_read(rt2x00dev, 138, &value);
5009         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5010         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5011                 value |= 0x20;
5012         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5013                 value &= ~0x02;
5014         rt2800_bbp_write(rt2x00dev, 138, value);
5015 }
5016
5017 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5018 {
5019         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5020
5021         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5022         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5023
5024         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5025         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5026
5027         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5028
5029         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5030         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5031
5032         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5033
5034         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5035
5036         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5037
5038         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5039
5040         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5041
5042         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5043
5044         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5045
5046         rt2800_bbp_write(rt2x00dev, 105, 0x01);
5047
5048         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5049 }
5050
5051 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5052 {
5053         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5054         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5055
5056         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5057                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5058                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5059         } else {
5060                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5061                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5062         }
5063
5064         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5065
5066         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5067
5068         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5069
5070         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5071
5072         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5073                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5074         else
5075                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5076
5077         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5078
5079         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5080
5081         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5082
5083         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5084
5085         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5086
5087         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5088 }
5089
5090 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5091 {
5092         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5093         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5094
5095         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5096         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5097
5098         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5099
5100         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5101         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5102         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5103
5104         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5105
5106         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5107
5108         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5109
5110         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5111
5112         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5113
5114         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5115
5116         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5117             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5118             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5119                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5120         else
5121                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5122
5123         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5124
5125         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5126
5127         if (rt2x00_rt(rt2x00dev, RT3071) ||
5128             rt2x00_rt(rt2x00dev, RT3090))
5129                 rt2800_disable_unused_dac_adc(rt2x00dev);
5130 }
5131
5132 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5133 {
5134         u8 value;
5135
5136         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5137
5138         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5139
5140         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5141         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5142
5143         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5144
5145         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5146         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5147         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5148         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5149
5150         rt2800_bbp_write(rt2x00dev, 77, 0x58);
5151
5152         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5153
5154         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5155         rt2800_bbp_write(rt2x00dev, 79, 0x18);
5156         rt2800_bbp_write(rt2x00dev, 80, 0x09);
5157         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5158
5159         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5160
5161         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5162
5163         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5164
5165         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5166
5167         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5168
5169         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5170
5171         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5172
5173         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5174
5175         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5176
5177         rt2800_bbp_write(rt2x00dev, 106, 0x03);
5178
5179         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5180
5181         rt2800_bbp_write(rt2x00dev, 67, 0x24);
5182         rt2800_bbp_write(rt2x00dev, 143, 0x04);
5183         rt2800_bbp_write(rt2x00dev, 142, 0x99);
5184         rt2800_bbp_write(rt2x00dev, 150, 0x30);
5185         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5186         rt2800_bbp_write(rt2x00dev, 152, 0x20);
5187         rt2800_bbp_write(rt2x00dev, 153, 0x34);
5188         rt2800_bbp_write(rt2x00dev, 154, 0x40);
5189         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5190         rt2800_bbp_write(rt2x00dev, 253, 0x04);
5191
5192         rt2800_bbp_read(rt2x00dev, 47, &value);
5193         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5194         rt2800_bbp_write(rt2x00dev, 47, value);
5195
5196         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5197         rt2800_bbp_read(rt2x00dev, 3, &value);
5198         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5199         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5200         rt2800_bbp_write(rt2x00dev, 3, value);
5201 }
5202
5203 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5204 {
5205         rt2800_bbp_write(rt2x00dev, 3, 0x00);
5206         rt2800_bbp_write(rt2x00dev, 4, 0x50);
5207
5208         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5209
5210         rt2800_bbp_write(rt2x00dev, 47, 0x48);
5211
5212         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5213         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5214
5215         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5216
5217         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5218         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5219         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5220         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5221
5222         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5223
5224         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5225
5226         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5227         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5228         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5229
5230         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5231
5232         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5233
5234         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5235
5236         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5237
5238         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5239
5240         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5241
5242         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5243
5244         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5245
5246         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5247
5248         rt2800_bbp_write(rt2x00dev, 105, 0x34);
5249
5250         rt2800_bbp_write(rt2x00dev, 106, 0x05);
5251
5252         rt2800_bbp_write(rt2x00dev, 120, 0x50);
5253
5254         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5255
5256         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5257         /* Set ITxBF timeout to 0x9c40=1000msec */
5258         rt2800_bbp_write(rt2x00dev, 179, 0x02);
5259         rt2800_bbp_write(rt2x00dev, 180, 0x00);
5260         rt2800_bbp_write(rt2x00dev, 182, 0x40);
5261         rt2800_bbp_write(rt2x00dev, 180, 0x01);
5262         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5263         rt2800_bbp_write(rt2x00dev, 179, 0x00);
5264         /* Reprogram the inband interface to put right values in RXWI */
5265         rt2800_bbp_write(rt2x00dev, 142, 0x04);
5266         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5267         rt2800_bbp_write(rt2x00dev, 142, 0x06);
5268         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5269         rt2800_bbp_write(rt2x00dev, 142, 0x07);
5270         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5271         rt2800_bbp_write(rt2x00dev, 142, 0x08);
5272         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5273
5274         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5275 }
5276
5277 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5278 {
5279         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5280         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5281
5282         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5283         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5284
5285         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5286
5287         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5288         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5289         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5290
5291         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5292
5293         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5294
5295         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5296
5297         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5298
5299         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5300
5301         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5302
5303         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5304                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5305         else
5306                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5307
5308         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5309
5310         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5311
5312         rt2800_disable_unused_dac_adc(rt2x00dev);
5313 }
5314
5315 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5316 {
5317         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5318
5319         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5320         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5321
5322         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5323         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5324
5325         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5326
5327         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5328         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5329         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5330
5331         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5332
5333         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5334
5335         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5336
5337         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5338
5339         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5340
5341         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5342
5343         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5344
5345         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5346
5347         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5348
5349         rt2800_disable_unused_dac_adc(rt2x00dev);
5350 }
5351
5352 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5353 {
5354         rt2800_init_bbp_early(rt2x00dev);
5355
5356         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5357         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5358         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5359         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5360
5361         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5362
5363         /* Enable DC filter */
5364         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5365                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5366 }
5367
5368 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5369 {
5370         int ant, div_mode;
5371         u16 eeprom;
5372         u8 value;
5373
5374         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5375
5376         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5377
5378         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5379         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5380
5381         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5382
5383         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5384         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5385         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5386         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5387
5388         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5389
5390         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5391
5392         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5393         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5394         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5395
5396         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5397
5398         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5399
5400         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5401
5402         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5403
5404         if (rt2x00_rt(rt2x00dev, RT5392))
5405                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5406
5407         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5408
5409         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5410
5411         if (rt2x00_rt(rt2x00dev, RT5392)) {
5412                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5413                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5414         }
5415
5416         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5417
5418         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5419
5420         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5421
5422         if (rt2x00_rt(rt2x00dev, RT5390))
5423                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5424         else if (rt2x00_rt(rt2x00dev, RT5392))
5425                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5426         else
5427                 WARN_ON(1);
5428
5429         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5430
5431         if (rt2x00_rt(rt2x00dev, RT5392)) {
5432                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5433                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5434         }
5435
5436         rt2800_disable_unused_dac_adc(rt2x00dev);
5437
5438         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5439         div_mode = rt2x00_get_field16(eeprom,
5440                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
5441         ant = (div_mode == 3) ? 1 : 0;
5442
5443         /* check if this is a Bluetooth combo card */
5444         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5445                 u32 reg;
5446
5447                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5448                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5449                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5450                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5451                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5452                 if (ant == 0)
5453                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5454                 else if (ant == 1)
5455                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5456                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5457         }
5458
5459         /* This chip has hardware antenna diversity*/
5460         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5461                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5462                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5463                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5464         }
5465
5466         rt2800_bbp_read(rt2x00dev, 152, &value);
5467         if (ant == 0)
5468                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5469         else
5470                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5471         rt2800_bbp_write(rt2x00dev, 152, value);
5472
5473         rt2800_init_freq_calibration(rt2x00dev);
5474 }
5475
5476 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5477 {
5478         int ant, div_mode;
5479         u16 eeprom;
5480         u8 value;
5481
5482         rt2800_init_bbp_early(rt2x00dev);
5483
5484         rt2800_bbp_read(rt2x00dev, 105, &value);
5485         rt2x00_set_field8(&value, BBP105_MLD,
5486                           rt2x00dev->default_ant.rx_chain_num == 2);
5487         rt2800_bbp_write(rt2x00dev, 105, value);
5488
5489         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5490
5491         rt2800_bbp_write(rt2x00dev, 20, 0x06);
5492         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5493         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5494         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5495         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5496         rt2800_bbp_write(rt2x00dev, 70, 0x05);
5497         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5498         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5499         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5500         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5501         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5502         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5503         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5504         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5505         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5506         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5507         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5508         rt2800_bbp_write(rt2x00dev, 98, 0x12);
5509         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5510         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5511         /* FIXME BBP105 owerwrite */
5512         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5513         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5514         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5515         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5516         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5517         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5518
5519         /* Initialize GLRT (Generalized Likehood Radio Test) */
5520         rt2800_init_bbp_5592_glrt(rt2x00dev);
5521
5522         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5523
5524         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5525         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5526         ant = (div_mode == 3) ? 1 : 0;
5527         rt2800_bbp_read(rt2x00dev, 152, &value);
5528         if (ant == 0) {
5529                 /* Main antenna */
5530                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5531         } else {
5532                 /* Auxiliary antenna */
5533                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5534         }
5535         rt2800_bbp_write(rt2x00dev, 152, value);
5536
5537         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5538                 rt2800_bbp_read(rt2x00dev, 254, &value);
5539                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5540                 rt2800_bbp_write(rt2x00dev, 254, value);
5541         }
5542
5543         rt2800_init_freq_calibration(rt2x00dev);
5544
5545         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5546         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5547                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5548 }
5549
5550 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5551 {
5552         unsigned int i;
5553         u16 eeprom;
5554         u8 reg_id;
5555         u8 value;
5556
5557         if (rt2800_is_305x_soc(rt2x00dev))
5558                 rt2800_init_bbp_305x_soc(rt2x00dev);
5559
5560         switch (rt2x00dev->chip.rt) {
5561         case RT2860:
5562         case RT2872:
5563         case RT2883:
5564                 rt2800_init_bbp_28xx(rt2x00dev);
5565                 break;
5566         case RT3070:
5567         case RT3071:
5568         case RT3090:
5569                 rt2800_init_bbp_30xx(rt2x00dev);
5570                 break;
5571         case RT3290:
5572                 rt2800_init_bbp_3290(rt2x00dev);
5573                 break;
5574         case RT3352:
5575                 rt2800_init_bbp_3352(rt2x00dev);
5576                 break;
5577         case RT3390:
5578                 rt2800_init_bbp_3390(rt2x00dev);
5579                 break;
5580         case RT3572:
5581                 rt2800_init_bbp_3572(rt2x00dev);
5582                 break;
5583         case RT3593:
5584                 rt2800_init_bbp_3593(rt2x00dev);
5585                 return;
5586         case RT5390:
5587         case RT5392:
5588                 rt2800_init_bbp_53xx(rt2x00dev);
5589                 break;
5590         case RT5592:
5591                 rt2800_init_bbp_5592(rt2x00dev);
5592                 return;
5593         }
5594
5595         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5596                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5597                                               &eeprom);
5598
5599                 if (eeprom != 0xffff && eeprom != 0x0000) {
5600                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5601                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5602                         rt2800_bbp_write(rt2x00dev, reg_id, value);
5603                 }
5604         }
5605 }
5606
5607 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5608 {
5609         u32 reg;
5610
5611         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5612         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5613         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5614 }
5615
5616 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5617                                 u8 filter_target)
5618 {
5619         unsigned int i;
5620         u8 bbp;
5621         u8 rfcsr;
5622         u8 passband;
5623         u8 stopband;
5624         u8 overtuned = 0;
5625         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5626
5627         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5628
5629         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5630         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5631         rt2800_bbp_write(rt2x00dev, 4, bbp);
5632
5633         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5634         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5635         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5636
5637         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5638         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5639         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5640
5641         /*
5642          * Set power & frequency of passband test tone
5643          */
5644         rt2800_bbp_write(rt2x00dev, 24, 0);
5645
5646         for (i = 0; i < 100; i++) {
5647                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5648                 msleep(1);
5649
5650                 rt2800_bbp_read(rt2x00dev, 55, &passband);
5651                 if (passband)
5652                         break;
5653         }
5654
5655         /*
5656          * Set power & frequency of stopband test tone
5657          */
5658         rt2800_bbp_write(rt2x00dev, 24, 0x06);
5659
5660         for (i = 0; i < 100; i++) {
5661                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5662                 msleep(1);
5663
5664                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5665
5666                 if ((passband - stopband) <= filter_target) {
5667                         rfcsr24++;
5668                         overtuned += ((passband - stopband) == filter_target);
5669                 } else
5670                         break;
5671
5672                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5673         }
5674
5675         rfcsr24 -= !!overtuned;
5676
5677         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5678         return rfcsr24;
5679 }
5680
5681 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5682                                        const unsigned int rf_reg)
5683 {
5684         u8 rfcsr;
5685
5686         rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5687         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5688         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5689         msleep(1);
5690         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5691         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5692 }
5693
5694 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5695 {
5696         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5697         u8 filter_tgt_bw20;
5698         u8 filter_tgt_bw40;
5699         u8 rfcsr, bbp;
5700
5701         /*
5702          * TODO: sync filter_tgt values with vendor driver
5703          */
5704         if (rt2x00_rt(rt2x00dev, RT3070)) {
5705                 filter_tgt_bw20 = 0x16;
5706                 filter_tgt_bw40 = 0x19;
5707         } else {
5708                 filter_tgt_bw20 = 0x13;
5709                 filter_tgt_bw40 = 0x15;
5710         }
5711
5712         drv_data->calibration_bw20 =
5713                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5714         drv_data->calibration_bw40 =
5715                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5716
5717         /*
5718          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5719          */
5720         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5721         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5722
5723         /*
5724          * Set back to initial state
5725          */
5726         rt2800_bbp_write(rt2x00dev, 24, 0);
5727
5728         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5729         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5730         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5731
5732         /*
5733          * Set BBP back to BW20
5734          */
5735         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5736         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5737         rt2800_bbp_write(rt2x00dev, 4, bbp);
5738 }
5739
5740 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5741 {
5742         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5743         u8 min_gain, rfcsr, bbp;
5744         u16 eeprom;
5745
5746         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5747
5748         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5749         if (rt2x00_rt(rt2x00dev, RT3070) ||
5750             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5751             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5752             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5753                 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5754                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5755         }
5756
5757         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5758         if (drv_data->txmixer_gain_24g >= min_gain) {
5759                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5760                                   drv_data->txmixer_gain_24g);
5761         }
5762
5763         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5764
5765         if (rt2x00_rt(rt2x00dev, RT3090)) {
5766                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5767                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5768                 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5769                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5770                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5771                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5772                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5773                 rt2800_bbp_write(rt2x00dev, 138, bbp);
5774         }
5775
5776         if (rt2x00_rt(rt2x00dev, RT3070)) {
5777                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5778                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5779                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5780                 else
5781                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5782                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5783                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5784                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5785                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5786         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5787                    rt2x00_rt(rt2x00dev, RT3090) ||
5788                    rt2x00_rt(rt2x00dev, RT3390)) {
5789                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5790                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5791                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5792                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5793                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5794                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5795                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5796
5797                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5798                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5799                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5800
5801                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5802                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5803                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5804
5805                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5806                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5807                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5808         }
5809 }
5810
5811 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5812 {
5813         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5814         u8 rfcsr;
5815         u8 tx_gain;
5816
5817         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5818         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5819         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5820
5821         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5822         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5823                                     RFCSR17_TXMIXER_GAIN);
5824         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5825         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5826
5827         rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5828         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5829         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5830
5831         rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5832         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5833         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5834
5835         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5836         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5837         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5838         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5839
5840         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5841         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5842         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5843
5844         /* TODO: enable stream mode */
5845 }
5846
5847 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5848 {
5849         u8 reg;
5850         u16 eeprom;
5851
5852         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5853         rt2800_bbp_read(rt2x00dev, 138, &reg);
5854         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5855         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5856                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5857         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5858                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5859         rt2800_bbp_write(rt2x00dev, 138, reg);
5860
5861         rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5862         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5863         rt2800_rfcsr_write(rt2x00dev, 38, reg);
5864
5865         rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5866         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5867         rt2800_rfcsr_write(rt2x00dev, 39, reg);
5868
5869         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5870
5871         rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5872         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5873         rt2800_rfcsr_write(rt2x00dev, 30, reg);
5874 }
5875
5876 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5877 {
5878         rt2800_rf_init_calibration(rt2x00dev, 30);
5879
5880         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5881         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5882         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5883         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5884         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5885         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5886         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5887         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5888         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5889         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5890         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5891         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5892         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5893         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5894         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5895         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5896         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5897         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5898         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5899         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5900         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5901         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5902         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5903         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5904         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5905         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5906         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5907         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5908         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5909         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5910         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5911         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5912 }
5913
5914 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5915 {
5916         u8 rfcsr;
5917         u16 eeprom;
5918         u32 reg;
5919
5920         /* XXX vendor driver do this only for 3070 */
5921         rt2800_rf_init_calibration(rt2x00dev, 30);
5922
5923         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5924         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5925         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5926         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5927         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5928         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5929         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5930         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5931         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5932         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5933         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5934         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5935         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5936         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5937         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5938         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5939         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5940         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5941         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
5942
5943         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5944                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5945                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5946                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5947                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5948         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5949                    rt2x00_rt(rt2x00dev, RT3090)) {
5950                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
5951
5952                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5953                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5954                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5955
5956                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5957                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5958                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5959                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
5960                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
5961                                            &eeprom);
5962                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5963                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5964                         else
5965                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5966                 }
5967                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5968
5969                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5970                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5971                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5972         }
5973
5974         rt2800_rx_filter_calibration(rt2x00dev);
5975
5976         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
5977             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5978             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
5979                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5980
5981         rt2800_led_open_drain_enable(rt2x00dev);
5982         rt2800_normal_mode_setup_3xxx(rt2x00dev);
5983 }
5984
5985 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
5986 {
5987         u8 rfcsr;
5988
5989         rt2800_rf_init_calibration(rt2x00dev, 2);
5990
5991         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5992         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5993         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5994         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5995         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5996         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
5997         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5998         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5999         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6000         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6001         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6002         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6003         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6004         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6005         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6006         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6007         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6008         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6009         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6010         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6011         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6012         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6013         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6014         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6015         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6016         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6017         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6018         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6019         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6020         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6021         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6022         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6023         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6024         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6025         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6026         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6027         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6028         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6029         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6030         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6031         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6032         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6033         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6034         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6035         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6036         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
6037
6038         rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6039         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6040         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
6041
6042         rt2800_led_open_drain_enable(rt2x00dev);
6043         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6044 }
6045
6046 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6047 {
6048         rt2800_rf_init_calibration(rt2x00dev, 30);
6049
6050         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6051         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6052         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6053         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6054         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6055         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6056         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6057         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6058         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6059         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6060         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6061         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6062         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6063         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6064         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6065         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6066         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6067         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6068         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6069         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6070         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6071         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6072         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6073         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6074         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6075         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6076         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6077         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6078         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6079         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6080         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6081         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6082         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6083         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6084         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6085         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6086         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6087         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6088         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6089         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6090         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6091         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6092         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6093         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6094         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6095         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6096         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6097         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6098         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6099         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6100         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6101         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6102         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6103         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6104         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6105         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6106         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6107         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6108         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6109         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6110         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6111         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6112         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6113
6114         rt2800_rx_filter_calibration(rt2x00dev);
6115         rt2800_led_open_drain_enable(rt2x00dev);
6116         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6117 }
6118
6119 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6120 {
6121         u32 reg;
6122
6123         rt2800_rf_init_calibration(rt2x00dev, 30);
6124
6125         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6126         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6127         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6128         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6129         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6130         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6131         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6132         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6133         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6134         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6135         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6136         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6137         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6138         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6139         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6140         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6141         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6142         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6143         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6144         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6145         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6146         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6147         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6148         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6149         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6150         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6151         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6152         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6153         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6154         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6155         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6156         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
6157
6158         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6159         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6160         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6161
6162         rt2800_rx_filter_calibration(rt2x00dev);
6163
6164         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6165                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6166
6167         rt2800_led_open_drain_enable(rt2x00dev);
6168         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6169 }
6170
6171 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6172 {
6173         u8 rfcsr;
6174         u32 reg;
6175
6176         rt2800_rf_init_calibration(rt2x00dev, 30);
6177
6178         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6179         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6180         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6181         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6182         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6183         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6184         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6185         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6186         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6187         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6188         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6189         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6190         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6191         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6192         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6193         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6194         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6195         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6196         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6197         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6198         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6199         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6200         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6201         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6202         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6203         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6204         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6205         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6206         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6207         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6208         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
6209
6210         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6211         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6212         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6213
6214         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6215         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6216         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6217         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6218         msleep(1);
6219         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6220         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6221         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6222         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6223
6224         rt2800_rx_filter_calibration(rt2x00dev);
6225         rt2800_led_open_drain_enable(rt2x00dev);
6226         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6227 }
6228
6229 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6230 {
6231         u8 bbp;
6232         bool txbf_enabled = false; /* FIXME */
6233
6234         rt2800_bbp_read(rt2x00dev, 105, &bbp);
6235         if (rt2x00dev->default_ant.rx_chain_num == 1)
6236                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6237         else
6238                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6239         rt2800_bbp_write(rt2x00dev, 105, bbp);
6240
6241         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6242
6243         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6244         rt2800_bbp_write(rt2x00dev, 82, 0x82);
6245         rt2800_bbp_write(rt2x00dev, 106, 0x05);
6246         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6247         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6248         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6249         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6250         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6251
6252         if (txbf_enabled)
6253                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6254         else
6255                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6256
6257         /* SNR mapping */
6258         rt2800_bbp_write(rt2x00dev, 142, 6);
6259         rt2800_bbp_write(rt2x00dev, 143, 160);
6260         rt2800_bbp_write(rt2x00dev, 142, 7);
6261         rt2800_bbp_write(rt2x00dev, 143, 161);
6262         rt2800_bbp_write(rt2x00dev, 142, 8);
6263         rt2800_bbp_write(rt2x00dev, 143, 162);
6264
6265         /* ADC/DAC control */
6266         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6267
6268         /* RX AGC energy lower bound in log2 */
6269         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6270
6271         /* FIXME: BBP 105 owerwrite? */
6272         rt2800_bbp_write(rt2x00dev, 105, 0x04);
6273
6274 }
6275
6276 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6277 {
6278         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6279         u32 reg;
6280         u8 rfcsr;
6281
6282         /* Disable GPIO #4 and #7 function for LAN PE control */
6283         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6284         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6285         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6286         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6287
6288         /* Initialize default register values */
6289         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6290         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6291         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6292         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6293         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6294         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6295         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6296         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6297         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6298         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6299         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6300         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6301         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6302         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6303         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6304         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6305         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6306         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6307         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6308         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6309         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6310         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6311         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6312         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6313         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6314         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6315         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6316         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6317         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6318         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6319         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6320         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6321
6322         /* Initiate calibration */
6323         /* TODO: use rt2800_rf_init_calibration ? */
6324         rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6325         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6326         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6327
6328         rt2800_adjust_freq_offset(rt2x00dev);
6329
6330         rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6331         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6332         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6333
6334         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6335         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6336         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6337         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6338         usleep_range(1000, 1500);
6339         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6340         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6341         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6342
6343         /* Set initial values for RX filter calibration */
6344         drv_data->calibration_bw20 = 0x1f;
6345         drv_data->calibration_bw40 = 0x2f;
6346
6347         /* Save BBP 25 & 26 values for later use in channel switching */
6348         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6349         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6350
6351         rt2800_led_open_drain_enable(rt2x00dev);
6352         rt2800_normal_mode_setup_3593(rt2x00dev);
6353
6354         rt3593_post_bbp_init(rt2x00dev);
6355
6356         /* TODO: enable stream mode support */
6357 }
6358
6359 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6360 {
6361         rt2800_rf_init_calibration(rt2x00dev, 2);
6362
6363         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6364         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6365         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6366         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6367         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6368                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6369         else
6370                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6371         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6372         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6373         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6374         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
6375         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6376         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6377         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6378         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6379         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6380         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6381
6382         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6383         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6384         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6385         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6386         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6387         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6388                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6389         else
6390                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6391         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6392         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6393         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6394         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6395
6396         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6397         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6398         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6399         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6400         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6401         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6402         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6403         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6404         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6405         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6406
6407         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6408                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6409         else
6410                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
6411         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6412         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6413         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6414         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6415         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6416         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6417                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6418         else
6419                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6420         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6421         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6422         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6423
6424         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6425         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6426                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6427         else
6428                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6429         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6430         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6431         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6432         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6433         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6434         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6435
6436         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6437         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6438                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6439         else
6440                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6441         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6442         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6443
6444         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6445
6446         rt2800_led_open_drain_enable(rt2x00dev);
6447 }
6448
6449 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6450 {
6451         rt2800_rf_init_calibration(rt2x00dev, 2);
6452
6453         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6454         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6455         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6456         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6457         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6458         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6459         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6460         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6461         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6462         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6463         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6464         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6465         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6466         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6467         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6468         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6469         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6470         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6471         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6472         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6473         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6474         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6475         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6476         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6477         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6478         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6479         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6480         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6481         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6482         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6483         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6484         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6485         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6486         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6487         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6488         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6489         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6490         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6491         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6492         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6493         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6494         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6495         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6496         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6497         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6498         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6499         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6500         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6501         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6502         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6503         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6504         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6505         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6506         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6507         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6508         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6509         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6510         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6511         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6512
6513         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6514
6515         rt2800_led_open_drain_enable(rt2x00dev);
6516 }
6517
6518 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6519 {
6520         rt2800_rf_init_calibration(rt2x00dev, 30);
6521
6522         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6523         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6524         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6525         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6526         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6527         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6528         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6529         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6530         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6531         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6532         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6533         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6534         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6535         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6536         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6537         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6538         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6539         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6540         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6541         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6542         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6543         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6544
6545         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6546         msleep(1);
6547
6548         rt2800_adjust_freq_offset(rt2x00dev);
6549
6550         /* Enable DC filter */
6551         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6552                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6553
6554         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6555
6556         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6557                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6558
6559         rt2800_led_open_drain_enable(rt2x00dev);
6560 }
6561
6562 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6563 {
6564         if (rt2800_is_305x_soc(rt2x00dev)) {
6565                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6566                 return;
6567         }
6568
6569         switch (rt2x00dev->chip.rt) {
6570         case RT3070:
6571         case RT3071:
6572         case RT3090:
6573                 rt2800_init_rfcsr_30xx(rt2x00dev);
6574                 break;
6575         case RT3290:
6576                 rt2800_init_rfcsr_3290(rt2x00dev);
6577                 break;
6578         case RT3352:
6579                 rt2800_init_rfcsr_3352(rt2x00dev);
6580                 break;
6581         case RT3390:
6582                 rt2800_init_rfcsr_3390(rt2x00dev);
6583                 break;
6584         case RT3572:
6585                 rt2800_init_rfcsr_3572(rt2x00dev);
6586                 break;
6587         case RT3593:
6588                 rt2800_init_rfcsr_3593(rt2x00dev);
6589                 break;
6590         case RT5390:
6591                 rt2800_init_rfcsr_5390(rt2x00dev);
6592                 break;
6593         case RT5392:
6594                 rt2800_init_rfcsr_5392(rt2x00dev);
6595                 break;
6596         case RT5592:
6597                 rt2800_init_rfcsr_5592(rt2x00dev);
6598                 break;
6599         }
6600 }
6601
6602 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6603 {
6604         u32 reg;
6605         u16 word;
6606
6607         /*
6608          * Initialize all registers.
6609          */
6610         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6611                      rt2800_init_registers(rt2x00dev)))
6612                 return -EIO;
6613
6614         /*
6615          * Send signal to firmware during boot time.
6616          */
6617         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6618         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6619         if (rt2x00_is_usb(rt2x00dev)) {
6620                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6621                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6622         }
6623         msleep(1);
6624
6625         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
6626                      rt2800_wait_bbp_ready(rt2x00dev)))
6627                 return -EIO;
6628
6629         rt2800_init_bbp(rt2x00dev);
6630         rt2800_init_rfcsr(rt2x00dev);
6631
6632         if (rt2x00_is_usb(rt2x00dev) &&
6633             (rt2x00_rt(rt2x00dev, RT3070) ||
6634              rt2x00_rt(rt2x00dev, RT3071) ||
6635              rt2x00_rt(rt2x00dev, RT3572))) {
6636                 udelay(200);
6637                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6638                 udelay(10);
6639         }
6640
6641         /*
6642          * Enable RX.
6643          */
6644         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6645         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6646         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6647         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6648
6649         udelay(50);
6650
6651         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6652         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6653         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6654         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6655         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6656         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6657
6658         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6659         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6660         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6661         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6662
6663         /*
6664          * Initialize LED control
6665          */
6666         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6667         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6668                            word & 0xff, (word >> 8) & 0xff);
6669
6670         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6671         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6672                            word & 0xff, (word >> 8) & 0xff);
6673
6674         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6675         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6676                            word & 0xff, (word >> 8) & 0xff);
6677
6678         return 0;
6679 }
6680 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6681
6682 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6683 {
6684         u32 reg;
6685
6686         rt2800_disable_wpdma(rt2x00dev);
6687
6688         /* Wait for DMA, ignore error */
6689         rt2800_wait_wpdma_ready(rt2x00dev);
6690
6691         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6692         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6693         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6694         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6695 }
6696 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6697
6698 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6699 {
6700         u32 reg;
6701         u16 efuse_ctrl_reg;
6702
6703         if (rt2x00_rt(rt2x00dev, RT3290))
6704                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6705         else
6706                 efuse_ctrl_reg = EFUSE_CTRL;
6707
6708         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6709         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6710 }
6711 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6712
6713 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6714 {
6715         u32 reg;
6716         u16 efuse_ctrl_reg;
6717         u16 efuse_data0_reg;
6718         u16 efuse_data1_reg;
6719         u16 efuse_data2_reg;
6720         u16 efuse_data3_reg;
6721
6722         if (rt2x00_rt(rt2x00dev, RT3290)) {
6723                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6724                 efuse_data0_reg = EFUSE_DATA0_3290;
6725                 efuse_data1_reg = EFUSE_DATA1_3290;
6726                 efuse_data2_reg = EFUSE_DATA2_3290;
6727                 efuse_data3_reg = EFUSE_DATA3_3290;
6728         } else {
6729                 efuse_ctrl_reg = EFUSE_CTRL;
6730                 efuse_data0_reg = EFUSE_DATA0;
6731                 efuse_data1_reg = EFUSE_DATA1;
6732                 efuse_data2_reg = EFUSE_DATA2;
6733                 efuse_data3_reg = EFUSE_DATA3;
6734         }
6735         mutex_lock(&rt2x00dev->csr_mutex);
6736
6737         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6738         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6739         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6740         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6741         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6742
6743         /* Wait until the EEPROM has been loaded */
6744         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6745         /* Apparently the data is read from end to start */
6746         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6747         /* The returned value is in CPU order, but eeprom is le */
6748         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6749         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6750         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6751         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6752         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6753         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6754         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6755
6756         mutex_unlock(&rt2x00dev->csr_mutex);
6757 }
6758
6759 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6760 {
6761         unsigned int i;
6762
6763         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6764                 rt2800_efuse_read(rt2x00dev, i);
6765
6766         return 0;
6767 }
6768 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6769
6770 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6771 {
6772         u16 word;
6773
6774         if (rt2x00_rt(rt2x00dev, RT3593))
6775                 return 0;
6776
6777         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6778         if ((word & 0x00ff) != 0x00ff)
6779                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6780
6781         return 0;
6782 }
6783
6784 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6785 {
6786         u16 word;
6787
6788         if (rt2x00_rt(rt2x00dev, RT3593))
6789                 return 0;
6790
6791         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6792         if ((word & 0x00ff) != 0x00ff)
6793                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6794
6795         return 0;
6796 }
6797
6798 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6799 {
6800         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6801         u16 word;
6802         u8 *mac;
6803         u8 default_lna_gain;
6804         int retval;
6805
6806         /*
6807          * Read the EEPROM.
6808          */
6809         retval = rt2800_read_eeprom(rt2x00dev);
6810         if (retval)
6811                 return retval;
6812
6813         /*
6814          * Start validation of the data that has been read.
6815          */
6816         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6817         if (!is_valid_ether_addr(mac)) {
6818                 eth_random_addr(mac);
6819                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6820         }
6821
6822         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6823         if (word == 0xffff) {
6824                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6825                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6826                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6827                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6828                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6829         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6830                    rt2x00_rt(rt2x00dev, RT2872)) {
6831                 /*
6832                  * There is a max of 2 RX streams for RT28x0 series
6833                  */
6834                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6835                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6836                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6837         }
6838
6839         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6840         if (word == 0xffff) {
6841                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6842                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6843                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6844                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6845                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6846                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6847                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6848                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6849                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6850                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6851                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6852                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6853                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6854                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6855                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6856                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6857                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6858         }
6859
6860         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6861         if ((word & 0x00ff) == 0x00ff) {
6862                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6863                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6864                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6865         }
6866         if ((word & 0xff00) == 0xff00) {
6867                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6868                                    LED_MODE_TXRX_ACTIVITY);
6869                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6870                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6871                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6872                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6873                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6874                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6875         }
6876
6877         /*
6878          * During the LNA validation we are going to use
6879          * lna0 as correct value. Note that EEPROM_LNA
6880          * is never validated.
6881          */
6882         rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6883         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6884
6885         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6886         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6887                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6888         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6889                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6890         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6891
6892         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
6893
6894         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6895         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6896                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6897         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6898                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6899                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6900                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6901                                            default_lna_gain);
6902         }
6903         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6904
6905         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
6906
6907         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6908         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6909                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6910         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6911                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6912         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6913
6914         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6915         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6916                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6917         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6918                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6919                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6920                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6921                                            default_lna_gain);
6922         }
6923         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6924
6925         if (rt2x00_rt(rt2x00dev, RT3593)) {
6926                 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
6927                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
6928                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
6929                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6930                                            default_lna_gain);
6931                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
6932                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
6933                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6934                                            default_lna_gain);
6935                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
6936         }
6937
6938         return 0;
6939 }
6940
6941 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
6942 {
6943         u16 value;
6944         u16 eeprom;
6945         u16 rf;
6946
6947         /*
6948          * Read EEPROM word for configuration.
6949          */
6950         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
6951
6952         /*
6953          * Identify RF chipset by EEPROM value
6954          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
6955          * RT53xx: defined in "EEPROM_CHIP_ID" field
6956          */
6957         if (rt2x00_rt(rt2x00dev, RT3290) ||
6958             rt2x00_rt(rt2x00dev, RT5390) ||
6959             rt2x00_rt(rt2x00dev, RT5392))
6960                 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
6961         else
6962                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
6963
6964         switch (rf) {
6965         case RF2820:
6966         case RF2850:
6967         case RF2720:
6968         case RF2750:
6969         case RF3020:
6970         case RF2020:
6971         case RF3021:
6972         case RF3022:
6973         case RF3052:
6974         case RF3053:
6975         case RF3290:
6976         case RF3320:
6977         case RF3322:
6978         case RF5360:
6979         case RF5370:
6980         case RF5372:
6981         case RF5390:
6982         case RF5392:
6983         case RF5592:
6984                 break;
6985         default:
6986                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
6987                            rf);
6988                 return -ENODEV;
6989         }
6990
6991         rt2x00_set_rf(rt2x00dev, rf);
6992
6993         /*
6994          * Identify default antenna configuration.
6995          */
6996         rt2x00dev->default_ant.tx_chain_num =
6997             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
6998         rt2x00dev->default_ant.rx_chain_num =
6999             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
7000
7001         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
7002
7003         if (rt2x00_rt(rt2x00dev, RT3070) ||
7004             rt2x00_rt(rt2x00dev, RT3090) ||
7005             rt2x00_rt(rt2x00dev, RT3352) ||
7006             rt2x00_rt(rt2x00dev, RT3390)) {
7007                 value = rt2x00_get_field16(eeprom,
7008                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7009                 switch (value) {
7010                 case 0:
7011                 case 1:
7012                 case 2:
7013                         rt2x00dev->default_ant.tx = ANTENNA_A;
7014                         rt2x00dev->default_ant.rx = ANTENNA_A;
7015                         break;
7016                 case 3:
7017                         rt2x00dev->default_ant.tx = ANTENNA_A;
7018                         rt2x00dev->default_ant.rx = ANTENNA_B;
7019                         break;
7020                 }
7021         } else {
7022                 rt2x00dev->default_ant.tx = ANTENNA_A;
7023                 rt2x00dev->default_ant.rx = ANTENNA_A;
7024         }
7025
7026         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7027                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7028                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7029         }
7030
7031         /*
7032          * Determine external LNA informations.
7033          */
7034         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7035                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
7036         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7037                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
7038
7039         /*
7040          * Detect if this device has an hardware controlled radio.
7041          */
7042         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7043                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7044
7045         /*
7046          * Detect if this device has Bluetooth co-existence.
7047          */
7048         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7049                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7050
7051         /*
7052          * Read frequency offset and RF programming sequence.
7053          */
7054         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
7055         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7056
7057         /*
7058          * Store led settings, for correct led behaviour.
7059          */
7060 #ifdef CONFIG_RT2X00_LIB_LEDS
7061         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7062         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7063         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7064
7065         rt2x00dev->led_mcu_reg = eeprom;
7066 #endif /* CONFIG_RT2X00_LIB_LEDS */
7067
7068         /*
7069          * Check if support EIRP tx power limit feature.
7070          */
7071         rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
7072
7073         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7074                                         EIRP_MAX_TX_POWER_LIMIT)
7075                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
7076
7077         return 0;
7078 }
7079
7080 /*
7081  * RF value list for rt28xx
7082  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7083  */
7084 static const struct rf_channel rf_vals[] = {
7085         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7086         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7087         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7088         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7089         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7090         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7091         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7092         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7093         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7094         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7095         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7096         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7097         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7098         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7099
7100         /* 802.11 UNI / HyperLan 2 */
7101         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7102         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7103         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7104         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7105         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7106         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7107         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7108         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7109         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7110         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7111         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7112         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7113
7114         /* 802.11 HyperLan 2 */
7115         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7116         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7117         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7118         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7119         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7120         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7121         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7122         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7123         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7124         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7125         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7126         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7127         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7128         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7129         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7130         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7131
7132         /* 802.11 UNII */
7133         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7134         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7135         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7136         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7137         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7138         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7139         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7140         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7141         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7142         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7143         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7144
7145         /* 802.11 Japan */
7146         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7147         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7148         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7149         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7150         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7151         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7152         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7153 };
7154
7155 /*
7156  * RF value list for rt3xxx
7157  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
7158  */
7159 static const struct rf_channel rf_vals_3x[] = {
7160         {1,  241, 2, 2 },
7161         {2,  241, 2, 7 },
7162         {3,  242, 2, 2 },
7163         {4,  242, 2, 7 },
7164         {5,  243, 2, 2 },
7165         {6,  243, 2, 7 },
7166         {7,  244, 2, 2 },
7167         {8,  244, 2, 7 },
7168         {9,  245, 2, 2 },
7169         {10, 245, 2, 7 },
7170         {11, 246, 2, 2 },
7171         {12, 246, 2, 7 },
7172         {13, 247, 2, 2 },
7173         {14, 248, 2, 4 },
7174
7175         /* 802.11 UNI / HyperLan 2 */
7176         {36, 0x56, 0, 4},
7177         {38, 0x56, 0, 6},
7178         {40, 0x56, 0, 8},
7179         {44, 0x57, 0, 0},
7180         {46, 0x57, 0, 2},
7181         {48, 0x57, 0, 4},
7182         {52, 0x57, 0, 8},
7183         {54, 0x57, 0, 10},
7184         {56, 0x58, 0, 0},
7185         {60, 0x58, 0, 4},
7186         {62, 0x58, 0, 6},
7187         {64, 0x58, 0, 8},
7188
7189         /* 802.11 HyperLan 2 */
7190         {100, 0x5b, 0, 8},
7191         {102, 0x5b, 0, 10},
7192         {104, 0x5c, 0, 0},
7193         {108, 0x5c, 0, 4},
7194         {110, 0x5c, 0, 6},
7195         {112, 0x5c, 0, 8},
7196         {116, 0x5d, 0, 0},
7197         {118, 0x5d, 0, 2},
7198         {120, 0x5d, 0, 4},
7199         {124, 0x5d, 0, 8},
7200         {126, 0x5d, 0, 10},
7201         {128, 0x5e, 0, 0},
7202         {132, 0x5e, 0, 4},
7203         {134, 0x5e, 0, 6},
7204         {136, 0x5e, 0, 8},
7205         {140, 0x5f, 0, 0},
7206
7207         /* 802.11 UNII */
7208         {149, 0x5f, 0, 9},
7209         {151, 0x5f, 0, 11},
7210         {153, 0x60, 0, 1},
7211         {157, 0x60, 0, 5},
7212         {159, 0x60, 0, 7},
7213         {161, 0x60, 0, 9},
7214         {165, 0x61, 0, 1},
7215         {167, 0x61, 0, 3},
7216         {169, 0x61, 0, 5},
7217         {171, 0x61, 0, 7},
7218         {173, 0x61, 0, 9},
7219 };
7220
7221 static const struct rf_channel rf_vals_5592_xtal20[] = {
7222         /* Channel, N, K, mod, R */
7223         {1, 482, 4, 10, 3},
7224         {2, 483, 4, 10, 3},
7225         {3, 484, 4, 10, 3},
7226         {4, 485, 4, 10, 3},
7227         {5, 486, 4, 10, 3},
7228         {6, 487, 4, 10, 3},
7229         {7, 488, 4, 10, 3},
7230         {8, 489, 4, 10, 3},
7231         {9, 490, 4, 10, 3},
7232         {10, 491, 4, 10, 3},
7233         {11, 492, 4, 10, 3},
7234         {12, 493, 4, 10, 3},
7235         {13, 494, 4, 10, 3},
7236         {14, 496, 8, 10, 3},
7237         {36, 172, 8, 12, 1},
7238         {38, 173, 0, 12, 1},
7239         {40, 173, 4, 12, 1},
7240         {42, 173, 8, 12, 1},
7241         {44, 174, 0, 12, 1},
7242         {46, 174, 4, 12, 1},
7243         {48, 174, 8, 12, 1},
7244         {50, 175, 0, 12, 1},
7245         {52, 175, 4, 12, 1},
7246         {54, 175, 8, 12, 1},
7247         {56, 176, 0, 12, 1},
7248         {58, 176, 4, 12, 1},
7249         {60, 176, 8, 12, 1},
7250         {62, 177, 0, 12, 1},
7251         {64, 177, 4, 12, 1},
7252         {100, 183, 4, 12, 1},
7253         {102, 183, 8, 12, 1},
7254         {104, 184, 0, 12, 1},
7255         {106, 184, 4, 12, 1},
7256         {108, 184, 8, 12, 1},
7257         {110, 185, 0, 12, 1},
7258         {112, 185, 4, 12, 1},
7259         {114, 185, 8, 12, 1},
7260         {116, 186, 0, 12, 1},
7261         {118, 186, 4, 12, 1},
7262         {120, 186, 8, 12, 1},
7263         {122, 187, 0, 12, 1},
7264         {124, 187, 4, 12, 1},
7265         {126, 187, 8, 12, 1},
7266         {128, 188, 0, 12, 1},
7267         {130, 188, 4, 12, 1},
7268         {132, 188, 8, 12, 1},
7269         {134, 189, 0, 12, 1},
7270         {136, 189, 4, 12, 1},
7271         {138, 189, 8, 12, 1},
7272         {140, 190, 0, 12, 1},
7273         {149, 191, 6, 12, 1},
7274         {151, 191, 10, 12, 1},
7275         {153, 192, 2, 12, 1},
7276         {155, 192, 6, 12, 1},
7277         {157, 192, 10, 12, 1},
7278         {159, 193, 2, 12, 1},
7279         {161, 193, 6, 12, 1},
7280         {165, 194, 2, 12, 1},
7281         {184, 164, 0, 12, 1},
7282         {188, 164, 4, 12, 1},
7283         {192, 165, 8, 12, 1},
7284         {196, 166, 0, 12, 1},
7285 };
7286
7287 static const struct rf_channel rf_vals_5592_xtal40[] = {
7288         /* Channel, N, K, mod, R */
7289         {1, 241, 2, 10, 3},
7290         {2, 241, 7, 10, 3},
7291         {3, 242, 2, 10, 3},
7292         {4, 242, 7, 10, 3},
7293         {5, 243, 2, 10, 3},
7294         {6, 243, 7, 10, 3},
7295         {7, 244, 2, 10, 3},
7296         {8, 244, 7, 10, 3},
7297         {9, 245, 2, 10, 3},
7298         {10, 245, 7, 10, 3},
7299         {11, 246, 2, 10, 3},
7300         {12, 246, 7, 10, 3},
7301         {13, 247, 2, 10, 3},
7302         {14, 248, 4, 10, 3},
7303         {36, 86, 4, 12, 1},
7304         {38, 86, 6, 12, 1},
7305         {40, 86, 8, 12, 1},
7306         {42, 86, 10, 12, 1},
7307         {44, 87, 0, 12, 1},
7308         {46, 87, 2, 12, 1},
7309         {48, 87, 4, 12, 1},
7310         {50, 87, 6, 12, 1},
7311         {52, 87, 8, 12, 1},
7312         {54, 87, 10, 12, 1},
7313         {56, 88, 0, 12, 1},
7314         {58, 88, 2, 12, 1},
7315         {60, 88, 4, 12, 1},
7316         {62, 88, 6, 12, 1},
7317         {64, 88, 8, 12, 1},
7318         {100, 91, 8, 12, 1},
7319         {102, 91, 10, 12, 1},
7320         {104, 92, 0, 12, 1},
7321         {106, 92, 2, 12, 1},
7322         {108, 92, 4, 12, 1},
7323         {110, 92, 6, 12, 1},
7324         {112, 92, 8, 12, 1},
7325         {114, 92, 10, 12, 1},
7326         {116, 93, 0, 12, 1},
7327         {118, 93, 2, 12, 1},
7328         {120, 93, 4, 12, 1},
7329         {122, 93, 6, 12, 1},
7330         {124, 93, 8, 12, 1},
7331         {126, 93, 10, 12, 1},
7332         {128, 94, 0, 12, 1},
7333         {130, 94, 2, 12, 1},
7334         {132, 94, 4, 12, 1},
7335         {134, 94, 6, 12, 1},
7336         {136, 94, 8, 12, 1},
7337         {138, 94, 10, 12, 1},
7338         {140, 95, 0, 12, 1},
7339         {149, 95, 9, 12, 1},
7340         {151, 95, 11, 12, 1},
7341         {153, 96, 1, 12, 1},
7342         {155, 96, 3, 12, 1},
7343         {157, 96, 5, 12, 1},
7344         {159, 96, 7, 12, 1},
7345         {161, 96, 9, 12, 1},
7346         {165, 97, 1, 12, 1},
7347         {184, 82, 0, 12, 1},
7348         {188, 82, 4, 12, 1},
7349         {192, 82, 8, 12, 1},
7350         {196, 83, 0, 12, 1},
7351 };
7352
7353 static const struct rf_channel rf_vals_3053[] = {
7354         /* Channel, N, R, K */
7355         {1, 241, 2, 2},
7356         {2, 241, 2, 7},
7357         {3, 242, 2, 2},
7358         {4, 242, 2, 7},
7359         {5, 243, 2, 2},
7360         {6, 243, 2, 7},
7361         {7, 244, 2, 2},
7362         {8, 244, 2, 7},
7363         {9, 245, 2, 2},
7364         {10, 245, 2, 7},
7365         {11, 246, 2, 2},
7366         {12, 246, 2, 7},
7367         {13, 247, 2, 2},
7368         {14, 248, 2, 4},
7369
7370         {36, 0x56, 0, 4},
7371         {38, 0x56, 0, 6},
7372         {40, 0x56, 0, 8},
7373         {44, 0x57, 0, 0},
7374         {46, 0x57, 0, 2},
7375         {48, 0x57, 0, 4},
7376         {52, 0x57, 0, 8},
7377         {54, 0x57, 0, 10},
7378         {56, 0x58, 0, 0},
7379         {60, 0x58, 0, 4},
7380         {62, 0x58, 0, 6},
7381         {64, 0x58, 0, 8},
7382
7383         {100, 0x5B, 0, 8},
7384         {102, 0x5B, 0, 10},
7385         {104, 0x5C, 0, 0},
7386         {108, 0x5C, 0, 4},
7387         {110, 0x5C, 0, 6},
7388         {112, 0x5C, 0, 8},
7389
7390         /* NOTE: Channel 114 has been removed intentionally.
7391          * The EEPROM contains no TX power values for that,
7392          * and it is disabled in the vendor driver as well.
7393          */
7394
7395         {116, 0x5D, 0, 0},
7396         {118, 0x5D, 0, 2},
7397         {120, 0x5D, 0, 4},
7398         {124, 0x5D, 0, 8},
7399         {126, 0x5D, 0, 10},
7400         {128, 0x5E, 0, 0},
7401         {132, 0x5E, 0, 4},
7402         {134, 0x5E, 0, 6},
7403         {136, 0x5E, 0, 8},
7404         {140, 0x5F, 0, 0},
7405
7406         {149, 0x5F, 0, 9},
7407         {151, 0x5F, 0, 11},
7408         {153, 0x60, 0, 1},
7409         {157, 0x60, 0, 5},
7410         {159, 0x60, 0, 7},
7411         {161, 0x60, 0, 9},
7412         {165, 0x61, 0, 1},
7413         {167, 0x61, 0, 3},
7414         {169, 0x61, 0, 5},
7415         {171, 0x61, 0, 7},
7416         {173, 0x61, 0, 9},
7417 };
7418
7419 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
7420 {
7421         struct hw_mode_spec *spec = &rt2x00dev->spec;
7422         struct channel_info *info;
7423         char *default_power1;
7424         char *default_power2;
7425         char *default_power3;
7426         unsigned int i;
7427         u16 eeprom;
7428         u32 reg;
7429
7430         /*
7431          * Disable powersaving as default on PCI devices.
7432          */
7433         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
7434                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7435
7436         /*
7437          * Initialize all hw fields.
7438          */
7439         rt2x00dev->hw->flags =
7440             IEEE80211_HW_SIGNAL_DBM |
7441             IEEE80211_HW_SUPPORTS_PS |
7442             IEEE80211_HW_PS_NULLFUNC_STACK |
7443             IEEE80211_HW_AMPDU_AGGREGATION |
7444             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
7445
7446         /*
7447          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7448          * unless we are capable of sending the buffered frames out after the
7449          * DTIM transmission using rt2x00lib_beacondone. This will send out
7450          * multicast and broadcast traffic immediately instead of buffering it
7451          * infinitly and thus dropping it after some time.
7452          */
7453         if (!rt2x00_is_usb(rt2x00dev))
7454                 rt2x00dev->hw->flags |=
7455                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
7456
7457         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7458         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
7459                                 rt2800_eeprom_addr(rt2x00dev,
7460                                                    EEPROM_MAC_ADDR_0));
7461
7462         /*
7463          * As rt2800 has a global fallback table we cannot specify
7464          * more then one tx rate per frame but since the hw will
7465          * try several rates (based on the fallback table) we should
7466          * initialize max_report_rates to the maximum number of rates
7467          * we are going to try. Otherwise mac80211 will truncate our
7468          * reported tx rates and the rc algortihm will end up with
7469          * incorrect data.
7470          */
7471         rt2x00dev->hw->max_rates = 1;
7472         rt2x00dev->hw->max_report_rates = 7;
7473         rt2x00dev->hw->max_rate_tries = 1;
7474
7475         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7476
7477         /*
7478          * Initialize hw_mode information.
7479          */
7480         spec->supported_bands = SUPPORT_BAND_2GHZ;
7481         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7482
7483         if (rt2x00_rf(rt2x00dev, RF2820) ||
7484             rt2x00_rf(rt2x00dev, RF2720)) {
7485                 spec->num_channels = 14;
7486                 spec->channels = rf_vals;
7487         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
7488                    rt2x00_rf(rt2x00dev, RF2750)) {
7489                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7490                 spec->num_channels = ARRAY_SIZE(rf_vals);
7491                 spec->channels = rf_vals;
7492         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
7493                    rt2x00_rf(rt2x00dev, RF2020) ||
7494                    rt2x00_rf(rt2x00dev, RF3021) ||
7495                    rt2x00_rf(rt2x00dev, RF3022) ||
7496                    rt2x00_rf(rt2x00dev, RF3290) ||
7497                    rt2x00_rf(rt2x00dev, RF3320) ||
7498                    rt2x00_rf(rt2x00dev, RF3322) ||
7499                    rt2x00_rf(rt2x00dev, RF5360) ||
7500                    rt2x00_rf(rt2x00dev, RF5370) ||
7501                    rt2x00_rf(rt2x00dev, RF5372) ||
7502                    rt2x00_rf(rt2x00dev, RF5390) ||
7503                    rt2x00_rf(rt2x00dev, RF5392)) {
7504                 spec->num_channels = 14;
7505                 spec->channels = rf_vals_3x;
7506         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
7507                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7508                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7509                 spec->channels = rf_vals_3x;
7510         } else if (rt2x00_rf(rt2x00dev, RF3053)) {
7511                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7512                 spec->num_channels = ARRAY_SIZE(rf_vals_3053);
7513                 spec->channels = rf_vals_3053;
7514         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
7515                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7516
7517                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7518                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7519                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7520                         spec->channels = rf_vals_5592_xtal40;
7521                 } else {
7522                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7523                         spec->channels = rf_vals_5592_xtal20;
7524                 }
7525         }
7526
7527         if (WARN_ON_ONCE(!spec->channels))
7528                 return -ENODEV;
7529
7530         /*
7531          * Initialize HT information.
7532          */
7533         if (!rt2x00_rf(rt2x00dev, RF2020))
7534                 spec->ht.ht_supported = true;
7535         else
7536                 spec->ht.ht_supported = false;
7537
7538         spec->ht.cap =
7539             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7540             IEEE80211_HT_CAP_GRN_FLD |
7541             IEEE80211_HT_CAP_SGI_20 |
7542             IEEE80211_HT_CAP_SGI_40;
7543
7544         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
7545                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7546
7547         spec->ht.cap |=
7548             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
7549                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7550
7551         spec->ht.ampdu_factor = 3;
7552         spec->ht.ampdu_density = 4;
7553         spec->ht.mcs.tx_params =
7554             IEEE80211_HT_MCS_TX_DEFINED |
7555             IEEE80211_HT_MCS_TX_RX_DIFF |
7556             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
7557                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7558
7559         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
7560         case 3:
7561                 spec->ht.mcs.rx_mask[2] = 0xff;
7562         case 2:
7563                 spec->ht.mcs.rx_mask[1] = 0xff;
7564         case 1:
7565                 spec->ht.mcs.rx_mask[0] = 0xff;
7566                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7567                 break;
7568         }
7569
7570         /*
7571          * Create channel information array
7572          */
7573         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7574         if (!info)
7575                 return -ENOMEM;
7576
7577         spec->channels_info = info;
7578
7579         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7580         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7581
7582         if (rt2x00dev->default_ant.tx_chain_num > 2)
7583                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7584                                                     EEPROM_EXT_TXPOWER_BG3);
7585         else
7586                 default_power3 = NULL;
7587
7588         for (i = 0; i < 14; i++) {
7589                 info[i].default_power1 = default_power1[i];
7590                 info[i].default_power2 = default_power2[i];
7591                 if (default_power3)
7592                         info[i].default_power3 = default_power3[i];
7593         }
7594
7595         if (spec->num_channels > 14) {
7596                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7597                                                     EEPROM_TXPOWER_A1);
7598                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7599                                                     EEPROM_TXPOWER_A2);
7600
7601                 if (rt2x00dev->default_ant.tx_chain_num > 2)
7602                         default_power3 =
7603                                 rt2800_eeprom_addr(rt2x00dev,
7604                                                    EEPROM_EXT_TXPOWER_A3);
7605                 else
7606                         default_power3 = NULL;
7607
7608                 for (i = 14; i < spec->num_channels; i++) {
7609                         info[i].default_power1 = default_power1[i - 14];
7610                         info[i].default_power2 = default_power2[i - 14];
7611                         if (default_power3)
7612                                 info[i].default_power3 = default_power3[i - 14];
7613                 }
7614         }
7615
7616         switch (rt2x00dev->chip.rf) {
7617         case RF2020:
7618         case RF3020:
7619         case RF3021:
7620         case RF3022:
7621         case RF3320:
7622         case RF3052:
7623         case RF3053:
7624         case RF3290:
7625         case RF5360:
7626         case RF5370:
7627         case RF5372:
7628         case RF5390:
7629         case RF5392:
7630                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7631                 break;
7632         }
7633
7634         return 0;
7635 }
7636
7637 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7638 {
7639         u32 reg;
7640         u32 rt;
7641         u32 rev;
7642
7643         if (rt2x00_rt(rt2x00dev, RT3290))
7644                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7645         else
7646                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7647
7648         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7649         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7650
7651         switch (rt) {
7652         case RT2860:
7653         case RT2872:
7654         case RT2883:
7655         case RT3070:
7656         case RT3071:
7657         case RT3090:
7658         case RT3290:
7659         case RT3352:
7660         case RT3390:
7661         case RT3572:
7662         case RT3593:
7663         case RT5390:
7664         case RT5392:
7665         case RT5592:
7666                 break;
7667         default:
7668                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7669                            rt, rev);
7670                 return -ENODEV;
7671         }
7672
7673         rt2x00_set_rt(rt2x00dev, rt, rev);
7674
7675         return 0;
7676 }
7677
7678 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7679 {
7680         int retval;
7681         u32 reg;
7682
7683         retval = rt2800_probe_rt(rt2x00dev);
7684         if (retval)
7685                 return retval;
7686
7687         /*
7688          * Allocate eeprom data.
7689          */
7690         retval = rt2800_validate_eeprom(rt2x00dev);
7691         if (retval)
7692                 return retval;
7693
7694         retval = rt2800_init_eeprom(rt2x00dev);
7695         if (retval)
7696                 return retval;
7697
7698         /*
7699          * Enable rfkill polling by setting GPIO direction of the
7700          * rfkill switch GPIO pin correctly.
7701          */
7702         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7703         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7704         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7705
7706         /*
7707          * Initialize hw specifications.
7708          */
7709         retval = rt2800_probe_hw_mode(rt2x00dev);
7710         if (retval)
7711                 return retval;
7712
7713         /*
7714          * Set device capabilities.
7715          */
7716         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7717         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7718         if (!rt2x00_is_usb(rt2x00dev))
7719                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7720
7721         /*
7722          * Set device requirements.
7723          */
7724         if (!rt2x00_is_soc(rt2x00dev))
7725                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7726         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7727         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7728         if (!rt2800_hwcrypt_disabled(rt2x00dev))
7729                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7730         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7731         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7732         if (rt2x00_is_usb(rt2x00dev))
7733                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7734         else {
7735                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7736                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7737         }
7738
7739         /*
7740          * Set the rssi offset.
7741          */
7742         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7743
7744         return 0;
7745 }
7746 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7747
7748 /*
7749  * IEEE80211 stack callback functions.
7750  */
7751 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7752                          u16 *iv16)
7753 {
7754         struct rt2x00_dev *rt2x00dev = hw->priv;
7755         struct mac_iveiv_entry iveiv_entry;
7756         u32 offset;
7757
7758         offset = MAC_IVEIV_ENTRY(hw_key_idx);
7759         rt2800_register_multiread(rt2x00dev, offset,
7760                                       &iveiv_entry, sizeof(iveiv_entry));
7761
7762         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7763         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7764 }
7765 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7766
7767 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7768 {
7769         struct rt2x00_dev *rt2x00dev = hw->priv;
7770         u32 reg;
7771         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7772
7773         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7774         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7775         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7776
7777         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7778         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7779         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7780
7781         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7782         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7783         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7784
7785         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7786         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7787         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7788
7789         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7790         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7791         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7792
7793         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7794         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7795         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7796
7797         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7798         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7799         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7800
7801         return 0;
7802 }
7803 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7804
7805 int rt2800_conf_tx(struct ieee80211_hw *hw,
7806                    struct ieee80211_vif *vif, u16 queue_idx,
7807                    const struct ieee80211_tx_queue_params *params)
7808 {
7809         struct rt2x00_dev *rt2x00dev = hw->priv;
7810         struct data_queue *queue;
7811         struct rt2x00_field32 field;
7812         int retval;
7813         u32 reg;
7814         u32 offset;
7815
7816         /*
7817          * First pass the configuration through rt2x00lib, that will
7818          * update the queue settings and validate the input. After that
7819          * we are free to update the registers based on the value
7820          * in the queue parameter.
7821          */
7822         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7823         if (retval)
7824                 return retval;
7825
7826         /*
7827          * We only need to perform additional register initialization
7828          * for WMM queues/
7829          */
7830         if (queue_idx >= 4)
7831                 return 0;
7832
7833         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7834
7835         /* Update WMM TXOP register */
7836         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7837         field.bit_offset = (queue_idx & 1) * 16;
7838         field.bit_mask = 0xffff << field.bit_offset;
7839
7840         rt2800_register_read(rt2x00dev, offset, &reg);
7841         rt2x00_set_field32(&reg, field, queue->txop);
7842         rt2800_register_write(rt2x00dev, offset, reg);
7843
7844         /* Update WMM registers */
7845         field.bit_offset = queue_idx * 4;
7846         field.bit_mask = 0xf << field.bit_offset;
7847
7848         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7849         rt2x00_set_field32(&reg, field, queue->aifs);
7850         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7851
7852         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7853         rt2x00_set_field32(&reg, field, queue->cw_min);
7854         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7855
7856         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7857         rt2x00_set_field32(&reg, field, queue->cw_max);
7858         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7859
7860         /* Update EDCA registers */
7861         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7862
7863         rt2800_register_read(rt2x00dev, offset, &reg);
7864         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7865         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7866         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7867         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7868         rt2800_register_write(rt2x00dev, offset, reg);
7869
7870         return 0;
7871 }
7872 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7873
7874 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7875 {
7876         struct rt2x00_dev *rt2x00dev = hw->priv;
7877         u64 tsf;
7878         u32 reg;
7879
7880         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7881         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7882         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7883         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7884
7885         return tsf;
7886 }
7887 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7888
7889 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7890                         enum ieee80211_ampdu_mlme_action action,
7891                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7892                         u8 buf_size)
7893 {
7894         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7895         int ret = 0;
7896
7897         /*
7898          * Don't allow aggregation for stations the hardware isn't aware
7899          * of because tx status reports for frames to an unknown station
7900          * always contain wcid=255 and thus we can't distinguish between
7901          * multiple stations which leads to unwanted situations when the
7902          * hw reorders frames due to aggregation.
7903          */
7904         if (sta_priv->wcid < 0)
7905                 return 1;
7906
7907         switch (action) {
7908         case IEEE80211_AMPDU_RX_START:
7909         case IEEE80211_AMPDU_RX_STOP:
7910                 /*
7911                  * The hw itself takes care of setting up BlockAck mechanisms.
7912                  * So, we only have to allow mac80211 to nagotiate a BlockAck
7913                  * agreement. Once that is done, the hw will BlockAck incoming
7914                  * AMPDUs without further setup.
7915                  */
7916                 break;
7917         case IEEE80211_AMPDU_TX_START:
7918                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7919                 break;
7920         case IEEE80211_AMPDU_TX_STOP_CONT:
7921         case IEEE80211_AMPDU_TX_STOP_FLUSH:
7922         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7923                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7924                 break;
7925         case IEEE80211_AMPDU_TX_OPERATIONAL:
7926                 break;
7927         default:
7928                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7929                             "Unknown AMPDU action\n");
7930         }
7931
7932         return ret;
7933 }
7934 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
7935
7936 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7937                       struct survey_info *survey)
7938 {
7939         struct rt2x00_dev *rt2x00dev = hw->priv;
7940         struct ieee80211_conf *conf = &hw->conf;
7941         u32 idle, busy, busy_ext;
7942
7943         if (idx != 0)
7944                 return -ENOENT;
7945
7946         survey->channel = conf->chandef.chan;
7947
7948         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7949         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7950         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
7951
7952         if (idle || busy) {
7953                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
7954                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
7955                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
7956
7957                 survey->channel_time = (idle + busy) / 1000;
7958                 survey->channel_time_busy = busy / 1000;
7959                 survey->channel_time_ext_busy = busy_ext / 1000;
7960         }
7961
7962         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
7963                 survey->filled |= SURVEY_INFO_IN_USE;
7964
7965         return 0;
7966
7967 }
7968 EXPORT_SYMBOL_GPL(rt2800_get_survey);
7969
7970 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
7971 MODULE_VERSION(DRV_VERSION);
7972 MODULE_DESCRIPTION("Ralink RT2800 library");
7973 MODULE_LICENSE("GPL");