1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/firmware.h>
11 #include <linux/iopoll.h>
12 #include <linux/workqueue.h>
13 #include <net/mac80211.h>
16 struct rtw89_pci_info;
18 extern const struct ieee80211_ops rtw89_ops;
20 #define MASKBYTE0 0xff
21 #define MASKBYTE1 0xff00
22 #define MASKBYTE2 0xff0000
23 #define MASKBYTE3 0xff000000
24 #define MASKBYTE4 0xff00000000ULL
25 #define MASKHWORD 0xffff0000
26 #define MASKLWORD 0x0000ffff
27 #define MASKDWORD 0xffffffff
28 #define RFREG_MASK 0xfffff
29 #define INV_RF_DATA 0xffffffff
31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
33 #define CFO_TRACK_MAX_USER 64
36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
38 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64)
40 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
41 #define RTW89_HTC_VARIANT_HE 3
42 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
43 #define RTW89_HTC_VARIANT_HE_CID_OM 1
44 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
45 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
47 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
48 enum htc_om_channel_width {
49 HTC_OM_CHANNEL_WIDTH_20 = 0,
50 HTC_OM_CHANNEL_WIDTH_40 = 1,
51 HTC_OM_CHANNEL_WIDTH_80 = 2,
52 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
54 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
55 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
56 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
57 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
58 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
59 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
61 #define RTW89_TF_PAD GENMASK(11, 0)
62 #define RTW89_TF_BASIC_USER_INFO_SZ 6
64 #define RTW89_GET_TF_USER_INFO_AID12(data) \
65 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
66 #define RTW89_GET_TF_USER_INFO_RUA(data) \
67 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
68 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
69 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
73 RTW89_CH_5G_BAND_1 = 1,
74 /* RTW89_CH_5G_BAND_2 = 2, unused */
75 RTW89_CH_5G_BAND_3 = 3,
76 RTW89_CH_5G_BAND_4 = 4,
78 RTW89_CH_6G_BAND_IDX0, /* Low */
79 RTW89_CH_6G_BAND_IDX1, /* Low */
80 RTW89_CH_6G_BAND_IDX2, /* Mid */
81 RTW89_CH_6G_BAND_IDX3, /* Mid */
82 RTW89_CH_6G_BAND_IDX4, /* High */
83 RTW89_CH_6G_BAND_IDX5, /* High */
84 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
85 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
88 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
91 enum rtw89_gain_offset {
92 RTW89_GAIN_OFFSET_2G_CCK,
93 RTW89_GAIN_OFFSET_2G_OFDM,
94 RTW89_GAIN_OFFSET_5G_LOW,
95 RTW89_GAIN_OFFSET_5G_MID,
96 RTW89_GAIN_OFFSET_5G_HIGH,
101 enum rtw89_hci_type {
107 enum rtw89_core_chip_id {
122 CHIP_CV_INVALID = CHIP_CV_MAX,
125 enum rtw89_core_tx_type {
126 RTW89_CORE_TX_TYPE_DATA,
127 RTW89_CORE_TX_TYPE_MGMT,
128 RTW89_CORE_TX_TYPE_FWCMD,
131 enum rtw89_core_rx_type {
132 RTW89_CORE_RX_TYPE_WIFI = 0,
133 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
134 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
135 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
136 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
137 RTW89_CORE_RX_TYPE_SS2FW = 5,
138 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
139 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
140 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
141 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
142 RTW89_CORE_RX_TYPE_C2H = 10,
143 RTW89_CORE_RX_TYPE_CSI = 11,
144 RTW89_CORE_RX_TYPE_CQI = 12,
145 RTW89_CORE_RX_TYPE_H2C = 13,
146 RTW89_CORE_RX_TYPE_FWDL = 14,
149 enum rtw89_txq_flags {
150 RTW89_TXQ_F_AMPDU = 0,
151 RTW89_TXQ_F_BLOCK_BA = 1,
152 RTW89_TXQ_F_FORBID_BA = 2,
155 enum rtw89_net_type {
156 RTW89_NET_TYPE_NO_LINK = 0,
157 RTW89_NET_TYPE_AD_HOC = 1,
158 RTW89_NET_TYPE_INFRA = 2,
159 RTW89_NET_TYPE_AP_MODE = 3,
162 enum rtw89_wifi_role {
163 RTW89_WIFI_ROLE_NONE,
164 RTW89_WIFI_ROLE_STATION,
166 RTW89_WIFI_ROLE_AP_VLAN,
167 RTW89_WIFI_ROLE_ADHOC,
168 RTW89_WIFI_ROLE_ADHOC_MASTER,
169 RTW89_WIFI_ROLE_MESH_POINT,
170 RTW89_WIFI_ROLE_MONITOR,
171 RTW89_WIFI_ROLE_P2P_DEVICE,
172 RTW89_WIFI_ROLE_P2P_CLIENT,
173 RTW89_WIFI_ROLE_P2P_GO,
175 RTW89_WIFI_ROLE_MLME_MAX
178 enum rtw89_upd_mode {
181 RTW89_ROLE_TYPE_CHANGE,
182 RTW89_ROLE_INFO_CHANGE,
183 RTW89_ROLE_CON_DISCONN,
185 RTW89_ROLE_FW_RESTORE,
188 enum rtw89_self_role {
189 RTW89_SELF_ROLE_CLIENT,
191 RTW89_SELF_ROLE_AP_CLIENT
194 enum rtw89_msk_sO_el {
201 enum rtw89_sch_tx_sel {
202 RTW89_SCH_TX_SEL_ALL,
203 RTW89_SCH_TX_SEL_HIQ,
204 RTW89_SCH_TX_SEL_MG0,
205 RTW89_SCH_TX_SEL_MACID,
208 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
209 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
210 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
211 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
213 enum rtw89_add_cam_sec_mode {
214 RTW89_ADDR_CAM_SEC_NONE = 0,
215 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
216 RTW89_ADDR_CAM_SEC_NORMAL = 2,
217 RTW89_ADDR_CAM_SEC_4GROUP = 3,
220 enum rtw89_sec_key_type {
221 RTW89_SEC_KEY_TYPE_NONE = 0,
222 RTW89_SEC_KEY_TYPE_WEP40 = 1,
223 RTW89_SEC_KEY_TYPE_WEP104 = 2,
224 RTW89_SEC_KEY_TYPE_TKIP = 3,
225 RTW89_SEC_KEY_TYPE_WAPI = 4,
226 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
227 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
228 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
229 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
230 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
231 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
251 RTW89_HW_RATE_CCK1 = 0x0,
252 RTW89_HW_RATE_CCK2 = 0x1,
253 RTW89_HW_RATE_CCK5_5 = 0x2,
254 RTW89_HW_RATE_CCK11 = 0x3,
255 RTW89_HW_RATE_OFDM6 = 0x4,
256 RTW89_HW_RATE_OFDM9 = 0x5,
257 RTW89_HW_RATE_OFDM12 = 0x6,
258 RTW89_HW_RATE_OFDM18 = 0x7,
259 RTW89_HW_RATE_OFDM24 = 0x8,
260 RTW89_HW_RATE_OFDM36 = 0x9,
261 RTW89_HW_RATE_OFDM48 = 0xA,
262 RTW89_HW_RATE_OFDM54 = 0xB,
263 RTW89_HW_RATE_MCS0 = 0x80,
264 RTW89_HW_RATE_MCS1 = 0x81,
265 RTW89_HW_RATE_MCS2 = 0x82,
266 RTW89_HW_RATE_MCS3 = 0x83,
267 RTW89_HW_RATE_MCS4 = 0x84,
268 RTW89_HW_RATE_MCS5 = 0x85,
269 RTW89_HW_RATE_MCS6 = 0x86,
270 RTW89_HW_RATE_MCS7 = 0x87,
271 RTW89_HW_RATE_MCS8 = 0x88,
272 RTW89_HW_RATE_MCS9 = 0x89,
273 RTW89_HW_RATE_MCS10 = 0x8A,
274 RTW89_HW_RATE_MCS11 = 0x8B,
275 RTW89_HW_RATE_MCS12 = 0x8C,
276 RTW89_HW_RATE_MCS13 = 0x8D,
277 RTW89_HW_RATE_MCS14 = 0x8E,
278 RTW89_HW_RATE_MCS15 = 0x8F,
279 RTW89_HW_RATE_MCS16 = 0x90,
280 RTW89_HW_RATE_MCS17 = 0x91,
281 RTW89_HW_RATE_MCS18 = 0x92,
282 RTW89_HW_RATE_MCS19 = 0x93,
283 RTW89_HW_RATE_MCS20 = 0x94,
284 RTW89_HW_RATE_MCS21 = 0x95,
285 RTW89_HW_RATE_MCS22 = 0x96,
286 RTW89_HW_RATE_MCS23 = 0x97,
287 RTW89_HW_RATE_MCS24 = 0x98,
288 RTW89_HW_RATE_MCS25 = 0x99,
289 RTW89_HW_RATE_MCS26 = 0x9A,
290 RTW89_HW_RATE_MCS27 = 0x9B,
291 RTW89_HW_RATE_MCS28 = 0x9C,
292 RTW89_HW_RATE_MCS29 = 0x9D,
293 RTW89_HW_RATE_MCS30 = 0x9E,
294 RTW89_HW_RATE_MCS31 = 0x9F,
295 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
296 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
297 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
298 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
299 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
300 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
301 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
302 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
303 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
304 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
305 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
306 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
307 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
308 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
309 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
310 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
311 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
312 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
313 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
314 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
315 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
316 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
317 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
318 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
319 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
320 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
321 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
322 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
323 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
324 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
325 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
326 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
327 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
328 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
329 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
330 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
331 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
332 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
333 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
334 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
335 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
336 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
337 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
338 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
339 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
340 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
341 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
342 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
343 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
344 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
345 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
346 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
347 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
348 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
349 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
350 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
351 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
352 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
353 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
354 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
355 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
356 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
357 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
358 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
359 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
360 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
361 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
362 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
363 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
364 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
365 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
366 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
367 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
368 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
369 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
370 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
371 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
372 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
373 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
374 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
375 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
376 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
377 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
378 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
379 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
380 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
381 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
382 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
385 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
386 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
390 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
392 #define RTW89_2G_CH_NUM 14
395 * 36, 38, 40, 42, 44, 46, 48, 50,
396 * 52, 54, 56, 58, 60, 62, 64,
397 * 100, 102, 104, 106, 108, 110, 112, 114,
398 * 116, 118, 120, 122, 124, 126, 128, 130,
399 * 132, 134, 136, 138, 140, 142, 144,
400 * 149, 151, 153, 155, 157, 159, 161, 163,
401 * 165, 167, 169, 171, 173, 175, 177
403 #define RTW89_5G_CH_NUM 53
406 * 1, 3, 5, 7, 9, 11, 13, 15,
407 * 17, 19, 21, 23, 25, 27, 29, 33,
408 * 35, 37, 39, 41, 43, 45, 47, 49,
409 * 51, 53, 55, 57, 59, 61, 65, 67,
410 * 69, 71, 73, 75, 77, 79, 81, 83,
411 * 85, 87, 89, 91, 93, 97, 99, 101,
412 * 103, 105, 107, 109, 111, 113, 115, 117,
413 * 119, 121, 123, 125, 129, 131, 133, 135,
414 * 137, 139, 141, 143, 145, 147, 149, 151,
415 * 153, 155, 157, 161, 163, 165, 167, 169,
416 * 171, 173, 175, 177, 179, 181, 183, 185,
417 * 187, 189, 193, 195, 197, 199, 201, 203,
418 * 205, 207, 209, 211, 213, 215, 217, 219,
419 * 221, 225, 227, 229, 231, 233, 235, 237,
420 * 239, 241, 243, 245, 247, 249, 251, 253,
422 #define RTW89_6G_CH_NUM 120
424 enum rtw89_rate_section {
427 RTW89_RS_MCS, /* for HT/VHT/HE */
431 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
432 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
435 enum rtw89_rate_max {
436 RTW89_RATE_CCK_MAX = 4,
437 RTW89_RATE_OFDM_MAX = 8,
438 RTW89_RATE_MCS_MAX = 12,
439 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */
440 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
446 /* HE DCM only support 1ss and 2ss */
447 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1,
459 enum rtw89_beamforming_type {
465 enum rtw89_regulation_type {
484 enum rtw89_fw_pkt_ofld_type {
485 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
486 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
487 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
488 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
489 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
490 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
491 RTW89_PKT_OFLD_TYPE_NDP = 6,
492 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
493 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
494 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
495 RTW89_PKT_OFLD_TYPE_NUM,
498 struct rtw89_txpwr_byrate {
499 s8 cck[RTW89_RATE_CCK_MAX];
500 s8 ofdm[RTW89_RATE_OFDM_MAX];
501 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX];
502 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX];
503 s8 offset[RTW89_RATE_OFFSET_MAX];
506 enum rtw89_bandwidth_section_num {
507 RTW89_BW20_SEC_NUM = 8,
508 RTW89_BW40_SEC_NUM = 4,
509 RTW89_BW80_SEC_NUM = 2,
512 #define RTW89_TXPWR_LMT_PAGE_SIZE 40
514 struct rtw89_txpwr_limit {
515 s8 cck_20m[RTW89_BF_NUM];
516 s8 cck_40m[RTW89_BF_NUM];
517 s8 ofdm[RTW89_BF_NUM];
518 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
519 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
520 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
521 s8 mcs_160m[RTW89_BF_NUM];
522 s8 mcs_40m_0p5[RTW89_BF_NUM];
523 s8 mcs_40m_2p5[RTW89_BF_NUM];
526 #define RTW89_RU_SEC_NUM 8
528 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24
530 struct rtw89_txpwr_limit_ru {
531 s8 ru26[RTW89_RU_SEC_NUM];
532 s8 ru52[RTW89_RU_SEC_NUM];
533 s8 ru106[RTW89_RU_SEC_NUM];
536 struct rtw89_rate_desc {
538 enum rtw89_rate_section rs;
542 #define PHY_STS_HDR_LEN 8
543 #define RF_PATH_MAX 4
544 #define RTW89_MAX_PPDU_CNT 8
545 struct rtw89_rx_phy_ppdu {
549 u8 rssi[RF_PATH_MAX];
569 enum rtw89_sub_entity_idx {
570 RTW89_SUB_ENTITY_0 = 0,
572 NUM_OF_RTW89_SUB_ENTITY,
573 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY,
594 enum rtw89_rf_path_bit {
600 RF_AB = (RF_A | RF_B),
601 RF_AC = (RF_A | RF_C),
602 RF_AD = (RF_A | RF_D),
603 RF_BC = (RF_B | RF_C),
604 RF_BD = (RF_B | RF_D),
605 RF_CD = (RF_C | RF_D),
607 RF_ABC = (RF_A | RF_B | RF_C),
608 RF_ABD = (RF_A | RF_B | RF_D),
609 RF_ACD = (RF_A | RF_C | RF_D),
610 RF_BCD = (RF_B | RF_C | RF_D),
612 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
615 enum rtw89_bandwidth {
616 RTW89_CHANNEL_WIDTH_20 = 0,
617 RTW89_CHANNEL_WIDTH_40 = 1,
618 RTW89_CHANNEL_WIDTH_80 = 2,
619 RTW89_CHANNEL_WIDTH_160 = 3,
620 RTW89_CHANNEL_WIDTH_80_80 = 4,
621 RTW89_CHANNEL_WIDTH_5 = 5,
622 RTW89_CHANNEL_WIDTH_10 = 6,
626 RTW89_PS_MODE_NONE = 0,
627 RTW89_PS_MODE_RFOFF = 1,
628 RTW89_PS_MODE_CLK_GATED = 2,
629 RTW89_PS_MODE_PWR_GATED = 3,
632 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
633 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
634 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
635 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
637 enum rtw89_ru_bandwidth {
644 enum rtw89_sc_offset {
645 RTW89_SC_DONT_CARE = 0,
646 RTW89_SC_20_UPPER = 1,
647 RTW89_SC_20_LOWER = 2,
648 RTW89_SC_20_UPMOST = 3,
649 RTW89_SC_20_LOWEST = 4,
650 RTW89_SC_20_UP2X = 5,
651 RTW89_SC_20_LOW2X = 6,
652 RTW89_SC_20_UP3X = 7,
653 RTW89_SC_20_LOW3X = 8,
654 RTW89_SC_40_UPPER = 9,
655 RTW89_SC_40_LOWER = 10,
658 enum rtw89_wow_flags {
659 RTW89_WOW_FLAG_EN_MAGIC_PKT,
660 RTW89_WOW_FLAG_EN_REKEY_PKT,
661 RTW89_WOW_FLAG_EN_DISCONNECT,
668 enum rtw89_band band_type;
669 enum rtw89_bandwidth band_width;
671 /* The follow-up are derived from the above. We must ensure that it
672 * is assigned correctly in rtw89_chan_create() if new one is added.
675 enum rtw89_subband subband_type;
676 enum rtw89_sc_offset pri_ch_idx;
679 struct rtw89_chan_rcd {
680 u8 prev_primary_channel;
681 enum rtw89_band prev_band_type;
684 struct rtw89_channel_help_params {
688 struct rtw89_port_reg {
706 struct rtw89_txwd_body {
715 struct rtw89_txwd_body_v1 {
726 struct rtw89_txwd_info {
735 struct rtw89_rx_desc_info {
769 struct rtw89_rxdesc_short {
776 struct rtw89_rxdesc_long {
787 struct rtw89_tx_desc_info {
811 u16 data_retry_lowest_rate;
816 #define RTW89_MGMT_HW_SSN_SEL 1
818 #define RTW89_MGMT_HW_SEQ_MODE 1
824 struct rtw89_core_tx_request {
825 enum rtw89_core_tx_type tx_type;
828 struct ieee80211_vif *vif;
829 struct ieee80211_sta *sta;
830 struct rtw89_tx_desc_info desc_info;
834 struct list_head list;
839 struct rtw89_mac_ax_gnt {
846 #define RTW89_MAC_AX_COEX_GNT_NR 2
847 struct rtw89_mac_ax_coex_gnt {
848 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
851 enum rtw89_btc_ncnt {
852 BTC_NCNT_POWER_ON = 0x0,
856 BTC_NCNT_SCAN_FINISH,
857 BTC_NCNT_SPECIAL_PACKET,
858 BTC_NCNT_SWITCH_BAND,
859 BTC_NCNT_RFK_TIMEOUT,
860 BTC_NCNT_SHOW_COEX_INFO,
863 BTC_NCNT_RADIO_STATE,
864 BTC_NCNT_CUSTOMERIZE,
872 enum rtw89_btc_btinfo {
884 enum rtw89_btc_dcnt {
895 BTC_DCNT_TDMA_NONSYNC,
896 BTC_DCNT_SLOT_NONSYNC,
898 BTC_DCNT_WL_SLOT_DRIFT,
899 BTC_DCNT_WL_STA_LAST,
900 BTC_DCNT_BT_SLOT_DRIFT,
901 BTC_DCNT_BT_SLOT_FLOOD,
908 enum rtw89_btc_wl_state_cnt {
909 BTC_WCNT_SCANAP = 0x0,
917 BTC_WCNT_RFK_TIMEOUT,
922 enum rtw89_btc_bt_state_cnt {
923 BTC_BCNT_RETRY = 0x0,
946 enum rtw89_btc_bt_profile {
947 BTC_BT_NOPROFILE = 0,
950 BTC_BT_A2DP = BIT(2),
955 struct rtw89_btc_ant_info {
956 u8 type; /* shared, dedicated */
960 u8 single_pos: 1;/* Single antenna at S0 or S1 */
971 struct rtw89_btc_wl_smap {
994 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
995 DECLARE_EWMA(tp, 10, 2);
997 struct rtw89_traffic_stats {
1004 /* count for packets */
1011 u32 tx_throughput_raw;
1012 u32 rx_throughput_raw;
1017 enum rtw89_tfc_lv tx_tfc_lv;
1018 enum rtw89_tfc_lv rx_tfc_lv;
1019 struct ewma_tp tx_ewma_tp;
1020 struct ewma_tp rx_ewma_tp;
1026 struct rtw89_btc_statistic {
1027 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1028 struct rtw89_traffic_stats traffic;
1031 #define BTC_WL_RSSI_THMAX 4
1033 struct rtw89_btc_wl_link_info {
1034 struct rtw89_btc_statistic stat;
1035 enum rtw89_tfc_dir dir;
1036 u8 rssi_state[BTC_WL_RSSI_THMAX];
1037 u8 mac_addr[ETH_ALEN];
1055 u32 rx_rate_drop_cnt;
1063 union rtw89_btc_wl_state_map {
1065 struct rtw89_btc_wl_smap map;
1068 struct rtw89_btc_bt_hfp_desc {
1074 struct rtw89_btc_bt_hid_desc {
1082 struct rtw89_btc_bt_a2dp_desc {
1096 struct rtw89_btc_bt_pan_desc {
1103 struct rtw89_btc_bt_rfk_info {
1110 union rtw89_btc_bt_rfk_info_map {
1112 struct rtw89_btc_bt_rfk_info map;
1115 struct rtw89_btc_bt_ver_info {
1116 u32 fw_coex; /* match with which coex_ver */
1120 struct rtw89_btc_bool_sta_chg {
1127 struct rtw89_btc_u8_sta_chg {
1134 struct rtw89_btc_wl_scan_info {
1135 u8 band[RTW89_PHY_MAX];
1140 struct rtw89_btc_wl_dbcc_info {
1141 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1142 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1143 u8 real_band[RTW89_PHY_MAX];
1144 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1147 struct rtw89_btc_wl_active_role {
1166 struct rtw89_btc_wl_active_role_v1 {
1184 u32 noa_duration; /* ms */
1187 struct rtw89_btc_wl_active_role_v2 {
1200 u32 noa_duration; /* ms */
1203 struct rtw89_btc_wl_role_info_bpos {
1209 u16 adhoc_master: 1;
1218 struct rtw89_btc_wl_scc_ctrl {
1221 u8 ebt_null; /* if tx null at EBT slot */
1224 union rtw89_btc_wl_role_info_map {
1226 struct rtw89_btc_wl_role_info_bpos role;
1229 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1232 union rtw89_btc_wl_role_info_map role_map;
1233 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1236 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1239 union rtw89_btc_wl_role_info_map role_map;
1240 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1241 u32 mrole_type; /* btc_wl_mrole_type */
1242 u32 mrole_noa_duration; /* ms */
1246 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1247 u32 link_mode_chg: 1;
1251 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1254 union rtw89_btc_wl_role_info_map role_map;
1255 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1256 u32 mrole_type; /* btc_wl_mrole_type */
1257 u32 mrole_noa_duration; /* ms */
1261 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1262 u32 link_mode_chg: 1;
1266 struct rtw89_btc_wl_ver_info {
1267 u32 fw_coex; /* match with which coex_ver */
1274 struct rtw89_btc_wl_afh_info {
1281 struct rtw89_btc_wl_rfk_info {
1290 struct rtw89_btc_bt_smap {
1299 union rtw89_btc_bt_state_map {
1301 struct rtw89_btc_bt_smap map;
1304 #define BTC_BT_RSSI_THMAX 4
1305 #define BTC_BT_AFH_GROUP 12
1306 #define BTC_BT_AFH_LE_GROUP 5
1308 struct rtw89_btc_bt_link_info {
1309 struct rtw89_btc_u8_sta_chg profile_cnt;
1310 struct rtw89_btc_bool_sta_chg multi_link;
1311 struct rtw89_btc_bool_sta_chg relink;
1312 struct rtw89_btc_bt_hfp_desc hfp_desc;
1313 struct rtw89_btc_bt_hid_desc hid_desc;
1314 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1315 struct rtw89_btc_bt_pan_desc pan_desc;
1316 union rtw89_btc_bt_state_map status;
1318 u8 sut_pwr_level[BTC_PROFILE_MAX];
1319 u8 golden_rx_shift[BTC_PROFILE_MAX];
1320 u8 rssi_state[BTC_BT_RSSI_THMAX];
1321 u8 afh_map[BTC_BT_AFH_GROUP];
1322 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1333 struct rtw89_btc_3rdcx_info {
1334 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1339 struct rtw89_btc_dm_emap {
1342 u32 wl_rfk_timeout: 1;
1343 u32 bt_rfk_timeout: 1;
1348 u32 tdma_no_sync: 1;
1349 u32 slot_no_sync: 1;
1350 u32 wl_slot_drift: 1;
1351 u32 bt_slot_drift: 1;
1352 u32 role_num_mismatch: 1;
1353 u32 null1_tx_late: 1;
1354 u32 bt_afh_conflict: 1;
1355 u32 bt_leafh_conflict: 1;
1356 u32 bt_slot_flood: 1;
1358 u32 wl_ver_mismatch: 1;
1359 u32 bt_ver_mismatch: 1;
1362 union rtw89_btc_dm_error_map {
1364 struct rtw89_btc_dm_emap map;
1367 struct rtw89_btc_rf_para {
1369 u32 rx_gain_freerun;
1374 struct rtw89_btc_wl_nhm {
1375 u8 instant_wl_nhm_dbm;
1376 u8 instant_wl_nhm_per_mhz;
1377 u16 valid_record_times;
1379 u8 record_ratio[16];
1380 s8 pwr; /* dbm_per_MHz */
1385 u8 last_ccx_rpt_stamp;
1390 struct rtw89_btc_wl_info {
1391 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1392 struct rtw89_btc_wl_rfk_info rfk_info;
1393 struct rtw89_btc_wl_ver_info ver_info;
1394 struct rtw89_btc_wl_afh_info afh_info;
1395 struct rtw89_btc_wl_role_info role_info;
1396 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1397 struct rtw89_btc_wl_role_info_v2 role_info_v2;
1398 struct rtw89_btc_wl_scan_info scan_info;
1399 struct rtw89_btc_wl_dbcc_info dbcc_info;
1400 struct rtw89_btc_rf_para rf_para;
1401 struct rtw89_btc_wl_nhm nhm;
1402 union rtw89_btc_wl_state_map status;
1404 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1412 struct rtw89_btc_module {
1413 struct rtw89_btc_ant_info ant;
1425 #define RTW89_BTC_DM_MAXSTEP 30
1426 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1428 struct rtw89_btc_dm_step {
1429 u16 step[RTW89_BTC_DM_MAXSTEP];
1434 struct rtw89_btc_init_info {
1435 struct rtw89_btc_module module;
1447 struct rtw89_btc_wl_tx_limit_para {
1449 u32 tx_time; /* unit: us */
1453 enum rtw89_btc_bt_scan_type {
1463 enum rtw89_btc_ble_scan_type {
1470 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
1471 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
1473 struct rtw89_btc_bt_scan_info_v1 {
1479 struct rtw89_btc_bt_scan_info_v2 {
1484 struct rtw89_btc_fbtc_btscan_v1 {
1485 u8 fver; /* btc_ver::fcxbtscan */
1488 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
1491 struct rtw89_btc_fbtc_btscan_v2 {
1492 u8 fver; /* btc_ver::fcxbtscan */
1495 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
1498 union rtw89_btc_fbtc_btscan {
1499 struct rtw89_btc_fbtc_btscan_v1 v1;
1500 struct rtw89_btc_fbtc_btscan_v2 v2;
1503 struct rtw89_btc_bt_info {
1504 struct rtw89_btc_bt_link_info link_info;
1505 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
1506 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
1507 struct rtw89_btc_bt_ver_info ver_info;
1508 struct rtw89_btc_bool_sta_chg enable;
1509 struct rtw89_btc_bool_sta_chg inq_pag;
1510 struct rtw89_btc_rf_para rf_para;
1511 union rtw89_btc_bt_rfk_info_map rfk_info;
1513 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1526 u32 run_patch_code: 1;
1528 u32 scan_rx_low_pri: 1;
1529 u32 scan_info_update: 1;
1533 struct rtw89_btc_cx {
1534 struct rtw89_btc_wl_info wl;
1535 struct rtw89_btc_bt_info bt;
1536 struct rtw89_btc_3rdcx_info other;
1538 u32 cnt_bt[BTC_BCNT_NUM];
1539 u32 cnt_wl[BTC_WCNT_NUM];
1542 struct rtw89_btc_fbtc_tdma {
1543 u8 type; /* btc_ver::fcxtdma */
1553 struct rtw89_btc_fbtc_tdma_v3 {
1554 u8 fver; /* btc_ver::fcxtdma */
1557 struct rtw89_btc_fbtc_tdma tdma;
1560 union rtw89_btc_fbtc_tdma_le32 {
1561 struct rtw89_btc_fbtc_tdma v1;
1562 struct rtw89_btc_fbtc_tdma_v3 v3;
1565 #define CXMREG_MAX 30
1566 #define CXMREG_MAX_V2 20
1567 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1568 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1570 enum rtw89_btc_bt_sta_counter {
1571 BTC_BCNT_RFK_REQ = 0,
1572 BTC_BCNT_RFK_GO = 1,
1573 BTC_BCNT_RFK_REJECT = 2,
1574 BTC_BCNT_RFK_FAIL = 3,
1575 BTC_BCNT_RFK_TIMEOUT = 4,
1580 BTC_BCNT_POLLUTED = 9,
1584 enum rtw89_btc_bt_sta_counter_v105 {
1585 BTC_BCNT_RFK_REQ_V105 = 0,
1586 BTC_BCNT_HI_TX_V105 = 1,
1587 BTC_BCNT_HI_RX_V105 = 2,
1588 BTC_BCNT_LO_TX_V105 = 3,
1589 BTC_BCNT_LO_RX_V105 = 4,
1590 BTC_BCNT_POLLUTED_V105 = 5,
1591 BTC_BCNT_STA_MAX_V105
1594 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
1595 u16 fver; /* btc_ver::fcxbtcrpt */
1596 u16 rpt_cnt; /* tmr counters */
1597 u32 wl_fw_coex_ver; /* match which driver's coex version */
1598 u32 wl_fw_cx_offload;
1601 u32 rpt_para; /* ms */
1602 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1603 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1604 u32 mb_recv_cnt; /* fw recv mailbox counter */
1605 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1606 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1607 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1608 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
1609 u32 c2h_cnt; /* fw send c2h counter */
1610 u32 h2c_cnt; /* fw recv h2c counter */
1613 struct rtw89_btc_fbtc_rpt_ctrl_info {
1614 __le32 cnt; /* fw report counter */
1615 __le32 en; /* report map */
1616 __le32 para; /* not used */
1618 __le32 cnt_c2h; /* fw send c2h counter */
1619 __le32 cnt_h2c; /* fw recv h2c counter */
1620 __le32 len_c2h; /* The total length of the last C2H */
1622 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
1623 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1626 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
1627 __le32 cx_ver; /* match which driver's coex version */
1629 __le32 en; /* report map */
1631 __le16 cnt; /* fw report counter */
1632 __le16 cnt_c2h; /* fw send c2h counter */
1633 __le16 cnt_h2c; /* fw recv h2c counter */
1634 __le16 len_c2h; /* The total length of the last C2H */
1636 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
1637 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1640 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
1641 __le32 cx_ver; /* match which driver's coex version */
1646 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
1647 __le32 cnt_empty; /* a2dp empty count */
1648 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
1654 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
1655 __le32 cnt_send_ok; /* fw send mailbox ok counter */
1656 __le32 cnt_send_fail; /* fw send mailbox fail counter */
1657 __le32 cnt_recv; /* fw recv mailbox counter */
1658 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
1661 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
1665 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
1666 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
1667 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1668 __le32 bt_cnt[BTC_BCNT_STA_MAX];
1669 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
1672 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
1677 u8 gnt_val[RTW89_PHY_MAX][4];
1678 __le16 bt_cnt[BTC_BCNT_STA_MAX];
1680 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1681 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1684 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
1689 u8 gnt_val[RTW89_PHY_MAX][4];
1690 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
1692 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1693 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1696 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
1697 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
1698 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
1699 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
1700 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
1703 enum rtw89_fbtc_ext_ctrl_type {
1704 CXECTL_OFF = 0x0, /* tdma off */
1705 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
1710 union rtw89_btc_fbtc_rxflct {
1716 enum rtw89_btc_cxst_state {
1738 enum rtw89_btc_cxevnt {
1739 CXEVNT_TDMA_ENTRY = 0x0,
1776 enum btc_slot_type {
1777 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
1778 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
1788 enum { /* TIME-A2DP */
1789 CXT_FLCTRL_OFF = 0x0,
1790 CXT_FLCTRL_ON = 0x1,
1794 enum { /* STEP TYPE */
1801 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
1802 RPT_BT_AFH_SEQ_LEGACY = 0x10,
1803 RPT_BT_AFH_SEQ_LE = 0x20
1806 #define BTC_DBG_MAX1 32
1807 struct rtw89_btc_fbtc_gpio_dbg {
1808 u8 fver; /* btc_ver::fcxgpiodbg */
1811 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
1812 u32 pre_state; /* the debug signal is 1 or 0 */
1813 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
1816 struct rtw89_btc_fbtc_mreg_val_v1 {
1817 u8 fver; /* btc_ver::fcxmreg */
1820 __le32 mreg_val[CXMREG_MAX];
1823 struct rtw89_btc_fbtc_mreg_val_v2 {
1824 u8 fver; /* btc_ver::fcxmreg */
1827 __le32 mreg_val[CXMREG_MAX_V2];
1830 union rtw89_btc_fbtc_mreg_val {
1831 struct rtw89_btc_fbtc_mreg_val_v1 v1;
1832 struct rtw89_btc_fbtc_mreg_val_v2 v2;
1835 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
1836 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
1837 .offset = cpu_to_le32(__offset), }
1839 struct rtw89_btc_fbtc_mreg {
1845 struct rtw89_btc_fbtc_slot {
1851 struct rtw89_btc_fbtc_slots {
1852 u8 fver; /* btc_ver::fcxslots */
1856 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1859 struct rtw89_btc_fbtc_step {
1865 struct rtw89_btc_fbtc_steps_v2 {
1866 u8 fver; /* btc_ver::fcxstep */
1871 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
1874 struct rtw89_btc_fbtc_steps_v3 {
1879 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
1882 union rtw89_btc_fbtc_steps_info {
1883 struct rtw89_btc_fbtc_steps_v2 v2;
1884 struct rtw89_btc_fbtc_steps_v3 v3;
1887 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
1888 u8 fver; /* btc_ver::fcxcysta */
1890 __le16 cycles; /* total cycle number */
1891 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
1892 __le16 a2dpept; /* a2dp empty cnt */
1893 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
1894 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
1895 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
1896 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
1897 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
1898 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
1899 __le16 tavg_a2dpept; /* avg a2dp empty time */
1900 __le16 tmax_a2dpept; /* max a2dp empty time */
1901 __le16 tavg_lk; /* avg leak-slot time */
1902 __le16 tmax_lk; /* max leak-slot time */
1903 __le32 slot_cnt[CXST_MAX]; /* slot count */
1904 __le32 bcn_cnt[CXBCN_MAX];
1905 __le32 leakrx_cnt; /* the rximr occur at leak slot */
1906 __le32 collision_cnt; /* counter for event/timer occur at same time */
1910 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
1913 struct rtw89_btc_fbtc_fdd_try_info {
1914 __le16 cycles[CXT_FLCTRL_MAX];
1915 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
1916 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
1919 struct rtw89_btc_fbtc_cycle_time_info {
1920 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
1921 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
1922 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
1925 struct rtw89_btc_fbtc_cycle_time_info_v5 {
1926 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
1927 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
1930 struct rtw89_btc_fbtc_a2dp_trx_stat {
1941 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
1952 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
1953 __le16 cnt; /* a2dp empty cnt */
1954 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
1955 __le16 tavg; /* avg a2dp empty time */
1956 __le16 tmax; /* max a2dp empty time */
1959 struct rtw89_btc_fbtc_cycle_leak_info {
1960 __le32 cnt_rximr; /* the rximr occur at leak slot */
1961 __le16 tavg; /* avg leak-slot time */
1962 __le16 tmax; /* max leak-slot time */
1965 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
1966 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
1968 struct rtw89_btc_fbtc_cycle_fddt_info {
1972 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
1973 s8 bt_tx_power; /* decrease Tx power (dB) */
1974 s8 bt_rx_gain; /* LNA constrain level */
1977 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
1978 u8 cn; /* condition_num */
1979 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
1980 u8 train_result; /* refer to enum btc_fddt_check_map */
1983 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
1984 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
1986 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
1990 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
1991 s8 bt_tx_power; /* decrease Tx power (dB) */
1992 s8 bt_rx_gain; /* LNA constrain level */
1995 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
1996 u8 cn; /* condition_num */
1997 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
1998 u8 train_result; /* refer to enum btc_fddt_check_map */
2001 struct rtw89_btc_fbtc_fddt_cell_status {
2005 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2008 struct rtw89_btc_fbtc_fddt_cell_status_v5 {
2014 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2017 __le16 cycles; /* total cycle number */
2018 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2019 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2020 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2021 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2022 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2023 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2024 __le32 slot_cnt[CXST_MAX]; /* slot count */
2025 __le32 bcn_cnt[CXBCN_MAX];
2026 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2032 #define FDD_TRAIN_WL_DIRECTION 2
2033 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2034 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2036 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2039 u8 collision_cnt; /* counter for event/timer occur at the same time */
2043 __le16 cycles; /* total cycle number */
2045 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2046 __le16 slot_cnt[CXST_MAX]; /* slot count */
2047 __le16 bcn_cnt[CXBCN_MAX];
2048 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2049 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2050 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2051 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2052 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2053 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2054 [FDD_TRAIN_WL_RSSI_LEVEL]
2055 [FDD_TRAIN_BT_RSSI_LEVEL];
2059 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2062 u8 collision_cnt; /* counter for event/timer occur at the same time */
2064 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2067 __le16 cycles; /* total cycle number */
2069 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2070 __le16 slot_cnt[CXST_MAX]; /* slot count */
2071 __le16 bcn_cnt[CXBCN_MAX];
2072 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2073 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2074 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2075 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2076 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2077 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION]
2078 [FDD_TRAIN_WL_RSSI_LEVEL]
2079 [FDD_TRAIN_BT_RSSI_LEVEL];
2083 union rtw89_btc_fbtc_cysta_info {
2084 struct rtw89_btc_fbtc_cysta_v2 v2;
2085 struct rtw89_btc_fbtc_cysta_v3 v3;
2086 struct rtw89_btc_fbtc_cysta_v4 v4;
2087 struct rtw89_btc_fbtc_cysta_v5 v5;
2090 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2091 u8 fver; /* btc_ver::fcxnullsta */
2094 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2095 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2096 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2099 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2100 u8 fver; /* btc_ver::fcxnullsta */
2103 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2104 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2105 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2108 union rtw89_btc_fbtc_cynullsta_info {
2109 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2110 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2113 struct rtw89_btc_fbtc_btver {
2114 u8 fver; /* btc_ver::fcxbtver */
2117 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2122 struct rtw89_btc_fbtc_btafh {
2123 u8 fver; /* btc_ver::fcxbtafh */
2126 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2127 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2128 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2131 struct rtw89_btc_fbtc_btafh_v2 {
2132 u8 fver; /* btc_ver::fcxbtafh */
2143 struct rtw89_btc_fbtc_btdevinfo {
2144 u8 fver; /* btc_ver::fcxbtdevinfo */
2147 __le32 dev_name; /* only 24 bits valid */
2151 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2152 struct rtw89_btc_rf_trx_para {
2153 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2154 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2155 u8 bt_tx_power; /* decrease Tx power (dB) */
2156 u8 bt_rx_gain; /* LNA constrain level */
2159 struct rtw89_btc_trx_info {
2165 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2166 s8 rx_gain; /* rx gain table index (TBD.) */
2167 s8 bt_tx_power; /* decrease Tx power (dB) */
2168 s8 bt_rx_gain; /* LNA constrain level */
2170 u8 cn; /* condition_num */
2183 struct rtw89_btc_dm {
2184 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2185 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
2186 struct rtw89_btc_fbtc_tdma tdma;
2187 struct rtw89_btc_fbtc_tdma tdma_now;
2188 struct rtw89_mac_ax_coex_gnt gnt;
2189 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
2190 struct rtw89_btc_rf_trx_para rf_trx_para;
2191 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2192 struct rtw89_btc_dm_step dm_step;
2193 struct rtw89_btc_wl_scc_ctrl wl_scc;
2194 struct rtw89_btc_trx_info trx_info;
2195 union rtw89_btc_dm_error_map error;
2196 u32 cnt_dm[BTC_DCNT_NUM];
2197 u32 cnt_notify[BTC_NCNT_NUM];
2199 u32 update_slot_map;
2203 u32 wl_fw_cx_offload: 1;
2210 u32 coex_info_map: 8;
2213 u32 trx_para_level: 8;
2216 u32 tdma_instant_excute: 1;
2218 u16 slot_dur[CXST_MAX];
2226 struct rtw89_btc_ctrl {
2229 u32 always_freerun: 1;
2234 struct rtw89_btc_dbg {
2240 enum rtw89_btc_btf_fw_event {
2242 BTF_EVNT_BT_INFO = 1,
2243 BTF_EVNT_BT_SCBD = 2,
2244 BTF_EVNT_BT_REG = 3,
2245 BTF_EVNT_CX_RUNINFO = 4,
2246 BTF_EVNT_BT_PSD = 5,
2247 BTF_EVNT_BUF_OVERFLOW,
2248 BTF_EVNT_C2H_LOOPBACK,
2252 enum btf_fw_event_report {
2253 BTC_RPT_TYPE_CTRL = 0x0,
2258 BTC_RPT_TYPE_NULLSTA,
2260 BTC_RPT_TYPE_GPIO_DBG,
2261 BTC_RPT_TYPE_BT_VER,
2262 BTC_RPT_TYPE_BT_SCAN,
2263 BTC_RPT_TYPE_BT_AFH,
2264 BTC_RPT_TYPE_BT_DEVICE,
2266 BTC_RPT_TYPE_MAX = 31
2269 enum rtw_btc_btf_reg_type {
2275 REG_BT_BLUEWIZE = 0x5,
2276 REG_BT_VENDOR = 0x6,
2281 struct rtw89_btc_rpt_cmn_info {
2284 u32 req_len; /* expected rsp len */
2285 u8 req_fver; /* expected rsp fver */
2286 u8 rsp_fver; /* fver from fw */
2290 union rtw89_btc_fbtc_btafh_info {
2291 struct rtw89_btc_fbtc_btafh v1;
2292 struct rtw89_btc_fbtc_btafh_v2 v2;
2295 struct rtw89_btc_report_ctrl_state {
2296 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2297 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
2300 struct rtw89_btc_rpt_fbtc_tdma {
2301 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2302 union rtw89_btc_fbtc_tdma_le32 finfo;
2305 struct rtw89_btc_rpt_fbtc_slots {
2306 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2307 struct rtw89_btc_fbtc_slots finfo; /* info from fw */
2310 struct rtw89_btc_rpt_fbtc_cysta {
2311 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2312 union rtw89_btc_fbtc_cysta_info finfo;
2315 struct rtw89_btc_rpt_fbtc_step {
2316 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2317 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
2320 struct rtw89_btc_rpt_fbtc_nullsta {
2321 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2322 union rtw89_btc_fbtc_cynullsta_info finfo;
2325 struct rtw89_btc_rpt_fbtc_mreg {
2326 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2327 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
2330 struct rtw89_btc_rpt_fbtc_gpio_dbg {
2331 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2332 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
2335 struct rtw89_btc_rpt_fbtc_btver {
2336 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2337 struct rtw89_btc_fbtc_btver finfo; /* info from fw */
2340 struct rtw89_btc_rpt_fbtc_btscan {
2341 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2342 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
2345 struct rtw89_btc_rpt_fbtc_btafh {
2346 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2347 union rtw89_btc_fbtc_btafh_info finfo;
2350 struct rtw89_btc_rpt_fbtc_btdev {
2351 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2352 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
2355 enum rtw89_btc_btfre_type {
2356 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
2362 struct rtw89_btc_btf_fwinfo {
2366 u32 event[BTF_EVNT_MAX];
2373 struct rtw89_btc_report_ctrl_state rpt_ctrl;
2374 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
2375 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
2376 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
2377 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
2378 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
2379 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
2380 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
2381 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
2382 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
2383 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
2384 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
2387 struct rtw89_btc_ver {
2388 enum rtw89_core_chip_id chip_id;
2411 #define RTW89_BTC_POLICY_MAXLEN 512
2414 const struct rtw89_btc_ver *ver;
2416 struct rtw89_btc_cx cx;
2417 struct rtw89_btc_dm dm;
2418 struct rtw89_btc_ctrl ctrl;
2419 struct rtw89_btc_module mdinfo;
2420 struct rtw89_btc_btf_fwinfo fwinfo;
2421 struct rtw89_btc_dbg dbg;
2423 struct work_struct eapol_notify_work;
2424 struct work_struct arp_notify_work;
2425 struct work_struct dhcp_notify_work;
2426 struct work_struct icmp_notify_work;
2430 u8 policy[RTW89_BTC_POLICY_MAXLEN];
2434 bool update_policy_force;
2438 enum rtw89_ra_mode {
2439 RTW89_RA_MODE_CCK = BIT(0),
2440 RTW89_RA_MODE_OFDM = BIT(1),
2441 RTW89_RA_MODE_HT = BIT(2),
2442 RTW89_RA_MODE_VHT = BIT(3),
2443 RTW89_RA_MODE_HE = BIT(4),
2446 enum rtw89_ra_report_mode {
2447 RTW89_RA_RPT_MODE_LEGACY,
2448 RTW89_RA_RPT_MODE_HT,
2449 RTW89_RA_RPT_MODE_VHT,
2450 RTW89_RA_RPT_MODE_HE,
2453 enum rtw89_dig_noisy_level {
2454 RTW89_DIG_NOISY_LEVEL0 = -1,
2455 RTW89_DIG_NOISY_LEVEL1 = 0,
2456 RTW89_DIG_NOISY_LEVEL2 = 1,
2457 RTW89_DIG_NOISY_LEVEL3 = 2,
2458 RTW89_DIG_NOISY_LEVEL_MAX = 3,
2462 RTW89_GILTF_LGI_4XHE32 = 0,
2463 RTW89_GILTF_SGI_4XHE08 = 1,
2464 RTW89_GILTF_2XHE16 = 2,
2465 RTW89_GILTF_2XHE08 = 3,
2466 RTW89_GILTF_1XHE16 = 4,
2467 RTW89_GILTF_1XHE08 = 5,
2471 enum rtw89_rx_frame_type {
2472 RTW89_RX_TYPE_MGNT = 0,
2473 RTW89_RX_TYPE_CTRL = 1,
2474 RTW89_RX_TYPE_DATA = 2,
2475 RTW89_RX_TYPE_RSVD = 3,
2478 struct rtw89_ra_info {
2498 u8 upd_bw_nss_mask:1;
2500 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
2503 u8 ra_csi_rate_en:1;
2504 u8 fixed_csi_rate_en:1;
2515 #define RTW89_PPDU_MAX_USR 4
2516 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
2517 #define RTW89_PPDU_MAC_INFO_SIZE 8
2518 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
2520 #define RTW89_MAX_RX_AGG_NUM 64
2521 #define RTW89_MAX_TX_AGG_NUM 128
2523 struct rtw89_ampdu_params {
2528 struct rtw89_ra_report {
2529 struct rate_info txrate;
2532 bool might_fallback_legacy;
2535 DECLARE_EWMA(rssi, 10, 16);
2537 struct rtw89_ba_cam_entry {
2538 struct list_head list;
2542 #define RTW89_MAX_ADDR_CAM_NUM 128
2543 #define RTW89_MAX_BSSID_CAM_NUM 20
2544 #define RTW89_MAX_SEC_CAM_NUM 128
2545 #define RTW89_MAX_BA_CAM_NUM 8
2546 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
2548 struct rtw89_addr_cam_entry {
2556 u8 bssid_cam_idx: 6;
2559 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
2560 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
2561 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
2562 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
2565 struct rtw89_bssid_cam_entry {
2575 struct rtw89_sec_cam_entry {
2590 struct rtw89_dev *rtwdev;
2591 struct rtw89_vif *rtwvif;
2592 struct rtw89_ra_info ra;
2593 struct rtw89_ra_report ra_report;
2596 struct ewma_rssi avg_rssi;
2597 struct ewma_rssi rssi[RF_PATH_MAX];
2598 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
2599 struct ieee80211_rx_status rx_status;
2601 __le32 htc_template;
2602 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
2603 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
2604 struct list_head ba_cam_list;
2605 struct sk_buff_head roc_queue;
2608 struct cfg80211_bitrate_mask mask;
2611 u32 ampdu_max_time:4;
2612 bool cctl_tx_retry_limit;
2613 u32 data_tx_cnt_lmt:6;
2616 struct rtw89_efuse {
2622 char country_code[2];
2625 struct rtw89_phy_rate_pattern {
2632 struct rtw89_tx_wait_info {
2633 struct rcu_head rcu_head;
2634 struct completion completion;
2638 struct rtw89_tx_skb_data {
2639 struct rtw89_tx_wait_info __rcu *wait;
2643 #define RTW89_ROC_IDLE_TIMEOUT 500
2644 #define RTW89_ROC_TX_TIMEOUT 30
2645 enum rtw89_roc_state {
2652 struct ieee80211_channel chan;
2653 struct delayed_work roc_work;
2654 enum ieee80211_roc_type type;
2655 enum rtw89_roc_state state;
2659 #define RTW89_P2P_MAX_NOA_NUM 2
2662 struct list_head list;
2663 struct rtw89_dev *rtwdev;
2664 struct rtw89_roc roc;
2665 enum rtw89_sub_entity_idx sub_entity_idx;
2669 u8 mac_addr[ETH_ALEN];
2685 bool wowlan_pattern;
2690 bool dyn_tb_bedge_en;
2693 struct work_struct update_beacon_work;
2694 struct rtw89_addr_cam_entry addr_cam;
2695 struct rtw89_bssid_cam_entry bssid_cam;
2696 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
2697 struct rtw89_traffic_stats stats;
2698 struct rtw89_phy_rate_pattern rate_pattern;
2699 struct cfg80211_scan_request *scan_req;
2700 struct ieee80211_scan_ies *scan_ies;
2701 struct list_head general_pkt_list;
2704 enum rtw89_lv1_rcvy_step {
2705 RTW89_LV1_RCVY_STEP_1,
2706 RTW89_LV1_RCVY_STEP_2,
2709 struct rtw89_hci_ops {
2710 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
2711 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
2712 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
2713 void (*reset)(struct rtw89_dev *rtwdev);
2714 int (*start)(struct rtw89_dev *rtwdev);
2715 void (*stop)(struct rtw89_dev *rtwdev);
2716 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
2717 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
2718 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
2720 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
2721 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
2722 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
2723 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
2724 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
2725 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
2727 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
2728 int (*mac_post_init)(struct rtw89_dev *rtwdev);
2729 int (*deinit)(struct rtw89_dev *rtwdev);
2731 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
2732 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
2733 void (*dump_err_status)(struct rtw89_dev *rtwdev);
2734 int (*napi_poll)(struct napi_struct *napi, int budget);
2736 /* Deal with locks inside recovery_start and recovery_complete callbacks
2737 * by hci instance, and handle things which need to consider under SER.
2738 * e.g. turn on/off interrupts except for the one for halt notification.
2740 void (*recovery_start)(struct rtw89_dev *rtwdev);
2741 void (*recovery_complete)(struct rtw89_dev *rtwdev);
2743 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
2744 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
2745 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
2746 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev);
2747 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
2748 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
2749 void (*disable_intr)(struct rtw89_dev *rtwdev);
2750 void (*enable_intr)(struct rtw89_dev *rtwdev);
2751 int (*rst_bdram)(struct rtw89_dev *rtwdev);
2754 struct rtw89_hci_info {
2755 const struct rtw89_hci_ops *ops;
2756 enum rtw89_hci_type type;
2762 struct rtw89_chip_ops {
2763 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
2764 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
2765 void (*bb_reset)(struct rtw89_dev *rtwdev,
2766 enum rtw89_phy_idx phy_idx);
2767 void (*bb_sethw)(struct rtw89_dev *rtwdev);
2768 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
2769 u32 addr, u32 mask);
2770 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
2771 u32 addr, u32 mask, u32 data);
2772 void (*set_channel)(struct rtw89_dev *rtwdev,
2773 const struct rtw89_chan *chan,
2774 enum rtw89_mac_idx mac_idx,
2775 enum rtw89_phy_idx phy_idx);
2776 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
2777 struct rtw89_channel_help_params *p,
2778 const struct rtw89_chan *chan,
2779 enum rtw89_mac_idx mac_idx,
2780 enum rtw89_phy_idx phy_idx);
2781 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
2782 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
2783 void (*fem_setup)(struct rtw89_dev *rtwdev);
2784 void (*rfk_init)(struct rtw89_dev *rtwdev);
2785 void (*rfk_channel)(struct rtw89_dev *rtwdev);
2786 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
2787 enum rtw89_phy_idx phy_idx);
2788 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
2789 void (*rfk_track)(struct rtw89_dev *rtwdev);
2790 void (*power_trim)(struct rtw89_dev *rtwdev);
2791 void (*set_txpwr)(struct rtw89_dev *rtwdev,
2792 const struct rtw89_chan *chan,
2793 enum rtw89_phy_idx phy_idx);
2794 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
2795 enum rtw89_phy_idx phy_idx);
2796 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
2797 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
2798 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);
2799 void (*query_ppdu)(struct rtw89_dev *rtwdev,
2800 struct rtw89_rx_phy_ppdu *phy_ppdu,
2801 struct ieee80211_rx_status *status);
2802 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);
2803 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
2804 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
2805 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
2806 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
2807 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
2808 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
2809 struct rtw89_tx_desc_info *desc_info,
2811 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
2812 struct rtw89_tx_desc_info *desc_info,
2814 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
2815 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
2816 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
2817 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
2818 u32 *tx_en, enum rtw89_sch_tx_sel sel);
2819 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
2820 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
2821 struct rtw89_vif *rtwvif,
2822 struct rtw89_sta *rtwsta);
2824 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
2825 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
2826 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
2827 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
2828 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
2829 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
2830 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
2831 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
2832 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
2846 RTW89_DMA_B1MG = 10,
2847 RTW89_DMA_B1HI = 11,
2849 RTW89_DMA_CH_NUM = 13
2852 enum rtw89_qta_mode {
2861 struct rtw89_hfc_ch_cfg {
2870 struct rtw89_hfc_ch_info {
2875 struct rtw89_hfc_pub_cfg {
2882 struct rtw89_hfc_pub_info {
2891 struct rtw89_hfc_prec_cfg {
2898 u8 wp_ch07_full_cond;
2899 u8 wp_ch811_full_cond;
2902 struct rtw89_hfc_param {
2906 const struct rtw89_hfc_ch_cfg *ch_cfg;
2907 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
2908 struct rtw89_hfc_pub_cfg pub_cfg;
2909 struct rtw89_hfc_pub_info pub_info;
2910 struct rtw89_hfc_prec_cfg prec_cfg;
2913 struct rtw89_hfc_param_ini {
2914 const struct rtw89_hfc_ch_cfg *ch_cfg;
2915 const struct rtw89_hfc_pub_cfg *pub_cfg;
2916 const struct rtw89_hfc_prec_cfg *prec_cfg;
2920 struct rtw89_dle_size {
2926 struct rtw89_wde_quota {
2933 struct rtw89_ple_quota {
2948 struct rtw89_dle_mem {
2949 enum rtw89_qta_mode mode;
2950 const struct rtw89_dle_size *wde_size;
2951 const struct rtw89_dle_size *ple_size;
2952 const struct rtw89_wde_quota *wde_min_qt;
2953 const struct rtw89_wde_quota *wde_max_qt;
2954 const struct rtw89_ple_quota *ple_min_qt;
2955 const struct rtw89_ple_quota *ple_max_qt;
2958 struct rtw89_reg_def {
2963 struct rtw89_reg2_def {
2968 struct rtw89_reg3_def {
2974 struct rtw89_reg5_def {
2975 u8 flag; /* recognized by parsers */
2982 struct rtw89_phy_table {
2983 const struct rtw89_reg2_def *regs;
2985 enum rtw89_rf_path rf_path;
2986 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
2987 enum rtw89_rf_path rf_path, void *data);
2990 struct rtw89_txpwr_table {
2993 void (*load)(struct rtw89_dev *rtwdev,
2994 const struct rtw89_txpwr_table *tbl);
2997 struct rtw89_txpwr_rule_2ghz {
2998 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
2999 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3000 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3001 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3002 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3005 struct rtw89_txpwr_rule_5ghz {
3006 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3007 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3008 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3009 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3010 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3013 struct rtw89_txpwr_rule_6ghz {
3014 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3015 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3016 [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
3017 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3018 [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
3021 struct rtw89_rfe_parms {
3022 struct rtw89_txpwr_rule_2ghz rule_2ghz;
3023 struct rtw89_txpwr_rule_5ghz rule_5ghz;
3024 struct rtw89_txpwr_rule_6ghz rule_6ghz;
3027 struct rtw89_rfe_parms_conf {
3028 const struct rtw89_rfe_parms *rfe_parms;
3032 struct rtw89_page_regs {
3047 struct rtw89_imr_info {
3051 u32 mpdu_tx_imr_set;
3052 u32 mpdu_rx_imr_set;
3053 u32 sta_sch_imr_set;
3054 u32 txpktctl_imr_b0_reg;
3055 u32 txpktctl_imr_b0_clr;
3056 u32 txpktctl_imr_b0_set;
3057 u32 txpktctl_imr_b1_reg;
3058 u32 txpktctl_imr_b1_clr;
3059 u32 txpktctl_imr_b1_set;
3064 u32 host_disp_imr_clr;
3065 u32 host_disp_imr_set;
3066 u32 cpu_disp_imr_clr;
3067 u32 cpu_disp_imr_set;
3068 u32 other_disp_imr_clr;
3069 u32 other_disp_imr_set;
3070 u32 bbrpt_com_err_imr_reg;
3071 u32 bbrpt_chinfo_err_imr_reg;
3072 u32 bbrpt_err_imr_set;
3073 u32 bbrpt_dfs_err_imr_reg;
3082 u32 phy_intf_imr_reg;
3083 u32 phy_intf_imr_clr;
3084 u32 phy_intf_imr_set;
3093 struct rtw89_rrsr_cfgs {
3094 struct rtw89_reg3_def ref_rate;
3095 struct rtw89_reg3_def rsc;
3098 struct rtw89_dig_regs {
3100 u32 pd_lower_bound_mask;
3101 u32 pd_spatial_reuse_en;
3102 struct rtw89_reg_def p0_lna_init;
3103 struct rtw89_reg_def p1_lna_init;
3104 struct rtw89_reg_def p0_tia_init;
3105 struct rtw89_reg_def p1_tia_init;
3106 struct rtw89_reg_def p0_rxb_init;
3107 struct rtw89_reg_def p1_rxb_init;
3108 struct rtw89_reg_def p0_p20_pagcugc_en;
3109 struct rtw89_reg_def p0_s20_pagcugc_en;
3110 struct rtw89_reg_def p1_p20_pagcugc_en;
3111 struct rtw89_reg_def p1_s20_pagcugc_en;
3114 struct rtw89_phy_ul_tb_info {
3119 struct rtw89_chip_info {
3120 enum rtw89_core_chip_id chip_id;
3121 const struct rtw89_chip_ops *ops;
3122 const char *fw_basename;
3126 u32 dle_scc_rsvd_size;
3127 u16 max_amsdu_limit;
3128 bool dis_2g_40m_ul_ofdma;
3130 const struct rtw89_hfc_param_ini *hfc_param_ini;
3131 const struct rtw89_dle_mem *dle_mem;
3132 u8 wde_qempty_acq_num;
3133 u8 wde_qempty_mgq_sel;
3134 u32 rf_base_addr[2];
3135 u8 support_chanctx_num;
3138 bool support_ul_tb_ctrl;
3147 u8 bacam_dynamic_num;
3150 u8 sec_ctrl_efuse_size;
3151 u32 physical_efuse_size;
3152 u32 logical_efuse_size;
3153 u32 limit_efuse_size;
3154 u32 dav_phy_efuse_size;
3155 u32 dav_log_efuse_size;
3159 const struct rtw89_pwr_cfg * const *pwr_on_seq;
3160 const struct rtw89_pwr_cfg * const *pwr_off_seq;
3161 const struct rtw89_phy_table *bb_table;
3162 const struct rtw89_phy_table *bb_gain_table;
3163 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
3164 const struct rtw89_phy_table *nctl_table;
3165 const struct rtw89_txpwr_table *byr_table;
3166 const struct rtw89_phy_dig_gain_table *dig_table;
3167 const struct rtw89_dig_regs *dig_regs;
3168 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
3170 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
3171 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
3172 const struct rtw89_rfe_parms *dflt_parms;
3175 u8 txpwr_factor_mac;
3184 const u8 *wl_rssi_thres;
3185 const u8 *bt_rssi_thres;
3189 const struct rtw89_btc_fbtc_mreg *mon_reg;
3190 u8 rf_para_ulink_num;
3191 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
3192 u8 rf_para_dlink_num;
3193 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
3194 u8 ps_mode_supported;
3195 u8 low_power_hci_modes;
3197 u32 h2c_cctl_func_id;
3198 u32 hci_func_en_addr;
3202 const u32 *h2c_regs;
3203 struct rtw89_reg_def h2c_counter_reg;
3205 const u32 *c2h_regs;
3206 struct rtw89_reg_def c2h_counter_reg;
3207 const struct rtw89_page_regs *page_regs;
3210 const struct rtw89_reg_def *dcfo_comp;
3212 const struct rtw89_imr_info *imr_info;
3213 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
3214 u32 bss_clr_map_reg;
3217 const struct wiphy_wowlan_support *wowlan_stub;
3220 union rtw89_bus_info {
3221 const struct rtw89_pci_info *pci;
3224 struct rtw89_driver_info {
3225 const struct rtw89_chip_info *chip;
3226 union rtw89_bus_info bus;
3229 enum rtw89_hcifc_mode {
3230 RTW89_HCIFC_POH = 0,
3231 RTW89_HCIFC_STF = 1,
3232 RTW89_HCIFC_SDIO = 2,
3235 RTW89_HCIFC_MODE_INVALID,
3238 struct rtw89_dle_info {
3239 enum rtw89_qta_mode qta_mode;
3246 enum rtw89_host_rpr_mode {
3247 RTW89_RPR_MODE_POH = 0,
3251 struct rtw89_mac_info {
3252 struct rtw89_dle_info dle_info;
3253 struct rtw89_hfc_param hfc_param;
3254 enum rtw89_qta_mode qta_mode;
3259 #define RTW89_COMPLETION_BUF_SIZE 24
3260 #define RTW89_WAIT_COND_IDLE UINT_MAX
3262 struct rtw89_completion_data {
3264 u8 buf[RTW89_COMPLETION_BUF_SIZE];
3267 struct rtw89_wait_info {
3269 struct completion completion;
3270 struct rtw89_completion_data data;
3273 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
3275 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
3277 init_completion(&wait->completion);
3278 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
3281 enum rtw89_fw_type {
3282 RTW89_FW_NORMAL = 1,
3283 RTW89_FW_WOWLAN = 3,
3284 RTW89_FW_NORMAL_CE = 5,
3287 enum rtw89_fw_feature {
3288 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
3289 RTW89_FW_FEATURE_SCAN_OFFLOAD,
3290 RTW89_FW_FEATURE_TX_WAKE,
3291 RTW89_FW_FEATURE_CRASH_TRIGGER,
3292 RTW89_FW_FEATURE_NO_PACKET_DROP,
3293 RTW89_FW_FEATURE_NO_DEEP_PS,
3294 RTW89_FW_FEATURE_NO_LPS_PG,
3295 RTW89_FW_FEATURE_BEACON_FILTER,
3298 struct rtw89_fw_suit {
3313 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
3314 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
3315 #define RTW89_FW_SUIT_VER_CODE(s) \
3316 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
3318 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
3319 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
3320 (mfw_hdr)->ver.minor, \
3321 (mfw_hdr)->ver.sub, \
3324 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \
3325 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \
3326 GET_FW_HDR_MINOR_VERSION(fw_hdr), \
3327 GET_FW_HDR_SUBVERSION(fw_hdr), \
3328 GET_FW_HDR_SUBINDEX(fw_hdr))
3330 struct rtw89_fw_req_info {
3331 const struct firmware *firmware;
3332 struct completion completion;
3335 struct rtw89_fw_info {
3336 struct rtw89_fw_req_info req;
3342 struct rtw89_fw_suit normal;
3343 struct rtw89_fw_suit wowlan;
3348 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
3349 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
3351 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
3352 ((_fw)->feature_map |= BIT(_fw_feature))
3354 struct rtw89_cam_info {
3355 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
3356 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
3357 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
3358 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
3359 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
3362 enum rtw89_sar_sources {
3363 RTW89_SAR_SOURCE_NONE,
3364 RTW89_SAR_SOURCE_COMMON,
3366 RTW89_SAR_SOURCE_NR,
3369 enum rtw89_sar_subband {
3370 RTW89_SAR_2GHZ_SUBBAND,
3371 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
3372 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
3373 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */
3374 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
3375 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
3376 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
3377 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
3378 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
3379 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
3381 RTW89_SAR_SUBBAND_NR,
3384 struct rtw89_sar_cfg_common {
3385 bool set[RTW89_SAR_SUBBAND_NR];
3386 s32 cfg[RTW89_SAR_SUBBAND_NR];
3389 struct rtw89_sar_info {
3390 /* used to decide how to acces SAR cfg union */
3391 enum rtw89_sar_sources src;
3393 /* reserved for different knids of SAR cfg struct.
3394 * supposed that a single cfg struct cannot handle various SAR sources.
3397 struct rtw89_sar_cfg_common cfg_common;
3401 struct rtw89_chanctx_cfg {
3402 enum rtw89_sub_entity_idx idx;
3405 enum rtw89_entity_mode {
3406 RTW89_ENTITY_MODE_SCC,
3409 struct rtw89_sub_entity {
3410 struct cfg80211_chan_def chandef;
3411 struct rtw89_chan chan;
3412 struct rtw89_chan_rcd rcd;
3413 struct rtw89_chanctx_cfg *cfg;
3420 u32 sw_amsdu_max_size;
3425 bool tx_path_diversity;
3428 atomic_t roc_entity_idx;
3430 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
3431 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
3432 struct cfg80211_chan_def roc_chandef;
3435 enum rtw89_entity_mode entity_mode;
3440 #define RTW89_MAX_MAC_ID_NUM 128
3441 #define RTW89_MAX_PKT_OFLD_NUM 255
3447 RTW89_FLAG_BFEE_MON,
3449 RTW89_FLAG_BFEE_TIMER_KEEP,
3450 RTW89_FLAG_NAPI_RUNNING,
3451 RTW89_FLAG_LEISURE_PS,
3452 RTW89_FLAG_LOW_POWER_MODE,
3453 RTW89_FLAG_INACTIVE_PS,
3454 RTW89_FLAG_CRASH_SIMULATING,
3456 RTW89_FLAG_FORBIDDEN_TRACK_WROK,
3457 RTW89_FLAG_CHANGING_INTERFACE,
3462 enum rtw89_pkt_drop_sel {
3463 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
3464 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
3465 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
3466 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
3467 RTW89_PKT_DROP_SEL_MACID_ALL,
3468 RTW89_PKT_DROP_SEL_MG0_ONCE,
3469 RTW89_PKT_DROP_SEL_HIQ_ONCE,
3470 RTW89_PKT_DROP_SEL_HIQ_PORT,
3471 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
3472 RTW89_PKT_DROP_SEL_BAND,
3473 RTW89_PKT_DROP_SEL_BAND_ONCE,
3474 RTW89_PKT_DROP_SEL_REL_MACID,
3475 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
3476 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
3479 struct rtw89_pkt_drop_params {
3480 enum rtw89_pkt_drop_sel sel;
3481 enum rtw89_mac_idx mac_band;
3486 u32 macid_band_sel[4];
3489 struct rtw89_pkt_stat {
3491 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
3494 DECLARE_EWMA(thermal, 4, 4);
3496 struct rtw89_phy_stat {
3497 struct ewma_thermal avg_thermal[RF_PATH_MAX];
3498 struct rtw89_pkt_stat cur_pkt_stat;
3499 struct rtw89_pkt_stat last_pkt_stat;
3502 #define RTW89_DACK_PATH_NR 2
3503 #define RTW89_DACK_IDX_NR 2
3504 #define RTW89_DACK_MSBK_NR 16
3505 struct rtw89_dack_info {
3507 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
3508 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3509 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3510 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3512 bool addck_timeout[RTW89_DACK_PATH_NR];
3513 bool dadck_timeout[RTW89_DACK_PATH_NR];
3514 bool msbk_timeout[RTW89_DACK_PATH_NR];
3517 #define RTW89_IQK_CHS_NR 2
3518 #define RTW89_IQK_PATH_NR 4
3520 struct rtw89_rfk_mcc_info {
3521 u8 ch[RTW89_IQK_CHS_NR];
3522 u8 band[RTW89_IQK_CHS_NR];
3526 struct rtw89_lck_info {
3527 u8 thermal[RF_PATH_MAX];
3530 struct rtw89_rx_dck_info {
3531 u8 thermal[RF_PATH_MAX];
3534 struct rtw89_iqk_info {
3535 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3536 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3537 bool lok_fail[RTW89_IQK_PATH_NR];
3538 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3539 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3542 u32 iqk_channel[RTW89_IQK_CHS_NR];
3543 u8 iqk_band[RTW89_IQK_PATH_NR];
3544 u8 iqk_ch[RTW89_IQK_PATH_NR];
3545 u8 iqk_bw[RTW89_IQK_PATH_NR];
3549 u32 nb_txcfir[RTW89_IQK_PATH_NR];
3550 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
3551 u32 bp_txkresult[RTW89_IQK_PATH_NR];
3552 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
3553 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
3554 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
3555 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
3561 u8 thermal[RTW89_IQK_PATH_NR];
3562 bool thermal_rek_en;
3564 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3565 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
3566 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3567 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3570 #define RTW89_DPK_RF_PATH 2
3571 #define RTW89_DPK_AVG_THERMAL_NUM 8
3572 #define RTW89_DPK_BKUP_NUM 2
3573 struct rtw89_dpk_bkup_para {
3574 enum rtw89_band band;
3575 enum rtw89_bandwidth bw;
3585 struct rtw89_dpk_info {
3587 bool is_dpk_reload_en;
3588 u8 dpk_gs[RTW89_PHY_MAX];
3589 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3590 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3591 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3592 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3593 u8 cur_idx[RTW89_DPK_RF_PATH];
3595 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3598 struct rtw89_fem_info {
3606 struct rtw89_phy_ch_info {
3620 struct rtw89_agc_gaincode_set {
3626 #define IGI_RSSI_TH_NUM 5
3628 #define LNA_GAIN_NUM 7
3629 #define TIA_GAIN_NUM 2
3630 struct rtw89_dig_info {
3631 struct rtw89_agc_gaincode_set cur_gaincode;
3632 bool force_gaincode_idx_en;
3633 struct rtw89_agc_gaincode_set force_gaincode;
3634 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
3635 u16 fa_th[FA_TH_NUM];
3646 s8 lna_gain_a[LNA_GAIN_NUM];
3647 s8 lna_gain_g[LNA_GAIN_NUM];
3649 s8 tia_gain_a[TIA_GAIN_NUM];
3650 s8 tia_gain_g[TIA_GAIN_NUM];
3656 enum rtw89_multi_cfo_mode {
3657 RTW89_PKT_BASED_AVG_MODE = 0,
3658 RTW89_ENTRY_BASED_AVG_MODE = 1,
3659 RTW89_TP_BASED_AVG_MODE = 2,
3662 enum rtw89_phy_cfo_status {
3663 RTW89_PHY_DCFO_STATE_NORMAL = 0,
3664 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
3665 RTW89_PHY_DCFO_STATE_HOLD = 2,
3666 RTW89_PHY_DCFO_STATE_MAX
3669 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
3670 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
3671 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
3674 struct rtw89_cfo_tracking_info {
3676 bool cfo_trig_by_timer_en;
3677 enum rtw89_phy_cfo_status phy_cfo_status;
3678 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
3681 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
3682 bool apply_compensation;
3684 u8 crystal_cap_default;
3687 u32 sta_cfo_tolerance;
3688 s32 cfo_tail[CFO_TRACK_MAX_USER];
3689 u16 cfo_cnt[CFO_TRACK_MAX_USER];
3691 s32 cfo_avg[CFO_TRACK_MAX_USER];
3692 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
3696 u32 packet_count_pre;
3697 s32 residual_cfo_acc;
3698 u8 phy_cfotrk_state;
3700 bool divergence_lock_en;
3706 enum rtw89_tssi_alimk_band {
3714 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
3715 #define TSSI_TRIM_CH_GROUP_NUM 8
3716 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
3718 #define TSSI_CCK_CH_GROUP_NUM 6
3719 #define TSSI_MCS_2G_CH_GROUP_NUM 5
3720 #define TSSI_MCS_5G_CH_GROUP_NUM 14
3721 #define TSSI_MCS_6G_CH_GROUP_NUM 32
3722 #define TSSI_MCS_CH_GROUP_NUM \
3723 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
3724 #define TSSI_MAX_CH_NUM 67
3725 #define TSSI_ALIMK_VALUE_NUM 8
3727 struct rtw89_tssi_info {
3728 u8 thermal[RF_PATH_MAX];
3729 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
3730 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
3731 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
3732 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
3733 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
3734 s8 extra_ofst[RF_PATH_MAX];
3735 bool tssi_tracking_check[RF_PATH_MAX];
3736 u8 default_txagc_offset[RF_PATH_MAX];
3737 u32 base_thermal[RF_PATH_MAX];
3738 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
3739 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
3740 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
3741 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
3742 u32 tssi_alimk_time;
3745 struct rtw89_power_trim_info {
3746 bool pg_thermal_trim;
3747 bool pg_pa_bias_trim;
3748 u8 thermal_trim[RF_PATH_MAX];
3749 u8 pa_bias_trim[RF_PATH_MAX];
3752 struct rtw89_regulatory {
3754 u8 txpwr_regd[RTW89_BAND_MAX];
3757 enum rtw89_ifs_clm_application {
3758 RTW89_IFS_CLM_INIT = 0,
3759 RTW89_IFS_CLM_BACKGROUND = 1,
3760 RTW89_IFS_CLM_ACS = 2,
3761 RTW89_IFS_CLM_DIG = 3,
3762 RTW89_IFS_CLM_TDMA_DIG = 4,
3763 RTW89_IFS_CLM_DBG = 5,
3764 RTW89_IFS_CLM_DBG_MANUAL = 6
3767 enum rtw89_env_racing_lv {
3768 RTW89_RAC_RELEASE = 0,
3773 RTW89_RAC_MAX_NUM = 5
3776 struct rtw89_ccx_para_info {
3777 enum rtw89_env_racing_lv rac_lv;
3779 u8 nhm_manual_th_ofst;
3781 enum rtw89_ifs_clm_application ifs_clm_app;
3782 u32 ifs_clm_manual_th_times;
3783 u32 ifs_clm_manual_th0;
3784 u8 fahm_manual_th_ofst;
3790 enum rtw89_ccx_edcca_opt_sc_idx {
3791 RTW89_CCX_EDCCA_SEG0_P0 = 0,
3792 RTW89_CCX_EDCCA_SEG0_S1 = 1,
3793 RTW89_CCX_EDCCA_SEG0_S2 = 2,
3794 RTW89_CCX_EDCCA_SEG0_S3 = 3,
3795 RTW89_CCX_EDCCA_SEG1_P0 = 4,
3796 RTW89_CCX_EDCCA_SEG1_S1 = 5,
3797 RTW89_CCX_EDCCA_SEG1_S2 = 6,
3798 RTW89_CCX_EDCCA_SEG1_S3 = 7
3801 enum rtw89_ccx_edcca_opt_bw_idx {
3802 RTW89_CCX_EDCCA_BW20_0 = 0,
3803 RTW89_CCX_EDCCA_BW20_1 = 1,
3804 RTW89_CCX_EDCCA_BW20_2 = 2,
3805 RTW89_CCX_EDCCA_BW20_3 = 3,
3806 RTW89_CCX_EDCCA_BW20_4 = 4,
3807 RTW89_CCX_EDCCA_BW20_5 = 5,
3808 RTW89_CCX_EDCCA_BW20_6 = 6,
3809 RTW89_CCX_EDCCA_BW20_7 = 7
3812 #define RTW89_NHM_TH_NUM 11
3813 #define RTW89_FAHM_TH_NUM 11
3814 #define RTW89_NHM_RPT_NUM 12
3815 #define RTW89_FAHM_RPT_NUM 12
3816 #define RTW89_IFS_CLM_NUM 4
3817 struct rtw89_env_monitor_info {
3818 u32 ccx_trigger_time;
3821 u8 ccx_watchdog_result;
3824 bool ccx_manual_ctrl;
3828 u16 ifs_clm_mntr_time;
3829 enum rtw89_ifs_clm_application ifs_clm_app;
3831 u16 edcca_clm_mntr_time;
3834 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx;
3835 u8 nhm_th[RTW89_NHM_TH_NUM];
3836 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
3837 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
3840 u8 fahm_th[RTW89_FAHM_TH_NUM];
3842 u16 nhm_result[RTW89_NHM_RPT_NUM];
3843 u8 nhm_wgt[RTW89_NHM_RPT_NUM];
3848 u16 ifs_clm_edcca_excl_cca;
3850 u16 ifs_clm_ofdmcca_excl_fa;
3852 u16 ifs_clm_cckcca_excl_fa;
3853 u16 ifs_clm_total_ifs;
3854 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
3855 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
3856 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
3857 u16 fahm_result[RTW89_FAHM_RPT_NUM];
3858 u16 fahm_denom_result;
3859 u16 edcca_clm_result;
3861 u8 nhm_rpt[RTW89_NHM_RPT_NUM];
3868 u8 ifs_clm_tx_ratio;
3869 u8 ifs_clm_edcca_excl_cca_ratio;
3870 u8 ifs_clm_cck_fa_ratio;
3871 u8 ifs_clm_ofdm_fa_ratio;
3872 u8 ifs_clm_cck_cca_excl_fa_ratio;
3873 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
3874 u16 ifs_clm_cck_fa_permil;
3875 u16 ifs_clm_ofdm_fa_permil;
3876 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
3877 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
3878 u8 fahm_rpt[RTW89_FAHM_RPT_NUM];
3879 u16 fahm_result_sum;
3881 u8 fahm_denom_ratio;
3886 enum rtw89_ser_rcvy_step {
3887 RTW89_SER_DRV_STOP_TX,
3888 RTW89_SER_DRV_STOP_RX,
3889 RTW89_SER_DRV_STOP_RUN,
3890 RTW89_SER_HAL_STOP_DMA,
3891 RTW89_NUM_OF_SER_FLAGS
3898 struct work_struct ser_hdl_work;
3899 struct delayed_work ser_alarm_work;
3900 const struct state_ent *st_tbl;
3901 const struct event_ent *ev_tbl;
3902 struct list_head msg_q;
3903 spinlock_t msg_q_lock; /* lock when read/write ser msg */
3904 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
3907 enum rtw89_mac_ax_ps_mode {
3908 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
3909 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
3910 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
3911 RTW89_MAC_AX_PS_MODE_MAX = 3,
3914 enum rtw89_last_rpwm_mode {
3915 RTW89_LAST_RPWM_PS = 0x0,
3916 RTW89_LAST_RPWM_ACTIVE = 0x6,
3919 struct rtw89_lps_parm {
3921 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
3922 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
3925 struct rtw89_ppdu_sts_info {
3926 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
3927 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
3930 struct rtw89_early_h2c {
3931 struct list_head list;
3936 struct rtw89_hw_scan_info {
3937 struct ieee80211_vif *scanning_vif;
3938 struct list_head pkt_list[NUM_NL80211_BANDS];
3939 struct rtw89_chan op_chan;
3943 enum rtw89_phy_bb_gain_band {
3944 RTW89_BB_GAIN_BAND_2G = 0,
3945 RTW89_BB_GAIN_BAND_5G_L = 1,
3946 RTW89_BB_GAIN_BAND_5G_M = 2,
3947 RTW89_BB_GAIN_BAND_5G_H = 3,
3948 RTW89_BB_GAIN_BAND_6G_L = 4,
3949 RTW89_BB_GAIN_BAND_6G_M = 5,
3950 RTW89_BB_GAIN_BAND_6G_H = 6,
3951 RTW89_BB_GAIN_BAND_6G_UH = 7,
3953 RTW89_BB_GAIN_BAND_NR,
3956 enum rtw89_phy_bb_rxsc_num {
3957 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
3958 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
3959 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
3962 struct rtw89_phy_bb_gain_info {
3963 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3964 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
3965 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3966 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3967 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3968 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
3969 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
3970 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3971 [RTW89_BB_RXSC_NUM_40];
3972 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3973 [RTW89_BB_RXSC_NUM_80];
3974 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3975 [RTW89_BB_RXSC_NUM_160];
3978 struct rtw89_phy_efuse_gain {
3981 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
3982 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
3983 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
3984 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
3987 #define RTW89_MAX_PATTERN_NUM 18
3988 #define RTW89_MAX_PATTERN_MASK_SIZE 4
3989 #define RTW89_MAX_PATTERN_SIZE 128
3991 struct rtw89_wow_cam_info {
3994 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
3996 bool negative_pattern_match;
4004 struct rtw89_wow_param {
4005 struct ieee80211_vif *wow_vif;
4006 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
4007 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
4011 struct rtw89_mcc_info {
4012 struct rtw89_wait_info wait;
4016 struct ieee80211_hw *hw;
4018 const struct ieee80211_ops *ops;
4021 struct rtw89_hw_scan_info scan_info;
4022 const struct rtw89_chip_info *chip;
4023 const struct rtw89_pci_info *pci_info;
4024 const struct rtw89_rfe_parms *rfe_parms;
4025 struct rtw89_hal hal;
4026 struct rtw89_mcc_info mcc;
4027 struct rtw89_mac_info mac;
4028 struct rtw89_fw_info fw;
4029 struct rtw89_hci_info hci;
4030 struct rtw89_efuse efuse;
4031 struct rtw89_traffic_stats stats;
4033 /* ensures exclusive access from mac80211 callbacks */
4035 struct list_head rtwvifs_list;
4036 /* used to protect rf read write */
4037 struct mutex rf_mutex;
4038 struct workqueue_struct *txq_wq;
4039 struct work_struct txq_work;
4040 struct delayed_work txq_reinvoke_work;
4041 /* used to protect ba_list and forbid_ba_list */
4043 /* txqs to setup ba session */
4044 struct list_head ba_list;
4045 /* txqs to forbid ba session */
4046 struct list_head forbid_ba_list;
4047 struct work_struct ba_work;
4048 /* used to protect rpwm */
4049 spinlock_t rpwm_lock;
4051 struct rtw89_cam_info cam_info;
4053 struct sk_buff_head c2h_queue;
4054 struct work_struct c2h_work;
4055 struct work_struct ips_work;
4056 struct work_struct load_firmware_work;
4058 struct list_head early_h2c_list;
4060 struct rtw89_ser ser;
4062 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
4063 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
4064 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
4065 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
4067 struct rtw89_phy_stat phystat;
4068 struct rtw89_dack_info dack;
4069 struct rtw89_iqk_info iqk;
4070 struct rtw89_dpk_info dpk;
4071 struct rtw89_rfk_mcc_info rfk_mcc;
4072 struct rtw89_lck_info lck;
4073 struct rtw89_rx_dck_info rx_dck;
4074 bool is_tssi_mode[RF_PATH_MAX];
4075 bool is_bt_iqk_timeout;
4077 struct rtw89_fem_info fem;
4078 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX];
4079 struct rtw89_tssi_info tssi;
4080 struct rtw89_power_trim_info pwr_trim;
4082 struct rtw89_cfo_tracking_info cfo_tracking;
4083 struct rtw89_env_monitor_info env_monitor;
4084 struct rtw89_dig_info dig;
4085 struct rtw89_phy_ch_info ch_info;
4086 struct rtw89_phy_bb_gain_info bb_gain;
4087 struct rtw89_phy_efuse_gain efuse_gain;
4088 struct rtw89_phy_ul_tb_info ul_tb_info;
4090 struct delayed_work track_work;
4091 struct delayed_work coex_act1_work;
4092 struct delayed_work coex_bt_devinfo_work;
4093 struct delayed_work coex_rfk_chk_work;
4094 struct delayed_work cfo_track_work;
4095 struct delayed_work forbid_ba_work;
4096 struct delayed_work roc_work;
4097 struct rtw89_ppdu_sts_info ppdu_sts;
4101 const struct rtw89_regulatory *regd;
4102 struct rtw89_sar_info sar;
4104 struct rtw89_btc btc;
4105 enum rtw89_ps_mode ps_mode;
4108 struct rtw89_wow_param wow;
4110 /* napi structure */
4111 struct net_device netdev;
4112 struct napi_struct napi;
4113 int napi_budget_countdown;
4115 /* HCI related data, keep last */
4116 u8 priv[] __aligned(sizeof(void *));
4119 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
4120 struct rtw89_core_tx_request *tx_req)
4122 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
4125 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
4127 rtwdev->hci.ops->reset(rtwdev);
4130 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
4132 return rtwdev->hci.ops->start(rtwdev);
4135 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
4137 rtwdev->hci.ops->stop(rtwdev);
4140 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
4142 return rtwdev->hci.ops->deinit(rtwdev);
4145 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
4147 rtwdev->hci.ops->pause(rtwdev, pause);
4150 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
4152 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
4155 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
4157 rtwdev->hci.ops->recalc_int_mit(rtwdev);
4160 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
4162 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
4165 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
4167 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
4170 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
4173 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4176 if (rtwdev->hci.ops->flush_queues)
4177 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
4180 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
4182 if (rtwdev->hci.ops->recovery_start)
4183 rtwdev->hci.ops->recovery_start(rtwdev);
4186 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
4188 if (rtwdev->hci.ops->recovery_complete)
4189 rtwdev->hci.ops->recovery_complete(rtwdev);
4192 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
4194 if (rtwdev->hci.ops->enable_intr)
4195 rtwdev->hci.ops->enable_intr(rtwdev);
4198 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
4200 if (rtwdev->hci.ops->disable_intr)
4201 rtwdev->hci.ops->disable_intr(rtwdev);
4204 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
4206 if (rtwdev->hci.ops->ctrl_txdma_ch)
4207 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
4210 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
4212 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
4213 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
4216 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
4218 if (rtwdev->hci.ops->ctrl_trxhci)
4219 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
4222 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev)
4226 if (rtwdev->hci.ops->poll_txdma_ch)
4227 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev);
4231 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
4233 if (rtwdev->hci.ops->clr_idx_all)
4234 rtwdev->hci.ops->clr_idx_all(rtwdev);
4237 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
4241 if (rtwdev->hci.ops->rst_bdram)
4242 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
4246 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
4248 if (rtwdev->hci.ops->clear)
4249 rtwdev->hci.ops->clear(rtwdev, pdev);
4253 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
4255 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
4257 return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
4260 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
4262 return rtwdev->hci.ops->read8(rtwdev, addr);
4265 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
4267 return rtwdev->hci.ops->read16(rtwdev, addr);
4270 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
4272 return rtwdev->hci.ops->read32(rtwdev, addr);
4275 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
4277 rtwdev->hci.ops->write8(rtwdev, addr, data);
4280 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
4282 rtwdev->hci.ops->write16(rtwdev, addr, data);
4285 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
4287 rtwdev->hci.ops->write32(rtwdev, addr, data);
4291 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
4295 val = rtw89_read8(rtwdev, addr);
4296 rtw89_write8(rtwdev, addr, val | bit);
4300 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
4304 val = rtw89_read16(rtwdev, addr);
4305 rtw89_write16(rtwdev, addr, val | bit);
4309 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
4313 val = rtw89_read32(rtwdev, addr);
4314 rtw89_write32(rtwdev, addr, val | bit);
4318 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
4322 val = rtw89_read8(rtwdev, addr);
4323 rtw89_write8(rtwdev, addr, val & ~bit);
4327 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
4331 val = rtw89_read16(rtwdev, addr);
4332 rtw89_write16(rtwdev, addr, val & ~bit);
4336 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
4340 val = rtw89_read32(rtwdev, addr);
4341 rtw89_write32(rtwdev, addr, val & ~bit);
4345 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4347 u32 shift = __ffs(mask);
4351 orig = rtw89_read32(rtwdev, addr);
4352 ret = (orig & mask) >> shift;
4358 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4360 u32 shift = __ffs(mask);
4364 orig = rtw89_read16(rtwdev, addr);
4365 ret = (orig & mask) >> shift;
4371 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4373 u32 shift = __ffs(mask);
4377 orig = rtw89_read8(rtwdev, addr);
4378 ret = (orig & mask) >> shift;
4384 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
4386 u32 shift = __ffs(mask);
4390 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
4392 orig = rtw89_read32(rtwdev, addr);
4393 set = (orig & ~mask) | ((data << shift) & mask);
4394 rtw89_write32(rtwdev, addr, set);
4398 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
4404 shift = __ffs(mask);
4406 orig = rtw89_read16(rtwdev, addr);
4407 set = (orig & ~mask) | ((data << shift) & mask);
4408 rtw89_write16(rtwdev, addr, set);
4412 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
4418 shift = __ffs(mask);
4420 orig = rtw89_read8(rtwdev, addr);
4421 set = (orig & ~mask) | ((data << shift) & mask);
4422 rtw89_write8(rtwdev, addr, set);
4426 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
4431 mutex_lock(&rtwdev->rf_mutex);
4432 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
4433 mutex_unlock(&rtwdev->rf_mutex);
4439 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
4440 u32 addr, u32 mask, u32 data)
4442 mutex_lock(&rtwdev->rf_mutex);
4443 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
4444 mutex_unlock(&rtwdev->rf_mutex);
4447 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
4451 return container_of(p, struct ieee80211_txq, drv_priv);
4454 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
4455 struct ieee80211_txq *txq)
4457 struct rtw89_txq *rtwtxq;
4462 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4463 INIT_LIST_HEAD(&rtwtxq->list);
4466 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
4470 return container_of(p, struct ieee80211_vif, drv_priv);
4473 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
4475 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
4478 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
4480 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
4483 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
4487 return container_of(p, struct ieee80211_sta, drv_priv);
4490 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
4492 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
4495 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
4497 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
4500 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
4502 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
4503 return RATE_INFO_BW_160;
4504 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
4505 return RATE_INFO_BW_80;
4506 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
4507 return RATE_INFO_BW_40;
4509 return RATE_INFO_BW_20;
4513 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
4518 return NL80211_BAND_2GHZ;
4520 return NL80211_BAND_5GHZ;
4522 return NL80211_BAND_6GHZ;
4527 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
4531 case NL80211_BAND_2GHZ:
4532 return RTW89_BAND_2G;
4533 case NL80211_BAND_5GHZ:
4534 return RTW89_BAND_5G;
4535 case NL80211_BAND_6GHZ:
4536 return RTW89_BAND_6G;
4541 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
4545 WARN(1, "Not support bandwidth %d\n", width);
4547 case NL80211_CHAN_WIDTH_20_NOHT:
4548 case NL80211_CHAN_WIDTH_20:
4549 return RTW89_CHANNEL_WIDTH_20;
4550 case NL80211_CHAN_WIDTH_40:
4551 return RTW89_CHANNEL_WIDTH_40;
4552 case NL80211_CHAN_WIDTH_80:
4553 return RTW89_CHANNEL_WIDTH_80;
4554 case NL80211_CHAN_WIDTH_160:
4555 return RTW89_CHANNEL_WIDTH_160;
4560 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
4561 struct rtw89_sta *rtwsta)
4564 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4566 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
4567 return &rtwsta->addr_cam;
4569 return &rtwvif->addr_cam;
4573 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
4574 struct rtw89_sta *rtwsta)
4577 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4580 return &rtwsta->bssid_cam;
4582 return &rtwvif->bssid_cam;
4586 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
4587 struct rtw89_channel_help_params *p,
4588 const struct rtw89_chan *chan,
4589 enum rtw89_mac_idx mac_idx,
4590 enum rtw89_phy_idx phy_idx)
4592 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
4597 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
4598 struct rtw89_channel_help_params *p,
4599 const struct rtw89_chan *chan,
4600 enum rtw89_mac_idx mac_idx,
4601 enum rtw89_phy_idx phy_idx)
4603 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
4608 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
4609 enum rtw89_sub_entity_idx idx)
4611 struct rtw89_hal *hal = &rtwdev->hal;
4612 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx);
4615 return &hal->roc_chandef;
4617 return &hal->sub[idx].chandef;
4621 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
4622 enum rtw89_sub_entity_idx idx)
4624 struct rtw89_hal *hal = &rtwdev->hal;
4626 return &hal->sub[idx].chan;
4630 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
4631 enum rtw89_sub_entity_idx idx)
4633 struct rtw89_hal *hal = &rtwdev->hal;
4635 return &hal->sub[idx].rcd;
4638 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
4640 const struct rtw89_chip_info *chip = rtwdev->chip;
4642 if (chip->ops->fem_setup)
4643 chip->ops->fem_setup(rtwdev);
4646 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
4648 const struct rtw89_chip_info *chip = rtwdev->chip;
4650 if (chip->ops->bb_sethw)
4651 chip->ops->bb_sethw(rtwdev);
4654 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
4656 const struct rtw89_chip_info *chip = rtwdev->chip;
4658 if (chip->ops->rfk_init)
4659 chip->ops->rfk_init(rtwdev);
4662 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
4664 const struct rtw89_chip_info *chip = rtwdev->chip;
4666 if (chip->ops->rfk_channel)
4667 chip->ops->rfk_channel(rtwdev);
4670 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
4671 enum rtw89_phy_idx phy_idx)
4673 const struct rtw89_chip_info *chip = rtwdev->chip;
4675 if (chip->ops->rfk_band_changed)
4676 chip->ops->rfk_band_changed(rtwdev, phy_idx);
4679 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
4681 const struct rtw89_chip_info *chip = rtwdev->chip;
4683 if (chip->ops->rfk_scan)
4684 chip->ops->rfk_scan(rtwdev, start);
4687 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
4689 const struct rtw89_chip_info *chip = rtwdev->chip;
4691 if (chip->ops->rfk_track)
4692 chip->ops->rfk_track(rtwdev);
4695 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
4697 const struct rtw89_chip_info *chip = rtwdev->chip;
4699 if (chip->ops->set_txpwr_ctrl)
4700 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
4703 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
4705 const struct rtw89_chip_info *chip = rtwdev->chip;
4707 if (chip->ops->power_trim)
4708 chip->ops->power_trim(rtwdev);
4711 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
4712 enum rtw89_phy_idx phy_idx)
4714 const struct rtw89_chip_info *chip = rtwdev->chip;
4716 if (chip->ops->init_txpwr_unit)
4717 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
4720 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
4721 enum rtw89_rf_path rf_path)
4723 const struct rtw89_chip_info *chip = rtwdev->chip;
4725 if (!chip->ops->get_thermal)
4728 return chip->ops->get_thermal(rtwdev, rf_path);
4731 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
4732 struct rtw89_rx_phy_ppdu *phy_ppdu,
4733 struct ieee80211_rx_status *status)
4735 const struct rtw89_chip_info *chip = rtwdev->chip;
4737 if (chip->ops->query_ppdu)
4738 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
4741 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,
4744 const struct rtw89_chip_info *chip = rtwdev->chip;
4746 if (chip->ops->bb_ctrl_btc_preagc)
4747 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en);
4750 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
4752 const struct rtw89_chip_info *chip = rtwdev->chip;
4754 if (chip->ops->cfg_txrx_path)
4755 chip->ops->cfg_txrx_path(rtwdev);
4759 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
4760 struct ieee80211_vif *vif)
4762 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4763 const struct rtw89_chip_info *chip = rtwdev->chip;
4765 if (!vif->bss_conf.he_support || !vif->cfg.assoc)
4768 if (chip->ops->set_txpwr_ul_tb_offset)
4769 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
4772 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
4773 const struct rtw89_txpwr_table *tbl)
4775 tbl->load(rtwdev, tbl);
4778 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
4780 return rtwdev->regd->txpwr_regd[band];
4783 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
4785 const struct rtw89_chip_info *chip = rtwdev->chip;
4787 if (chip->ops->ctrl_btg)
4788 chip->ops->ctrl_btg(rtwdev, btg);
4792 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
4793 struct rtw89_tx_desc_info *desc_info,
4796 const struct rtw89_chip_info *chip = rtwdev->chip;
4798 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
4802 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
4803 struct rtw89_tx_desc_info *desc_info,
4806 const struct rtw89_chip_info *chip = rtwdev->chip;
4808 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
4812 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
4813 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
4815 const struct rtw89_chip_info *chip = rtwdev->chip;
4817 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
4820 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
4822 const struct rtw89_chip_info *chip = rtwdev->chip;
4824 chip->ops->cfg_ctrl_path(rtwdev, wl);
4828 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
4829 u32 *tx_en, enum rtw89_sch_tx_sel sel)
4831 const struct rtw89_chip_info *chip = rtwdev->chip;
4833 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
4837 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
4839 const struct rtw89_chip_info *chip = rtwdev->chip;
4841 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
4845 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
4846 struct rtw89_vif *rtwvif,
4847 struct rtw89_sta *rtwsta)
4849 const struct rtw89_chip_info *chip = rtwdev->chip;
4851 if (!chip->ops->h2c_dctl_sec_cam)
4853 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
4856 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
4858 __le16 fc = hdr->frame_control;
4860 if (ieee80211_has_tods(fc))
4862 else if (ieee80211_has_fromds(fc))
4868 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
4870 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
4871 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
4872 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
4873 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
4874 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
4875 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
4880 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
4881 enum rtw89_fw_type type)
4883 struct rtw89_fw_info *fw_info = &rtwdev->fw;
4885 if (type == RTW89_FW_WOWLAN)
4886 return &fw_info->wowlan;
4887 return &fw_info->normal;
4890 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
4891 unsigned int length)
4893 struct sk_buff *skb;
4895 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
4896 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
4900 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
4904 return dev_alloc_skb(length);
4907 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
4908 struct rtw89_tx_skb_data *skb_data,
4911 struct rtw89_tx_wait_info *wait;
4915 wait = rcu_dereference(skb_data->wait);
4919 wait->tx_done = tx_done;
4920 complete(&wait->completion);
4926 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4927 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
4928 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
4929 struct sk_buff *skb, bool fwdl);
4930 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
4931 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4932 int qsel, unsigned int timeout);
4933 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
4934 struct rtw89_tx_desc_info *desc_info,
4936 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
4937 struct rtw89_tx_desc_info *desc_info,
4939 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
4940 struct rtw89_tx_desc_info *desc_info,
4942 void rtw89_core_rx(struct rtw89_dev *rtwdev,
4943 struct rtw89_rx_desc_info *desc_info,
4944 struct sk_buff *skb);
4945 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
4946 struct rtw89_rx_desc_info *desc_info,
4947 u8 *data, u32 data_offset);
4948 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
4949 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
4950 void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
4951 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
4952 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
4953 struct ieee80211_vif *vif,
4954 struct ieee80211_sta *sta);
4955 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
4956 struct ieee80211_vif *vif,
4957 struct ieee80211_sta *sta);
4958 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
4959 struct ieee80211_vif *vif,
4960 struct ieee80211_sta *sta);
4961 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
4962 struct ieee80211_vif *vif,
4963 struct ieee80211_sta *sta);
4964 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
4965 struct ieee80211_vif *vif,
4966 struct ieee80211_sta *sta);
4967 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
4968 struct ieee80211_sta *sta,
4969 struct cfg80211_tid_config *tid_config);
4970 int rtw89_core_init(struct rtw89_dev *rtwdev);
4971 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
4972 int rtw89_core_register(struct rtw89_dev *rtwdev);
4973 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
4974 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
4976 const struct rtw89_chip_info *chip);
4977 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
4978 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
4979 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
4980 void rtw89_set_channel(struct rtw89_dev *rtwdev);
4981 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4982 struct rtw89_chan *chan);
4983 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
4984 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
4985 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
4986 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
4987 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
4988 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
4989 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
4990 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
4991 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
4992 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
4993 int rtw89_regd_init(struct rtw89_dev *rtwdev,
4994 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
4995 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
4996 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
4997 struct rtw89_traffic_stats *stats);
4998 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
4999 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
5000 const struct rtw89_completion_data *data);
5001 int rtw89_core_start(struct rtw89_dev *rtwdev);
5002 void rtw89_core_stop(struct rtw89_dev *rtwdev);
5003 void rtw89_core_update_beacon_work(struct work_struct *work);
5004 void rtw89_roc_work(struct work_struct *work);
5005 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5006 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5007 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5008 const u8 *mac_addr, bool hw_scan);
5009 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
5010 struct ieee80211_vif *vif, bool hw_scan);