1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
12 #include "rtw8822b_table.h"
17 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
18 u8 rx_path, bool is_tx2_path);
20 static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse,
21 struct rtw8822b_efuse *map)
23 ether_addr_copy(efuse->addr, map->e.mac_addr);
26 static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
28 struct rtw_efuse *efuse = &rtwdev->efuse;
29 struct rtw8822b_efuse *map;
32 map = (struct rtw8822b_efuse *)log_map;
34 efuse->rfe_option = map->rfe_option;
35 efuse->rf_board_option = map->rf_board_option;
36 efuse->crystal_cap = map->xtal_k;
37 efuse->pa_type_2g = map->pa_type;
38 efuse->pa_type_5g = map->pa_type;
39 efuse->lna_type_2g = map->lna_type_2g[0];
40 efuse->lna_type_5g = map->lna_type_5g[0];
41 efuse->channel_plan = map->channel_plan;
42 efuse->country_code[0] = map->country_code[0];
43 efuse->country_code[1] = map->country_code[1];
44 efuse->bt_setting = map->rf_bt_setting;
45 efuse->regd = map->rf_board_option & 0x7;
47 for (i = 0; i < 4; i++)
48 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
50 switch (rtw_hci_type(rtwdev)) {
51 case RTW_HCI_TYPE_PCIE:
52 rtw8822be_efuse_parsing(efuse, map);
62 static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev)
65 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3);
66 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0);
67 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1);
70 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30);
71 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3);
74 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f);
75 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3);
78 static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev)
80 struct rtw_hal *hal = &rtwdev->hal;
84 /* power on BB/RF domain */
85 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
86 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
87 rtw_write8_set(rtwdev, REG_RF_CTRL,
88 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
89 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
91 /* pre init before header files config */
92 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
94 rtw_phy_load_tables(rtwdev);
96 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
97 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap);
98 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap);
100 /* post init after header files config */
101 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
104 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
106 rtw_phy_init(rtwdev);
108 rtw8822b_phy_rfe_init(rtwdev);
111 #define WLAN_SLOT_TIME 0x09
112 #define WLAN_PIFS_TIME 0x19
113 #define WLAN_SIFS_CCK_CONT_TX 0xA
114 #define WLAN_SIFS_OFDM_CONT_TX 0xE
115 #define WLAN_SIFS_CCK_TRX 0x10
116 #define WLAN_SIFS_OFDM_TRX 0x10
117 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
118 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
119 #define WLAN_RDG_NAV 0x05
120 #define WLAN_TXOP_NAV 0x1B
121 #define WLAN_CCK_RX_TSF 0x30
122 #define WLAN_OFDM_RX_TSF 0x30
123 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
124 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
125 #define WLAN_DRV_EARLY_INT 0x04
126 #define WLAN_BCN_DMA_TIME 0x02
128 #define WLAN_RX_FILTER0 0x0FFFFFFF
129 #define WLAN_RX_FILTER2 0xFFFF
130 #define WLAN_RCR_CFG 0xE400220E
131 #define WLAN_RXPKT_MAX_SZ 12288
132 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
134 #define WLAN_AMPDU_MAX_TIME 0x70
135 #define WLAN_RTS_LEN_TH 0xFF
136 #define WLAN_RTS_TX_TIME_TH 0x08
137 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
138 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
139 #define FAST_EDCA_VO_TH 0x06
140 #define FAST_EDCA_VI_TH 0x06
141 #define FAST_EDCA_BE_TH 0x06
142 #define FAST_EDCA_BK_TH 0x06
143 #define WLAN_BAR_RETRY_LIMIT 0x01
144 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
146 #define WLAN_TX_FUNC_CFG1 0x30
147 #define WLAN_TX_FUNC_CFG2 0x30
148 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
149 #define WLAN_MAC_OPT_LB_FUNC1 0x80
150 #define WLAN_MAC_OPT_FUNC2 0x30810041
152 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
153 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
154 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
155 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
157 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
158 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
160 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
161 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
163 static int rtw8822b_mac_init(struct rtw_dev *rtwdev)
167 /* protocol configuration */
168 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD);
169 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
170 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
171 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
172 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
173 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
174 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
175 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
176 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
177 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
178 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
179 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
180 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
181 /* EDCA configuration */
182 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
183 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
184 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
185 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
186 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
187 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
188 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
189 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
190 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
191 /* Set beacon cotnrol - enable TSF and other related functions */
192 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
193 /* Set send beacon related registers */
194 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
195 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
196 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
197 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
198 /* WMAC configuration */
199 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
200 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
201 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
202 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
203 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
204 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
205 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
206 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
211 static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel)
213 struct rtw_hal *hal = &rtwdev->hal;
214 bool is_channel_2g = (channel <= 14) ? true : false;
217 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770);
218 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
219 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0);
221 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517);
222 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
223 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0);
226 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
228 if (hal->antenna_rx == BB_PATH_AB ||
229 hal->antenna_tx == BB_PATH_AB) {
231 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
232 } else if (hal->antenna_rx == hal->antenna_tx) {
233 /* TXA+RXA or TXB+RXB */
234 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
236 /* TXB+RXA or TXA+RXB */
237 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
241 static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel)
243 struct rtw_hal *hal = &rtwdev->hal;
244 bool is_channel_2g = (channel <= 14) ? true : false;
248 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774);
249 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
252 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547);
253 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
256 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
259 if (hal->antenna_rx == BB_PATH_AB ||
260 hal->antenna_tx == BB_PATH_AB) {
262 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
263 } else if (hal->antenna_rx == hal->antenna_tx) {
264 /* TXA+RXA or TXB+RXB */
265 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
267 /* TXB+RXA or TXA+RXB */
268 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
271 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5);
284 u32 reg82c[CCUT_IDX_NR];
285 u32 reg830[CCUT_IDX_NR];
286 u32 reg838[CCUT_IDX_NR];
289 static const struct cca_ccut cca_ifem_ccut = {
290 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
291 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
292 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/
295 static const struct cca_ccut cca_efem_ccut = {
296 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/
297 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/
298 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
301 static const struct cca_ccut cca_ifem_ccut_ext = {
302 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/
303 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
304 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/
307 static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col,
308 u32 *reg82c, u32 *reg830, u32 *reg838)
310 *reg82c = cca_ccut->reg82c[col];
311 *reg830 = cca_ccut->reg830[col];
312 *reg838 = cca_ccut->reg838[col];
315 struct rtw8822b_rfe_info {
316 const struct cca_ccut *cca_ccut_2g;
317 const struct cca_ccut *cca_ccut_5g;
318 enum rtw_rfe_fem fem;
320 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel);
323 #define I2GE5G_CCUT(set_ch) { \
324 .cca_ccut_2g = &cca_ifem_ccut, \
325 .cca_ccut_5g = &cca_efem_ccut, \
326 .fem = RTW_RFE_IFEM2G_EFEM5G, \
328 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
330 #define IFEM_EXT_CCUT(set_ch) { \
331 .cca_ccut_2g = &cca_ifem_ccut_ext, \
332 .cca_ccut_5g = &cca_ifem_ccut_ext, \
333 .fem = RTW_RFE_IFEM, \
335 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
338 static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = {
339 [2] = I2GE5G_CCUT(efem),
340 [5] = IFEM_EXT_CCUT(ifem),
343 static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw,
344 const struct rtw8822b_rfe_info *rfe_info)
346 struct rtw_hal *hal = &rtwdev->hal;
347 struct rtw_efuse *efuse = &rtwdev->efuse;
348 const struct cca_ccut *cca_ccut;
350 u32 reg82c, reg830, reg838;
351 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false;
354 cca_ccut = rfe_info->cca_ccut_2g;
356 if (hal->antenna_rx == BB_PATH_A ||
357 hal->antenna_rx == BB_PATH_B)
358 col = CCUT_IDX_1R_2G;
360 col = CCUT_IDX_2R_2G;
362 cca_ccut = rfe_info->cca_ccut_5g;
364 if (hal->antenna_rx == BB_PATH_A ||
365 hal->antenna_rx == BB_PATH_B)
366 col = CCUT_IDX_1R_5G;
368 col = CCUT_IDX_2R_5G;
371 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838);
373 switch (rfe_info->fem) {
377 if (rfe_info->ifem_ext)
383 case RTW_RFE_IFEM2G_EFEM5G:
392 if ((hal->cut_version == RTW_CHIP_VER_CUT_B &&
393 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) &&
394 bw == RTW_CHANNEL_WIDTH_40) ||
395 (!is_rfe_type && col == CCUT_IDX_2R_5G &&
396 bw == RTW_CHANNEL_WIDTH_40) ||
397 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G))
401 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c);
402 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830);
403 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838);
405 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B))
406 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9);
408 if (bw == RTW_CHANNEL_WIDTH_20 &&
409 ((channel >= 52 && channel <= 64) ||
410 (channel >= 100 && channel <= 144)))
411 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4);
414 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
415 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
416 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
417 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
418 0x6, 0x5, 0x0, 0x0, 0x7};
419 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
420 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
422 static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
424 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
425 #define RF18_BAND_2G (0)
426 #define RF18_BAND_5G (BIT(16) | BIT(8))
427 #define RF18_CHANNEL_MASK (MASKBYTE0)
428 #define RF18_RFSI_MASK (BIT(18) | BIT(17))
429 #define RF18_RFSI_GE_CH80 (BIT(17))
430 #define RF18_RFSI_GT_CH144 (BIT(18))
431 #define RF18_BW_MASK (BIT(11) | BIT(10))
432 #define RF18_BW_20M (BIT(11) | BIT(10))
433 #define RF18_BW_40M (BIT(11))
434 #define RF18_BW_80M (BIT(10))
435 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15))
437 struct rtw_hal *hal = &rtwdev->hal;
438 u32 rf_reg18, rf_reg_be;
440 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
442 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
445 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
446 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
448 rf_reg18 |= RF18_RFSI_GT_CH144;
449 else if (channel >= 80)
450 rf_reg18 |= RF18_RFSI_GE_CH80;
453 case RTW_CHANNEL_WIDTH_5:
454 case RTW_CHANNEL_WIDTH_10:
455 case RTW_CHANNEL_WIDTH_20:
457 rf_reg18 |= RF18_BW_20M;
459 case RTW_CHANNEL_WIDTH_40:
460 rf_reg18 |= RF18_BW_40M;
462 case RTW_CHANNEL_WIDTH_80:
463 rf_reg18 |= RF18_BW_80M;
469 else if (channel >= 36 && channel <= 64)
470 rf_reg_be = low_band[(channel - 36) >> 1];
471 else if (channel >= 100 && channel <= 144)
472 rf_reg_be = middle_band[(channel - 100) >> 1];
473 else if (channel >= 149 && channel <= 177)
474 rf_reg_be = high_band[(channel - 149) >> 1];
478 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be);
480 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
482 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1);
484 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0);
486 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
487 if (hal->rf_type > RF_1T1R)
488 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18);
490 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
491 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
499 static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev)
501 struct rtw_hal *hal = &rtwdev->hal;
504 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f);
505 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2);
506 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi);
507 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2);
508 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi);
510 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0);
511 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0,
512 hal->antenna_rx | (hal->antenna_rx << 4));
515 static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
517 if (bw == RTW_CHANNEL_WIDTH_40) {
518 /* RX DFIR for BW40 */
519 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1);
520 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0);
521 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
522 } else if (bw == RTW_CHANNEL_WIDTH_80) {
523 /* RX DFIR for BW80 */
524 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
525 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
526 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
528 /* RX DFIR for BW20, BW10 and BW5*/
529 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
530 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
531 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
535 static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
538 struct rtw_efuse *efuse = &rtwdev->efuse;
539 u8 rfe_option = efuse->rfe_option;
543 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
544 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
545 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
546 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
548 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0);
549 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
551 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577);
552 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
554 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577);
555 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525);
558 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2);
559 } else if (channel > 35) {
560 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
561 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
562 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
563 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34);
565 if (channel >= 36 && channel <= 64)
566 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1);
567 else if (channel >= 100 && channel <= 144)
568 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2);
569 else if (channel >= 149)
570 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3);
572 if (channel >= 36 && channel <= 48)
573 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
574 else if (channel >= 52 && channel <= 64)
575 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
576 else if (channel >= 100 && channel <= 116)
577 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
578 else if (channel >= 118 && channel <= 177)
579 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
581 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1);
585 case RTW_CHANNEL_WIDTH_20:
587 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
589 val32 |= (RTW_CHANNEL_WIDTH_20);
590 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
592 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
594 case RTW_CHANNEL_WIDTH_40:
595 if (primary_ch_idx == 1)
596 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
598 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
600 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
602 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40);
603 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
605 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
607 case RTW_CHANNEL_WIDTH_80:
608 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
610 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80);
611 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
613 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
615 if (rfe_option == 2) {
616 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6);
617 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1);
620 case RTW_CHANNEL_WIDTH_5:
621 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
623 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20));
624 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
626 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
627 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
629 case RTW_CHANNEL_WIDTH_10:
630 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
632 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20));
633 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
635 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
636 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
641 static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
644 struct rtw_efuse *efuse = &rtwdev->efuse;
645 const struct rtw8822b_rfe_info *rfe_info;
647 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
648 "rfe_option %d is out of boundary\n", efuse->rfe_option))
651 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
653 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
654 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
655 rtw8822b_set_channel_rf(rtwdev, channel, bw);
656 rtw8822b_set_channel_rxdfir(rtwdev, bw);
657 rtw8822b_toggle_igi(rtwdev);
658 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info);
659 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel);
662 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
663 u8 rx_path, bool is_tx2_path)
665 struct rtw_efuse *efuse = &rtwdev->efuse;
666 const struct rtw8822b_rfe_info *rfe_info;
667 u8 ch = rtwdev->hal.current_channel;
668 u8 tx_path_sel, rx_path_sel;
671 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
672 "rfe_option %d is out of boundary\n", efuse->rfe_option))
675 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
677 if ((tx_path | rx_path) & BB_PATH_A)
678 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231);
680 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111);
682 if ((tx_path | rx_path) & BB_PATH_B)
683 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231);
685 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111);
687 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3);
688 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1);
689 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1);
691 if (tx_path & BB_PATH_A) {
692 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001);
693 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8);
694 } else if (tx_path & BB_PATH_B) {
695 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002);
696 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4);
699 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B)
700 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01);
702 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43);
704 tx_path_sel = (tx_path << 4) | tx_path;
705 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel);
707 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) {
708 if (is_tx2_path || rtwdev->mp_mode) {
709 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043);
710 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc);
714 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0);
715 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0);
717 if (rx_path & BB_PATH_A)
718 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0);
719 else if (rx_path & BB_PATH_B)
720 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5);
722 rx_path_sel = (rx_path << 4) | rx_path;
723 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel);
725 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
726 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0);
727 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0);
728 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0);
730 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1);
731 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1);
732 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1);
735 for (counter = 100; counter > 0; counter--) {
738 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
739 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
742 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK);
744 if (rf_reg33 == 0x00001)
748 if (WARN(counter <= 0, "write RF mode table fail\n"))
751 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
752 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
753 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034);
754 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c);
755 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
756 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
758 rtw8822b_toggle_igi(rtwdev);
759 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info);
760 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch);
763 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
764 struct rtw_rx_pkt_stat *pkt_stat)
766 s8 min_rx_power = -120;
767 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status);
769 /* 8822B uses only 1 antenna to RX CCK rates */
770 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110;
771 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
772 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
773 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
777 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
778 struct rtw_rx_pkt_stat *pkt_stat)
781 s8 min_rx_power = -120;
783 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
784 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
786 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
788 if (rxsc >= 1 && rxsc <= 8)
789 bw = RTW_CHANNEL_WIDTH_20;
790 else if (rxsc >= 9 && rxsc <= 12)
791 bw = RTW_CHANNEL_WIDTH_40;
793 bw = RTW_CHANNEL_WIDTH_80;
795 bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
797 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
798 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
799 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
801 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
802 pkt_stat->rx_power[RF_PATH_B],
806 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
807 struct rtw_rx_pkt_stat *pkt_stat)
811 page = *phy_status & 0xf;
815 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
818 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
821 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
826 static void rtw8822b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
827 struct rtw_rx_pkt_stat *pkt_stat,
828 struct ieee80211_rx_status *rx_status)
830 struct ieee80211_hdr *hdr;
831 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
832 u8 *phy_status = NULL;
834 memset(pkt_stat, 0, sizeof(*pkt_stat));
836 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
837 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
838 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
839 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc);
840 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
841 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
842 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
843 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
844 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
845 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
846 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
847 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
849 /* drv_info_sz is in unit of 8-bytes */
850 pkt_stat->drv_info_sz *= 8;
852 /* c2h cmd pkt's rx/phy status is not interested */
853 if (pkt_stat->is_c2h)
856 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
857 pkt_stat->drv_info_sz);
858 if (pkt_stat->phy_status) {
859 phy_status = rx_desc + desc_sz + pkt_stat->shift;
860 query_phy_status(rtwdev, phy_status, pkt_stat);
863 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
867 rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
869 struct rtw_hal *hal = &rtwdev->hal;
870 static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
871 static u32 phy_pwr_idx;
872 u8 rate, rate_idx, pwr_index, shift;
875 for (j = 0; j < rtw_rate_size[rs]; j++) {
876 rate = rtw_rate_section[rs][j];
877 pwr_index = hal->tx_pwr_tbl[path][rate];
879 phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
881 rate_idx = rate & 0xfc;
882 rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
889 static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev)
891 struct rtw_hal *hal = &rtwdev->hal;
894 for (path = 0; path < hal->rf_path_num; path++) {
895 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
896 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs);
900 static bool rtw8822b_check_rf_path(u8 antenna)
912 static void rtw8822b_set_antenna(struct rtw_dev *rtwdev, u8 antenna_tx,
915 struct rtw_hal *hal = &rtwdev->hal;
917 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n",
918 antenna_tx, antenna_rx);
920 if (!rtw8822b_check_rf_path(antenna_tx)) {
921 rtw_info(rtwdev, "unsupport tx path, set to default path ab\n");
922 antenna_tx = BB_PATH_AB;
924 if (!rtw8822b_check_rf_path(antenna_rx)) {
925 rtw_info(rtwdev, "unsupport rx path, set to default path ab\n");
926 antenna_rx = BB_PATH_AB;
928 hal->antenna_tx = antenna_tx;
929 hal->antenna_rx = antenna_rx;
930 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
933 static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
937 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
938 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
939 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
942 static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev)
944 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
950 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
951 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c);
952 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48);
954 dm_info->cck_fa_cnt = cck_fa_cnt;
955 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
956 dm_info->total_fa_cnt = ofdm_fa_cnt;
957 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
959 crc32_cnt = rtw_read32(rtwdev, 0xf04);
960 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
961 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
962 crc32_cnt = rtw_read32(rtwdev, 0xf14);
963 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
964 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
965 crc32_cnt = rtw_read32(rtwdev, 0xf10);
966 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
967 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
968 crc32_cnt = rtw_read32(rtwdev, 0xf0c);
969 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
970 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
972 rtw_write32_set(rtwdev, 0x9a4, BIT(17));
973 rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
974 rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
975 rtw_write32_set(rtwdev, 0xa2c, BIT(15));
976 rtw_write32_set(rtwdev, 0xb58, BIT(0));
977 rtw_write32_clr(rtwdev, 0xb58, BIT(0));
980 static void rtw8822b_do_iqk(struct rtw_dev *rtwdev)
982 static int do_iqk_cnt;
983 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
984 u32 rf_reg, iqk_fail_mask;
988 rtw_fw_do_iqk(rtwdev, ¶);
990 for (counter = 0; counter < 300; counter++) {
991 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
992 if (rf_reg == 0xabcde)
996 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
998 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
999 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
1000 rtw_dbg(rtwdev, RTW_DBG_PHY,
1001 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
1002 counter, reload, ++do_iqk_cnt, iqk_fail_mask);
1005 static void rtw8822b_phy_calibration(struct rtw_dev *rtwdev)
1007 rtw8822b_do_iqk(rtwdev);
1010 static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev)
1012 /* enable TBTT nterrupt */
1013 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1015 /* BT report packet sample rate */
1016 /* 0x790[5:0]=0x5 */
1017 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
1019 /* enable BT counter statistics */
1020 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
1022 /* enable PTA (3-wire function form BT side) */
1023 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
1024 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
1026 /* enable PTA (tx/rx signal form WiFi side) */
1027 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
1028 /* wl tx signal to PTA not case EDCCA */
1029 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
1030 /* GNT_BT=1 while select both */
1031 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
1034 static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev,
1035 u8 ctrl_type, u8 pos_type)
1037 struct rtw_coex *coex = &rtwdev->coex;
1038 struct rtw_coex_dm *coex_dm = &coex->dm;
1039 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1040 bool polarity_inverse;
1043 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)
1046 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;
1048 if (coex_rfe->ant_switch_diversity &&
1049 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
1050 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
1052 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
1054 switch (ctrl_type) {
1056 case COEX_SWITCH_CTRL_BY_BBSW:
1058 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1060 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1061 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
1062 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77);
1064 if (pos_type == COEX_SWITCH_TO_WLG_BT) {
1065 if (coex_rfe->rfe_module_type != 0x4 &&
1066 coex_rfe->rfe_module_type != 0x2)
1069 regval = (!polarity_inverse ? 0x2 : 0x1);
1070 } else if (pos_type == COEX_SWITCH_TO_WLG) {
1071 regval = (!polarity_inverse ? 0x2 : 0x1);
1073 regval = (!polarity_inverse ? 0x1 : 0x2);
1076 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1078 case COEX_SWITCH_CTRL_BY_PTA:
1080 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1082 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1083 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
1084 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66);
1086 regval = (!polarity_inverse ? 0x2 : 0x1);
1087 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1089 case COEX_SWITCH_CTRL_BY_ANTDIV:
1091 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1093 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1094 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88);
1096 case COEX_SWITCH_CTRL_BY_MAC:
1098 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1);
1100 regval = (!polarity_inverse ? 0x0 : 0x1);
1101 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval);
1103 case COEX_SWITCH_CTRL_BY_FW:
1105 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1107 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1109 case COEX_SWITCH_CTRL_BY_BT:
1111 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1113 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0);
1118 static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1122 static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1124 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
1125 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
1126 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
1127 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
1128 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
1131 static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1133 struct rtw_coex *coex = &rtwdev->coex;
1134 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1135 struct rtw_efuse *efuse = &rtwdev->efuse;
1136 bool is_ext_fem = false;
1138 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1139 coex_rfe->ant_switch_polarity = 0;
1140 coex_rfe->ant_switch_diversity = false;
1141 if (coex_rfe->rfe_module_type == 0x12 ||
1142 coex_rfe->rfe_module_type == 0x15 ||
1143 coex_rfe->rfe_module_type == 0x16)
1144 coex_rfe->ant_switch_exist = false;
1146 coex_rfe->ant_switch_exist = true;
1148 if (coex_rfe->rfe_module_type == 2 ||
1149 coex_rfe->rfe_module_type == 4) {
1150 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true);
1153 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false);
1156 coex_rfe->wlg_at_btg = false;
1158 if (efuse->share_ant &&
1159 coex_rfe->ant_switch_exist && !is_ext_fem)
1160 coex_rfe->ant_switch_with_bt = true;
1162 coex_rfe->ant_switch_with_bt = false;
1164 /* Ext switch buffer mux */
1165 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff);
1166 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0);
1167 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0);
1169 /* Disable LTE Coex Function in WiFi side */
1170 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0);
1172 /* BTC_CTT_WL_VS_LTE */
1173 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1175 /* BTC_CTT_BT_VS_LTE */
1176 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1179 static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1181 struct rtw_coex *coex = &rtwdev->coex;
1182 struct rtw_coex_dm *coex_dm = &coex->dm;
1183 static const u16 reg_addr[] = {0xc58, 0xe58};
1184 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8};
1187 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1190 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1192 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1193 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1195 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1197 for (i = 0; i < ARRAY_SIZE(reg_addr); i++)
1198 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr);
1201 static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1203 struct rtw_coex *coex = &rtwdev->coex;
1204 struct rtw_coex_dm *coex_dm = &coex->dm;
1205 /* WL Rx Low gain on */
1206 static const u32 wl_rx_low_gain_on[] = {
1207 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003,
1208 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003,
1209 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003,
1210 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003,
1211 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003,
1212 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003,
1213 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003,
1214 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003,
1218 /* WL Rx Low gain off */
1219 static const u32 wl_rx_low_gain_off[] = {
1220 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003,
1221 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003,
1222 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003,
1223 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003,
1224 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003,
1225 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003,
1226 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003,
1227 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003,
1232 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1235 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1237 if (coex_dm->cur_wl_rx_low_gain_en) {
1238 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1239 rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]);
1241 /* set Rx filter corner RCK offset */
1242 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1);
1243 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f);
1244 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1);
1245 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f);
1247 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1248 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]);
1250 /* set Rx filter corner RCK offset */
1251 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4);
1252 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0);
1253 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4);
1254 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0);
1258 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = {
1260 RTW_PWR_CUT_ALL_MSK,
1261 RTW_PWR_INTF_SDIO_MSK,
1263 RTW_PWR_CMD_WRITE, BIT(0), 0},
1265 RTW_PWR_CUT_ALL_MSK,
1266 RTW_PWR_INTF_SDIO_MSK,
1268 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1270 RTW_PWR_CUT_ALL_MSK,
1271 RTW_PWR_INTF_USB_MSK,
1273 RTW_PWR_CMD_WRITE, BIT(0), 0},
1275 RTW_PWR_CUT_ALL_MSK,
1276 RTW_PWR_INTF_ALL_MSK,
1278 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1280 RTW_PWR_CUT_ALL_MSK,
1281 RTW_PWR_INTF_PCI_MSK,
1283 RTW_PWR_CMD_WRITE, 0xFF, 0},
1285 RTW_PWR_CUT_ALL_MSK,
1286 RTW_PWR_INTF_PCI_MSK,
1288 RTW_PWR_CMD_WRITE, 0xFF, 0},
1290 RTW_PWR_CUT_ALL_MSK,
1291 RTW_PWR_INTF_ALL_MSK,
1293 RTW_PWR_CMD_END, 0, 0},
1296 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = {
1298 RTW_PWR_CUT_ALL_MSK,
1299 RTW_PWR_INTF_ALL_MSK,
1301 RTW_PWR_CMD_WRITE, BIT(1), 0},
1303 RTW_PWR_CUT_ALL_MSK,
1304 RTW_PWR_INTF_ALL_MSK,
1306 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1308 RTW_PWR_CUT_ALL_MSK,
1309 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1311 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1313 RTW_PWR_CUT_ALL_MSK,
1314 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1316 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1318 RTW_PWR_CUT_ALL_MSK,
1319 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1321 RTW_PWR_CMD_WRITE, BIT(5), 0},
1323 RTW_PWR_CUT_ALL_MSK,
1324 RTW_PWR_INTF_ALL_MSK,
1326 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1328 RTW_PWR_CUT_ALL_MSK,
1329 RTW_PWR_INTF_PCI_MSK,
1331 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1333 RTW_PWR_CUT_ALL_MSK,
1334 RTW_PWR_INTF_ALL_MSK,
1336 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1338 RTW_PWR_CUT_ALL_MSK,
1339 RTW_PWR_INTF_PCI_MSK,
1341 RTW_PWR_CMD_WRITE, BIT(0), 0},
1343 RTW_PWR_CUT_ALL_MSK,
1344 RTW_PWR_INTF_USB_MSK,
1346 RTW_PWR_CMD_WRITE, 0xFF, 0},
1348 RTW_PWR_CUT_ALL_MSK,
1349 RTW_PWR_INTF_ALL_MSK,
1351 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1353 RTW_PWR_CUT_ALL_MSK,
1354 RTW_PWR_INTF_ALL_MSK,
1356 RTW_PWR_CMD_WRITE, BIT(7), 0},
1358 RTW_PWR_CUT_ALL_MSK,
1359 RTW_PWR_INTF_ALL_MSK,
1361 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1363 RTW_PWR_CUT_ALL_MSK,
1364 RTW_PWR_INTF_USB_MSK,
1366 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1368 RTW_PWR_CUT_ALL_MSK,
1369 RTW_PWR_INTF_ALL_MSK,
1371 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1373 RTW_PWR_CUT_ALL_MSK,
1374 RTW_PWR_INTF_ALL_MSK,
1376 RTW_PWR_CMD_POLLING, BIT(0), 0},
1378 RTW_PWR_CUT_ALL_MSK,
1379 RTW_PWR_INTF_ALL_MSK,
1381 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1384 RTW_PWR_INTF_ALL_MSK,
1386 RTW_PWR_CMD_WRITE, 0xFF, 0},
1389 RTW_PWR_INTF_ALL_MSK,
1391 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1394 RTW_PWR_INTF_ALL_MSK,
1396 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1399 RTW_PWR_INTF_SDIO_MSK,
1401 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1403 RTW_PWR_CUT_ALL_MSK,
1404 RTW_PWR_INTF_ALL_MSK,
1406 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1408 RTW_PWR_CUT_ALL_MSK,
1409 RTW_PWR_INTF_ALL_MSK,
1411 RTW_PWR_CMD_WRITE, BIT(2), 0},
1413 RTW_PWR_CUT_ALL_MSK,
1414 RTW_PWR_INTF_PCI_MSK,
1416 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1418 RTW_PWR_CUT_ALL_MSK,
1419 RTW_PWR_INTF_ALL_MSK,
1421 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1423 RTW_PWR_CUT_ALL_MSK,
1424 RTW_PWR_INTF_ALL_MSK,
1426 RTW_PWR_CMD_END, 0, 0},
1429 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = {
1431 RTW_PWR_CUT_ALL_MSK,
1432 RTW_PWR_INTF_SDIO_MSK,
1434 RTW_PWR_CMD_WRITE, BIT(2), 0},
1436 RTW_PWR_CUT_ALL_MSK,
1437 RTW_PWR_INTF_ALL_MSK,
1439 RTW_PWR_CMD_WRITE, BIT(3), 0},
1441 RTW_PWR_CUT_ALL_MSK,
1442 RTW_PWR_INTF_ALL_MSK,
1444 RTW_PWR_CMD_WRITE, 0xFF, 0},
1446 RTW_PWR_CUT_ALL_MSK,
1447 RTW_PWR_INTF_ALL_MSK,
1449 RTW_PWR_CMD_WRITE, 0xFF, 0},
1451 RTW_PWR_CUT_ALL_MSK,
1452 RTW_PWR_INTF_USB_MSK,
1454 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1456 RTW_PWR_CUT_ALL_MSK,
1457 RTW_PWR_INTF_ALL_MSK,
1459 RTW_PWR_CMD_WRITE, BIT(1), 0},
1461 RTW_PWR_CUT_ALL_MSK,
1462 RTW_PWR_INTF_ALL_MSK,
1464 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1466 RTW_PWR_CUT_ALL_MSK,
1467 RTW_PWR_INTF_ALL_MSK,
1469 RTW_PWR_CMD_WRITE, BIT(1), 0},
1471 RTW_PWR_CUT_ALL_MSK,
1472 RTW_PWR_INTF_USB_MSK,
1474 RTW_PWR_CMD_WRITE, BIT(0), 0},
1476 RTW_PWR_CUT_ALL_MSK,
1477 RTW_PWR_INTF_ALL_MSK,
1479 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1481 RTW_PWR_CUT_ALL_MSK,
1482 RTW_PWR_INTF_ALL_MSK,
1484 RTW_PWR_CMD_POLLING, BIT(1), 0},
1486 RTW_PWR_CUT_ALL_MSK,
1487 RTW_PWR_INTF_ALL_MSK,
1489 RTW_PWR_CMD_WRITE, BIT(3), 0},
1491 RTW_PWR_CUT_ALL_MSK,
1492 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1494 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1496 RTW_PWR_CUT_ALL_MSK,
1497 RTW_PWR_INTF_ALL_MSK,
1499 RTW_PWR_CMD_END, 0, 0},
1502 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = {
1504 RTW_PWR_CUT_ALL_MSK,
1505 RTW_PWR_INTF_SDIO_MSK,
1507 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1509 RTW_PWR_CUT_ALL_MSK,
1510 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1512 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1514 RTW_PWR_CUT_ALL_MSK,
1515 RTW_PWR_INTF_ALL_MSK,
1517 RTW_PWR_CMD_WRITE, BIT(5), 0},
1519 RTW_PWR_CUT_ALL_MSK,
1520 RTW_PWR_INTF_PCI_MSK,
1522 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1524 RTW_PWR_CUT_ALL_MSK,
1525 RTW_PWR_INTF_USB_MSK,
1527 RTW_PWR_CMD_WRITE, BIT(0), 0},
1529 RTW_PWR_CUT_ALL_MSK,
1530 RTW_PWR_INTF_SDIO_MSK,
1532 RTW_PWR_CMD_WRITE, BIT(5), 0},
1534 RTW_PWR_CUT_ALL_MSK,
1535 RTW_PWR_INTF_SDIO_MSK,
1537 RTW_PWR_CMD_WRITE, BIT(4), 0},
1539 RTW_PWR_CUT_ALL_MSK,
1540 RTW_PWR_INTF_SDIO_MSK,
1542 RTW_PWR_CMD_WRITE, BIT(0), 0},
1544 RTW_PWR_CUT_ALL_MSK,
1545 RTW_PWR_INTF_SDIO_MSK,
1547 RTW_PWR_CMD_WRITE, BIT(1), 0},
1549 RTW_PWR_CUT_ALL_MSK,
1550 RTW_PWR_INTF_SDIO_MSK,
1552 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1554 RTW_PWR_CUT_ALL_MSK,
1555 RTW_PWR_INTF_SDIO_MSK,
1557 RTW_PWR_CMD_WRITE, BIT(2), 0},
1559 RTW_PWR_CUT_ALL_MSK,
1560 RTW_PWR_INTF_SDIO_MSK,
1562 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1564 RTW_PWR_CUT_ALL_MSK,
1565 RTW_PWR_INTF_SDIO_MSK,
1567 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1569 RTW_PWR_CUT_ALL_MSK,
1570 RTW_PWR_INTF_ALL_MSK,
1572 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1574 RTW_PWR_CUT_ALL_MSK,
1575 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1577 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1579 RTW_PWR_CUT_ALL_MSK,
1580 RTW_PWR_INTF_SDIO_MSK,
1582 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1584 RTW_PWR_CUT_ALL_MSK,
1585 RTW_PWR_INTF_SDIO_MSK,
1587 RTW_PWR_CMD_POLLING, BIT(1), 0},
1589 RTW_PWR_CUT_ALL_MSK,
1590 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1592 RTW_PWR_CMD_WRITE, BIT(1), 0},
1594 RTW_PWR_CUT_ALL_MSK,
1595 RTW_PWR_INTF_SDIO_MSK,
1597 RTW_PWR_CMD_WRITE, 0xFF, 0},
1599 RTW_PWR_CUT_ALL_MSK,
1600 RTW_PWR_INTF_SDIO_MSK,
1602 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1604 RTW_PWR_CUT_ALL_MSK,
1605 RTW_PWR_INTF_SDIO_MSK,
1607 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1609 RTW_PWR_CUT_ALL_MSK,
1610 RTW_PWR_INTF_SDIO_MSK,
1612 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1614 RTW_PWR_CUT_ALL_MSK,
1615 RTW_PWR_INTF_ALL_MSK,
1617 RTW_PWR_CMD_END, 0, 0},
1620 static struct rtw_pwr_seq_cmd *card_enable_flow_8822b[] = {
1621 trans_carddis_to_cardemu_8822b,
1622 trans_cardemu_to_act_8822b,
1626 static struct rtw_pwr_seq_cmd *card_disable_flow_8822b[] = {
1627 trans_act_to_cardemu_8822b,
1628 trans_cardemu_to_carddis_8822b,
1632 static struct rtw_intf_phy_para usb2_param_8822b[] = {
1635 RTW_INTF_PHY_CUT_ALL,
1636 RTW_INTF_PHY_PLATFORM_ALL},
1639 static struct rtw_intf_phy_para usb3_param_8822b[] = {
1643 RTW_INTF_PHY_PLATFORM_ALL},
1646 RTW_INTF_PHY_CUT_ALL,
1647 RTW_INTF_PHY_PLATFORM_ALL},
1650 static struct rtw_intf_phy_para pcie_gen1_param_8822b[] = {
1654 RTW_INTF_PHY_PLATFORM_ALL},
1658 RTW_INTF_PHY_PLATFORM_ALL},
1662 RTW_INTF_PHY_PLATFORM_ALL},
1666 RTW_INTF_PHY_PLATFORM_ALL},
1670 RTW_INTF_PHY_PLATFORM_ALL},
1674 RTW_INTF_PHY_PLATFORM_ALL},
1678 RTW_INTF_PHY_PLATFORM_ALL},
1682 RTW_INTF_PHY_PLATFORM_ALL},
1686 RTW_INTF_PHY_PLATFORM_ALL},
1690 RTW_INTF_PHY_PLATFORM_ALL},
1693 RTW_INTF_PHY_CUT_ALL,
1694 RTW_INTF_PHY_PLATFORM_ALL},
1697 static struct rtw_intf_phy_para pcie_gen2_param_8822b[] = {
1701 RTW_INTF_PHY_PLATFORM_ALL},
1705 RTW_INTF_PHY_PLATFORM_ALL},
1709 RTW_INTF_PHY_PLATFORM_ALL},
1713 RTW_INTF_PHY_PLATFORM_ALL},
1717 RTW_INTF_PHY_PLATFORM_ALL},
1721 RTW_INTF_PHY_PLATFORM_ALL},
1725 RTW_INTF_PHY_PLATFORM_ALL},
1729 RTW_INTF_PHY_PLATFORM_ALL},
1733 RTW_INTF_PHY_PLATFORM_ALL},
1737 RTW_INTF_PHY_PLATFORM_ALL},
1740 RTW_INTF_PHY_CUT_ALL,
1741 RTW_INTF_PHY_PLATFORM_ALL},
1744 static struct rtw_intf_phy_para_table phy_para_table_8822b = {
1745 .usb2_para = usb2_param_8822b,
1746 .usb3_para = usb3_param_8822b,
1747 .gen1_para = pcie_gen1_param_8822b,
1748 .gen2_para = pcie_gen2_param_8822b,
1749 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b),
1750 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b),
1751 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b),
1752 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b),
1755 static const struct rtw_rfe_def rtw8822b_rfe_defs[] = {
1756 [2] = RTW_DEF_RFE(8822b, 2, 2),
1757 [5] = RTW_DEF_RFE(8822b, 5, 5),
1760 static struct rtw_hw_reg rtw8822b_dig[] = {
1761 [0] = { .addr = 0xc50, .mask = 0x7f },
1762 [1] = { .addr = 0xe50, .mask = 0x7f },
1765 static struct rtw_page_table page_table_8822b[] = {
1766 {64, 64, 64, 64, 1},
1767 {64, 64, 64, 64, 1},
1770 {64, 64, 64, 64, 1},
1773 static struct rtw_rqpn rqpn_table_8822b[] = {
1774 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1775 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1776 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1777 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1778 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1779 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1780 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1781 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1782 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1783 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1784 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1785 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1786 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1787 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1788 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1791 static struct rtw_chip_ops rtw8822b_ops = {
1792 .phy_set_param = rtw8822b_phy_set_param,
1793 .read_efuse = rtw8822b_read_efuse,
1794 .query_rx_desc = rtw8822b_query_rx_desc,
1795 .set_channel = rtw8822b_set_channel,
1796 .mac_init = rtw8822b_mac_init,
1797 .read_rf = rtw_phy_read_rf,
1798 .write_rf = rtw_phy_write_rf_reg_sipi,
1799 .set_tx_power_index = rtw8822b_set_tx_power_index,
1800 .set_antenna = rtw8822b_set_antenna,
1801 .cfg_ldo25 = rtw8822b_cfg_ldo25,
1802 .false_alarm_statistics = rtw8822b_false_alarm_statistics,
1803 .phy_calibration = rtw8822b_phy_calibration,
1805 .coex_set_init = rtw8822b_coex_cfg_init,
1806 .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch,
1807 .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix,
1808 .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug,
1809 .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type,
1810 .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power,
1811 .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain,
1814 /* Shared-Antenna Coex Table */
1815 static const struct coex_table_para table_sant_8822b[] = {
1816 {0xffffffff, 0xffffffff}, /* case-0 */
1817 {0x55555555, 0x55555555},
1818 {0x66555555, 0x66555555},
1819 {0xaaaaaaaa, 0xaaaaaaaa},
1820 {0x5a5a5a5a, 0x5a5a5a5a},
1821 {0xfafafafa, 0xfafafafa}, /* case-5 */
1822 {0x6a5a6a5a, 0xaaaaaaaa},
1823 {0x6a5a56aa, 0x6a5a56aa},
1824 {0x6a5a5a5a, 0x6a5a5a5a},
1825 {0x66555555, 0x5a5a5a5a},
1826 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1827 {0x66555555, 0xfafafafa},
1828 {0x66555555, 0x6a5a5aaa},
1829 {0x66555555, 0x5aaa5aaa},
1830 {0x66555555, 0xaaaa5aaa},
1831 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1832 {0xffff55ff, 0xfafafafa},
1833 {0xffff55ff, 0x6afa5afa},
1834 {0xaaffffaa, 0xfafafafa},
1835 {0xaa5555aa, 0x5a5a5a5a},
1836 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1837 {0xaa5555aa, 0xaaaaaaaa},
1838 {0xffffffff, 0x5a5a5a5a},
1839 {0xffffffff, 0x6a5a5a5a},
1840 {0xffffffff, 0x55555555},
1841 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
1842 {0x55555555, 0x5a5a5a5a},
1843 {0x55555555, 0xaaaaaaaa},
1844 {0x55555555, 0x6a5a6a5a},
1845 {0x66556655, 0x66556655}
1848 /* Non-Shared-Antenna Coex Table */
1849 static const struct coex_table_para table_nsant_8822b[] = {
1850 {0xffffffff, 0xffffffff}, /* case-100 */
1851 {0x55555555, 0x55555555},
1852 {0x66555555, 0x66555555},
1853 {0xaaaaaaaa, 0xaaaaaaaa},
1854 {0x5a5a5a5a, 0x5a5a5a5a},
1855 {0xfafafafa, 0xfafafafa}, /* case-105 */
1856 {0x5afa5afa, 0x5afa5afa},
1857 {0x55555555, 0xfafafafa},
1858 {0x66555555, 0xfafafafa},
1859 {0x66555555, 0x5a5a5a5a},
1860 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1861 {0x66555555, 0xaaaaaaaa},
1862 {0xffff55ff, 0xfafafafa},
1863 {0xffff55ff, 0x5afa5afa},
1864 {0xffff55ff, 0xaaaaaaaa},
1865 {0xaaffffaa, 0xfafafafa}, /* case-115 */
1866 {0xaaffffaa, 0x5afa5afa},
1867 {0xaaffffaa, 0xaaaaaaaa},
1868 {0xffffffff, 0xfafafafa},
1869 {0xffffffff, 0x5afa5afa},
1870 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1871 {0x55ff55ff, 0x5afa5afa},
1872 {0x55ff55ff, 0xaaaaaaaa},
1873 {0x55ff55ff, 0x55ff55ff}
1876 /* Shared-Antenna TDMA */
1877 static const struct coex_tdma_para tdma_sant_8822b[] = {
1878 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1879 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1880 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1881 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1882 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1883 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1884 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1885 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1886 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1887 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1888 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1889 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1890 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1891 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1892 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1893 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1894 { {0x51, 0x45, 0x03, 0x10, 0x10} },
1895 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1896 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1897 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1898 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1899 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1900 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
1901 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1902 { {0x65, 0x10, 0x03, 0x11, 0x11} },
1903 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1904 { {0x51, 0x08, 0x03, 0x10, 0x50} }
1907 /* Non-Shared-Antenna TDMA */
1908 static const struct coex_tdma_para tdma_nsant_8822b[] = {
1909 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
1910 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1911 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1912 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1913 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1914 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1915 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1916 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1917 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1918 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1919 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1920 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1921 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1922 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1923 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1924 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1925 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1926 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1927 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1928 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1929 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */
1932 /* rssi in percentage % (dbm = % - 100) */
1933 static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30};
1934 static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30};
1935 static const struct coex_5g_afh_map afh_5g_8822b[] = { {0, 0, 0} };
1937 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
1938 static const struct coex_rf_para rf_para_tx_8822b[] = {
1939 {0, 0, false, 7}, /* for normal */
1940 {0, 16, false, 7}, /* for WL-CPT */
1947 static const struct coex_rf_para rf_para_rx_8822b[] = {
1948 {0, 0, false, 7}, /* for normal */
1949 {0, 16, false, 7}, /* for WL-CPT */
1956 static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b));
1958 struct rtw_chip_info rtw8822b_hw_spec = {
1959 .ops = &rtw8822b_ops,
1960 .id = RTW_CHIP_TYPE_8822B,
1961 .fw_name = "rtw88/rtw8822b_fw.bin",
1962 .tx_pkt_desc_sz = 48,
1963 .tx_buf_desc_sz = 16,
1964 .rx_pkt_desc_sz = 24,
1965 .rx_buf_desc_sz = 8,
1966 .phy_efuse_size = 1024,
1967 .log_efuse_size = 768,
1968 .ptct_efuse_size = 96,
1969 .txff_size = 262144,
1972 .is_pwr_by_rate_dec = true,
1973 .max_power_index = 0x3f,
1974 .csi_buf_pg_num = 0,
1975 .band = RTW_BAND_2G | RTW_BAND_5G,
1978 .ht_supported = true,
1979 .vht_supported = true,
1980 .sys_func_en = 0xDC,
1981 .pwr_on_seq = card_enable_flow_8822b,
1982 .pwr_off_seq = card_disable_flow_8822b,
1983 .page_table = page_table_8822b,
1984 .rqpn_table = rqpn_table_8822b,
1985 .intf_table = &phy_para_table_8822b,
1986 .dig = rtw8822b_dig,
1987 .rf_base_addr = {0x2800, 0x2c00},
1988 .rf_sipi_addr = {0xc90, 0xe90},
1989 .mac_tbl = &rtw8822b_mac_tbl,
1990 .agc_tbl = &rtw8822b_agc_tbl,
1991 .bb_tbl = &rtw8822b_bb_tbl,
1992 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl},
1993 .rfe_defs = rtw8822b_rfe_defs,
1994 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs),
1996 .coex_para_ver = 0x19062706,
1997 .bt_desired_ver = 0x6,
1998 .scbd_support = true,
1999 .new_scbd10_def = false,
2000 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2001 .bt_rssi_type = COEX_BTRSSI_RATIO,
2002 .ant_isolation = 15,
2003 .rssi_tolerance = 2,
2004 .wl_rssi_step = wl_rssi_step_8822b,
2005 .bt_rssi_step = bt_rssi_step_8822b,
2006 .table_sant_num = ARRAY_SIZE(table_sant_8822b),
2007 .table_sant = table_sant_8822b,
2008 .table_nsant_num = ARRAY_SIZE(table_nsant_8822b),
2009 .table_nsant = table_nsant_8822b,
2010 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b),
2011 .tdma_sant = tdma_sant_8822b,
2012 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b),
2013 .tdma_nsant = tdma_nsant_8822b,
2014 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b),
2015 .wl_rf_para_tx = rf_para_tx_8822b,
2016 .wl_rf_para_rx = rf_para_rx_8822b,
2017 .bt_afh_span_bw20 = 0x24,
2018 .bt_afh_span_bw40 = 0x36,
2019 .afh_5g_num = ARRAY_SIZE(afh_5g_8822b),
2020 .afh_5g = afh_5g_8822b,
2022 EXPORT_SYMBOL(rtw8822b_hw_spec);
2024 MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin");