1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
90 /*Max: define total number.*/
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
102 #define ASPM_L1_LATENCY 7
104 #define TOTAL_CAM_ENTRY 32
106 /*slot time for 11g. */
107 #define RTL_SLOT_TIME_9 9
108 #define RTL_SLOT_TIME_20 20
110 /*related to tcp/ip. */
112 #define PROTOC_TYPE_SIZE 2
114 /*related with 802.11 frame*/
115 #define MAC80211_3ADDR_LEN 24
116 #define MAC80211_4ADDR_LEN 30
118 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
119 #define CHANNEL_MAX_NUMBER_2G 14
120 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
121 *"phy_GetChnlGroup8812A" and
122 * "Hal_ReadTxPowerInfo8812A"
124 #define CHANNEL_MAX_NUMBER_5G_80M 7
125 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
126 #define MAX_PG_GROUP 13
127 #define CHANNEL_GROUP_MAX_2G 3
128 #define CHANNEL_GROUP_IDX_5GL 3
129 #define CHANNEL_GROUP_IDX_5GM 6
130 #define CHANNEL_GROUP_IDX_5GH 9
131 #define CHANNEL_GROUP_MAX_5G 9
132 #define CHANNEL_MAX_NUMBER_2G 14
133 #define AVG_THERMAL_NUM 8
134 #define AVG_THERMAL_NUM_88E 4
135 #define AVG_THERMAL_NUM_8723BE 4
136 #define MAX_TID_COUNT 9
142 enum rtl8192c_h2c_cmd {
149 H2C_MACID_PS_MODE = 7,
150 H2C_P2P_PS_OFFLOAD = 8,
151 H2C_MAC_MODE_SEL = 9,
153 H2C_P2P_PS_CTW_CMD = 24,
158 H2C_BT_PORT_ID = 0x71,
161 #define GET_TX_REPORT_SN_V1(c2h) (c2h[6])
162 #define GET_TX_REPORT_ST_V1(c2h) (c2h[0] & 0xC0)
163 #define GET_TX_REPORT_RETRY_V1(c2h) (c2h[2] & 0x3F)
164 #define GET_TX_REPORT_SN_V2(c2h) (c2h[6])
165 #define GET_TX_REPORT_ST_V2(c2h) (c2h[7] & 0xC0)
166 #define GET_TX_REPORT_RETRY_V2(c2h) (c2h[8] & 0x3F)
168 #define MAX_TX_COUNT 4
169 #define MAX_REGULATION_NUM 4
170 #define MAX_RF_PATH_NUM 4
171 #define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */
172 #define MAX_2_4G_BANDWIDTH_NUM 4
173 #define MAX_5G_BANDWIDTH_NUM 4
174 #define MAX_RF_PATH 4
175 #define MAX_CHNL_GROUP_24G 6
176 #define MAX_CHNL_GROUP_5G 14
178 #define TX_PWR_BY_RATE_NUM_BAND 2
179 #define TX_PWR_BY_RATE_NUM_RF 4
180 #define TX_PWR_BY_RATE_NUM_SECTION 12
181 #define TX_PWR_BY_RATE_NUM_RATE 84 /* >= TX_PWR_BY_RATE_NUM_SECTION */
182 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */
183 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */
185 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
187 #define DEL_SW_IDX_SZ 30
189 /* For now, it's just for 8192ee
190 * but not OK yet, keep it 0
192 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
198 RF_TX_NUM_NONIMPLEMENT,
201 #define PACKET_NORMAL 0
202 #define PACKET_DHCP 1
204 #define PACKET_EAPOL 3
206 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
207 #define RSVD_WOL_PATTERN_NUM 1
208 #define WKFMCAM_ADDR_NUM 6
209 #define WKFMCAM_SIZE 24
211 #define MAX_WOL_BIT_MASK_SIZE 16
212 /* MIN LEN keeps 13 here */
213 #define MIN_WOL_PATTERN_SIZE 13
214 #define MAX_WOL_PATTERN_SIZE 128
216 #define WAKE_ON_MAGIC_PACKET BIT(0)
217 #define WAKE_ON_PATTERN_MATCH BIT(1)
219 #define WOL_REASON_PTK_UPDATE BIT(0)
220 #define WOL_REASON_GTK_UPDATE BIT(1)
221 #define WOL_REASON_DISASSOC BIT(2)
222 #define WOL_REASON_DEAUTH BIT(3)
223 #define WOL_REASON_AP_LOST BIT(4)
224 #define WOL_REASON_MAGIC_PKT BIT(5)
225 #define WOL_REASON_UNICAST_PKT BIT(6)
226 #define WOL_REASON_PATTERN_PKT BIT(7)
227 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
228 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
229 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
231 struct rtlwifi_firmware_header {
250 struct txpower_info_2g {
251 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
252 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
253 /*If only one tx, only BW20 and OFDM are used.*/
254 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
255 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
256 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
257 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
258 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
259 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
262 struct txpower_info_5g {
263 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
264 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
265 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
266 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
267 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
268 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
269 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
301 enum regulation_txpwr_lmt {
307 TXPWR_LMT_MAX_REGULATION_NUM = 4
310 enum rt_eeprom_type {
317 RTL_STATUS_INTERFACE_START = 0,
321 HARDWARE_TYPE_RTL8192E,
322 HARDWARE_TYPE_RTL8192U,
323 HARDWARE_TYPE_RTL8192SE,
324 HARDWARE_TYPE_RTL8192SU,
325 HARDWARE_TYPE_RTL8192CE,
326 HARDWARE_TYPE_RTL8192CU,
327 HARDWARE_TYPE_RTL8192DE,
328 HARDWARE_TYPE_RTL8192DU,
329 HARDWARE_TYPE_RTL8723AE,
330 HARDWARE_TYPE_RTL8723U,
331 HARDWARE_TYPE_RTL8188EE,
332 HARDWARE_TYPE_RTL8723BE,
333 HARDWARE_TYPE_RTL8192EE,
334 HARDWARE_TYPE_RTL8821AE,
335 HARDWARE_TYPE_RTL8812AE,
336 HARDWARE_TYPE_RTL8822BE,
342 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
343 #define IS_NEW_GENERATION_IC(rtlpriv) \
344 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
345 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
346 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
347 #define IS_HARDWARE_TYPE_8812(rtlpriv) \
348 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
349 #define IS_HARDWARE_TYPE_8821(rtlpriv) \
350 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
351 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \
352 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
353 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \
354 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
355 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \
356 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
357 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \
358 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
360 #define RX_HAL_IS_CCK_RATE(rxmcs) \
361 ((rxmcs) == DESC_RATE1M || \
362 (rxmcs) == DESC_RATE2M || \
363 (rxmcs) == DESC_RATE5_5M || \
364 (rxmcs) == DESC_RATE11M)
366 enum scan_operation_backup_opt {
368 SCAN_OPT_BACKUP_BAND0 = 0,
369 SCAN_OPT_BACKUP_BAND1,
398 u32 rf_rb; /* rflssi_readback */
399 u32 rf_rbpi; /* rflssi_readbackpi */
403 IO_CMD_PAUSE_DM_BY_SCAN = 0,
404 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
405 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
406 IO_CMD_RESUME_DM_BY_SCAN = 2,
410 HW_VAR_ETHER_ADDR = 0x0,
411 HW_VAR_MULTICAST_REG = 0x1,
412 HW_VAR_BASIC_RATE = 0x2,
414 HW_VAR_MEDIA_STATUS= 0x4,
415 HW_VAR_SECURITY_CONF= 0x5,
416 HW_VAR_BEACON_INTERVAL = 0x6,
417 HW_VAR_ATIM_WINDOW = 0x7,
418 HW_VAR_LISTEN_INTERVAL = 0x8,
419 HW_VAR_CS_COUNTER = 0x9,
420 HW_VAR_DEFAULTKEY0 = 0xa,
421 HW_VAR_DEFAULTKEY1 = 0xb,
422 HW_VAR_DEFAULTKEY2 = 0xc,
423 HW_VAR_DEFAULTKEY3 = 0xd,
425 HW_VAR_R2T_SIFS = 0xf,
428 HW_VAR_SLOT_TIME = 0x12,
429 HW_VAR_ACK_PREAMBLE = 0x13,
430 HW_VAR_CW_CONFIG = 0x14,
431 HW_VAR_CW_VALUES = 0x15,
432 HW_VAR_RATE_FALLBACK_CONTROL= 0x16,
433 HW_VAR_CONTENTION_WINDOW = 0x17,
434 HW_VAR_RETRY_COUNT = 0x18,
435 HW_VAR_TR_SWITCH = 0x19,
436 HW_VAR_COMMAND = 0x1a,
437 HW_VAR_WPA_CONFIG = 0x1b,
438 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
439 HW_VAR_SHORTGI_DENSITY = 0x1d,
440 HW_VAR_AMPDU_FACTOR = 0x1e,
441 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
442 HW_VAR_AC_PARAM = 0x20,
443 HW_VAR_ACM_CTRL = 0x21,
444 HW_VAR_DIS_Req_Qsize = 0x22,
445 HW_VAR_CCX_CHNL_LOAD = 0x23,
446 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
447 HW_VAR_CCX_CLM_NHM = 0x25,
448 HW_VAR_TxOPLimit = 0x26,
449 HW_VAR_TURBO_MODE = 0x27,
450 HW_VAR_RF_STATE = 0x28,
451 HW_VAR_RF_OFF_BY_HW = 0x29,
452 HW_VAR_BUS_SPEED = 0x2a,
453 HW_VAR_SET_DEV_POWER = 0x2b,
456 HW_VAR_RATR_0 = 0x2d,
458 HW_VAR_CPU_RST = 0x2f,
459 HW_VAR_CHECK_BSSID = 0x30,
460 HW_VAR_LBK_MODE = 0x31,
461 HW_VAR_AES_11N_FIX = 0x32,
462 HW_VAR_USB_RX_AGGR = 0x33,
463 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
464 HW_VAR_RETRY_LIMIT = 0x35,
465 HW_VAR_INIT_TX_RATE = 0x36,
466 HW_VAR_TX_RATE_REG = 0x37,
467 HW_VAR_EFUSE_USAGE = 0x38,
468 HW_VAR_EFUSE_BYTES = 0x39,
469 HW_VAR_AUTOLOAD_STATUS = 0x3a,
470 HW_VAR_RF_2R_DISABLE = 0x3b,
471 HW_VAR_SET_RPWM = 0x3c,
472 HW_VAR_H2C_FW_PWRMODE = 0x3d,
473 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
474 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
475 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
476 HW_VAR_FW_PSMODE_STATUS = 0x41,
477 HW_VAR_INIT_RTS_RATE = 0x42,
478 HW_VAR_RESUME_CLK_ON = 0x43,
479 HW_VAR_FW_LPS_ACTION = 0x44,
480 HW_VAR_1X1_RECV_COMBINE = 0x45,
481 HW_VAR_STOP_SEND_BEACON = 0x46,
482 HW_VAR_TSF_TIMER = 0x47,
483 HW_VAR_IO_CMD = 0x48,
485 HW_VAR_RF_RECOVERY = 0x49,
486 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
487 HW_VAR_WF_MASK = 0x4b,
488 HW_VAR_WF_CRC = 0x4c,
489 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
490 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
491 HW_VAR_RESET_WFCRC = 0x4f,
493 HW_VAR_HANDLE_FW_C2H = 0x50,
494 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
496 HW_VAR_HW_SEQ_ENABLE = 0x53,
497 HW_VAR_CORRECT_TSF = 0x54,
498 HW_VAR_BCN_VALID = 0x55,
499 HW_VAR_FWLPS_RF_ON = 0x56,
500 HW_VAR_DUAL_TSF_RST = 0x57,
501 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58,
502 HW_VAR_INT_MIGRATION = 0x59,
503 HW_VAR_INT_AC = 0x5a,
504 HW_VAR_RF_TIMING = 0x5b,
506 HAL_DEF_WOWLAN = 0x5c,
508 HW_VAR_KEEP_ALIVE = 0x5e,
509 HW_VAR_NAV_UPPER = 0x5f,
511 HW_VAR_MGT_FILTER = 0x60,
512 HW_VAR_CTRL_FILTER = 0x61,
513 HW_VAR_DATA_FILTER = 0x62,
516 enum rt_media_status {
517 RT_MEDIA_DISCONNECT = 0,
523 RT_CID_8187_ALPHA0 = 1,
524 RT_CID_8187_SERCOMM_PS = 2,
525 RT_CID_8187_HW_LED = 3,
526 RT_CID_8187_NETGEAR = 4,
528 RT_CID_819X_CAMEO = 6,
529 RT_CID_819X_RUNTOP = 7,
530 RT_CID_819X_SENAO = 8,
532 RT_CID_819X_NETCORE = 10,
533 RT_CID_NETTRONIX = 11,
537 RT_CID_819X_ALPHA = 15,
538 RT_CID_819X_SITECOM = 16,
540 RT_CID_819X_LENOVO = 18,
541 RT_CID_819X_QMI = 19,
542 RT_CID_819X_EDIMAX_BELKIN = 20,
543 RT_CID_819X_SERCOMM_BELKIN = 21,
544 RT_CID_819X_CAMEO1 = 22,
545 RT_CID_819X_MSI = 23,
546 RT_CID_819X_ACER = 24,
548 RT_CID_819X_CLEVO = 28,
549 RT_CID_819X_ARCADYAN_BELKIN = 29,
550 RT_CID_819X_SAMSUNG = 30,
551 RT_CID_819X_WNC_COREGA = 31,
552 RT_CID_819X_FOXCOON = 32,
553 RT_CID_819X_DELL = 33,
554 RT_CID_819X_PRONETS = 34,
555 RT_CID_819X_EDIMAX_ASUS = 35,
559 RT_CID_LENOVO_CHINA = 40,
565 HW_DESC_TX_NEXTDESC_ADDR,
574 PRIME_CHNL_OFFSET_DONT_CARE = 0,
575 PRIME_CHNL_OFFSET_LOWER = 1,
576 PRIME_CHNL_OFFSET_UPPER = 2,
591 enum ht_channel_width {
592 HT_CHANNEL_WIDTH_20 = 0,
593 HT_CHANNEL_WIDTH_20_40 = 1,
594 HT_CHANNEL_WIDTH_80 = 2,
595 HT_CHANNEL_WIDTH_MAX,
598 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
599 Cipher Suites Encryption Algorithms */
602 WEP40_ENCRYPTION = 1,
604 RSERVED_ENCRYPTION = 3,
605 AESCCMP_ENCRYPTION = 4,
606 WEP104_ENCRYPTION = 5,
607 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
612 _HAL_STATE_START = 1,
618 DESC_RATE5_5M = 0x02,
630 DESC_RATEMCS0 = 0x0c,
631 DESC_RATEMCS1 = 0x0d,
632 DESC_RATEMCS2 = 0x0e,
633 DESC_RATEMCS3 = 0x0f,
634 DESC_RATEMCS4 = 0x10,
635 DESC_RATEMCS5 = 0x11,
636 DESC_RATEMCS6 = 0x12,
637 DESC_RATEMCS7 = 0x13,
638 DESC_RATEMCS8 = 0x14,
639 DESC_RATEMCS9 = 0x15,
640 DESC_RATEMCS10 = 0x16,
641 DESC_RATEMCS11 = 0x17,
642 DESC_RATEMCS12 = 0x18,
643 DESC_RATEMCS13 = 0x19,
644 DESC_RATEMCS14 = 0x1a,
645 DESC_RATEMCS15 = 0x1b,
646 DESC_RATEMCS15_SG = 0x1c,
647 DESC_RATEMCS32 = 0x20,
649 DESC_RATEVHT1SS_MCS0 = 0x2c,
650 DESC_RATEVHT1SS_MCS1 = 0x2d,
651 DESC_RATEVHT1SS_MCS2 = 0x2e,
652 DESC_RATEVHT1SS_MCS3 = 0x2f,
653 DESC_RATEVHT1SS_MCS4 = 0x30,
654 DESC_RATEVHT1SS_MCS5 = 0x31,
655 DESC_RATEVHT1SS_MCS6 = 0x32,
656 DESC_RATEVHT1SS_MCS7 = 0x33,
657 DESC_RATEVHT1SS_MCS8 = 0x34,
658 DESC_RATEVHT1SS_MCS9 = 0x35,
659 DESC_RATEVHT2SS_MCS0 = 0x36,
660 DESC_RATEVHT2SS_MCS1 = 0x37,
661 DESC_RATEVHT2SS_MCS2 = 0x38,
662 DESC_RATEVHT2SS_MCS3 = 0x39,
663 DESC_RATEVHT2SS_MCS4 = 0x3a,
664 DESC_RATEVHT2SS_MCS5 = 0x3b,
665 DESC_RATEVHT2SS_MCS6 = 0x3c,
666 DESC_RATEVHT2SS_MCS7 = 0x3d,
667 DESC_RATEVHT2SS_MCS8 = 0x3e,
668 DESC_RATEVHT2SS_MCS9 = 0x3f,
694 EFUSE_HWSET_MAX_SIZE,
695 EFUSE_MAX_SECTION_MAP,
696 EFUSE_REAL_CONTENT_SIZE,
697 EFUSE_OOB_PROTECT_BYTES_LEN,
713 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
714 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
715 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
716 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
717 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
718 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
719 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
720 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
721 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
722 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
723 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
724 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
725 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
726 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
727 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
728 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
729 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
730 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
731 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
732 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
733 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
734 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
735 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */
736 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
737 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
738 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
739 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
740 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
741 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
742 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
743 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
744 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
745 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
746 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
747 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
748 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
750 RTL_IMR_C2HCMD, /*fw interrupt*/
752 /*CCK Rates, TxHT = 0 */
758 /*OFDM Rates, TxHT = 0 */
771 RTL_RC_VHT_RATE_1SS_MCS7,
772 RTL_RC_VHT_RATE_1SS_MCS8,
773 RTL_RC_VHT_RATE_1SS_MCS9,
774 RTL_RC_VHT_RATE_2SS_MCS7,
775 RTL_RC_VHT_RATE_2SS_MCS8,
776 RTL_RC_VHT_RATE_2SS_MCS9,
782 /*Firmware PS mode for control LPS.*/
784 FW_PS_ACTIVE_MODE = 0,
789 FW_PS_UAPSD_WMM_MODE = 5,
790 FW_PS_UAPSD_MODE = 6,
792 FW_PS_WWLAN_MODE = 8,
793 FW_PS_PM_Radio_Off = 9,
794 FW_PS_PM_Card_Disable = 10,
798 EACTIVE, /*Active/Continuous access. */
799 EMAXPS, /*Max power save mode. */
800 EFASTPS, /*Fast power save mode. */
801 EAUTOPS, /*Auto power save mode. */
806 LED_CTL_POWER_ON = 1,
811 LED_CTL_SITE_SURVEY = 6,
812 LED_CTL_POWER_OFF = 7,
813 LED_CTL_START_TO_LINK = 8,
814 LED_CTL_START_WPS = 9,
815 LED_CTL_STOP_WPS = 10,
826 /*acm implementation method.*/
828 eAcmWay0_SwAndHw = 0,
834 SINGLEMAC_SINGLEPHY = 0,
847 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
861 WIRELESS_MODE_UNKNOWN = 0x00,
862 WIRELESS_MODE_A = 0x01,
863 WIRELESS_MODE_B = 0x02,
864 WIRELESS_MODE_G = 0x04,
865 WIRELESS_MODE_AUTO = 0x08,
866 WIRELESS_MODE_N_24G = 0x10,
867 WIRELESS_MODE_N_5G = 0x20,
868 WIRELESS_MODE_AC_5G = 0x40,
869 WIRELESS_MODE_AC_24G = 0x80,
870 WIRELESS_MODE_AC_ONLY = 0x100,
871 WIRELESS_MODE_MAX = 0x800
874 #define IS_WIRELESS_MODE_A(wirelessmode) \
875 (wirelessmode == WIRELESS_MODE_A)
876 #define IS_WIRELESS_MODE_B(wirelessmode) \
877 (wirelessmode == WIRELESS_MODE_B)
878 #define IS_WIRELESS_MODE_G(wirelessmode) \
879 (wirelessmode == WIRELESS_MODE_G)
880 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
881 (wirelessmode == WIRELESS_MODE_N_24G)
882 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
883 (wirelessmode == WIRELESS_MODE_N_5G)
885 enum ratr_table_mode {
886 RATR_INX_WIRELESS_NGB = 0,
887 RATR_INX_WIRELESS_NG = 1,
888 RATR_INX_WIRELESS_NB = 2,
889 RATR_INX_WIRELESS_N = 3,
890 RATR_INX_WIRELESS_GB = 4,
891 RATR_INX_WIRELESS_G = 5,
892 RATR_INX_WIRELESS_B = 6,
893 RATR_INX_WIRELESS_MC = 7,
894 RATR_INX_WIRELESS_A = 8,
895 RATR_INX_WIRELESS_AC_5N = 8,
896 RATR_INX_WIRELESS_AC_24N = 9,
899 enum ratr_table_mode_new {
900 RATEID_IDX_BGN_40M_2SS = 0,
901 RATEID_IDX_BGN_40M_1SS = 1,
902 RATEID_IDX_BGN_20M_2SS_BN = 2,
903 RATEID_IDX_BGN_20M_1SS_BN = 3,
904 RATEID_IDX_GN_N2SS = 4,
905 RATEID_IDX_GN_N1SS = 5,
909 RATEID_IDX_VHT_2SS = 9,
910 RATEID_IDX_VHT_1SS = 10,
911 RATEID_IDX_MIX1 = 11,
912 RATEID_IDX_MIX2 = 12,
913 RATEID_IDX_VHT_3SS = 13,
914 RATEID_IDX_BGN_3SS = 14,
917 enum rtl_link_state {
919 MAC80211_LINKING = 1,
921 MAC80211_LINKED_SCANNING = 3,
938 enum rt_polarity_ctl {
939 RT_POLARITY_LOW_ACT = 0,
940 RT_POLARITY_HIGH_ACT = 1,
943 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
944 enum fw_wow_reason_v2 {
945 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
946 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
947 FW_WOW_V2_DISASSOC_EVENT = 0x04,
948 FW_WOW_V2_DEAUTH_EVENT = 0x08,
949 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
950 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
951 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
952 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
953 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
954 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
955 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
956 FW_WOW_V2_REASON_MAX = 0xff,
959 enum wolpattern_type {
961 MULTICAST_PATTERN = 1,
962 BROADCAST_PATTERN = 2,
976 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */
977 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */
978 RTL_SPEC_EXT_C2H = BIT(2), /* extend FW C2H (e.g. TX REPORT) */
988 DM_INFO_CRC32_OK_VHT,
990 DM_INFO_CRC32_OK_LEGACY,
991 DM_INFO_CRC32_OK_CCK,
992 DM_INFO_CRC32_ERROR_VHT,
993 DM_INFO_CRC32_ERROR_HT,
994 DM_INFO_CRC32_ERROR_LEGACY,
995 DM_INFO_CRC32_ERROR_CCK,
999 DM_INFO_CRC32_OK_HT_AGG,
1000 DM_INFO_CRC32_ERROR_HT_AGG,
1013 struct octet_string {
1018 struct rtl_hdr_3addr {
1028 struct rtl_info_element {
1034 struct rtl_probe_rsp {
1035 struct rtl_hdr_3addr header;
1037 __le16 beacon_interval;
1039 /*SSID, supported rates, FH params, DS params,
1040 CF params, IBSS params, TIM (if beacon), RSN */
1041 struct rtl_info_element info_element[0];
1045 /*ledpin Identify how to implement this SW led.*/
1048 enum rtl_led_pin ledpin;
1052 struct rtl_led_ctl {
1054 struct rtl_led sw_led0;
1055 struct rtl_led sw_led1;
1058 struct rtl_qos_parameters {
1066 struct rt_smooth_data {
1067 u32 elements[100]; /*array to store values */
1068 u32 index; /*index to current array to store */
1069 u32 total_num; /*num of valid elements */
1070 u32 total_val; /*sum of valid elements */
1073 struct false_alarm_statistics {
1074 u32 cnt_parity_fail;
1075 u32 cnt_rate_illegal;
1078 u32 cnt_fast_fsync_fail;
1079 u32 cnt_sb_search_fail;
1099 struct wireless_stats {
1101 u64 txbytesmulticast;
1102 u64 txbytesbroadcast;
1105 u64 txbytesunicast_inperiod;
1106 u64 rxbytesunicast_inperiod;
1107 u32 txbytesunicast_inperiod_tp;
1108 u32 rxbytesunicast_inperiod_tp;
1109 u64 txbytesunicast_last;
1110 u64 rxbytesunicast_last;
1113 /*Correct smoothed ss in Dbm, only used
1114 in driver to report real power now. */
1115 long recv_signal_power;
1116 long signal_quality;
1117 long last_sigstrength_inpercent;
1119 u32 rssi_calculate_cnt;
1122 /*Transformed, in dbm. Beautified signal
1123 strength for UI, not correct. */
1124 long signal_strength;
1126 u8 rx_rssi_percentage[4];
1128 u8 rx_evm_percentage[2];
1130 u16 rx_cfo_short[4];
1133 struct rt_smooth_data ui_rssi;
1134 struct rt_smooth_data ui_link_quality;
1137 struct rate_adaptive {
1138 u8 rate_adaptive_disabled;
1142 u32 high_rssi_thresh_for_ra;
1143 u32 high2low_rssi_thresh_for_ra;
1144 u8 low2high_rssi_thresh_for_ra40m;
1145 u32 low_rssi_thresh_for_ra40m;
1146 u8 low2high_rssi_thresh_for_ra20m;
1147 u32 low_rssi_thresh_for_ra20m;
1148 u32 upper_rssi_threshold_ratr;
1149 u32 middleupper_rssi_threshold_ratr;
1150 u32 middle_rssi_threshold_ratr;
1151 u32 middlelow_rssi_threshold_ratr;
1152 u32 low_rssi_threshold_ratr;
1153 u32 ultralow_rssi_threshold_ratr;
1154 u32 low_rssi_threshold_ratr_40m;
1155 u32 low_rssi_threshold_ratr_20m;
1156 u8 ping_rssi_enable;
1158 u32 ping_rssi_thresh_for_ra;
1163 bool lower_rts_rate;
1164 bool is_special_data;
1167 struct regd_pair_mapping {
1173 struct dynamic_primary_cca {
1183 struct rtl_regulatory {
1186 u16 max_power_level;
1190 int16_t power_limit;
1191 struct regd_pair_mapping *regpair;
1195 bool rfkill_state; /*0 is off, 1 is on */
1199 #define P2P_MAX_NOA_NUM 2
1202 P2P_ROLE_DISABLE = 0,
1203 P2P_ROLE_DEVICE = 1,
1204 P2P_ROLE_CLIENT = 2,
1212 P2P_PS_SCAN_DONE = 3,
1213 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1218 P2P_PS_CTWINDOW = 1,
1220 P2P_PS_MIX = 3, /* CTWindow and NoA */
1223 struct rtl_p2p_ps_info {
1224 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1225 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1226 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1227 /* Client traffic window. A period of time in TU after TBTT. */
1229 u8 opp_ps; /* opportunistic power save. */
1230 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1231 /* Count for owner, Type of client. */
1232 u8 noa_count_type[P2P_MAX_NOA_NUM];
1233 /* Max duration for owner, preferred or min acceptable duration
1236 u32 noa_duration[P2P_MAX_NOA_NUM];
1237 /* Length of interval for owner, preferred or max acceptable intervali
1240 u32 noa_interval[P2P_MAX_NOA_NUM];
1241 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1242 u32 noa_start_time[P2P_MAX_NOA_NUM];
1245 struct p2p_ps_offload_t {
1247 u8 role:1; /* 1: Owner, 0: Client */
1256 #define IQK_MATRIX_REG_NUM 8
1257 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1259 struct iqk_matrix_regs {
1261 long value[1][IQK_MATRIX_REG_NUM];
1264 struct phy_parameters {
1269 enum hw_param_tab_index {
1284 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1285 struct init_gain initgain_backup;
1286 enum io_type current_io_type;
1291 u8 set_bwmode_inprogress;
1292 u8 sw_chnl_inprogress;
1297 u8 set_io_inprogress;
1300 /* record for power tracking */
1312 u32 reg_c04, reg_c08, reg_874;
1313 u32 adda_backup[16];
1314 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1315 u32 iqk_bb_backup[10];
1316 bool iqk_initialized;
1318 bool rfpath_rx_enable[MAX_RF_PATH];
1322 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1325 bool iqk_in_progress;
1329 /* this is for 88E & 8723A */
1330 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1331 /* MAX_PG_GROUP groups of pwr diff by rates */
1332 u32 mcs_offset[MAX_PG_GROUP][16];
1333 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1334 [TX_PWR_BY_RATE_NUM_RF]
1335 [TX_PWR_BY_RATE_NUM_RF]
1336 [TX_PWR_BY_RATE_NUM_RATE];
1337 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1338 [TX_PWR_BY_RATE_NUM_RF]
1339 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1340 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1341 [TX_PWR_BY_RATE_NUM_RF]
1342 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1343 u8 default_initialgain[4];
1345 /* the current Tx power level */
1346 u8 cur_cck_txpwridx;
1347 u8 cur_ofdm24g_txpwridx;
1348 u8 cur_bw20_txpwridx;
1349 u8 cur_bw40_txpwridx;
1351 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1352 [MAX_2_4G_BANDWIDTH_NUM]
1353 [MAX_RATE_SECTION_NUM]
1354 [CHANNEL_MAX_NUMBER_2G]
1356 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1357 [MAX_5G_BANDWIDTH_NUM]
1358 [MAX_RATE_SECTION_NUM]
1359 [CHANNEL_MAX_NUMBER_5G]
1362 u32 rfreg_chnlval[2];
1364 u32 reg_rf3c[2]; /* pathA / pathB */
1366 u32 backup_rf_0x1a;/*92ee*/
1371 u8 num_total_rfpath;
1372 struct phy_parameters hwparam_tables[MAX_TAB];
1375 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1376 enum rt_polarity_ctl polarity_ctl;
1379 #define MAX_TID_COUNT 9
1380 #define RTL_AGG_STOP 0
1381 #define RTL_AGG_PROGRESS 1
1382 #define RTL_AGG_START 2
1383 #define RTL_AGG_OPERATIONAL 3
1384 #define RTL_AGG_OFF 0
1385 #define RTL_AGG_ON 1
1386 #define RTL_RX_AGG_START 1
1387 #define RTL_RX_AGG_STOP 0
1388 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1389 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1406 struct rtl_tid_data {
1407 struct rtl_ht_agg agg;
1410 struct rtl_sta_info {
1411 struct list_head list;
1412 struct rtl_tid_data tids[MAX_TID_COUNT];
1413 /* just used for ap adhoc or mesh*/
1414 struct rssi_sta rssi_stat;
1419 u8 mac_addr[ETH_ALEN];
1425 struct mutex bb_mutex;
1428 unsigned long pci_mem_end; /*shared mem end */
1429 unsigned long pci_mem_start; /*shared mem start */
1432 unsigned long pci_base_addr; /*device I/O address */
1434 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1435 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1436 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1437 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1440 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1441 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1442 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1447 u8 mac_addr[ETH_ALEN];
1448 u8 mac80211_registered;
1454 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1455 struct ieee80211_hw *hw;
1456 struct ieee80211_vif *vif;
1457 enum nl80211_iftype opmode;
1459 /*Probe Beacon management */
1460 struct rtl_tid_data tids[MAX_TID_COUNT];
1461 enum rtl_link_state link_state;
1467 u8 p2p; /*using p2p role*/
1477 u8 cnt_after_linked;
1481 /* skb wait queue */
1482 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1499 u8 bssid[ETH_ALEN] __aligned(2);
1501 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1502 u32 basic_rates; /* b/g rates */
1507 u16 mode; /* wireless mode */
1512 u8 cur_40_prime_sc_bk;
1521 int beacon_interval;
1524 u8 min_space_cfg; /*For Min spacing configurations */
1526 u8 current_ampdu_factor;
1527 u8 current_ampdu_density;
1530 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1531 struct rtl_qos_parameters ac[AC_MAX];
1536 u32 last_bt_edca_ul;
1537 u32 last_bt_edca_dl;
1543 bool adc_back_off_on;
1545 bool low_penalty_rate_adaptive;
1546 bool rf_rx_lpf_shrink;
1547 bool reject_aggre_pkt;
1555 u8 fw_dac_swing_lvl;
1562 bool sw_dac_swing_on;
1563 u32 sw_dac_swing_lvl;
1568 bool ignore_wlan_act;
1571 struct bt_coexist_8723 {
1572 u32 high_priority_tx;
1573 u32 high_priority_rx;
1574 u32 low_priority_tx;
1575 u32 low_priority_rx;
1577 bool c2h_bt_info_req_sent;
1578 bool c2h_bt_inquiry_page;
1579 u32 bt_inq_page_start_time;
1581 u8 c2h_bt_info_original;
1582 u8 bt_inquiry_page_cnt;
1583 struct btdm_8723 btdm;
1587 struct ieee80211_hw *hw;
1588 bool driver_is_goingto_unload;
1591 bool being_init_adapter;
1593 bool mac_func_enable;
1594 bool pre_edcca_enable;
1595 struct bt_coexist_8723 hal_coex_8723;
1597 enum intf_type interface;
1598 u16 hw_type; /*92c or 92d or 92s and so on */
1601 u32 version; /*version of chip */
1602 u8 state; /*stop 0, start 1 */
1627 bool h2c_setinprogress;
1630 /*Reserve page start offset except beacon in TxQ. */
1631 u8 fw_rsvdpage_startoffset;
1635 /* FW Cmd IO related */
1638 bool set_fwcmd_inprogress;
1639 u8 current_fwcmd_io;
1641 struct p2p_ps_offload_t p2p_ps_offload;
1642 bool fw_clk_change_in_progress;
1643 bool allow_sw_to_change_hwclc;
1646 bool driver_going2unload;
1648 /*AMPDU init min space*/
1649 u8 minspace_cfg; /*For Min spacing configurations */
1652 enum macphy_mode macphymode;
1653 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1654 enum band_type current_bandtypebackup;
1655 enum band_type bandset;
1656 /* dual MAC 0--Mac0 1--Mac1 */
1658 /* just for DualMac S3S4 */
1660 bool earlymode_enable;
1661 u8 max_earlymode_num;
1663 bool during_mac0init_radiob;
1664 bool during_mac1init_radioa;
1665 bool reloadtxpowerindex;
1666 /* True if IMR or IQK have done
1667 for 2.4G in scan progress */
1668 bool load_imrandiqk_setting_for2g;
1670 bool disable_amsdu_8k;
1671 bool master_of_dmsp;
1674 u16 rx_tag;/*for 92ee*/
1679 bool enter_pnp_sleep;
1680 bool wake_from_pnp_sleep;
1682 time64_t last_suspend_sec;
1684 u8 *wowlan_firmware;
1686 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1688 bool real_wow_v2_enable;
1689 bool re_init_llt_table;
1692 struct rtl_security {
1697 bool use_defaultkey;
1698 /*Encryption Algorithm for Unicast Packet */
1699 enum rt_enc_alg pairwise_enc_algorithm;
1700 /*Encryption Algorithm for Brocast/Multicast */
1701 enum rt_enc_alg group_enc_algorithm;
1702 /*Cam Entry Bitmap */
1703 u32 hwsec_cam_bitmap;
1704 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1705 /*local Key buffer, indx 0 is for
1706 pairwise key 1-4 is for agoup key. */
1707 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1708 u8 key_len[KEY_BUF_SIZE];
1710 /*The pointer of Pairwise Key,
1711 it always points to KeyBuf[4] */
1715 #define ASSOCIATE_ENTRY_NUM 33
1717 struct fast_ant_training {
1719 u8 antsel_rx_keep_0;
1720 u8 antsel_rx_keep_1;
1721 u8 antsel_rx_keep_2;
1727 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1728 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1729 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1730 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1731 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1732 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1733 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1738 struct dm_phy_dbg_info {
1740 u64 num_qry_phy_status;
1741 u64 num_qry_phy_status_cck;
1742 u64 num_qry_phy_status_ofdm;
1743 u16 num_qry_beacon_pkt;
1749 /*PHY status for Dynamic Management */
1750 long entry_min_undec_sm_pwdb;
1752 long undec_sm_pwdb; /*out dm */
1753 long entry_max_undec_sm_pwdb;
1755 bool dm_initialgain_enable;
1756 bool dynamic_txpower_enable;
1757 bool current_turbo_edca;
1758 bool is_any_nonbepkts; /*out dm */
1759 bool is_cur_rdlstate;
1760 bool txpower_trackinginit;
1761 bool disable_framebursting;
1763 bool txpower_tracking;
1765 bool rfpath_rxenable[4];
1766 bool inform_fw_driverctrldm;
1767 bool current_mrc_switch;
1769 u8 powerindex_backup[6];
1771 u8 thermalvalue_rxgain;
1772 u8 thermalvalue_iqk;
1773 u8 thermalvalue_lck;
1776 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1777 u8 thermalvalue_avg_index;
1780 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1781 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1785 u8 txpower_track_control;
1786 bool interrupt_migration;
1787 bool disable_tx_int;
1788 s8 ofdm_index[MAX_RF_PATH];
1789 u8 default_ofdm_index;
1790 u8 default_cck_index;
1792 s8 delta_power_index[MAX_RF_PATH];
1793 s8 delta_power_index_last[MAX_RF_PATH];
1794 s8 power_index_offset[MAX_RF_PATH];
1795 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1796 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1798 bool modify_txagc_flag_path_a;
1799 bool modify_txagc_flag_path_b;
1801 bool one_entry_only;
1802 struct dm_phy_dbg_info dbginfo;
1804 /* Dynamic ATC switch */
1813 u32 packet_count_pre;
1816 /*88e tx power tracking*/
1817 u8 swing_idx_ofdm[MAX_RF_PATH];
1818 u8 swing_idx_ofdm_cur;
1819 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1820 bool swing_flag_ofdm;
1822 u8 swing_idx_cck_cur;
1823 u8 swing_idx_cck_base;
1824 bool swing_flag_cck;
1830 bool supp_phymode_switch;
1833 struct fast_ant_training fat_table;
1850 #define EFUSE_MAX_LOGICAL_SIZE 512
1853 const struct rtl_efuse_ops *efuse_ops;
1856 u16 max_physical_size;
1858 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1859 u16 efuse_usedbytes;
1860 u8 efuse_usedpercentage;
1861 #ifdef EFUSE_REPG_WORKAROUND
1862 bool efuse_re_pg_sec1flag;
1863 u8 efuse_re_pg_data[8];
1866 u8 autoload_failflag;
1875 u16 eeprom_channelplan;
1883 u8 antenna_div_type;
1885 bool txpwr_fromeprom;
1886 u8 eeprom_crystalcap;
1888 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1889 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1890 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1891 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1892 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1893 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1895 u8 internal_pa_5g[2]; /* pathA / pathB */
1899 /*For power group */
1900 u8 eeprom_pwrgroup[2][3];
1901 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1902 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1904 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1905 /*For HT 40MHZ pwr */
1906 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1907 /*For HT 40MHZ pwr */
1908 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1910 /*--------------------------------------------------------*
1911 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1912 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1913 * define new arrays in Windows code.
1914 * BUT, in linux code, we use the same array for all ICs.
1916 * The Correspondance relation between two arrays is:
1917 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1918 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1919 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1920 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1922 * Sizes of these arrays are decided by the larger ones.
1924 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1925 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1926 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1927 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1929 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1930 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1931 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1932 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1933 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1934 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1936 u8 txpwr_safetyflag; /* Band edge enable flag */
1937 u16 eeprom_txpowerdiff;
1938 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1939 u8 antenna_txpwdiff[3];
1941 u8 eeprom_regulatory;
1942 u8 eeprom_thermalmeter;
1943 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1945 u8 crystalcap; /* CrystalCap. */
1949 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1950 bool apk_thermalmeterignore;
1952 bool b1x1_recvcombine;
1959 struct rtl_efuse_ops {
1960 int (*efuse_onebyte_read)(struct ieee80211_hw *hw, u16 addr, u8 *data);
1961 void (*efuse_logical_map_read)(struct ieee80211_hw *hw, u8 type,
1962 u16 offset, u32 *value);
1965 struct rtl_tx_report {
1968 unsigned long last_sent_time;
1973 bool pwrdomain_protect;
1974 bool in_powersavemode;
1975 bool rfchange_inprogress;
1976 bool swrf_processing;
1979 * just for PCIE ASPM
1980 * If it supports ASPM, Offset[560h] = 0x40,
1981 * otherwise Offset[560h] = 0x00.
1984 bool support_backdoor;
1987 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1992 /*For Fw control LPS mode */
1994 /*Record Fw PS mode status. */
1995 bool fw_current_inpsmode;
1996 u8 reg_max_lps_awakeintvl;
1998 bool low_power_enable;/*for 32k*/
2009 /*just for PCIE ASPM */
2010 u8 const_amdpci_aspm;
2013 enum rf_pwrstate inactive_pwrstate;
2014 enum rf_pwrstate rfpwr_state; /*cur power state */
2020 bool multi_buffered;
2022 unsigned int dtim_counter;
2023 unsigned int sleep_ms;
2024 unsigned long last_sleep_jiffies;
2025 unsigned long last_awake_jiffies;
2026 unsigned long last_delaylps_stamp_jiffies;
2027 unsigned long last_dtim;
2028 unsigned long last_beacon;
2029 unsigned long last_action;
2030 unsigned long last_slept;
2033 struct rtl_p2p_ps_info p2p_ps_info;
2037 /* wake up on line */
2039 u8 arp_offload_enable;
2040 u8 gtk_offload_enable;
2041 /* Used for WOL, indicates the reason for waking event.*/
2046 u8 psaddr[ETH_ALEN];
2051 u8 rate; /* hw desc rate */
2052 u8 received_channel;
2061 u8 signalquality; /*in 0-100 index. */
2063 * Real power in dBm for this packet,
2064 * no beautification and aggregation.
2066 s32 recvsignalpower;
2067 s8 rxpower; /*in dBm Translate from PWdB */
2068 u8 signalstrength; /*in 0-100 index. */
2072 u16 shortpreamble:1;
2084 bool rx_is40Mhzpacket;
2087 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2088 s8 rx_mimo_signalquality[4];
2089 u8 rx_mimo_evm_dbm[4];
2090 u16 cfo_short[4]; /* per-path's Cfo_short */
2093 s8 rx_mimo_sig_qual[4];
2094 u8 rx_pwr[4]; /* per-path's pwdb */
2095 u8 rx_snr[4]; /* per-path's SNR */
2097 u8 bt_coex_pwr_adjust;
2098 bool packet_matchbssid;
2102 bool packet_beacon; /*for rssi */
2103 s8 cck_adc_pwdb[4]; /*for rx path selection */
2109 u8 packet_report_type;
2113 u32 bt_rx_rssi_percentage;
2114 u32 macid_valid_entry[2];
2118 struct rt_link_detect {
2119 /* count for roaming */
2120 u32 bcn_rx_inperiod;
2123 u32 num_tx_in4period[4];
2124 u32 num_rx_in4period[4];
2126 u32 num_tx_inperiod;
2127 u32 num_rx_inperiod;
2130 bool tx_busy_traffic;
2131 bool rx_busy_traffic;
2132 bool higher_busytraffic;
2133 bool higher_busyrxtraffic;
2135 u32 tidtx_in4period[MAX_TID_COUNT][4];
2136 u32 tidtx_inperiod[MAX_TID_COUNT];
2137 bool higher_busytxtraffic[MAX_TID_COUNT];
2140 struct rtl_tcb_desc {
2148 u8 rts_use_shortpreamble:1;
2149 u8 rts_use_shortgi:1;
2155 u8 use_shortpreamble:1;
2156 u8 use_driver_rate:1;
2157 u8 disable_ratefallback:1;
2171 /* The max value by HW */
2173 bool tx_enable_sw_calc_duration;
2176 struct rtl_wow_pattern {
2182 /* struct to store contents of interrupt vectors */
2190 struct rtl_hal_ops {
2191 int (*init_sw_vars) (struct ieee80211_hw *hw);
2192 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
2193 void (*read_chip_version)(struct ieee80211_hw *hw);
2194 void (*read_eeprom_info) (struct ieee80211_hw *hw);
2195 void (*interrupt_recognized) (struct ieee80211_hw *hw,
2196 struct rtl_int *intvec);
2197 int (*hw_init) (struct ieee80211_hw *hw);
2198 void (*hw_disable) (struct ieee80211_hw *hw);
2199 void (*hw_suspend) (struct ieee80211_hw *hw);
2200 void (*hw_resume) (struct ieee80211_hw *hw);
2201 void (*enable_interrupt) (struct ieee80211_hw *hw);
2202 void (*disable_interrupt) (struct ieee80211_hw *hw);
2203 int (*set_network_type) (struct ieee80211_hw *hw,
2204 enum nl80211_iftype type);
2205 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2207 void (*set_bw_mode) (struct ieee80211_hw *hw,
2208 enum nl80211_channel_type ch_type);
2209 u8(*switch_channel) (struct ieee80211_hw *hw);
2210 void (*set_qos) (struct ieee80211_hw *hw, int aci);
2211 void (*set_bcn_reg) (struct ieee80211_hw *hw);
2212 void (*set_bcn_intv) (struct ieee80211_hw *hw);
2213 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
2214 u32 add_msr, u32 rm_msr);
2215 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2216 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2217 void (*update_rate_tbl) (struct ieee80211_hw *hw,
2218 struct ieee80211_sta *sta, u8 rssi_leve,
2220 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2221 u8 *desc, u8 queue_index,
2222 struct sk_buff *skb, dma_addr_t addr);
2223 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2224 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2226 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2228 void (*fill_tx_desc) (struct ieee80211_hw *hw,
2229 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2231 struct ieee80211_tx_info *info,
2232 struct ieee80211_sta *sta,
2233 struct sk_buff *skb, u8 hw_queue,
2234 struct rtl_tcb_desc *ptcb_desc);
2235 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2236 u32 buffer_len, bool bIsPsPoll);
2237 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2238 bool firstseg, bool lastseg,
2239 struct sk_buff *skb);
2240 void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
2241 u8 *pdesc, u8 *pbd_desc,
2242 struct sk_buff *skb, u8 hw_queue);
2243 bool (*query_rx_desc) (struct ieee80211_hw *hw,
2244 struct rtl_stats *stats,
2245 struct ieee80211_rx_status *rx_status,
2246 u8 *pdesc, struct sk_buff *skb);
2247 void (*set_channel_access) (struct ieee80211_hw *hw);
2248 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2249 void (*dm_watchdog) (struct ieee80211_hw *hw);
2250 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2251 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2252 enum rf_pwrstate rfpwr_state);
2253 void (*led_control) (struct ieee80211_hw *hw,
2254 enum led_ctl_mode ledaction);
2255 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2256 u8 desc_name, u8 *val);
2257 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2259 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2260 u8 hw_queue, u16 index);
2261 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2262 void (*enable_hw_sec) (struct ieee80211_hw *hw);
2263 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2264 u8 *macaddr, bool is_group, u8 enc_algo,
2265 bool is_wepkey, bool clear_all);
2266 void (*init_sw_leds) (struct ieee80211_hw *hw);
2267 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2268 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2269 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2271 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2272 u32 regaddr, u32 bitmask);
2273 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2274 u32 regaddr, u32 bitmask, u32 data);
2275 void (*linked_set_reg) (struct ieee80211_hw *hw);
2276 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2277 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2278 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2279 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2280 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2282 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2283 u8 *ppowerlevel, u8 channel);
2284 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2286 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2288 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2289 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2290 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2291 void (*c2h_command_handle) (struct ieee80211_hw *hw);
2292 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2294 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2295 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2296 u32 cmd_len, u8 *p_cmdbuffer);
2297 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw);
2298 bool (*get_btc_status) (void);
2299 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2300 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2301 const struct rtl_stats *status, struct sk_buff *skb);
2302 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2303 struct rtl_wow_pattern *rtl_pattern,
2305 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2306 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len,
2310 struct rtl_intf_ops {
2312 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2313 int (*adapter_start) (struct ieee80211_hw *hw);
2314 void (*adapter_stop) (struct ieee80211_hw *hw);
2315 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2316 struct rtl_priv **buddy_priv);
2318 int (*adapter_tx) (struct ieee80211_hw *hw,
2319 struct ieee80211_sta *sta,
2320 struct sk_buff *skb,
2321 struct rtl_tcb_desc *ptcb_desc);
2322 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2323 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2324 bool (*waitq_insert) (struct ieee80211_hw *hw,
2325 struct ieee80211_sta *sta,
2326 struct sk_buff *skb);
2329 void (*disable_aspm) (struct ieee80211_hw *hw);
2330 void (*enable_aspm) (struct ieee80211_hw *hw);
2335 struct rtl_mod_params {
2338 /* default: 0 = using hardware encryption */
2341 /* default: 0 = DBG_EMERG (0)*/
2344 /* default: 1 = using no linked power save */
2347 /* default: 1 = using linked sw power save */
2350 /* default: 1 = using linked fw power save */
2353 /* default: 0 = not using MSI interrupts mode
2354 * submodules should set their own default value
2358 /* default: 0 = dma 32 */
2361 /* default: 1 = enable aspm */
2364 /* default 0: 1 means disable */
2365 bool disable_watchdog;
2367 /* default 0: 1 means do not disable interrupts */
2370 /* select antenna */
2374 struct rtl_hal_usbint_cfg {
2381 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2382 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2383 struct sk_buff_head *);
2386 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2387 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2389 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2390 struct sk_buff_head *);
2392 /* endpoint mapping */
2393 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2394 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2397 struct rtl_hal_cfg {
2399 bool write_readback;
2402 struct rtl_hal_ops *ops;
2403 struct rtl_mod_params *mod_params;
2404 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2405 enum rtl_spec_ver spec_ver;
2407 /*this map used for some registers or vars
2408 defined int HAL but used in MAIN */
2409 u32 maps[RTL_VAR_MAP_MAX];
2415 struct mutex conf_mutex;
2416 struct mutex ips_mutex; /* mutex for enter/leave IPS */
2417 struct mutex lps_mutex; /* mutex for enter/leave LPS */
2420 spinlock_t irq_th_lock;
2421 spinlock_t h2c_lock;
2422 spinlock_t rf_ps_lock;
2424 spinlock_t waitq_lock;
2425 spinlock_t entry_list_lock;
2426 spinlock_t usb_lock;
2427 spinlock_t c2hcmd_lock;
2428 spinlock_t scan_list_lock; /* lock for the scan list */
2430 /*FW clock change */
2431 spinlock_t fw_ps_lock;
2434 spinlock_t cck_and_rw_pagea_lock;
2436 spinlock_t iqk_lock;
2440 struct ieee80211_hw *hw;
2443 struct timer_list watchdog_timer;
2444 struct timer_list dualmac_easyconcurrent_retrytimer;
2445 struct timer_list fw_clockoff_timer;
2446 struct timer_list fast_antenna_training_timer;
2448 struct tasklet_struct irq_tasklet;
2449 struct tasklet_struct irq_prepare_bcn_tasklet;
2452 struct workqueue_struct *rtl_wq;
2453 struct delayed_work watchdog_wq;
2454 struct delayed_work ips_nic_off_wq;
2455 struct delayed_work c2hcmd_wq;
2458 struct delayed_work ps_work;
2459 struct delayed_work ps_rfon_wq;
2460 struct delayed_work fwevt_wq;
2462 struct work_struct lps_change_work;
2463 struct work_struct fill_h2c_cmd;
2468 struct dentry *debugfs_dir;
2469 char debugfs_name[20];
2472 #define MIMO_PS_STATIC 0
2473 #define MIMO_PS_DYNAMIC 1
2474 #define MIMO_PS_NOLIMIT 3
2476 struct rtl_dualmac_easy_concurrent_ctl {
2477 enum band_type currentbandtype_backfordmdp;
2478 bool close_bbandrf_for_dmsp;
2479 bool change_to_dmdp;
2480 bool change_to_dmsp;
2481 bool switch_in_process;
2484 struct rtl_dmsp_ctl {
2485 bool activescan_for_slaveofdmsp;
2486 bool scan_for_anothermac_fordmsp;
2487 bool scan_for_itself_fordmsp;
2488 bool writedig_for_anothermacofdmsp;
2489 u32 curdigvalue_for_anothermacofdmsp;
2490 bool changecckpdstate_for_anothermacofdmsp;
2491 u8 curcckpdstate_for_anothermacofdmsp;
2492 bool changetxhighpowerlvl_for_anothermacofdmsp;
2493 u8 curtxhighlvl_for_anothermacofdmsp;
2494 long rssivalmin_for_anothermacofdmsp;
2508 u32 rssi_highthresh;
2511 long last_min_undec_pwdb_for_dm;
2512 long rssi_highpower_lowthresh;
2513 long rssi_highpower_highthresh;
2519 u8 dig_ext_port_stage;
2521 u8 dig_twoport_algorithm;
2523 u8 dig_slgorithm_switch;
2526 u8 curmultista_cstate;
2533 u8 min_undec_pwdb_for_dm;
2535 u8 pre_cck_cca_thres;
2536 u8 cur_cck_cca_thres;
2537 u8 pre_cck_pd_state;
2538 u8 cur_cck_pd_state;
2539 u8 pre_cck_fa_state;
2540 u8 cur_cck_fa_state;
2546 u8 dig_highpwrstate;
2553 u8 cur_cs_ratiostate;
2554 u8 pre_cs_ratiostate;
2555 u8 backoff_enable_flag;
2556 s8 backoffval_range_max;
2557 s8 backoffval_range_min;
2561 bool media_connect_0;
2562 bool media_connect_1;
2564 u32 antdiv_rssi_max;
2568 struct rtl_global_var {
2569 /* from this list we can get
2570 * other adapter's rtl_priv */
2571 struct list_head glb_priv_list;
2572 spinlock_t glb_list_lock;
2575 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
2577 struct rtl_btc_info {
2585 unsigned long in_4way_ts;
2588 struct bt_coexist_info {
2589 struct rtl_btc_ops *btc_ops;
2590 struct rtl_btc_info btc_info;
2593 void *wifi_only_context;
2594 /* EEPROM BT info. */
2595 u8 eeprom_bt_coexist;
2597 u8 eeprom_bt_ant_num;
2598 u8 eeprom_bt_ant_isol;
2599 u8 eeprom_bt_radio_shared;
2605 u8 bt_cur_state; /* 0:on, 1:off */
2606 u8 bt_ant_isolation; /* 0:good, 1:bad */
2607 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2609 u8 bt_radio_shared_type;
2610 u8 bt_rfreg_origin_1e;
2611 u8 bt_rfreg_origin_1f;
2619 bool bt_busy_traffic;
2620 bool bt_traffic_mode_set;
2621 bool bt_non_traffic_mode_set;
2623 bool fw_coexist_all_off;
2624 bool sw_coexist_all_off;
2625 bool hw_coexist_all_off;
2629 u32 previous_state_h;
2631 u8 bt_pre_rssi_state;
2632 u8 bt_pre_rssi_state1;
2637 u8 bt_active_zero_cnt;
2638 bool cur_bt_disabled;
2639 bool pre_bt_disabled;
2642 u8 bt_profile_action;
2644 bool hold_for_bt_operation;
2648 struct rtl_btc_ops {
2649 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2650 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
2651 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
2652 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2653 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2654 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2655 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
2656 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2657 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2658 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2659 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
2661 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2662 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2663 enum rt_media_status mstatus);
2664 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2665 void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
2666 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2667 u8 *tmp_buf, u8 length);
2668 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2669 u8 *tmp_buf, u8 length);
2670 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2671 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2672 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2673 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2675 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
2677 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
2678 u8 type, bool scanning);
2679 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
2680 struct seq_file *m);
2681 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2682 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2683 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2684 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2685 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2686 u8 *ctrl_agg_size, u8 *agg_size);
2687 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2693 void *proximity_priv;
2694 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2695 struct sk_buff *skb);
2696 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2700 struct list_head list;
2706 struct rtl_bssid_entry {
2707 struct list_head list;
2712 struct rtl_scan_list {
2714 struct list_head list; /* sort by age */
2718 struct ieee80211_hw *hw;
2719 struct completion firmware_loading_complete;
2720 struct list_head list;
2721 struct rtl_priv *buddy_priv;
2722 struct rtl_global_var *glb_var;
2723 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2724 struct rtl_dmsp_ctl dmsp_ctl;
2725 struct rtl_locks locks;
2726 struct rtl_works works;
2727 struct rtl_mac mac80211;
2728 struct rtl_hal rtlhal;
2729 struct rtl_regulatory regd;
2730 struct rtl_rfkill rfkill;
2734 struct rtl_security sec;
2735 struct rtl_efuse efuse;
2736 struct rtl_led_ctl ledctl;
2737 struct rtl_tx_report tx_report;
2738 struct rtl_scan_list scan_list;
2740 struct rtl_ps_ctl psc;
2741 struct rate_adaptive ra;
2742 struct dynamic_primary_cca primarycca;
2743 struct wireless_stats stats;
2744 struct rt_link_detect link_info;
2745 struct false_alarm_statistics falsealm_cnt;
2747 struct rtl_rate_priv *rate_priv;
2749 /* sta entry list for ap adhoc or mesh */
2750 struct list_head entry_list;
2752 /* c2hcmd list for kthread level access */
2753 struct list_head c2hcmd_list;
2755 struct rtl_debug dbg;
2759 *hal_cfg : for diff cards
2760 *intf_ops : for diff interrface usb/pcie
2762 struct rtl_hal_cfg *cfg;
2763 const struct rtl_intf_ops *intf_ops;
2765 /*this var will be set by set_bit,
2766 and was used to indicate status of
2767 interface or hardware */
2768 unsigned long status;
2771 struct dig_t dm_digtable;
2772 struct ps_t dm_pstable;
2778 bool reg_init; /* true if regs saved */
2779 bool bt_operation_on;
2783 bool enter_ps; /* true when entering PS */
2786 /* intel Proximity, should be alloc mem
2787 * in intel Proximity module and can only
2788 * be used in intel Proximity mode
2790 struct proxim proximity;
2792 /*for bt coexist use*/
2793 struct bt_coexist_info btcoexist;
2795 /* separate 92ee from other ICs,
2796 * 92ee use new trx flow.
2798 bool use_new_trx_flow;
2801 struct wiphy_wowlan_support wowlan;
2803 /*This must be the last item so
2804 that it points to the data allocated
2805 beyond this structure like:
2806 rtl_pci_priv or rtl_usb_priv */
2807 u8 priv[0] __aligned(sizeof(void *));
2810 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2811 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2812 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2813 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2814 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2817 /***************************************
2818 Bluetooth Co-existence Related
2819 ****************************************/
2840 enum bt_total_ant_num {
2850 enum bt_service_type {
2857 BT_OTHER_ACTION = 6,
2863 enum bt_radio_shared {
2864 BT_RADIO_SHARED = 0,
2865 BT_RADIO_INDIVIDUAL = 1,
2869 /****************************************
2870 mem access macro define start
2871 Call endian free function when
2872 1. Read/write packet content.
2873 2. Before write integer to IO.
2874 3. After read integer from IO.
2875 ****************************************/
2876 /* Convert little data endian to host ordering */
2877 #define EF1BYTE(_val) \
2879 #define EF2BYTE(_val) \
2881 #define EF4BYTE(_val) \
2884 /* Read data from memory */
2885 #define READEF1BYTE(_ptr) \
2886 EF1BYTE(*((u8 *)(_ptr)))
2887 /* Read le16 data from memory and convert to host ordering */
2888 #define READEF2BYTE(_ptr) \
2890 #define READEF4BYTE(_ptr) \
2893 /* Create a bit mask
2895 * BIT_LEN_MASK_32(0) => 0x00000000
2896 * BIT_LEN_MASK_32(1) => 0x00000001
2897 * BIT_LEN_MASK_32(2) => 0x00000003
2898 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2900 #define BIT_LEN_MASK_32(__bitlen) \
2901 (0xFFFFFFFF >> (32 - (__bitlen)))
2902 #define BIT_LEN_MASK_16(__bitlen) \
2903 (0xFFFF >> (16 - (__bitlen)))
2904 #define BIT_LEN_MASK_8(__bitlen) \
2905 (0xFF >> (8 - (__bitlen)))
2907 /* Create an offset bit mask
2909 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2910 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2912 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2913 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2914 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2915 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2916 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2917 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2920 * Return 4-byte value in host byte ordering from
2921 * 4-byte pointer in little-endian system.
2923 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2924 (EF4BYTE(*((__le32 *)(__pstart))))
2925 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2926 (EF2BYTE(*((__le16 *)(__pstart))))
2927 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2928 (EF1BYTE(*((u8 *)(__pstart))))
2931 Translate subfield (continuous bits in little-endian) of 4-byte
2932 value to host byte ordering.*/
2933 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2935 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2936 BIT_LEN_MASK_32(__bitlen) \
2938 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2940 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2941 BIT_LEN_MASK_16(__bitlen) \
2943 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2945 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2946 BIT_LEN_MASK_8(__bitlen) \
2950 * Mask subfield (continuous bits in little-endian) of 4-byte value
2951 * and return the result in 4-byte value in host byte ordering.
2953 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2955 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2956 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2958 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2960 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2961 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2963 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2965 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2966 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2970 * Set subfield of little-endian 4-byte value to specified value.
2972 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2973 *((__le32 *)(__pstart)) = \
2975 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2976 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2978 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2979 *((__le16 *)(__pstart)) = \
2981 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2982 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2984 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2985 *((u8 *)(__pstart)) = EF1BYTE \
2987 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2988 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2991 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2992 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2994 /****************************************
2995 mem access macro define end
2996 ****************************************/
2998 #define byte(x, n) ((x >> (8 * n)) & 0xff)
3000 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
3001 #define RTL_WATCH_DOG_TIME 2000
3002 #define MSECS(t) msecs_to_jiffies(t)
3003 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
3004 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
3005 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
3006 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
3007 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
3009 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
3010 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
3011 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
3012 /*NIC halt, re-initialize hw parameters*/
3013 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
3014 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
3015 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
3016 /*Always enable ASPM and Clock Req in initialization.*/
3017 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
3018 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
3019 #define RT_PS_LEVEL_ASPM BIT(7)
3020 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
3021 #define RT_RF_LPS_DISALBE_2R BIT(30)
3022 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
3023 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
3024 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
3025 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
3026 (ppsc->cur_ps_level &= (~(_ps_flg)))
3027 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
3028 (ppsc->cur_ps_level |= _ps_flg)
3030 #define container_of_dwork_rtl(x, y, z) \
3031 container_of(to_delayed_work(x), y, z)
3033 #define FILL_OCTET_STRING(_os, _octet, _len) \
3034 (_os).octet = (u8 *)(_octet); \
3035 (_os).length = (_len);
3037 #define CP_MACADDR(des, src) \
3038 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
3039 (des)[2] = (src)[2], (des)[3] = (src)[3],\
3040 (des)[4] = (src)[4], (des)[5] = (src)[5])
3042 #define LDPC_HT_ENABLE_RX BIT(0)
3043 #define LDPC_HT_ENABLE_TX BIT(1)
3044 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
3045 #define LDPC_HT_CAP_TX BIT(3)
3047 #define STBC_HT_ENABLE_RX BIT(0)
3048 #define STBC_HT_ENABLE_TX BIT(1)
3049 #define STBC_HT_TEST_TX_ENABLE BIT(2)
3050 #define STBC_HT_CAP_TX BIT(3)
3052 #define LDPC_VHT_ENABLE_RX BIT(0)
3053 #define LDPC_VHT_ENABLE_TX BIT(1)
3054 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
3055 #define LDPC_VHT_CAP_TX BIT(3)
3057 #define STBC_VHT_ENABLE_RX BIT(0)
3058 #define STBC_VHT_ENABLE_TX BIT(1)
3059 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
3060 #define STBC_VHT_CAP_TX BIT(3)
3062 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
3064 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
3066 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
3068 return rtlpriv->io.read8_sync(rtlpriv, addr);
3071 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
3073 return rtlpriv->io.read16_sync(rtlpriv, addr);
3076 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
3078 return rtlpriv->io.read32_sync(rtlpriv, addr);
3081 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
3083 rtlpriv->io.write8_async(rtlpriv, addr, val8);
3085 if (rtlpriv->cfg->write_readback)
3086 rtlpriv->io.read8_sync(rtlpriv, addr);
3089 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
3092 struct rtl_priv *rtlpriv = rtl_priv(hw);
3094 rtl_write_byte(rtlpriv, addr, (u8)val8);
3097 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
3099 rtlpriv->io.write16_async(rtlpriv, addr, val16);
3101 if (rtlpriv->cfg->write_readback)
3102 rtlpriv->io.read16_sync(rtlpriv, addr);
3105 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
3106 u32 addr, u32 val32)
3108 rtlpriv->io.write32_async(rtlpriv, addr, val32);
3110 if (rtlpriv->cfg->write_readback)
3111 rtlpriv->io.read32_sync(rtlpriv, addr);
3114 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
3115 u32 regaddr, u32 bitmask)
3117 struct rtl_priv *rtlpriv = hw->priv;
3119 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
3122 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
3123 u32 bitmask, u32 data)
3125 struct rtl_priv *rtlpriv = hw->priv;
3127 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
3130 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
3131 u32 regaddr, u32 data)
3133 rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
3136 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
3137 enum radio_path rfpath, u32 regaddr,
3140 struct rtl_priv *rtlpriv = hw->priv;
3142 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
3145 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
3146 enum radio_path rfpath, u32 regaddr,
3147 u32 bitmask, u32 data)
3149 struct rtl_priv *rtlpriv = hw->priv;
3151 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
3154 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
3156 return (_HAL_STATE_STOP == rtlhal->state);
3159 static inline void set_hal_start(struct rtl_hal *rtlhal)
3161 rtlhal->state = _HAL_STATE_START;
3164 static inline void set_hal_stop(struct rtl_hal *rtlhal)
3166 rtlhal->state = _HAL_STATE_STOP;
3169 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3171 return rtlphy->rf_type;
3174 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3176 return (struct ieee80211_hdr *)(skb->data);
3179 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3181 return rtl_get_hdr(skb)->frame_control;
3184 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3186 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3189 static inline u16 rtl_get_tid(struct sk_buff *skb)
3191 return rtl_get_tid_h(rtl_get_hdr(skb));
3194 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3195 struct ieee80211_vif *vif,
3198 return ieee80211_find_sta(vif, bssid);
3201 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3204 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3205 return ieee80211_find_sta(mac->vif, mac_addr);