drivers/net/wireless/ralink/rt2x00/rt73usb.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   4         <http://rt2x00.serialmonkey.com>
   5
   6  */
   7
   8 /*
   9         Module: rt73usb
  10         Abstract: rt73usb device specific routines.
  11         Supported chipsets: rt2571W & rt2671.
  12  */
  13
  14 #include <linux/crc-itu-t.h>
  15 #include <linux/delay.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/slab.h>
  20 #include <linux/usb.h>
  21
  22 #include "rt2x00.h"
  23 #include "rt2x00usb.h"
  24 #include "rt73usb.h"
  25
  26 /*
  27  * Allow hardware encryption to be disabled.
  28  */
  29 static bool modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  32
  33 /*
  34  * Register access.
  35  * All access to the CSR registers will go through the methods
  36  * rt2x00usb_register_read and rt2x00usb_register_write.
  37  * BBP and RF register require indirect register access,
  38  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  39  * These indirect registers work with busy bits,
  40  * and we will try maximal REGISTER_BUSY_COUNT times to access
  41  * the register while taking a REGISTER_BUSY_DELAY us delay
  42  * between each attampt. When the busy bit is still set at that time,
  43  * the access attempt is considered to have failed,
  44  * and we will print an error.
  45  * The _lock versions must be used if you already hold the csr_mutex
  46  */
  47 #define WAIT_FOR_BBP(__dev, __reg) \
  48         rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  49 #define WAIT_FOR_RF(__dev, __reg) \
  50         rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  51
  52 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  53                               const unsigned int word, const u8 value)
  54 {
  55         u32 reg;
  56
  57         mutex_lock(&rt2x00dev->csr_mutex);
  58
  59         /*
  60          * Wait until the BBP becomes available, afterwards we
  61          * can safely write the new data into the register.
  62          */
  63         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  64                 reg = 0;
  65                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  66                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  67                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  68                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  69
  70                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
  71         }
  72
  73         mutex_unlock(&rt2x00dev->csr_mutex);
  74 }
  75
  76 static u8 rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  77                            const unsigned int word)
  78 {
  79         u32 reg;
  80         u8 value;
  81
  82         mutex_lock(&rt2x00dev->csr_mutex);
  83
  84         /*
  85          * Wait until the BBP becomes available, afterwards we
  86          * can safely write the read request into the register.
  87          * After the data has been written, we wait until hardware
  88          * returns the correct value, if at any time the register
  89          * doesn't become available in time, reg will be 0xffffffff
  90          * which means we return 0xff to the caller.
  91          */
  92         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  93                 reg = 0;
  94                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  95                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  96                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
  97
  98                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
  99
 100                 WAIT_FOR_BBP(rt2x00dev, &reg);
 101         }
 102
 103         value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 104
 105         mutex_unlock(&rt2x00dev->csr_mutex);
 106
 107         return value;
 108 }
 109
 110 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
 111                              const unsigned int word, const u32 value)
 112 {
 113         u32 reg;
 114
 115         mutex_lock(&rt2x00dev->csr_mutex);
 116
 117         /*
 118          * Wait until the RF becomes available, afterwards we
 119          * can safely write the new data into the register.
 120          */
 121         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 122                 reg = 0;
 123                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 124                 /*
 125                  * RF5225 and RF2527 contain 21 bits per RF register value,
 126                  * all others contain 20 bits.
 127                  */
 128                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
 129                                    20 + (rt2x00_rf(rt2x00dev, RF5225) ||
 130                                          rt2x00_rf(rt2x00dev, RF2527)));
 131                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 132                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 133
 134                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
 135                 rt2x00_rf_write(rt2x00dev, word, value);
 136         }
 137
 138         mutex_unlock(&rt2x00dev->csr_mutex);
 139 }
 140
 141 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 142 static const struct rt2x00debug rt73usb_rt2x00debug = {
 143         .owner  = THIS_MODULE,
 144         .csr    = {
 145                 .read           = rt2x00usb_register_read,
 146                 .write          = rt2x00usb_register_write,
 147                 .flags          = RT2X00DEBUGFS_OFFSET,
 148                 .word_base      = CSR_REG_BASE,
 149                 .word_size      = sizeof(u32),
 150                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 151         },
 152         .eeprom = {
 153                 .read           = rt2x00_eeprom_read,
 154                 .write          = rt2x00_eeprom_write,
 155                 .word_base      = EEPROM_BASE,
 156                 .word_size      = sizeof(u16),
 157                 .word_count     = EEPROM_SIZE / sizeof(u16),
 158         },
 159         .bbp    = {
 160                 .read           = rt73usb_bbp_read,
 161                 .write          = rt73usb_bbp_write,
 162                 .word_base      = BBP_BASE,
 163                 .word_size      = sizeof(u8),
 164                 .word_count     = BBP_SIZE / sizeof(u8),
 165         },
 166         .rf     = {
 167                 .read           = rt2x00_rf_read,
 168                 .write          = rt73usb_rf_write,
 169                 .word_base      = RF_BASE,
 170                 .word_size      = sizeof(u32),
 171                 .word_count     = RF_SIZE / sizeof(u32),
 172         },
 173 };
 174 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 175
 176 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 177 {
 178         u32 reg;
 179
 180         reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR13);
 181         return rt2x00_get_field32(reg, MAC_CSR13_VAL7);
 182 }
 183
 184 #ifdef CONFIG_RT2X00_LIB_LEDS
 185 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
 186                                    enum led_brightness brightness)
 187 {
 188         struct rt2x00_led *led =
 189            container_of(led_cdev, struct rt2x00_led, led_dev);
 190         unsigned int enabled = brightness != LED_OFF;
 191         unsigned int a_mode =
 192             (enabled && led->rt2x00dev->curr_band == NL80211_BAND_5GHZ);
 193         unsigned int bg_mode =
 194             (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
 195
 196         if (led->type == LED_TYPE_RADIO) {
 197                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 198                                    MCU_LEDCS_RADIO_STATUS, enabled);
 199
 200                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 201                                             0, led->rt2x00dev->led_mcu_reg,
 202                                             REGISTER_TIMEOUT);
 203         } else if (led->type == LED_TYPE_ASSOC) {
 204                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 205                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 206                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 207                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 208
 209                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 210                                             0, led->rt2x00dev->led_mcu_reg,
 211                                             REGISTER_TIMEOUT);
 212         } else if (led->type == LED_TYPE_QUALITY) {
 213                 /*
 214                  * The brightness is divided into 6 levels (0 - 5),
 215                  * this means we need to convert the brightness
 216                  * argument into the matching level within that range.
 217                  */
 218                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 219                                             brightness / (LED_FULL / 6),
 220                                             led->rt2x00dev->led_mcu_reg,
 221                                             REGISTER_TIMEOUT);
 222         }
 223 }
 224
 225 static int rt73usb_blink_set(struct led_classdev *led_cdev,
 226                              unsigned long *delay_on,
 227                              unsigned long *delay_off)
 228 {
 229         struct rt2x00_led *led =
 230             container_of(led_cdev, struct rt2x00_led, led_dev);
 231         u32 reg;
 232
 233         reg = rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14);
 234         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 235         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 236         rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
 237
 238         return 0;
 239 }
 240
 241 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
 242                              struct rt2x00_led *led,
 243                              enum led_type type)
 244 {
 245         led->rt2x00dev = rt2x00dev;
 246         led->type = type;
 247         led->led_dev.brightness_set = rt73usb_brightness_set;
 248         led->led_dev.blink_set = rt73usb_blink_set;
 249         led->flags = LED_INITIALIZED;
 250 }
 251 #endif /* CONFIG_RT2X00_LIB_LEDS */
 252
 253 /*
 254  * Configuration handlers.
 255  */
 256 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 257                                      struct rt2x00lib_crypto *crypto,
 258                                      struct ieee80211_key_conf *key)
 259 {
 260         struct hw_key_entry key_entry;
 261         struct rt2x00_field32 field;
 262         u32 mask;
 263         u32 reg;
 264
 265         if (crypto->cmd == SET_KEY) {
 266                 /*
 267                  * rt2x00lib can't determine the correct free
 268                  * key_idx for shared keys. We have 1 register
 269                  * with key valid bits. The goal is simple, read
 270                  * the register, if that is full we have no slots
 271                  * left.
 272                  * Note that each BSS is allowed to have up to 4
 273                  * shared keys, so put a mask over the allowed
 274                  * entries.
 275                  */
 276                 mask = (0xf << crypto->bssidx);
 277
 278                 reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR0);
 279                 reg &= mask;
 280
 281                 if (reg && reg == mask)
 282                         return -ENOSPC;
 283
 284                 key->hw_key_idx += reg ? ffz(reg) : 0;
 285
 286                 /*
 287                  * Upload key to hardware
 288                  */
 289                 memcpy(key_entry.key, crypto->key,
 290                        sizeof(key_entry.key));
 291                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 292                        sizeof(key_entry.tx_mic));
 293                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 294                        sizeof(key_entry.rx_mic));
 295
 296                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 297                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 298                                               &key_entry, sizeof(key_entry));
 299
 300                 /*
 301                  * The cipher types are stored over 2 registers.
 302                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 303                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 304                  * Using the correct defines correctly will cause overhead,
 305                  * so just calculate the correct offset.
 306                  */
 307                 if (key->hw_key_idx < 8) {
 308                         field.bit_offset = (3 * key->hw_key_idx);
 309                         field.bit_mask = 0x7 << field.bit_offset;
 310
 311                         reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR1);
 312                         rt2x00_set_field32(&reg, field, crypto->cipher);
 313                         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
 314                 } else {
 315                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 316                         field.bit_mask = 0x7 << field.bit_offset;
 317
 318                         reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR5);
 319                         rt2x00_set_field32(&reg, field, crypto->cipher);
 320                         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
 321                 }
 322
 323                 /*
 324                  * The driver does not support the IV/EIV generation
 325                  * in hardware. However it doesn't support the IV/EIV
 326                  * inside the ieee80211 frame either, but requires it
 327                  * to be provided separately for the descriptor.
 328                  * rt2x00lib will cut the IV/EIV data out of all frames
 329                  * given to us by mac80211, but we must tell mac80211
 330                  * to generate the IV/EIV data.
 331                  */
 332                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 333         }
 334
 335         /*
 336          * SEC_CSR0 contains only single-bit fields to indicate
 337          * a particular key is valid. Because using the FIELD32()
 338          * defines directly will cause a lot of overhead we use
 339          * a calculation to determine the correct bit directly.
 340          */
 341         mask = 1 << key->hw_key_idx;
 342
 343         reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR0);
 344         if (crypto->cmd == SET_KEY)
 345                 reg |= mask;
 346         else if (crypto->cmd == DISABLE_KEY)
 347                 reg &= ~mask;
 348         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
 349
 350         return 0;
 351 }
 352
 353 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 354                                        struct rt2x00lib_crypto *crypto,
 355                                        struct ieee80211_key_conf *key)
 356 {
 357         struct hw_pairwise_ta_entry addr_entry;
 358         struct hw_key_entry key_entry;
 359         u32 mask;
 360         u32 reg;
 361
 362         if (crypto->cmd == SET_KEY) {
 363                 /*
 364                  * rt2x00lib can't determine the correct free
 365                  * key_idx for pairwise keys. We have 2 registers
 366                  * with key valid bits. The goal is simple, read
 367                  * the first register, if that is full move to
 368                  * the next register.
 369                  * When both registers are full, we drop the key,
 370                  * otherwise we use the first invalid entry.
 371                  */
 372                 reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR2);
 373                 if (reg && reg == ~0) {
 374                         key->hw_key_idx = 32;
 375                         reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR3);
 376                         if (reg && reg == ~0)
 377                                 return -ENOSPC;
 378                 }
 379
 380                 key->hw_key_idx += reg ? ffz(reg) : 0;
 381
 382                 /*
 383                  * Upload key to hardware
 384                  */
 385                 memcpy(key_entry.key, crypto->key,
 386                        sizeof(key_entry.key));
 387                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 388                        sizeof(key_entry.tx_mic));
 389                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 390                        sizeof(key_entry.rx_mic));
 391
 392                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 393                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 394                                               &key_entry, sizeof(key_entry));
 395
 396                 /*
 397                  * Send the address and cipher type to the hardware register.
 398                  */
 399                 memset(&addr_entry, 0, sizeof(addr_entry));
 400                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 401                 addr_entry.cipher = crypto->cipher;
 402
 403                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 404                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 405                                             &addr_entry, sizeof(addr_entry));
 406
 407                 /*
 408                  * Enable pairwise lookup table for given BSS idx,
 409                  * without this received frames will not be decrypted
 410                  * by the hardware.
 411                  */
 412                 reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR4);
 413                 reg |= (1 << crypto->bssidx);
 414                 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
 415
 416                 /*
 417                  * The driver does not support the IV/EIV generation
 418                  * in hardware. However it doesn't support the IV/EIV
 419                  * inside the ieee80211 frame either, but requires it
 420                  * to be provided separately for the descriptor.
 421                  * rt2x00lib will cut the IV/EIV data out of all frames
 422                  * given to us by mac80211, but we must tell mac80211
 423                  * to generate the IV/EIV data.
 424                  */
 425                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 426         }
 427
 428         /*
 429          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 430          * a particular key is valid. Because using the FIELD32()
 431          * defines directly will cause a lot of overhead we use
 432          * a calculation to determine the correct bit directly.
 433          */
 434         if (key->hw_key_idx < 32) {
 435                 mask = 1 << key->hw_key_idx;
 436
 437                 reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR2);
 438                 if (crypto->cmd == SET_KEY)
 439                         reg |= mask;
 440                 else if (crypto->cmd == DISABLE_KEY)
 441                         reg &= ~mask;
 442                 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
 443         } else {
 444                 mask = 1 << (key->hw_key_idx - 32);
 445
 446                 reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR3);
 447                 if (crypto->cmd == SET_KEY)
 448                         reg |= mask;
 449                 else if (crypto->cmd == DISABLE_KEY)
 450                         reg &= ~mask;
 451                 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
 452         }
 453
 454         return 0;
 455 }
 456
 457 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
 458                                   const unsigned int filter_flags)
 459 {
 460         u32 reg;
 461
 462         /*
 463          * Start configuration steps.
 464          * Note that the version error will always be dropped
 465          * and broadcast frames will always be accepted since
 466          * there is no filter for it at this time.
 467          */
 468         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
 469         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 470                            !(filter_flags & FIF_FCSFAIL));
 471         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 472                            !(filter_flags & FIF_PLCPFAIL));
 473         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 474                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
 475         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 476                            !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
 477         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 478                            !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) &&
 479                            !rt2x00dev->intf_ap_count);
 480         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 481         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 482                            !(filter_flags & FIF_ALLMULTI));
 483         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 484         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 485                            !(filter_flags & FIF_CONTROL));
 486         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 487 }
 488
 489 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
 490                                 struct rt2x00_intf *intf,
 491                                 struct rt2x00intf_conf *conf,
 492                                 const unsigned int flags)
 493 {
 494         u32 reg;
 495
 496         if (flags & CONFIG_UPDATE_TYPE) {
 497                 /*
 498                  * Enable synchronisation.
 499                  */
 500                 reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
 501                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 502                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 503         }
 504
 505         if (flags & CONFIG_UPDATE_MAC) {
 506                 reg = le32_to_cpu(conf->mac[1]);
 507                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 508                 conf->mac[1] = cpu_to_le32(reg);
 509
 510                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
 511                                             conf->mac, sizeof(conf->mac));
 512         }
 513
 514         if (flags & CONFIG_UPDATE_BSSID) {
 515                 reg = le32_to_cpu(conf->bssid[1]);
 516                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 517                 conf->bssid[1] = cpu_to_le32(reg);
 518
 519                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
 520                                             conf->bssid, sizeof(conf->bssid));
 521         }
 522 }
 523
 524 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
 525                                struct rt2x00lib_erp *erp,
 526                                u32 changed)
 527 {
 528         u32 reg;
 529
 530         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
 531         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
 532         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 533         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 534
 535         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 536                 reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR4);
 537                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 538                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 539                                    !!erp->short_preamble);
 540                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 541         }
 542
 543         if (changed & BSS_CHANGED_BASIC_RATES)
 544                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5,
 545                                          erp->basic_rates);
 546
 547         if (changed & BSS_CHANGED_BEACON_INT) {
 548                 reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
 549                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 550                                    erp->beacon_int * 16);
 551                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 552         }
 553
 554         if (changed & BSS_CHANGED_ERP_SLOT) {
 555                 reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR9);
 556                 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 557                 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
 558
 559                 reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR8);
 560                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 561                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 562                 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 563                 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
 564         }
 565 }
 566
 567 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 568                                       struct antenna_setup *ant)
 569 {
 570         u8 r3;
 571         u8 r4;
 572         u8 r77;
 573         u8 temp;
 574
 575         r3 = rt73usb_bbp_read(rt2x00dev, 3);
 576         r4 = rt73usb_bbp_read(rt2x00dev, 4);
 577         r77 = rt73usb_bbp_read(rt2x00dev, 77);
 578
 579         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 580
 581         /*
 582          * Configure the RX antenna.
 583          */
 584         switch (ant->rx) {
 585         case ANTENNA_HW_DIVERSITY:
 586                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 587                 temp = !rt2x00_has_cap_frame_type(rt2x00dev) &&
 588                        (rt2x00dev->curr_band != NL80211_BAND_5GHZ);
 589                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
 590                 break;
 591         case ANTENNA_A:
 592                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 593                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 594                 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ)
 595                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 596                 else
 597                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 598                 break;
 599         case ANTENNA_B:
 600         default:
 601                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 602                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 603                 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ)
 604                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 605                 else
 606                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 607                 break;
 608         }
 609
 610         rt73usb_bbp_write(rt2x00dev, 77, r77);
 611         rt73usb_bbp_write(rt2x00dev, 3, r3);
 612         rt73usb_bbp_write(rt2x00dev, 4, r4);
 613 }
 614
 615 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 616                                       struct antenna_setup *ant)
 617 {
 618         u8 r3;
 619         u8 r4;
 620         u8 r77;
 621
 622         r3 = rt73usb_bbp_read(rt2x00dev, 3);
 623         r4 = rt73usb_bbp_read(rt2x00dev, 4);
 624         r77 = rt73usb_bbp_read(rt2x00dev, 77);
 625
 626         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 627         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 628                           !rt2x00_has_cap_frame_type(rt2x00dev));
 629
 630         /*
 631          * Configure the RX antenna.
 632          */
 633         switch (ant->rx) {
 634         case ANTENNA_HW_DIVERSITY:
 635                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 636                 break;
 637         case ANTENNA_A:
 638                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 639                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 640                 break;
 641         case ANTENNA_B:
 642         default:
 643                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 644                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 645                 break;
 646         }
 647
 648         rt73usb_bbp_write(rt2x00dev, 77, r77);
 649         rt73usb_bbp_write(rt2x00dev, 3, r3);
 650         rt73usb_bbp_write(rt2x00dev, 4, r4);
 651 }
 652
 653 struct antenna_sel {
 654         u8 word;
 655         /*
 656          * value[0] -> non-LNA
 657          * value[1] -> LNA
 658          */
 659         u8 value[2];
 660 };
 661
 662 static const struct antenna_sel antenna_sel_a[] = {
 663         { 96,  { 0x58, 0x78 } },
 664         { 104, { 0x38, 0x48 } },
 665         { 75,  { 0xfe, 0x80 } },
 666         { 86,  { 0xfe, 0x80 } },
 667         { 88,  { 0xfe, 0x80 } },
 668         { 35,  { 0x60, 0x60 } },
 669         { 97,  { 0x58, 0x58 } },
 670         { 98,  { 0x58, 0x58 } },
 671 };
 672
 673 static const struct antenna_sel antenna_sel_bg[] = {
 674         { 96,  { 0x48, 0x68 } },
 675         { 104, { 0x2c, 0x3c } },
 676         { 75,  { 0xfe, 0x80 } },
 677         { 86,  { 0xfe, 0x80 } },
 678         { 88,  { 0xfe, 0x80 } },
 679         { 35,  { 0x50, 0x50 } },
 680         { 97,  { 0x48, 0x48 } },
 681         { 98,  { 0x48, 0x48 } },
 682 };
 683
 684 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
 685                                struct antenna_setup *ant)
 686 {
 687         const struct antenna_sel *sel;
 688         unsigned int lna;
 689         unsigned int i;
 690         u32 reg;
 691
 692         /*
 693          * We should never come here because rt2x00lib is supposed
 694          * to catch this and send us the correct antenna explicitely.
 695          */
 696         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 697                ant->tx == ANTENNA_SW_DIVERSITY);
 698
 699         if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
 700                 sel = antenna_sel_a;
 701                 lna = rt2x00_has_cap_external_lna_a(rt2x00dev);
 702         } else {
 703                 sel = antenna_sel_bg;
 704                 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev);
 705         }
 706
 707         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 708                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 709
 710         reg = rt2x00usb_register_read(rt2x00dev, PHY_CSR0);
 711
 712         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 713                            (rt2x00dev->curr_band == NL80211_BAND_2GHZ));
 714         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 715                            (rt2x00dev->curr_band == NL80211_BAND_5GHZ));
 716
 717         rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
 718
 719         if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
 720                 rt73usb_config_antenna_5x(rt2x00dev, ant);
 721         else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
 722                 rt73usb_config_antenna_2x(rt2x00dev, ant);
 723 }
 724
 725 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 726                                     struct rt2x00lib_conf *libconf)
 727 {
 728         u16 eeprom;
 729         short lna_gain = 0;
 730
 731         if (libconf->conf->chandef.chan->band == NL80211_BAND_2GHZ) {
 732                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 733                         lna_gain += 14;
 734
 735                 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG);
 736                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 737         } else {
 738                 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A);
 739                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 740         }
 741
 742         rt2x00dev->lna_gain = lna_gain;
 743 }
 744
 745 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
 746                                    struct rf_channel *rf, const int txpower)
 747 {
 748         u8 r3;
 749         u8 r94;
 750         u8 smart;
 751
 752         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 753         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 754
 755         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
 756
 757         r3 = rt73usb_bbp_read(rt2x00dev, 3);
 758         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 759         rt73usb_bbp_write(rt2x00dev, 3, r3);
 760
 761         r94 = 6;
 762         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 763                 r94 += txpower - MAX_TXPOWER;
 764         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 765                 r94 += txpower;
 766         rt73usb_bbp_write(rt2x00dev, 94, r94);
 767
 768         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 769         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 770         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 771         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 772
 773         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 774         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 775         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 776         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 777
 778         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 779         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 780         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 781         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 782
 783         udelay(10);
 784 }
 785
 786 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 787                                    const int txpower)
 788 {
 789         struct rf_channel rf;
 790
 791         rf.rf1 = rt2x00_rf_read(rt2x00dev, 1);
 792         rf.rf2 = rt2x00_rf_read(rt2x00dev, 2);
 793         rf.rf3 = rt2x00_rf_read(rt2x00dev, 3);
 794         rf.rf4 = rt2x00_rf_read(rt2x00dev, 4);
 795
 796         rt73usb_config_channel(rt2x00dev, &rf, txpower);
 797 }
 798
 799 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 800                                        struct rt2x00lib_conf *libconf)
 801 {
 802         u32 reg;
 803
 804         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR4);
 805         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
 806         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
 807         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
 808         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 809                            libconf->conf->long_frame_max_tx_count);
 810         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 811                            libconf->conf->short_frame_max_tx_count);
 812         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 813 }
 814
 815 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
 816                                 struct rt2x00lib_conf *libconf)
 817 {
 818         enum dev_state state =
 819             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 820                 STATE_SLEEP : STATE_AWAKE;
 821         u32 reg;
 822
 823         if (state == STATE_SLEEP) {
 824                 reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR11);
 825                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 826                                    rt2x00dev->beacon_int - 10);
 827                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 828                                    libconf->conf->listen_interval - 1);
 829                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 830
 831                 /* We must first disable autowake before it can be enabled */
 832                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 833                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 834
 835                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 836                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 837
 838                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
 839                                             USB_MODE_SLEEP, REGISTER_TIMEOUT);
 840         } else {
 841                 reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR11);
 842                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 843                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 844                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 845                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 846                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 847
 848                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
 849                                             USB_MODE_WAKEUP, REGISTER_TIMEOUT);
 850         }
 851 }
 852
 853 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
 854                            struct rt2x00lib_conf *libconf,
 855                            const unsigned int flags)
 856 {
 857         /* Always recalculate LNA gain before changing configuration */
 858         rt73usb_config_lna_gain(rt2x00dev, libconf);
 859
 860         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 861                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
 862                                        libconf->conf->power_level);
 863         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 864             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 865                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 866         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 867                 rt73usb_config_retry_limit(rt2x00dev, libconf);
 868         if (flags & IEEE80211_CONF_CHANGE_PS)
 869                 rt73usb_config_ps(rt2x00dev, libconf);
 870 }
 871
 872 /*
 873  * Link tuning
 874  */
 875 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
 876                                struct link_qual *qual)
 877 {
 878         u32 reg;
 879
 880         /*
 881          * Update FCS error count from register.
 882          */
 883         reg = rt2x00usb_register_read(rt2x00dev, STA_CSR0);
 884         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 885
 886         /*
 887          * Update False CCA count from register.
 888          */
 889         reg = rt2x00usb_register_read(rt2x00dev, STA_CSR1);
 890         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 891 }
 892
 893 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
 894                                    struct link_qual *qual, u8 vgc_level)
 895 {
 896         if (qual->vgc_level != vgc_level) {
 897                 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
 898                 qual->vgc_level = vgc_level;
 899                 qual->vgc_level_reg = vgc_level;
 900         }
 901 }
 902
 903 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
 904                                 struct link_qual *qual)
 905 {
 906         rt73usb_set_vgc(rt2x00dev, qual, 0x20);
 907 }
 908
 909 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
 910                                struct link_qual *qual, const u32 count)
 911 {
 912         u8 up_bound;
 913         u8 low_bound;
 914
 915         /*
 916          * Determine r17 bounds.
 917          */
 918         if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
 919                 low_bound = 0x28;
 920                 up_bound = 0x48;
 921
 922                 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
 923                         low_bound += 0x10;
 924                         up_bound += 0x10;
 925                 }
 926         } else {
 927                 if (qual->rssi > -82) {
 928                         low_bound = 0x1c;
 929                         up_bound = 0x40;
 930                 } else if (qual->rssi > -84) {
 931                         low_bound = 0x1c;
 932                         up_bound = 0x20;
 933                 } else {
 934                         low_bound = 0x1c;
 935                         up_bound = 0x1c;
 936                 }
 937
 938                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 939                         low_bound += 0x14;
 940                         up_bound += 0x10;
 941                 }
 942         }
 943
 944         /*
 945          * If we are not associated, we should go straight to the
 946          * dynamic CCA tuning.
 947          */
 948         if (!rt2x00dev->intf_associated)
 949                 goto dynamic_cca_tune;
 950
 951         /*
 952          * Special big-R17 for very short distance
 953          */
 954         if (qual->rssi > -35) {
 955                 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
 956                 return;
 957         }
 958
 959         /*
 960          * Special big-R17 for short distance
 961          */
 962         if (qual->rssi >= -58) {
 963                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
 964                 return;
 965         }
 966
 967         /*
 968          * Special big-R17 for middle-short distance
 969          */
 970         if (qual->rssi >= -66) {
 971                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
 972                 return;
 973         }
 974
 975         /*
 976          * Special mid-R17 for middle distance
 977          */
 978         if (qual->rssi >= -74) {
 979                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
 980                 return;
 981         }
 982
 983         /*
 984          * Special case: Change up_bound based on the rssi.
 985          * Lower up_bound when rssi is weaker then -74 dBm.
 986          */
 987         up_bound -= 2 * (-74 - qual->rssi);
 988         if (low_bound > up_bound)
 989                 up_bound = low_bound;
 990
 991         if (qual->vgc_level > up_bound) {
 992                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
 993                 return;
 994         }
 995
 996 dynamic_cca_tune:
 997
 998         /*
 999          * r17 does not yet exceed upper limit, continue and base
1000          * the r17 tuning on the false CCA count.
1001          */
1002         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1003                 rt73usb_set_vgc(rt2x00dev, qual,
1004                                 min_t(u8, qual->vgc_level + 4, up_bound));
1005         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1006                 rt73usb_set_vgc(rt2x00dev, qual,
1007                                 max_t(u8, qual->vgc_level - 4, low_bound));
1008 }
1009
1010 /*
1011  * Queue handlers.
1012  */
1013 static void rt73usb_start_queue(struct data_queue *queue)
1014 {
1015         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1016         u32 reg;
1017
1018         switch (queue->qid) {
1019         case QID_RX:
1020                 reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
1021                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1022                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1023                 break;
1024         case QID_BEACON:
1025                 reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1026                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1027                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1028                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1029                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1030                 break;
1031         default:
1032                 break;
1033         }
1034 }
1035
1036 static void rt73usb_stop_queue(struct data_queue *queue)
1037 {
1038         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1039         u32 reg;
1040
1041         switch (queue->qid) {
1042         case QID_RX:
1043                 reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
1044                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1045                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1046                 break;
1047         case QID_BEACON:
1048                 reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1049                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1050                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1051                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1052                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1053                 break;
1054         default:
1055                 break;
1056         }
1057 }
1058
1059 /*
1060  * Firmware functions
1061  */
1062 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1063 {
1064         return FIRMWARE_RT2571;
1065 }
1066
1067 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1068                                   const u8 *data, const size_t len)
1069 {
1070         u16 fw_crc;
1071         u16 crc;
1072
1073         /*
1074          * Only support 2kb firmware files.
1075          */
1076         if (len != 2048)
1077                 return FW_BAD_LENGTH;
1078
1079         /*
1080          * The last 2 bytes in the firmware array are the crc checksum itself,
1081          * this means that we should never pass those 2 bytes to the crc
1082          * algorithm.
1083          */
1084         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1085
1086         /*
1087          * Use the crc itu-t algorithm.
1088          */
1089         crc = crc_itu_t(0, data, len - 2);
1090         crc = crc_itu_t_byte(crc, 0);
1091         crc = crc_itu_t_byte(crc, 0);
1092
1093         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1094 }
1095
1096 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1097                                  const u8 *data, const size_t len)
1098 {
1099         unsigned int i;
1100         int status;
1101         u32 reg;
1102
1103         /*
1104          * Wait for stable hardware.
1105          */
1106         for (i = 0; i < 100; i++) {
1107                 reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR0);
1108                 if (reg)
1109                         break;
1110                 msleep(1);
1111         }
1112
1113         if (!reg) {
1114                 rt2x00_err(rt2x00dev, "Unstable hardware\n");
1115                 return -EBUSY;
1116         }
1117
1118         /*
1119          * Write firmware to device.
1120          */
1121         rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
1122
1123         /*
1124          * Send firmware request to device to load firmware,
1125          * we need to specify a long timeout time.
1126          */
1127         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1128                                              0, USB_MODE_FIRMWARE,
1129                                              REGISTER_TIMEOUT_FIRMWARE);
1130         if (status < 0) {
1131                 rt2x00_err(rt2x00dev, "Failed to write Firmware to device\n");
1132                 return status;
1133         }
1134
1135         return 0;
1136 }
1137
1138 /*
1139  * Initialization functions.
1140  */
1141 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1142 {
1143         u32 reg;
1144
1145         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0);
1146         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1147         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1148         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1149         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1150
1151         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR1);
1152         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1153         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1154         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1155         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1156         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1157         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1158         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1159         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1160         rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1161
1162         /*
1163          * CCK TXD BBP registers
1164          */
1165         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR2);
1166         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1167         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1168         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1169         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1170         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1171         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1172         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1173         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1174         rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1175
1176         /*
1177          * OFDM TXD BBP registers
1178          */
1179         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR3);
1180         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1181         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1182         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1183         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1184         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1185         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1186         rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1187
1188         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR7);
1189         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1190         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1191         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1192         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1193         rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1194
1195         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR8);
1196         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1197         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1198         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1199         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1200         rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1201
1202         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1203         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1204         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1205         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1206         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1207         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1208         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1209         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1210
1211         rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1212
1213         reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR6);
1214         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1215         rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1216
1217         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1218
1219         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1220                 return -EBUSY;
1221
1222         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1223
1224         /*
1225          * Invalidate all Shared Keys (SEC_CSR0),
1226          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1227          */
1228         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1229         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1230         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1231
1232         reg = 0x000023b0;
1233         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
1234                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1235         rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1236
1237         rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1238         rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1239         rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1240
1241         reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR9);
1242         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1243         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1244
1245         /*
1246          * Clear all beacons
1247          * For the Beacon base registers we only need to clear
1248          * the first byte since that byte contains the VALID and OWNER
1249          * bits which (when set to 0) will invalidate the entire beacon.
1250          */
1251         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1252         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1253         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1254         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1255
1256         /*
1257          * We must clear the error counters.
1258          * These registers are cleared on read,
1259          * so we may pass a useless variable to store the value.
1260          */
1261         reg = rt2x00usb_register_read(rt2x00dev, STA_CSR0);
1262         reg = rt2x00usb_register_read(rt2x00dev, STA_CSR1);
1263         reg = rt2x00usb_register_read(rt2x00dev, STA_CSR2);
1264
1265         /*
1266          * Reset MAC and BBP registers.
1267          */
1268         reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR1);
1269         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1270         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1271         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1272
1273         reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR1);
1274         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1275         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1276         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1277
1278         reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR1);
1279         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1280         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1281
1282         return 0;
1283 }
1284
1285 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1286 {
1287         unsigned int i;
1288         u8 value;
1289
1290         for (i = 0; i < REGISTER_USB_BUSY_COUNT; i++) {
1291                 value = rt73usb_bbp_read(rt2x00dev, 0);
1292                 if ((value != 0xff) && (value != 0x00))
1293                         return 0;
1294                 udelay(REGISTER_BUSY_DELAY);
1295         }
1296
1297         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1298         return -EACCES;
1299 }
1300
1301 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1302 {
1303         unsigned int i;
1304         u16 eeprom;
1305         u8 reg_id;
1306         u8 value;
1307
1308         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1309                 return -EACCES;
1310
1311         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1312         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1313         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1314         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1315         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1316         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1317         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1318         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1319         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1320         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1321         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1322         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1323         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1324         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1325         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1326         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1327         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1328         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1329         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1330         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1331         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1332         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1333         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1334         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1335         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1336
1337         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1338                 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i);
1339
1340                 if (eeprom != 0xffff && eeprom != 0x0000) {
1341                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1342                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1343                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1344                 }
1345         }
1346
1347         return 0;
1348 }
1349
1350 /*
1351  * Device state switch handlers.
1352  */
1353 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1354 {
1355         /*
1356          * Initialize all registers.
1357          */
1358         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1359                      rt73usb_init_bbp(rt2x00dev)))
1360                 return -EIO;
1361
1362         return 0;
1363 }
1364
1365 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1366 {
1367         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1368
1369         /*
1370          * Disable synchronisation.
1371          */
1372         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1373
1374         rt2x00usb_disable_radio(rt2x00dev);
1375 }
1376
1377 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1378 {
1379         u32 reg, reg2;
1380         unsigned int i;
1381         char put_to_sleep;
1382
1383         put_to_sleep = (state != STATE_AWAKE);
1384
1385         reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR12);
1386         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1387         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1388         rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1389
1390         /*
1391          * Device is not guaranteed to be in the requested state yet.
1392          * We must wait until the register indicates that the
1393          * device has entered the correct state.
1394          */
1395         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1396                 reg2 = rt2x00usb_register_read(rt2x00dev, MAC_CSR12);
1397                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1398                 if (state == !put_to_sleep)
1399                         return 0;
1400                 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1401                 msleep(10);
1402         }
1403
1404         return -EBUSY;
1405 }
1406
1407 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1408                                     enum dev_state state)
1409 {
1410         int retval = 0;
1411
1412         switch (state) {
1413         case STATE_RADIO_ON:
1414                 retval = rt73usb_enable_radio(rt2x00dev);
1415                 break;
1416         case STATE_RADIO_OFF:
1417                 rt73usb_disable_radio(rt2x00dev);
1418                 break;
1419         case STATE_RADIO_IRQ_ON:
1420         case STATE_RADIO_IRQ_OFF:
1421                 /* No support, but no error either */
1422                 break;
1423         case STATE_DEEP_SLEEP:
1424         case STATE_SLEEP:
1425         case STATE_STANDBY:
1426         case STATE_AWAKE:
1427                 retval = rt73usb_set_state(rt2x00dev, state);
1428                 break;
1429         default:
1430                 retval = -ENOTSUPP;
1431                 break;
1432         }
1433
1434         if (unlikely(retval))
1435                 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1436                            state, retval);
1437
1438         return retval;
1439 }
1440
1441 /*
1442  * TX descriptor initialization
1443  */
1444 static void rt73usb_write_tx_desc(struct queue_entry *entry,
1445                                   struct txentry_desc *txdesc)
1446 {
1447         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1448         __le32 *txd = (__le32 *) entry->skb->data;
1449         u32 word;
1450
1451         /*
1452          * Start writing the descriptor words.
1453          */
1454         word = rt2x00_desc_read(txd, 0);
1455         rt2x00_set_field32(&word, TXD_W0_BURST,
1456                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1457         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1458         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1459                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1460         rt2x00_set_field32(&word, TXD_W0_ACK,
1461                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1462         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1463                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1464         rt2x00_set_field32(&word, TXD_W0_OFDM,
1465                            (txdesc->rate_mode == RATE_MODE_OFDM));
1466         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1467         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1468                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1469         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1470                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1471         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1472                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1473         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1474         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1475         rt2x00_set_field32(&word, TXD_W0_BURST2,
1476                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1477         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1478         rt2x00_desc_write(txd, 0, word);
1479
1480         word = rt2x00_desc_read(txd, 1);
1481         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1482         rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1483         rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1484         rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1485         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1486         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1487                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1488         rt2x00_desc_write(txd, 1, word);
1489
1490         word = rt2x00_desc_read(txd, 2);
1491         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1492         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1493         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1494                            txdesc->u.plcp.length_low);
1495         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1496                            txdesc->u.plcp.length_high);
1497         rt2x00_desc_write(txd, 2, word);
1498
1499         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1500                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1501                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1502         }
1503
1504         word = rt2x00_desc_read(txd, 5);
1505         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1506                            TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1507         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1508         rt2x00_desc_write(txd, 5, word);
1509
1510         /*
1511          * Register descriptor details in skb frame descriptor.
1512          */
1513         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1514         skbdesc->desc = txd;
1515         skbdesc->desc_len = TXD_DESC_SIZE;
1516 }
1517
1518 /*
1519  * TX data initialization
1520  */
1521 static void rt73usb_write_beacon(struct queue_entry *entry,
1522                                  struct txentry_desc *txdesc)
1523 {
1524         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1525         unsigned int beacon_base;
1526         unsigned int padding_len;
1527         u32 orig_reg, reg;
1528
1529         /*
1530          * Disable beaconing while we are reloading the beacon data,
1531          * otherwise we might be sending out invalid data.
1532          */
1533         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1534         orig_reg = reg;
1535         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1536         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1537
1538         /*
1539          * Add space for the descriptor in front of the skb.
1540          */
1541         skb_push(entry->skb, TXD_DESC_SIZE);
1542         memset(entry->skb->data, 0, TXD_DESC_SIZE);
1543
1544         /*
1545          * Write the TX descriptor for the beacon.
1546          */
1547         rt73usb_write_tx_desc(entry, txdesc);
1548
1549         /*
1550          * Dump beacon to userspace through debugfs.
1551          */
1552         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1553
1554         /*
1555          * Write entire beacon with descriptor and padding to register.
1556          */
1557         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1558         if (padding_len && skb_pad(entry->skb, padding_len)) {
1559                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1560                 /* skb freed by skb_pad() on failure */
1561                 entry->skb = NULL;
1562                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1563                 return;
1564         }
1565
1566         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1567         rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1568                                       entry->skb->len + padding_len);
1569
1570         /*
1571          * Enable beaconing again.
1572          *
1573          * For Wi-Fi faily generated beacons between participating stations.
1574          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1575          */
1576         rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1577
1578         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1579         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1580
1581         /*
1582          * Clean up the beacon skb.
1583          */
1584         dev_kfree_skb(entry->skb);
1585         entry->skb = NULL;
1586 }
1587
1588 static void rt73usb_clear_beacon(struct queue_entry *entry)
1589 {
1590         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1591         unsigned int beacon_base;
1592         u32 orig_reg, reg;
1593
1594         /*
1595          * Disable beaconing while we are reloading the beacon data,
1596          * otherwise we might be sending out invalid data.
1597          */
1598         orig_reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9);
1599         reg = orig_reg;
1600         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1601         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1602
1603         /*
1604          * Clear beacon.
1605          */
1606         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1607         rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
1608
1609         /*
1610          * Restore beaconing state.
1611          */
1612         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1613 }
1614
1615 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1616 {
1617         int length;
1618
1619         /*
1620          * The length _must_ be a multiple of 4,
1621          * but it must _not_ be a multiple of the USB packet size.
1622          */
1623         length = roundup(entry->skb->len, 4);
1624         length += (4 * !(length % entry->queue->usb_maxpacket));
1625
1626         return length;
1627 }
1628
1629 /*
1630  * RX control handlers
1631  */
1632 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1633 {
1634         u8 offset = rt2x00dev->lna_gain;
1635         u8 lna;
1636
1637         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1638         switch (lna) {
1639         case 3:
1640                 offset += 90;
1641                 break;
1642         case 2:
1643                 offset += 74;
1644                 break;
1645         case 1:
1646                 offset += 64;
1647                 break;
1648         default:
1649                 return 0;
1650         }
1651
1652         if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
1653                 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
1654                         if (lna == 3 || lna == 2)
1655                                 offset += 10;
1656                 } else {
1657                         if (lna == 3)
1658                                 offset += 6;
1659                         else if (lna == 2)
1660                                 offset += 8;
1661                 }
1662         }
1663
1664         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1665 }
1666
1667 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1668                                 struct rxdone_entry_desc *rxdesc)
1669 {
1670         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1671         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1672         __le32 *rxd = (__le32 *)entry->skb->data;
1673         u32 word0;
1674         u32 word1;
1675
1676         /*
1677          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1678          * frame data in rt2x00usb.
1679          */
1680         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1681         rxd = (__le32 *)skbdesc->desc;
1682
1683         /*
1684          * It is now safe to read the descriptor on all architectures.
1685          */
1686         word0 = rt2x00_desc_read(rxd, 0);
1687         word1 = rt2x00_desc_read(rxd, 1);
1688
1689         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1690                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1691
1692         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1693         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1694
1695         if (rxdesc->cipher != CIPHER_NONE) {
1696                 rxdesc->iv[0] = _rt2x00_desc_read(rxd, 2);
1697                 rxdesc->iv[1] = _rt2x00_desc_read(rxd, 3);
1698                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1699
1700                 rxdesc->icv = _rt2x00_desc_read(rxd, 4);
1701                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1702
1703                 /*
1704                  * Hardware has stripped IV/EIV data from 802.11 frame during
1705                  * decryption. It has provided the data separately but rt2x00lib
1706                  * should decide if it should be reinserted.
1707                  */
1708                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1709
1710                 /*
1711                  * The hardware has already checked the Michael Mic and has
1712                  * stripped it from the frame. Signal this to mac80211.
1713                  */
1714                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1715
1716                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1717                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1718                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1719                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1720         }
1721
1722         /*
1723          * Obtain the status about this packet.
1724          * When frame was received with an OFDM bitrate,
1725          * the signal is the PLCP value. If it was received with
1726          * a CCK bitrate the signal is the rate in 100kbit/s.
1727          */
1728         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1729         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1730         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1731
1732         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1733                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1734         else
1735                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1736         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1737                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1738
1739         /*
1740          * Set skb pointers, and update frame information.
1741          */
1742         skb_pull(entry->skb, entry->queue->desc_size);
1743         skb_trim(entry->skb, rxdesc->size);
1744 }
1745
1746 /*
1747  * Device probe functions.
1748  */
1749 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1750 {
1751         u16 word;
1752         u8 *mac;
1753         s8 value;
1754
1755         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1756
1757         /*
1758          * Start validation of the data that has been read.
1759          */
1760         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1761         rt2x00lib_set_mac_address(rt2x00dev, mac);
1762
1763         word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1764         if (word == 0xffff) {
1765                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1766                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1767                                    ANTENNA_B);
1768                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1769                                    ANTENNA_B);
1770                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1771                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1772                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1773                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1774                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1775                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
1776         }
1777
1778         word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
1779         if (word == 0xffff) {
1780                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1781                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1782                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
1783         }
1784
1785         word = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED);
1786         if (word == 0xffff) {
1787                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1788                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1789                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1790                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1791                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1792                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1793                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1794                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1795                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1796                                    LED_MODE_DEFAULT);
1797                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1798                 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word);
1799         }
1800
1801         word = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ);
1802         if (word == 0xffff) {
1803                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1804                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1805                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1806                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
1807         }
1808
1809         word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG);
1810         if (word == 0xffff) {
1811                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1812                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1813                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1814                 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1815         } else {
1816                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1817                 if (value < -10 || value > 10)
1818                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1819                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1820                 if (value < -10 || value > 10)
1821                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1822                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1823         }
1824
1825         word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A);
1826         if (word == 0xffff) {
1827                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1828                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1829                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1830                 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1831         } else {
1832                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1833                 if (value < -10 || value > 10)
1834                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1835                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1836                 if (value < -10 || value > 10)
1837                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1838                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1839         }
1840
1841         return 0;
1842 }
1843
1844 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1845 {
1846         u32 reg;
1847         u16 value;
1848         u16 eeprom;
1849
1850         /*
1851          * Read EEPROM word for configuration.
1852          */
1853         eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA);
1854
1855         /*
1856          * Identify RF chipset.
1857          */
1858         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1859         reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR0);
1860         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1861                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1862
1863         if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
1864                 rt2x00_err(rt2x00dev, "Invalid RT chipset detected\n");
1865                 return -ENODEV;
1866         }
1867
1868         if (!rt2x00_rf(rt2x00dev, RF5226) &&
1869             !rt2x00_rf(rt2x00dev, RF2528) &&
1870             !rt2x00_rf(rt2x00dev, RF5225) &&
1871             !rt2x00_rf(rt2x00dev, RF2527)) {
1872                 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1873                 return -ENODEV;
1874         }
1875
1876         /*
1877          * Identify default antenna configuration.
1878          */
1879         rt2x00dev->default_ant.tx =
1880             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1881         rt2x00dev->default_ant.rx =
1882             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1883
1884         /*
1885          * Read the Frame type.
1886          */
1887         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1888                 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
1889
1890         /*
1891          * Detect if this device has an hardware controlled radio.
1892          */
1893         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1894                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1895
1896         /*
1897          * Read frequency offset.
1898          */
1899         eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ);
1900         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1901
1902         /*
1903          * Read external LNA informations.
1904          */
1905         eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC);
1906
1907         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1908                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
1909                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
1910         }
1911
1912         /*
1913          * Store led settings, for correct led behaviour.
1914          */
1915 #ifdef CONFIG_RT2X00_LIB_LEDS
1916         eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED);
1917
1918         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1919         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1920         if (value == LED_MODE_SIGNAL_STRENGTH)
1921                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1922                                  LED_TYPE_QUALITY);
1923
1924         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1925         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1926                            rt2x00_get_field16(eeprom,
1927                                               EEPROM_LED_POLARITY_GPIO_0));
1928         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1929                            rt2x00_get_field16(eeprom,
1930                                               EEPROM_LED_POLARITY_GPIO_1));
1931         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1932                            rt2x00_get_field16(eeprom,
1933                                               EEPROM_LED_POLARITY_GPIO_2));
1934         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1935                            rt2x00_get_field16(eeprom,
1936                                               EEPROM_LED_POLARITY_GPIO_3));
1937         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1938                            rt2x00_get_field16(eeprom,
1939                                               EEPROM_LED_POLARITY_GPIO_4));
1940         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1941                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1942         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1943                            rt2x00_get_field16(eeprom,
1944                                               EEPROM_LED_POLARITY_RDY_G));
1945         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1946                            rt2x00_get_field16(eeprom,
1947                                               EEPROM_LED_POLARITY_RDY_A));
1948 #endif /* CONFIG_RT2X00_LIB_LEDS */
1949
1950         return 0;
1951 }
1952
1953 /*
1954  * RF value list for RF2528
1955  * Supports: 2.4 GHz
1956  */
1957 static const struct rf_channel rf_vals_bg_2528[] = {
1958         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1959         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1960         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1961         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1962         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1963         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1964         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1965         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1966         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1967         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1968         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1969         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1970         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1971         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1972 };
1973
1974 /*
1975  * RF value list for RF5226
1976  * Supports: 2.4 GHz & 5.2 GHz
1977  */
1978 static const struct rf_channel rf_vals_5226[] = {
1979         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1980         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1981         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1982         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1983         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1984         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1985         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1986         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1987         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1988         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1989         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1990         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1991         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1992         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1993
1994         /* 802.11 UNI / HyperLan 2 */
1995         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1996         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1997         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1998         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1999         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2000         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2001         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2002         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2003
2004         /* 802.11 HyperLan 2 */
2005         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2006         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2007         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2008         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2009         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2010         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2011         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2012         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2013         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2014         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2015
2016         /* 802.11 UNII */
2017         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2018         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2019         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2020         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2021         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2022         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2023
2024         /* MMAC(Japan)J52 ch 34,38,42,46 */
2025         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2026         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2027         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2028         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2029 };
2030
2031 /*
2032  * RF value list for RF5225 & RF2527
2033  * Supports: 2.4 GHz & 5.2 GHz
2034  */
2035 static const struct rf_channel rf_vals_5225_2527[] = {
2036         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2037         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2038         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2039         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2040         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2041         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2042         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2043         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2044         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2045         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2046         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2047         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2048         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2049         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2050
2051         /* 802.11 UNI / HyperLan 2 */
2052         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2053         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2054         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2055         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2056         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2057         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2058         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2059         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2060
2061         /* 802.11 HyperLan 2 */
2062         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2063         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2064         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2065         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2066         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2067         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2068         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2069         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2070         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2071         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2072
2073         /* 802.11 UNII */
2074         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2075         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2076         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2077         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2078         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2079         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2080
2081         /* MMAC(Japan)J52 ch 34,38,42,46 */
2082         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2083         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2084         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2085         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2086 };
2087
2088
2089 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2090 {
2091         struct hw_mode_spec *spec = &rt2x00dev->spec;
2092         struct channel_info *info;
2093         char *tx_power;
2094         unsigned int i;
2095
2096         /*
2097          * Initialize all hw fields.
2098          *
2099          * Don't set IEEE80211_HOST_BROADCAST_PS_BUFFERING unless we are
2100          * capable of sending the buffered frames out after the DTIM
2101          * transmission using rt2x00lib_beacondone. This will send out
2102          * multicast and broadcast traffic immediately instead of buffering it
2103          * infinitly and thus dropping it after some time.
2104          */
2105         ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
2106         ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
2107         ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
2108
2109         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2110         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2111                                 rt2x00_eeprom_addr(rt2x00dev,
2112                                                    EEPROM_MAC_ADDR_0));
2113
2114         /*
2115          * Initialize hw_mode information.
2116          */
2117         spec->supported_bands = SUPPORT_BAND_2GHZ;
2118         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2119
2120         if (rt2x00_rf(rt2x00dev, RF2528)) {
2121                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2122                 spec->channels = rf_vals_bg_2528;
2123         } else if (rt2x00_rf(rt2x00dev, RF5226)) {
2124                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2125                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2126                 spec->channels = rf_vals_5226;
2127         } else if (rt2x00_rf(rt2x00dev, RF2527)) {
2128                 spec->num_channels = 14;
2129                 spec->channels = rf_vals_5225_2527;
2130         } else if (rt2x00_rf(rt2x00dev, RF5225)) {
2131                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2132                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2133                 spec->channels = rf_vals_5225_2527;
2134         }
2135
2136         /*
2137          * Create channel information array
2138          */
2139         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2140         if (!info)
2141                 return -ENOMEM;
2142
2143         spec->channels_info = info;
2144
2145         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2146         for (i = 0; i < 14; i++) {
2147                 info[i].max_power = MAX_TXPOWER;
2148                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2149         }
2150
2151         if (spec->num_channels > 14) {
2152                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2153                 for (i = 14; i < spec->num_channels; i++) {
2154                         info[i].max_power = MAX_TXPOWER;
2155                         info[i].default_power1 =
2156                                         TXPOWER_FROM_DEV(tx_power[i - 14]);
2157                 }
2158         }
2159
2160         return 0;
2161 }
2162
2163 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2164 {
2165         int retval;
2166         u32 reg;
2167
2168         /*
2169          * Allocate eeprom data.
2170          */
2171         retval = rt73usb_validate_eeprom(rt2x00dev);
2172         if (retval)
2173                 return retval;
2174
2175         retval = rt73usb_init_eeprom(rt2x00dev);
2176         if (retval)
2177                 return retval;
2178
2179         /*
2180          * Enable rfkill polling by setting GPIO direction of the
2181          * rfkill switch GPIO pin correctly.
2182          */
2183         reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR13);
2184         rt2x00_set_field32(&reg, MAC_CSR13_DIR7, 0);
2185         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, reg);
2186
2187         /*
2188          * Initialize hw specifications.
2189          */
2190         retval = rt73usb_probe_hw_mode(rt2x00dev);
2191         if (retval)
2192                 return retval;
2193
2194         /*
2195          * This device has multiple filters for control frames,
2196          * but has no a separate filter for PS Poll frames.
2197          */
2198         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2199
2200         /*
2201          * This device requires firmware.
2202          */
2203         __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2204         if (!modparam_nohwcrypt)
2205                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2206         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2207         __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
2208
2209         /*
2210          * Set the rssi offset.
2211          */
2212         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2213
2214         return 0;
2215 }
2216
2217 /*
2218  * IEEE80211 stack callback functions.
2219  */
2220 static int rt73usb_conf_tx(struct ieee80211_hw *hw,
2221                            struct ieee80211_vif *vif,
2222                            unsigned int link_id, u16 queue_idx,
2223                            const struct ieee80211_tx_queue_params *params)
2224 {
2225         struct rt2x00_dev *rt2x00dev = hw->priv;
2226         struct data_queue *queue;
2227         struct rt2x00_field32 field;
2228         int retval;
2229         u32 reg;
2230         u32 offset;
2231
2232         /*
2233          * First pass the configuration through rt2x00lib, that will
2234          * update the queue settings and validate the input. After that
2235          * we are free to update the registers based on the value
2236          * in the queue parameter.
2237          */
2238         retval = rt2x00mac_conf_tx(hw, vif, link_id, queue_idx, params);
2239         if (retval)
2240                 return retval;
2241
2242         /*
2243          * We only need to perform additional register initialization
2244          * for WMM queues/
2245          */
2246         if (queue_idx >= 4)
2247                 return 0;
2248
2249         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2250
2251         /* Update WMM TXOP register */
2252         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2253         field.bit_offset = (queue_idx & 1) * 16;
2254         field.bit_mask = 0xffff << field.bit_offset;
2255
2256         reg = rt2x00usb_register_read(rt2x00dev, offset);
2257         rt2x00_set_field32(&reg, field, queue->txop);
2258         rt2x00usb_register_write(rt2x00dev, offset, reg);
2259
2260         /* Update WMM registers */
2261         field.bit_offset = queue_idx * 4;
2262         field.bit_mask = 0xf << field.bit_offset;
2263
2264         reg = rt2x00usb_register_read(rt2x00dev, AIFSN_CSR);
2265         rt2x00_set_field32(&reg, field, queue->aifs);
2266         rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2267
2268         reg = rt2x00usb_register_read(rt2x00dev, CWMIN_CSR);
2269         rt2x00_set_field32(&reg, field, queue->cw_min);
2270         rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2271
2272         reg = rt2x00usb_register_read(rt2x00dev, CWMAX_CSR);
2273         rt2x00_set_field32(&reg, field, queue->cw_max);
2274         rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2275
2276         return 0;
2277 }
2278
2279 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2280 {
2281         struct rt2x00_dev *rt2x00dev = hw->priv;
2282         u64 tsf;
2283         u32 reg;
2284
2285         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR13);
2286         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2287         reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR12);
2288         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2289
2290         return tsf;
2291 }
2292
2293 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2294         .tx                     = rt2x00mac_tx,
2295         .start                  = rt2x00mac_start,
2296         .stop                   = rt2x00mac_stop,
2297         .add_interface          = rt2x00mac_add_interface,
2298         .remove_interface       = rt2x00mac_remove_interface,
2299         .config                 = rt2x00mac_config,
2300         .configure_filter       = rt2x00mac_configure_filter,
2301         .set_tim                = rt2x00mac_set_tim,
2302         .set_key                = rt2x00mac_set_key,
2303         .sw_scan_start          = rt2x00mac_sw_scan_start,
2304         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2305         .get_stats              = rt2x00mac_get_stats,
2306         .bss_info_changed       = rt2x00mac_bss_info_changed,
2307         .conf_tx                = rt73usb_conf_tx,
2308         .get_tsf                = rt73usb_get_tsf,
2309         .rfkill_poll            = rt2x00mac_rfkill_poll,
2310         .flush                  = rt2x00mac_flush,
2311         .set_antenna            = rt2x00mac_set_antenna,
2312         .get_antenna            = rt2x00mac_get_antenna,
2313         .get_ringparam          = rt2x00mac_get_ringparam,
2314         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
2315 };
2316
2317 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2318         .probe_hw               = rt73usb_probe_hw,
2319         .get_firmware_name      = rt73usb_get_firmware_name,
2320         .check_firmware         = rt73usb_check_firmware,
2321         .load_firmware          = rt73usb_load_firmware,
2322         .initialize             = rt2x00usb_initialize,
2323         .uninitialize           = rt2x00usb_uninitialize,
2324         .clear_entry            = rt2x00usb_clear_entry,
2325         .set_device_state       = rt73usb_set_device_state,
2326         .rfkill_poll            = rt73usb_rfkill_poll,
2327         .link_stats             = rt73usb_link_stats,
2328         .reset_tuner            = rt73usb_reset_tuner,
2329         .link_tuner             = rt73usb_link_tuner,
2330         .watchdog               = rt2x00usb_watchdog,
2331         .start_queue            = rt73usb_start_queue,
2332         .kick_queue             = rt2x00usb_kick_queue,
2333         .stop_queue             = rt73usb_stop_queue,
2334         .flush_queue            = rt2x00usb_flush_queue,
2335         .write_tx_desc          = rt73usb_write_tx_desc,
2336         .write_beacon           = rt73usb_write_beacon,
2337         .clear_beacon           = rt73usb_clear_beacon,
2338         .get_tx_data_len        = rt73usb_get_tx_data_len,
2339         .fill_rxdone            = rt73usb_fill_rxdone,
2340         .config_shared_key      = rt73usb_config_shared_key,
2341         .config_pairwise_key    = rt73usb_config_pairwise_key,
2342         .config_filter          = rt73usb_config_filter,
2343         .config_intf            = rt73usb_config_intf,
2344         .config_erp             = rt73usb_config_erp,
2345         .config_ant             = rt73usb_config_ant,
2346         .config                 = rt73usb_config,
2347 };
2348
2349 static void rt73usb_queue_init(struct data_queue *queue)
2350 {
2351         switch (queue->qid) {
2352         case QID_RX:
2353                 queue->limit = 32;
2354                 queue->data_size = DATA_FRAME_SIZE;
2355                 queue->desc_size = RXD_DESC_SIZE;
2356                 queue->priv_size = sizeof(struct queue_entry_priv_usb);
2357                 break;
2358
2359         case QID_AC_VO:
2360         case QID_AC_VI:
2361         case QID_AC_BE:
2362         case QID_AC_BK:
2363                 queue->limit = 32;
2364                 queue->data_size = DATA_FRAME_SIZE;
2365                 queue->desc_size = TXD_DESC_SIZE;
2366                 queue->priv_size = sizeof(struct queue_entry_priv_usb);
2367                 break;
2368
2369         case QID_BEACON:
2370                 queue->limit = 4;
2371                 queue->data_size = MGMT_FRAME_SIZE;
2372                 queue->desc_size = TXINFO_SIZE;
2373                 queue->priv_size = sizeof(struct queue_entry_priv_usb);
2374                 break;
2375
2376         case QID_ATIM:
2377         default:
2378                 BUG();
2379                 break;
2380         }
2381 }
2382
2383 static const struct rt2x00_ops rt73usb_ops = {
2384         .name                   = KBUILD_MODNAME,
2385         .max_ap_intf            = 4,
2386         .eeprom_size            = EEPROM_SIZE,
2387         .rf_size                = RF_SIZE,
2388         .tx_queues              = NUM_TX_QUEUES,
2389         .queue_init             = rt73usb_queue_init,
2390         .lib                    = &rt73usb_rt2x00_ops,
2391         .hw                     = &rt73usb_mac80211_ops,
2392 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2393         .debugfs                = &rt73usb_rt2x00debug,
2394 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2395 };
2396
2397 /*
2398  * rt73usb module information.
2399  */
2400 static const struct usb_device_id rt73usb_device_table[] = {
2401         /* AboCom */
2402         { USB_DEVICE(0x07b8, 0xb21b) },
2403         { USB_DEVICE(0x07b8, 0xb21c) },
2404         { USB_DEVICE(0x07b8, 0xb21d) },
2405         { USB_DEVICE(0x07b8, 0xb21e) },
2406         { USB_DEVICE(0x07b8, 0xb21f) },
2407         /* AL */
2408         { USB_DEVICE(0x14b2, 0x3c10) },
2409         /* Amigo */
2410         { USB_DEVICE(0x148f, 0x9021) },
2411         { USB_DEVICE(0x0eb0, 0x9021) },
2412         /* AMIT  */
2413         { USB_DEVICE(0x18c5, 0x0002) },
2414         /* Askey */
2415         { USB_DEVICE(0x1690, 0x0722) },
2416         /* ASUS */
2417         { USB_DEVICE(0x0b05, 0x1723) },
2418         { USB_DEVICE(0x0b05, 0x1724) },
2419         /* Belkin */
2420         { USB_DEVICE(0x050d, 0x7050) }, /* FCC ID: K7SF5D7050B ver. 3.x */
2421         { USB_DEVICE(0x050d, 0x705a) },
2422         { USB_DEVICE(0x050d, 0x905b) },
2423         { USB_DEVICE(0x050d, 0x905c) },
2424         /* Billionton */
2425         { USB_DEVICE(0x1631, 0xc019) },
2426         { USB_DEVICE(0x08dd, 0x0120) },
2427         /* Buffalo */
2428         { USB_DEVICE(0x0411, 0x00d8) },
2429         { USB_DEVICE(0x0411, 0x00d9) },
2430         { USB_DEVICE(0x0411, 0x00e6) },
2431         { USB_DEVICE(0x0411, 0x00f4) },
2432         { USB_DEVICE(0x0411, 0x0116) },
2433         { USB_DEVICE(0x0411, 0x0119) },
2434         { USB_DEVICE(0x0411, 0x0137) },
2435         /* CEIVA */
2436         { USB_DEVICE(0x178d, 0x02be) },
2437         /* CNet */
2438         { USB_DEVICE(0x1371, 0x9022) },
2439         { USB_DEVICE(0x1371, 0x9032) },
2440         /* Conceptronic */
2441         { USB_DEVICE(0x14b2, 0x3c22) },
2442         /* Corega */
2443         { USB_DEVICE(0x07aa, 0x002e) },
2444         /* D-Link */
2445         { USB_DEVICE(0x07d1, 0x3c03) },
2446         { USB_DEVICE(0x07d1, 0x3c04) },
2447         { USB_DEVICE(0x07d1, 0x3c06) },
2448         { USB_DEVICE(0x07d1, 0x3c07) },
2449         /* Edimax */
2450         { USB_DEVICE(0x7392, 0x7318) },
2451         { USB_DEVICE(0x7392, 0x7618) },
2452         /* EnGenius */
2453         { USB_DEVICE(0x1740, 0x3701) },
2454         /* Gemtek */
2455         { USB_DEVICE(0x15a9, 0x0004) },
2456         /* Gigabyte */
2457         { USB_DEVICE(0x1044, 0x8008) },
2458         { USB_DEVICE(0x1044, 0x800a) },
2459         /* Huawei-3Com */
2460         { USB_DEVICE(0x1472, 0x0009) },
2461         /* Hercules */
2462         { USB_DEVICE(0x06f8, 0xe002) },
2463         { USB_DEVICE(0x06f8, 0xe010) },
2464         { USB_DEVICE(0x06f8, 0xe020) },
2465         /* Linksys */
2466         { USB_DEVICE(0x13b1, 0x0020) },
2467         { USB_DEVICE(0x13b1, 0x0023) },
2468         { USB_DEVICE(0x13b1, 0x0028) },
2469         /* MSI */
2470         { USB_DEVICE(0x0db0, 0x4600) },
2471         { USB_DEVICE(0x0db0, 0x6877) },
2472         { USB_DEVICE(0x0db0, 0x6874) },
2473         { USB_DEVICE(0x0db0, 0xa861) },
2474         { USB_DEVICE(0x0db0, 0xa874) },
2475         /* Ovislink */
2476         { USB_DEVICE(0x1b75, 0x7318) },
2477         /* Ralink */
2478         { USB_DEVICE(0x04bb, 0x093d) },
2479         { USB_DEVICE(0x148f, 0x2573) },
2480         { USB_DEVICE(0x148f, 0x2671) },
2481         { USB_DEVICE(0x0812, 0x3101) },
2482         /* Qcom */
2483         { USB_DEVICE(0x18e8, 0x6196) },
2484         { USB_DEVICE(0x18e8, 0x6229) },
2485         { USB_DEVICE(0x18e8, 0x6238) },
2486         /* Samsung */
2487         { USB_DEVICE(0x04e8, 0x4471) },
2488         /* Senao */
2489         { USB_DEVICE(0x1740, 0x7100) },
2490         /* Sitecom */
2491         { USB_DEVICE(0x0df6, 0x0024) },
2492         { USB_DEVICE(0x0df6, 0x0027) },
2493         { USB_DEVICE(0x0df6, 0x002f) },
2494         { USB_DEVICE(0x0df6, 0x90ac) },
2495         { USB_DEVICE(0x0df6, 0x9712) },
2496         /* Surecom */
2497         { USB_DEVICE(0x0769, 0x31f3) },
2498         /* Tilgin */
2499         { USB_DEVICE(0x6933, 0x5001) },
2500         /* Philips */
2501         { USB_DEVICE(0x0471, 0x200a) },
2502         /* Planex */
2503         { USB_DEVICE(0x2019, 0xab01) },
2504         { USB_DEVICE(0x2019, 0xab50) },
2505         /* WideTell */
2506         { USB_DEVICE(0x7167, 0x3840) },
2507         /* Zcom */
2508         { USB_DEVICE(0x0cde, 0x001c) },
2509         /* ZyXEL */
2510         { USB_DEVICE(0x0586, 0x3415) },
2511         { 0, }
2512 };
2513
2514 MODULE_AUTHOR(DRV_PROJECT);
2515 MODULE_VERSION(DRV_VERSION);
2516 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2517 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2518 MODULE_FIRMWARE(FIRMWARE_RT2571);
2519 MODULE_LICENSE("GPL");
2520
2521 static int rt73usb_probe(struct usb_interface *usb_intf,
2522                          const struct usb_device_id *id)
2523 {
2524         return rt2x00usb_probe(usb_intf, &rt73usb_ops);
2525 }
2526
2527 static struct usb_driver rt73usb_driver = {
2528         .name           = KBUILD_MODNAME,
2529         .id_table       = rt73usb_device_table,
2530         .probe          = rt73usb_probe,
2531         .disconnect     = rt2x00usb_disconnect,
2532         .suspend        = rt2x00usb_suspend,
2533         .resume         = rt2x00usb_resume,
2534         .reset_resume   = rt2x00usb_resume,
2535         .disable_hub_initiated_lpm = 1,
2536 };
2537
2538 module_usb_driver(rt73usb_driver);