1 // SPDX-License-Identifier: ISC
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
6 #include <linux/module.h>
8 #include <asm/unaligned.h>
12 #define EE_FIELD(_name, _value) [MT_EE_##_name] = (_value) | 1
15 mt76x2_eeprom_get_macaddr(struct mt76x02_dev *dev)
17 void *src = dev->mt76.eeprom.data + MT_EE_MAC_ADDR;
19 memcpy(dev->mphy.macaddr, src, ETH_ALEN);
24 mt76x2_has_cal_free_data(struct mt76x02_dev *dev, u8 *efuse)
26 u16 *efuse_w = (u16 *)efuse;
28 if (efuse_w[MT_EE_NIC_CONF_0] != 0)
31 if (efuse_w[MT_EE_XTAL_TRIM_1] == 0xffff)
34 if (efuse_w[MT_EE_TX_POWER_DELTA_BW40] != 0)
37 if (efuse_w[MT_EE_TX_POWER_0_START_2G] == 0xffff)
40 if (efuse_w[MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA] != 0)
43 if (efuse_w[MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE] == 0xffff)
50 mt76x2_apply_cal_free_data(struct mt76x02_dev *dev, u8 *efuse)
52 #define GROUP_5G(_id) \
53 MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
54 MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1, \
55 MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
56 MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1
58 static const u8 cal_free_bytes[] = {
60 MT_EE_TX_POWER_EXT_PA_5G + 1,
61 MT_EE_TX_POWER_0_START_2G,
62 MT_EE_TX_POWER_0_START_2G + 1,
63 MT_EE_TX_POWER_1_START_2G,
64 MT_EE_TX_POWER_1_START_2G + 1,
71 MT_EE_RF_2G_TSSI_OFF_TXPOWER,
72 MT_EE_RF_2G_RX_HIGH_GAIN + 1,
73 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN,
74 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN + 1,
75 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN,
76 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN + 1,
77 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN,
78 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN + 1,
80 struct device_node *np = dev->mt76.dev->of_node;
81 u8 *eeprom = dev->mt76.eeprom.data;
83 eeprom[MT_EE_TX_POWER_0_START_5G],
84 eeprom[MT_EE_TX_POWER_0_START_5G + 1],
85 eeprom[MT_EE_TX_POWER_1_START_5G],
86 eeprom[MT_EE_TX_POWER_1_START_5G + 1]
91 if (!np || !of_property_read_bool(np, "mediatek,eeprom-merge-otp"))
94 if (!mt76x2_has_cal_free_data(dev, efuse))
97 for (i = 0; i < ARRAY_SIZE(cal_free_bytes); i++) {
98 int offset = cal_free_bytes[i];
100 eeprom[offset] = efuse[offset];
103 if (!(efuse[MT_EE_TX_POWER_0_START_5G] |
104 efuse[MT_EE_TX_POWER_0_START_5G + 1]))
105 memcpy(eeprom + MT_EE_TX_POWER_0_START_5G, prev_grp0, 2);
106 if (!(efuse[MT_EE_TX_POWER_1_START_5G] |
107 efuse[MT_EE_TX_POWER_1_START_5G + 1]))
108 memcpy(eeprom + MT_EE_TX_POWER_1_START_5G, prev_grp0 + 2, 2);
110 val = get_unaligned_le16(efuse + MT_EE_BT_RCAL_RESULT);
112 eeprom[MT_EE_BT_RCAL_RESULT] = val & 0xff;
114 val = get_unaligned_le16(efuse + MT_EE_BT_VCDL_CALIBRATION);
116 eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8;
118 val = get_unaligned_le16(efuse + MT_EE_BT_PMUCFG);
120 eeprom[MT_EE_BT_PMUCFG] = val & 0xff;
123 static int mt76x2_check_eeprom(struct mt76x02_dev *dev)
125 u16 val = get_unaligned_le16(dev->mt76.eeprom.data);
128 val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID);
135 dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val);
141 mt76x2_eeprom_load(struct mt76x02_dev *dev)
147 ret = mt76_eeprom_init(&dev->mt76, MT7662_EEPROM_SIZE);
153 found = !mt76x2_check_eeprom(dev);
155 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, MT7662_EEPROM_SIZE,
157 dev->mt76.otp.size = MT7662_EEPROM_SIZE;
158 if (!dev->mt76.otp.data)
161 efuse = dev->mt76.otp.data;
163 if (mt76x02_get_efuse_data(dev, 0, efuse, MT7662_EEPROM_SIZE,
168 mt76x2_apply_cal_free_data(dev, efuse);
170 /* FIXME: check if efuse data is complete */
172 memcpy(dev->mt76.eeprom.data, efuse, MT7662_EEPROM_SIZE);
183 mt76x2_set_rx_gain_group(struct mt76x02_dev *dev, u8 val)
185 s8 *dest = dev->cal.rx.high_gain;
187 if (!mt76x02_field_valid(val)) {
193 dest[0] = mt76x02_sign_extend(val, 4);
194 dest[1] = mt76x02_sign_extend(val >> 4, 4);
198 mt76x2_set_rssi_offset(struct mt76x02_dev *dev, int chain, u8 val)
200 s8 *dest = dev->cal.rx.rssi_offset;
202 if (!mt76x02_field_valid(val)) {
207 dest[chain] = mt76x02_sign_extend_optional(val, 7);
210 static enum mt76x2_cal_channel_group
211 mt76x2_get_cal_channel_group(int channel)
213 if (channel >= 184 && channel <= 196)
214 return MT_CH_5G_JAPAN;
216 return MT_CH_5G_UNII_1;
218 return MT_CH_5G_UNII_2;
220 return MT_CH_5G_UNII_2E_1;
222 return MT_CH_5G_UNII_2E_2;
223 return MT_CH_5G_UNII_3;
227 mt76x2_get_5g_rx_gain(struct mt76x02_dev *dev, u8 channel)
229 enum mt76x2_cal_channel_group group;
231 group = mt76x2_get_cal_channel_group(channel);
234 return mt76x02_eeprom_get(dev,
235 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
236 case MT_CH_5G_UNII_1:
237 return mt76x02_eeprom_get(dev,
238 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
239 case MT_CH_5G_UNII_2:
240 return mt76x02_eeprom_get(dev,
241 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
242 case MT_CH_5G_UNII_2E_1:
243 return mt76x02_eeprom_get(dev,
244 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
245 case MT_CH_5G_UNII_2E_2:
246 return mt76x02_eeprom_get(dev,
247 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
249 return mt76x02_eeprom_get(dev,
250 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
254 void mt76x2_read_rx_gain(struct mt76x02_dev *dev)
256 struct ieee80211_channel *chan = dev->mphy.chandef.chan;
257 int channel = chan->hw_value;
258 s8 lna_5g[3], lna_2g;
262 if (chan->band == NL80211_BAND_2GHZ)
263 val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
265 val = mt76x2_get_5g_rx_gain(dev, channel);
267 mt76x2_set_rx_gain_group(dev, val);
269 mt76x02_get_rx_gain(dev, chan->band, &val, &lna_2g, lna_5g);
270 mt76x2_set_rssi_offset(dev, 0, val);
271 mt76x2_set_rssi_offset(dev, 1, val >> 8);
273 dev->cal.rx.mcu_gain = (lna_2g & 0xff);
274 dev->cal.rx.mcu_gain |= (lna_5g[0] & 0xff) << 8;
275 dev->cal.rx.mcu_gain |= (lna_5g[1] & 0xff) << 16;
276 dev->cal.rx.mcu_gain |= (lna_5g[2] & 0xff) << 24;
278 lna = mt76x02_get_lna_gain(dev, &lna_2g, lna_5g, chan);
279 dev->cal.rx.lna_gain = mt76x02_sign_extend(lna, 8);
281 EXPORT_SYMBOL_GPL(mt76x2_read_rx_gain);
283 void mt76x2_get_rate_power(struct mt76x02_dev *dev, struct mt76x02_rate_power *t,
284 struct ieee80211_channel *chan)
289 is_5ghz = chan->band == NL80211_BAND_5GHZ;
291 memset(t, 0, sizeof(*t));
293 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_CCK);
294 t->cck[0] = t->cck[1] = mt76x02_rate_power_val(val);
295 t->cck[2] = t->cck[3] = mt76x02_rate_power_val(val >> 8);
298 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_6M);
300 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_6M);
301 t->ofdm[0] = t->ofdm[1] = mt76x02_rate_power_val(val);
302 t->ofdm[2] = t->ofdm[3] = mt76x02_rate_power_val(val >> 8);
305 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_24M);
307 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_24M);
308 t->ofdm[4] = t->ofdm[5] = mt76x02_rate_power_val(val);
309 t->ofdm[6] = t->ofdm[7] = mt76x02_rate_power_val(val >> 8);
311 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS0);
312 t->ht[0] = t->ht[1] = mt76x02_rate_power_val(val);
313 t->ht[2] = t->ht[3] = mt76x02_rate_power_val(val >> 8);
315 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS4);
316 t->ht[4] = t->ht[5] = mt76x02_rate_power_val(val);
317 t->ht[6] = t->ht[7] = mt76x02_rate_power_val(val >> 8);
319 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS8);
320 t->ht[8] = t->ht[9] = mt76x02_rate_power_val(val);
321 t->ht[10] = t->ht[11] = mt76x02_rate_power_val(val >> 8);
323 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS12);
324 t->ht[12] = t->ht[13] = mt76x02_rate_power_val(val);
325 t->ht[14] = t->ht[15] = mt76x02_rate_power_val(val >> 8);
327 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS8);
330 t->vht[0] = t->vht[1] = mt76x02_rate_power_val(val >> 8);
332 EXPORT_SYMBOL_GPL(mt76x2_get_rate_power);
335 mt76x2_get_power_info_2g(struct mt76x02_dev *dev,
336 struct mt76x2_tx_power_info *t,
337 struct ieee80211_channel *chan,
338 int chain, int offset)
340 int channel = chan->hw_value;
347 else if (channel < 11)
352 mt76x02_eeprom_copy(dev, offset, data, sizeof(data));
354 t->chain[chain].tssi_slope = data[0];
355 t->chain[chain].tssi_offset = data[1];
356 t->chain[chain].target_power = data[2];
357 t->chain[chain].delta =
358 mt76x02_sign_extend_optional(data[delta_idx], 7);
360 val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_TSSI_OFF_TXPOWER);
361 t->target_power = val >> 8;
365 mt76x2_get_power_info_5g(struct mt76x02_dev *dev,
366 struct mt76x2_tx_power_info *t,
367 struct ieee80211_channel *chan,
368 int chain, int offset)
370 int channel = chan->hw_value;
371 enum mt76x2_cal_channel_group group;
376 group = mt76x2_get_cal_channel_group(channel);
377 offset += group * MT_TX_POWER_GROUP_SIZE_5G;
381 else if (channel >= 184)
383 else if (channel < 44)
385 else if (channel < 52)
387 else if (channel < 58)
389 else if (channel < 98)
391 else if (channel < 106)
393 else if (channel < 116)
395 else if (channel < 130)
397 else if (channel < 149)
399 else if (channel < 157)
404 mt76x02_eeprom_copy(dev, offset, data, sizeof(data));
406 t->chain[chain].tssi_slope = data[0];
407 t->chain[chain].tssi_offset = data[1];
408 t->chain[chain].target_power = data[2];
409 t->chain[chain].delta =
410 mt76x02_sign_extend_optional(data[delta_idx], 7);
412 val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN);
413 t->target_power = val & 0xff;
416 void mt76x2_get_power_info(struct mt76x02_dev *dev,
417 struct mt76x2_tx_power_info *t,
418 struct ieee80211_channel *chan)
422 memset(t, 0, sizeof(*t));
424 bw40 = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
425 bw80 = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80);
427 if (chan->band == NL80211_BAND_5GHZ) {
429 mt76x2_get_power_info_5g(dev, t, chan, 0,
430 MT_EE_TX_POWER_0_START_5G);
431 mt76x2_get_power_info_5g(dev, t, chan, 1,
432 MT_EE_TX_POWER_1_START_5G);
434 mt76x2_get_power_info_2g(dev, t, chan, 0,
435 MT_EE_TX_POWER_0_START_2G);
436 mt76x2_get_power_info_2g(dev, t, chan, 1,
437 MT_EE_TX_POWER_1_START_2G);
440 if (mt76x2_tssi_enabled(dev) ||
441 !mt76x02_field_valid(t->target_power))
442 t->target_power = t->chain[0].target_power;
444 t->delta_bw40 = mt76x02_rate_power_val(bw40);
445 t->delta_bw80 = mt76x02_rate_power_val(bw80);
447 EXPORT_SYMBOL_GPL(mt76x2_get_power_info);
449 int mt76x2_get_temp_comp(struct mt76x02_dev *dev, struct mt76x2_temp_comp *t)
451 enum nl80211_band band = dev->mphy.chandef.chan->band;
455 memset(t, 0, sizeof(*t));
457 if (!mt76x2_temp_tx_alc_enabled(dev))
460 if (!mt76x02_ext_pa_enabled(dev, band))
463 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G) >> 8;
464 t->temp_25_ref = val & 0x7f;
465 if (band == NL80211_BAND_5GHZ) {
466 slope = mt76x02_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_5G);
467 bounds = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
469 slope = mt76x02_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_2G);
470 bounds = mt76x02_eeprom_get(dev,
471 MT_EE_TX_POWER_DELTA_BW80) >> 8;
474 t->high_slope = slope & 0xff;
475 t->low_slope = slope >> 8;
476 t->lower_bound = 0 - (bounds & 0xf);
477 t->upper_bound = (bounds >> 4) & 0xf;
481 EXPORT_SYMBOL_GPL(mt76x2_get_temp_comp);
483 int mt76x2_eeprom_init(struct mt76x02_dev *dev)
487 ret = mt76x2_eeprom_load(dev);
491 mt76x02_eeprom_parse_hw_cap(dev);
492 mt76x2_eeprom_get_macaddr(dev);
493 mt76_eeprom_override(&dev->mphy);
494 dev->mphy.macaddr[0] &= ~BIT(1);
498 EXPORT_SYMBOL_GPL(mt76x2_eeprom_init);
500 MODULE_LICENSE("Dual BSD/GPL");