1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2019 MediaTek Inc. */
7 struct mt7615_mcu_txd {
15 u8 set_query; /* FW don't care */
24 } __packed __aligned(4);
28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
29 MCU_EVENT_FW_START = 0x01,
30 MCU_EVENT_GENERIC = 0x01,
31 MCU_EVENT_ACCESS_REG = 0x02,
32 MCU_EVENT_MT_PATCH_SEM = 0x04,
33 MCU_EVENT_CH_PRIVILEGE = 0x18,
35 MCU_EVENT_RESTART_DL = 0xef,
40 MCU_EXT_EVENT_PS_SYNC = 0x5,
41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
44 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
48 struct mt7615_mcu_rxd {
63 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
64 #define MCU_PKT_ID 0xa0
81 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
82 MCU_CMD_FW_START_REQ = 0x02,
83 MCU_CMD_INIT_ACCESS_REG = 0x3,
84 MCU_CMD_PATCH_START_REQ = 0x05,
85 MCU_CMD_PATCH_FINISH_REQ = 0x07,
86 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
87 MCU_CMD_EXT_CID = 0xED,
88 MCU_CMD_FW_SCATTER = 0xEE,
89 MCU_CMD_RESTART_DL_REQ = 0xEF,
93 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
94 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
95 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
96 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
97 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
98 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
99 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
100 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
101 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
102 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
103 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
104 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
105 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
106 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
107 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
111 PATCH_SEM_RELEASE = 0x0,
116 PATCH_NOT_DL_SEM_FAIL = 0x0,
118 PATCH_NOT_DL_SEM_SUCCESS = 0x2,
119 PATCH_REL_SEM_SUCCESS = 0x3
123 FW_STATE_INITIAL = 0,
124 FW_STATE_FW_DOWNLOAD = 1,
125 FW_STATE_NORMAL_OPERATION = 2,
126 FW_STATE_NORMAL_TRX = 3,
130 #define STA_TYPE_STA BIT(0)
131 #define STA_TYPE_AP BIT(1)
132 #define STA_TYPE_ADHOC BIT(2)
133 #define STA_TYPE_WDS BIT(4)
134 #define STA_TYPE_BC BIT(5)
136 #define NETWORK_INFRA BIT(16)
137 #define NETWORK_P2P BIT(17)
138 #define NETWORK_IBSS BIT(18)
139 #define NETWORK_WDS BIT(21)
141 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
142 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
143 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
144 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
145 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
146 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
147 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
149 #define CONN_STATE_DISCONNECT 0
150 #define CONN_STATE_CONNECT 1
151 #define CONN_STATE_PORT_SECURE 2
158 struct bss_info_omac {
169 struct bss_info_basic {
180 u8 cipher; /* not used */
181 u8 phymode; /* not used */
185 struct bss_info_rf_ch {
194 struct bss_info_ext_bss {
197 __le32 mbss_tsf_offset; /* in unit of us */
204 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
205 BSS_INFO_PM, /* sta only */
206 BSS_INFO_UAPSD, /* sta only */
207 BSS_INFO_ROAM_DETECTION, /* obsoleted */
208 BSS_INFO_LQ_RM, /* obsoleted */
210 BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */
211 BSS_INFO_SYNC_MODE, /* obsoleted */
217 WTBL_RESET_AND_SET = 1,
223 struct wtbl_req_hdr {
230 struct wtbl_generic {
233 u8 peer_addr[ETH_ALEN];
282 struct wtbl_hdr_trans {
291 struct wtbl_sec_key {
294 u8 add; /* 0: add, 1: remove */
306 MT_BA_TYPE_ORIGINATOR,
311 RST_BA_MAC_TID_MATCH,
323 /* originator only */
329 u8 peer_addr[ETH_ALEN];
380 #define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
381 sizeof(struct wtbl_generic) + \
382 sizeof(struct wtbl_rx) + \
383 sizeof(struct wtbl_ht) + \
384 sizeof(struct wtbl_vht) + \
385 sizeof(struct wtbl_tx_ps) + \
386 sizeof(struct wtbl_hdr_trans) + \
387 sizeof(struct wtbl_sec_key) + \
388 sizeof(struct wtbl_ba) + \
389 sizeof(struct wtbl_bf) + \
390 sizeof(struct wtbl_smps) + \
391 sizeof(struct wtbl_pn) + \
392 sizeof(struct wtbl_spe))
399 WTBL_PEER_PS, /* not used */
404 WTBL_RDG, /* obsoleted */
405 WTBL_PROTECT, /* not used */
406 WTBL_CLEAR, /* not used */
409 WTBL_RAW_DATA, /* debug only */
424 struct sta_rec_basic {
431 u8 peer_addr[ETH_ALEN];
432 #define EXTRA_INFO_VER BIT(0)
433 #define EXTRA_INFO_NEW BIT(1)
448 __le16 vht_rx_mcs_map;
449 __le16 vht_tx_mcs_map;
463 #define MT7615_STA_REC_UPDATE_MAX_SIZE (sizeof(struct sta_rec_basic) + \
464 sizeof(struct sta_rec_ht) + \
465 sizeof(struct sta_rec_vht))
473 STA_REC_AMSDU, /* for CR4 */
475 STA_REC_RED, /* not used */
476 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
494 CH_SWITCH_NORMAL = 0,
498 CH_SWITCH_BACKGROUND_SCAN_START = 6,
499 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
500 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
501 CH_SWITCH_SCAN_BYPASS_DPD = 9
504 static inline struct sk_buff *
505 mt7615_mcu_msg_alloc(const void *data, int len)
507 return mt76_mcu_msg_alloc(data, sizeof(struct mt7615_mcu_txd),