1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
34 * All rights reserved.
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37 * modification, are permitted provided that the following conditions
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43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
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48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
72 #include "iwl-trans.h"
75 #include "iwl-agn-hw.h"
78 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
80 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
81 ((reg & 0x0000ffff) | (2 << 28)));
82 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
85 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
87 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
88 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
89 ((reg & 0x0000ffff) | (3 << 28)));
92 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
94 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
95 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
96 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
97 ~APMG_PS_CTRL_MSK_PWR_SRC);
99 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
100 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
101 ~APMG_PS_CTRL_MSK_PWR_SRC);
105 #define PCI_CFG_RETRY_TIMEOUT 0x041
107 static void iwl_pcie_apm_config(struct iwl_trans *trans)
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
113 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
114 * Check if BIOS (or OS) enabled L1-ASPM on this device.
115 * If so (likely), disable L0S, so device moves directly L0->L1;
116 * costs negligible amount of power savings.
117 * If not (unlikely), enable L0S, so there is at least some
118 * power savings, even without L1.
120 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
121 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
122 /* L1-ASPM enabled; disable(!) L0S */
123 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
124 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
126 /* L1-ASPM disabled; enable(!) L0S */
127 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
128 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
130 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
134 * Start up NIC's basic functionality after it has been reset
135 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
136 * NOTE: This does not load uCode nor start the embedded processor
138 static int iwl_pcie_apm_init(struct iwl_trans *trans)
141 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
144 * Use "set_bit" below rather than "write", to preserve any hardware
145 * bits already set by default after reset.
148 /* Disable L0S exit timer (platform NMI Work/Around) */
149 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
150 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
151 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
154 * Disable L0s without affecting L1;
155 * don't wait for ICH L0s (ICH bug W/A)
157 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
158 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
160 /* Set FH wait threshold to maximum (HW error during stress W/A) */
161 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
164 * Enable HAP INTA (interrupt from management bus) to
165 * wake device's PCI Express link L1a -> L0s
167 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
168 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
170 iwl_pcie_apm_config(trans);
172 /* Configure analog phase-lock-loop before activating to D0A */
173 if (trans->cfg->base_params->pll_cfg_val)
174 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
175 trans->cfg->base_params->pll_cfg_val);
178 * Set "initialization complete" bit to move adapter from
179 * D0U* --> D0A* (powered-up active) state.
181 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
184 * Wait for clock stabilization; once stabilized, access to
185 * device-internal resources is supported, e.g. iwl_write_prph()
186 * and accesses to uCode SRAM.
188 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
189 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
190 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
192 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
196 if (trans->cfg->host_interrupt_operation_mode) {
198 * This is a bit of an abuse - This is needed for 7260 / 3160
199 * only check host_interrupt_operation_mode even if this is
200 * not related to host_interrupt_operation_mode.
202 * Enable the oscillator to count wake up time for L1 exit. This
203 * consumes slightly more power (100uA) - but allows to be sure
204 * that we wake up from L1 on time.
206 * This looks weird: read twice the same register, discard the
207 * value, set a bit, and yet again, read that same register
208 * just to discard the value. But that's the way the hardware
211 iwl_read_prph(trans, OSC_CLK);
212 iwl_read_prph(trans, OSC_CLK);
213 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
214 iwl_read_prph(trans, OSC_CLK);
215 iwl_read_prph(trans, OSC_CLK);
219 * Enable DMA clock and wait for it to stabilize.
221 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
222 * bits do not disable clocks. This preserves any hardware
223 * bits already set by default in "CLK_CTRL_REG" after reset.
225 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
226 iwl_write_prph(trans, APMG_CLK_EN_REG,
227 APMG_CLK_VAL_DMA_CLK_RQT);
230 /* Disable L1-Active */
231 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
232 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
234 /* Clear the interrupt in APMG if the NIC is in RFKILL */
235 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
236 APMG_RTC_INT_STT_RFKILL);
239 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
246 * Enable LP XTAL to avoid HW bug where device may consume much power if
247 * FW is not loaded after device reset. LP XTAL is disabled by default
248 * after device HW reset. Do it only if XTAL is fed by internal source.
249 * Configure device's "persistence" mode to avoid resetting XTAL again when
250 * SHRD_HW_RST occurs in S3.
252 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
256 u32 apmg_xtal_cfg_reg;
260 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
261 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
263 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
264 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
269 * Set "initialization complete" bit to move adapter from
270 * D0U* --> D0A* (powered-up active) state.
272 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
275 * Wait for clock stabilization; once stabilized, access to
276 * device-internal resources is possible.
278 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
279 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
280 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
282 if (WARN_ON(ret < 0)) {
283 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
284 /* Release XTAL ON request */
285 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
286 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
291 * Clear "disable persistence" to avoid LP XTAL resetting when
292 * SHRD_HW_RST is applied in S3.
294 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
295 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
298 * Force APMG XTAL to be active to prevent its disabling by HW
299 * caused by APMG idle state.
301 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
302 SHR_APMG_XTAL_CFG_REG);
303 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
305 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
308 * Reset entire device again - do controller reset (results in
309 * SHRD_HW_RST). Turn MAC off before proceeding.
311 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
315 /* Enable LP XTAL by indirect access through CSR */
316 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
317 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
318 SHR_APMG_GP1_WF_XTAL_LP_EN |
319 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
321 /* Clear delay line clock power up */
322 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
323 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
324 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
327 * Enable persistence mode to avoid LP XTAL resetting when
328 * SHRD_HW_RST is applied in S3.
330 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
331 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
334 * Clear "initialization complete" bit to move adapter from
335 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
337 iwl_clear_bit(trans, CSR_GP_CNTRL,
338 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
340 /* Activates XTAL resources monitor */
341 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
342 CSR_MONITOR_XTAL_RESOURCES);
344 /* Release XTAL ON request */
345 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
346 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
349 /* Release APMG XTAL */
350 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
352 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
355 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
359 /* stop device's busmaster DMA activity */
360 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
362 ret = iwl_poll_bit(trans, CSR_RESET,
363 CSR_RESET_REG_FLAG_MASTER_DISABLED,
364 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
366 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
368 IWL_DEBUG_INFO(trans, "stop master\n");
373 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
375 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
377 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
379 /* Stop device's DMA activity */
380 iwl_pcie_apm_stop_master(trans);
382 if (trans->cfg->lp_xtal_workaround) {
383 iwl_pcie_apm_lp_xtal_enable(trans);
387 /* Reset the entire device */
388 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
393 * Clear "initialization complete" bit to move adapter from
394 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
396 iwl_clear_bit(trans, CSR_GP_CNTRL,
397 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
400 static int iwl_pcie_nic_init(struct iwl_trans *trans)
402 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
405 spin_lock(&trans_pcie->irq_lock);
406 iwl_pcie_apm_init(trans);
408 spin_unlock(&trans_pcie->irq_lock);
410 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
411 iwl_pcie_set_pwr(trans, false);
413 iwl_op_mode_nic_config(trans->op_mode);
415 /* Allocate the RX queue, or reset if it is already allocated */
416 iwl_pcie_rx_init(trans);
418 /* Allocate or reset and init all Tx and Command queues */
419 if (iwl_pcie_tx_init(trans))
422 if (trans->cfg->base_params->shadow_reg_enable) {
423 /* enable shadow regs in HW */
424 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
425 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
431 #define HW_READY_TIMEOUT (50)
433 /* Note: returns poll_bit return value, which is >= 0 if success */
434 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
438 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
439 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
441 /* See if we got it */
442 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
443 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
444 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
447 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
451 /* Note: returns standard 0/-ERROR code */
452 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
457 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
459 ret = iwl_pcie_set_hw_ready(trans);
460 /* If the card is ready, exit 0 */
464 /* If HW is not ready, prepare the conditions to check again */
465 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
466 CSR_HW_IF_CONFIG_REG_PREPARE);
469 ret = iwl_pcie_set_hw_ready(trans);
473 usleep_range(200, 1000);
475 } while (t < 150000);
483 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
484 dma_addr_t phy_addr, u32 byte_cnt)
486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
489 trans_pcie->ucode_write_complete = false;
491 iwl_write_direct32(trans,
492 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
493 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
495 iwl_write_direct32(trans,
496 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
499 iwl_write_direct32(trans,
500 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
501 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
503 iwl_write_direct32(trans,
504 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
505 (iwl_get_dma_hi_addr(phy_addr)
506 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
508 iwl_write_direct32(trans,
509 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
510 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
511 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
512 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
514 iwl_write_direct32(trans,
515 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
516 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
517 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
518 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
520 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
521 trans_pcie->ucode_write_complete, 5 * HZ);
523 IWL_ERR(trans, "Failed to load firmware chunk!\n");
530 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
531 const struct fw_desc *section)
535 u32 offset, chunk_sz = section->len;
538 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
541 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
542 GFP_KERNEL | __GFP_NOWARN);
544 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
545 chunk_sz = PAGE_SIZE;
546 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
547 &p_addr, GFP_KERNEL);
552 for (offset = 0; offset < section->len; offset += chunk_sz) {
555 copy_size = min_t(u32, chunk_sz, section->len - offset);
557 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
558 ret = iwl_pcie_load_firmware_chunk(trans,
559 section->offset + offset,
563 "Could not load the [%d] uCode section\n",
569 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
573 static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
574 const struct fw_img *image,
576 int *first_ucode_section)
580 u32 last_read_idx = 0;
584 *first_ucode_section = 0;
587 (*first_ucode_section)++;
590 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
593 if (!image->sec[i].data ||
594 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
596 "Break since Data not valid or Empty section, sec = %d\n",
601 if (i == (*first_ucode_section) + 1)
602 /* set CPU to started */
603 iwl_set_bits_prph(trans,
604 CSR_UCODE_LOAD_STATUS_ADDR,
605 LMPM_CPU_HDRS_LOADING_COMPLETED
608 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
612 /* image loading complete */
613 iwl_set_bits_prph(trans,
614 CSR_UCODE_LOAD_STATUS_ADDR,
615 LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
617 *first_ucode_section = last_read_idx;
622 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
623 const struct fw_img *image,
625 int *first_ucode_section)
629 u32 last_read_idx = 0;
633 *first_ucode_section = 0;
636 (*first_ucode_section)++;
639 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
642 if (!image->sec[i].data ||
643 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
645 "Break since Data not valid or Empty section, sec = %d\n",
650 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
655 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
656 iwl_set_bits_prph(trans,
657 CSR_UCODE_LOAD_STATUS_ADDR,
658 (LMPM_CPU_UCODE_LOADING_COMPLETED |
659 LMPM_CPU_HDRS_LOADING_COMPLETED |
660 LMPM_CPU_UCODE_LOADING_STARTED) <<
663 *first_ucode_section = last_read_idx;
668 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
669 const struct fw_img *image)
672 int first_ucode_section;
675 "working with %s image\n",
676 image->is_secure ? "Secured" : "Non Secured");
678 "working with %s CPU\n",
679 image->is_dual_cpus ? "Dual" : "Single");
681 /* configure the ucode to be ready to get the secured image */
682 if (image->is_secure) {
683 /* set secure boot inspector addresses */
684 iwl_write_prph(trans,
685 LMPM_SECURE_INSPECTOR_CODE_ADDR,
686 LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
688 iwl_write_prph(trans,
689 LMPM_SECURE_INSPECTOR_DATA_ADDR,
690 LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
692 /* set CPU1 header address */
693 iwl_write_prph(trans,
694 LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
695 LMPM_SECURE_CPU1_HDR_MEM_SPACE);
697 /* load to FW the binary Secured sections of CPU1 */
698 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
699 &first_ucode_section);
704 /* load to FW the binary Non secured sections of CPU1 */
705 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
706 &first_ucode_section);
711 if (image->is_dual_cpus) {
712 /* set CPU2 header address */
713 iwl_write_prph(trans,
714 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
715 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
717 /* load to FW the binary sections of CPU2 */
718 if (image->is_secure)
719 ret = iwl_pcie_load_cpu_secured_sections(
721 &first_ucode_section);
723 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
724 &first_ucode_section);
729 /* release CPU reset */
730 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
731 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
733 iwl_write32(trans, CSR_RESET, 0);
735 if (image->is_secure) {
736 /* wait for image verification to complete */
737 ret = iwl_poll_prph_bit(trans,
738 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
739 LMPM_SECURE_BOOT_STATUS_SUCCESS,
740 LMPM_SECURE_BOOT_STATUS_SUCCESS,
741 LMPM_SECURE_TIME_OUT);
744 IWL_ERR(trans, "Time out on secure boot process\n");
752 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
753 const struct fw_img *fw, bool run_in_rfkill)
758 /* This may fail if AMT took ownership of the device */
759 if (iwl_pcie_prepare_card_hw(trans)) {
760 IWL_WARN(trans, "Exit HW not ready\n");
764 iwl_enable_rfkill_int(trans);
766 /* If platform's RF_KILL switch is NOT set to KILL */
767 hw_rfkill = iwl_is_rfkill_set(trans);
769 set_bit(STATUS_RFKILL, &trans->status);
771 clear_bit(STATUS_RFKILL, &trans->status);
772 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
773 if (hw_rfkill && !run_in_rfkill)
776 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
778 ret = iwl_pcie_nic_init(trans);
780 IWL_ERR(trans, "Unable to init nic\n");
784 /* make sure rfkill handshake bits are cleared */
785 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
786 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
787 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
789 /* clear (again), then enable host interrupts */
790 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
791 iwl_enable_interrupts(trans);
793 /* really make sure rfkill handshake bits are cleared */
794 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
795 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
797 /* Load the given image to the HW */
798 return iwl_pcie_load_given_ucode(trans, fw);
801 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
803 iwl_pcie_reset_ict(trans);
804 iwl_pcie_tx_start(trans, scd_addr);
807 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
809 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
810 bool hw_rfkill, was_hw_rfkill;
812 was_hw_rfkill = iwl_is_rfkill_set(trans);
814 /* tell the device to stop sending interrupts */
815 spin_lock(&trans_pcie->irq_lock);
816 iwl_disable_interrupts(trans);
817 spin_unlock(&trans_pcie->irq_lock);
819 /* device going down, Stop using ICT table */
820 iwl_pcie_disable_ict(trans);
823 * If a HW restart happens during firmware loading,
824 * then the firmware loading might call this function
825 * and later it might be called again due to the
826 * restart. So don't process again if the device is
829 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
830 iwl_pcie_tx_stop(trans);
831 iwl_pcie_rx_stop(trans);
833 /* Power-down device's busmaster DMA clocks */
834 iwl_write_prph(trans, APMG_CLK_DIS_REG,
835 APMG_CLK_VAL_DMA_CLK_RQT);
839 /* Make sure (redundant) we've released our request to stay awake */
840 iwl_clear_bit(trans, CSR_GP_CNTRL,
841 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
843 /* Stop the device, and put it in low power state */
844 iwl_pcie_apm_stop(trans);
846 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
847 * Clean again the interrupt here
849 spin_lock(&trans_pcie->irq_lock);
850 iwl_disable_interrupts(trans);
851 spin_unlock(&trans_pcie->irq_lock);
853 /* stop and reset the on-board processor */
854 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
856 /* clear all status bits */
857 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
858 clear_bit(STATUS_INT_ENABLED, &trans->status);
859 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
860 clear_bit(STATUS_TPOWER_PMI, &trans->status);
861 clear_bit(STATUS_RFKILL, &trans->status);
864 * Even if we stop the HW, we still want the RF kill
867 iwl_enable_rfkill_int(trans);
870 * Check again since the RF kill state may have changed while
871 * all the interrupts were disabled, in this case we couldn't
872 * receive the RF kill interrupt and update the state in the
874 * Don't call the op_mode if the rkfill state hasn't changed.
875 * This allows the op_mode to call stop_device from the rfkill
876 * notification without endless recursion. Under very rare
877 * circumstances, we might have a small recursion if the rfkill
878 * state changed exactly now while we were called from stop_device.
879 * This is very unlikely but can happen and is supported.
881 hw_rfkill = iwl_is_rfkill_set(trans);
883 set_bit(STATUS_RFKILL, &trans->status);
885 clear_bit(STATUS_RFKILL, &trans->status);
886 if (hw_rfkill != was_hw_rfkill)
887 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
890 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
892 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
893 iwl_trans_pcie_stop_device(trans);
896 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
898 iwl_disable_interrupts(trans);
901 * in testing mode, the host stays awake and the
902 * hardware won't be reset (not even partially)
907 iwl_pcie_disable_ict(trans);
909 iwl_clear_bit(trans, CSR_GP_CNTRL,
910 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
911 iwl_clear_bit(trans, CSR_GP_CNTRL,
912 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
915 * reset TX queues -- some of their registers reset during S3
916 * so if we don't reset everything here the D3 image would try
917 * to execute some invalid memory upon resume
919 iwl_trans_pcie_tx_reset(trans);
921 iwl_pcie_set_pwr(trans, true);
924 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
925 enum iwl_d3_status *status,
932 iwl_enable_interrupts(trans);
933 *status = IWL_D3_STATUS_ALIVE;
937 iwl_pcie_set_pwr(trans, false);
939 val = iwl_read32(trans, CSR_RESET);
940 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
941 *status = IWL_D3_STATUS_RESET;
946 * Also enables interrupts - none will happen as the device doesn't
947 * know we're waking it up, only when the opmode actually tells it
950 iwl_pcie_reset_ict(trans);
952 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
953 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
955 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
956 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
957 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
960 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
964 iwl_trans_pcie_tx_reset(trans);
966 ret = iwl_pcie_rx_init(trans);
968 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
972 *status = IWL_D3_STATUS_ALIVE;
976 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
981 err = iwl_pcie_prepare_card_hw(trans);
983 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
987 /* Reset the entire device */
988 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
990 usleep_range(10, 15);
992 iwl_pcie_apm_init(trans);
994 /* From now on, the op_mode will be kept updated about RF kill state */
995 iwl_enable_rfkill_int(trans);
997 hw_rfkill = iwl_is_rfkill_set(trans);
999 set_bit(STATUS_RFKILL, &trans->status);
1001 clear_bit(STATUS_RFKILL, &trans->status);
1002 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1007 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1009 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1011 /* disable interrupts - don't enable HW RF kill interrupt */
1012 spin_lock(&trans_pcie->irq_lock);
1013 iwl_disable_interrupts(trans);
1014 spin_unlock(&trans_pcie->irq_lock);
1016 iwl_pcie_apm_stop(trans);
1018 spin_lock(&trans_pcie->irq_lock);
1019 iwl_disable_interrupts(trans);
1020 spin_unlock(&trans_pcie->irq_lock);
1022 iwl_pcie_disable_ict(trans);
1025 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1027 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1030 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1032 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1035 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1037 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1040 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1042 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1043 ((reg & 0x000FFFFF) | (3 << 24)));
1044 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1047 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1050 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1051 ((addr & 0x000FFFFF) | (3 << 24)));
1052 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1055 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1061 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1062 const struct iwl_trans_config *trans_cfg)
1064 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1066 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1067 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1068 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1069 trans_pcie->n_no_reclaim_cmds = 0;
1071 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1072 if (trans_pcie->n_no_reclaim_cmds)
1073 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1074 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1076 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1077 if (trans_pcie->rx_buf_size_8k)
1078 trans_pcie->rx_page_order = get_order(8 * 1024);
1080 trans_pcie->rx_page_order = get_order(4 * 1024);
1082 trans_pcie->wd_timeout =
1083 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1085 trans_pcie->command_names = trans_cfg->command_names;
1086 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1088 /* Initialize NAPI here - it should be before registering to mac80211
1089 * in the opmode but after the HW struct is allocated.
1090 * As this function may be called again in some corner cases don't
1091 * do anything if NAPI was already initialized.
1093 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1094 init_dummy_netdev(&trans_pcie->napi_dev);
1095 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1096 &trans_pcie->napi_dev,
1097 iwl_pcie_dummy_napi_poll, 64);
1101 void iwl_trans_pcie_free(struct iwl_trans *trans)
1103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1105 synchronize_irq(trans_pcie->pci_dev->irq);
1107 iwl_pcie_tx_free(trans);
1108 iwl_pcie_rx_free(trans);
1110 free_irq(trans_pcie->pci_dev->irq, trans);
1111 iwl_pcie_free_ict(trans);
1113 pci_disable_msi(trans_pcie->pci_dev);
1114 iounmap(trans_pcie->hw_base);
1115 pci_release_regions(trans_pcie->pci_dev);
1116 pci_disable_device(trans_pcie->pci_dev);
1117 kmem_cache_destroy(trans->dev_cmd_pool);
1119 if (trans_pcie->napi.poll)
1120 netif_napi_del(&trans_pcie->napi);
1125 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1128 set_bit(STATUS_TPOWER_PMI, &trans->status);
1130 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1133 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1134 unsigned long *flags)
1137 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1139 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1141 if (trans_pcie->cmd_in_flight)
1144 /* this bit wakes up the NIC */
1145 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1146 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1149 * These bits say the device is running, and should keep running for
1150 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1151 * but they do not indicate that embedded SRAM is restored yet;
1152 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1153 * to/from host DRAM when sleeping/waking for power-saving.
1154 * Each direction takes approximately 1/4 millisecond; with this
1155 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1156 * series of register accesses are expected (e.g. reading Event Log),
1157 * to keep device from sleeping.
1159 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1160 * SRAM is okay/restored. We don't check that here because this call
1161 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1162 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1164 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1165 * and do not save/restore SRAM when power cycling.
1167 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1168 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1169 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1170 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1171 if (unlikely(ret < 0)) {
1172 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1174 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1176 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1178 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1185 * Fool sparse by faking we release the lock - sparse will
1186 * track nic_access anyway.
1188 __release(&trans_pcie->reg_lock);
1192 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1193 unsigned long *flags)
1195 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1197 lockdep_assert_held(&trans_pcie->reg_lock);
1200 * Fool sparse by faking we acquiring the lock - sparse will
1201 * track nic_access anyway.
1203 __acquire(&trans_pcie->reg_lock);
1205 if (trans_pcie->cmd_in_flight)
1208 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1209 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1211 * Above we read the CSR_GP_CNTRL register, which will flush
1212 * any previous writes, but we need the write that clears the
1213 * MAC_ACCESS_REQ bit to be performed before any other writes
1214 * scheduled on different CPUs (after we drop reg_lock).
1218 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1221 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1222 void *buf, int dwords)
1224 unsigned long flags;
1228 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1229 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1230 for (offs = 0; offs < dwords; offs++)
1231 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1232 iwl_trans_release_nic_access(trans, &flags);
1239 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1240 const void *buf, int dwords)
1242 unsigned long flags;
1244 const u32 *vals = buf;
1246 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1247 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1248 for (offs = 0; offs < dwords; offs++)
1249 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1250 vals ? vals[offs] : 0);
1251 iwl_trans_release_nic_access(trans, &flags);
1258 #define IWL_FLUSH_WAIT_MS 2000
1260 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1262 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1263 struct iwl_txq *txq;
1264 struct iwl_queue *q;
1266 unsigned long now = jiffies;
1271 /* waiting for all the tx frames complete might take a while */
1272 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1275 if (cnt == trans_pcie->cmd_queue)
1277 if (!test_bit(cnt, trans_pcie->queue_used))
1279 if (!(BIT(cnt) & txq_bm))
1282 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1283 txq = &trans_pcie->txq[cnt];
1285 wr_ptr = ACCESS_ONCE(q->write_ptr);
1287 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1288 !time_after(jiffies,
1289 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1290 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1292 if (WARN_ONCE(wr_ptr != write_ptr,
1293 "WR pointer moved while flushing %d -> %d\n",
1299 if (q->read_ptr != q->write_ptr) {
1301 "fail to flush all tx fifo queues Q %d\n", cnt);
1305 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1311 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1312 txq->q.read_ptr, txq->q.write_ptr);
1314 scd_sram_addr = trans_pcie->scd_base_addr +
1315 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1316 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1318 iwl_print_hex_error(trans, buf, sizeof(buf));
1320 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1321 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1322 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1324 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1325 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1326 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1327 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1329 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1330 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1333 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1335 tbl_dw = tbl_dw & 0x0000FFFF;
1338 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1339 cnt, active ? "" : "in", fifo, tbl_dw,
1340 iwl_read_prph(trans,
1341 SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1342 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1348 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1349 u32 mask, u32 value)
1351 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1352 unsigned long flags;
1354 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1355 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1356 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1359 static const char *get_csr_string(int cmd)
1361 #define IWL_CMD(x) case x: return #x
1363 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1364 IWL_CMD(CSR_INT_COALESCING);
1366 IWL_CMD(CSR_INT_MASK);
1367 IWL_CMD(CSR_FH_INT_STATUS);
1368 IWL_CMD(CSR_GPIO_IN);
1370 IWL_CMD(CSR_GP_CNTRL);
1371 IWL_CMD(CSR_HW_REV);
1372 IWL_CMD(CSR_EEPROM_REG);
1373 IWL_CMD(CSR_EEPROM_GP);
1374 IWL_CMD(CSR_OTP_GP_REG);
1375 IWL_CMD(CSR_GIO_REG);
1376 IWL_CMD(CSR_GP_UCODE_REG);
1377 IWL_CMD(CSR_GP_DRIVER_REG);
1378 IWL_CMD(CSR_UCODE_DRV_GP1);
1379 IWL_CMD(CSR_UCODE_DRV_GP2);
1380 IWL_CMD(CSR_LED_REG);
1381 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1382 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1383 IWL_CMD(CSR_ANA_PLL_CFG);
1384 IWL_CMD(CSR_HW_REV_WA_REG);
1385 IWL_CMD(CSR_MONITOR_STATUS_REG);
1386 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1393 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1396 static const u32 csr_tbl[] = {
1397 CSR_HW_IF_CONFIG_REG,
1415 CSR_DRAM_INT_TBL_REG,
1416 CSR_GIO_CHICKEN_BITS,
1418 CSR_MONITOR_STATUS_REG,
1420 CSR_DBG_HPET_MEM_REG
1422 IWL_ERR(trans, "CSR values:\n");
1423 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1424 "CSR_INT_PERIODIC_REG)\n");
1425 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1426 IWL_ERR(trans, " %25s: 0X%08x\n",
1427 get_csr_string(csr_tbl[i]),
1428 iwl_read32(trans, csr_tbl[i]));
1432 #ifdef CONFIG_IWLWIFI_DEBUGFS
1433 /* create and remove of files */
1434 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1435 if (!debugfs_create_file(#name, mode, parent, trans, \
1436 &iwl_dbgfs_##name##_ops)) \
1440 /* file operation */
1441 #define DEBUGFS_READ_FILE_OPS(name) \
1442 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1443 .read = iwl_dbgfs_##name##_read, \
1444 .open = simple_open, \
1445 .llseek = generic_file_llseek, \
1448 #define DEBUGFS_WRITE_FILE_OPS(name) \
1449 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1450 .write = iwl_dbgfs_##name##_write, \
1451 .open = simple_open, \
1452 .llseek = generic_file_llseek, \
1455 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1456 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1457 .write = iwl_dbgfs_##name##_write, \
1458 .read = iwl_dbgfs_##name##_read, \
1459 .open = simple_open, \
1460 .llseek = generic_file_llseek, \
1463 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1464 char __user *user_buf,
1465 size_t count, loff_t *ppos)
1467 struct iwl_trans *trans = file->private_data;
1468 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1469 struct iwl_txq *txq;
1470 struct iwl_queue *q;
1477 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1479 if (!trans_pcie->txq)
1482 buf = kzalloc(bufsz, GFP_KERNEL);
1486 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1487 txq = &trans_pcie->txq[cnt];
1489 pos += scnprintf(buf + pos, bufsz - pos,
1490 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1491 cnt, q->read_ptr, q->write_ptr,
1492 !!test_bit(cnt, trans_pcie->queue_used),
1493 !!test_bit(cnt, trans_pcie->queue_stopped));
1495 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1500 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1501 char __user *user_buf,
1502 size_t count, loff_t *ppos)
1504 struct iwl_trans *trans = file->private_data;
1505 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1506 struct iwl_rxq *rxq = &trans_pcie->rxq;
1509 const size_t bufsz = sizeof(buf);
1511 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1513 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1515 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1518 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1519 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1521 pos += scnprintf(buf + pos, bufsz - pos,
1522 "closed_rb_num: Not Allocated\n");
1524 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1527 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1528 char __user *user_buf,
1529 size_t count, loff_t *ppos)
1531 struct iwl_trans *trans = file->private_data;
1532 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1533 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1537 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1540 buf = kzalloc(bufsz, GFP_KERNEL);
1544 pos += scnprintf(buf + pos, bufsz - pos,
1545 "Interrupt Statistics Report:\n");
1547 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1549 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1551 if (isr_stats->sw || isr_stats->hw) {
1552 pos += scnprintf(buf + pos, bufsz - pos,
1553 "\tLast Restarting Code: 0x%X\n",
1554 isr_stats->err_code);
1556 #ifdef CONFIG_IWLWIFI_DEBUG
1557 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1559 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1562 pos += scnprintf(buf + pos, bufsz - pos,
1563 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1565 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1568 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1571 pos += scnprintf(buf + pos, bufsz - pos,
1572 "Rx command responses:\t\t %u\n", isr_stats->rx);
1574 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1577 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1578 isr_stats->unhandled);
1580 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1585 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1586 const char __user *user_buf,
1587 size_t count, loff_t *ppos)
1589 struct iwl_trans *trans = file->private_data;
1590 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1591 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1597 memset(buf, 0, sizeof(buf));
1598 buf_size = min(count, sizeof(buf) - 1);
1599 if (copy_from_user(buf, user_buf, buf_size))
1601 if (sscanf(buf, "%x", &reset_flag) != 1)
1603 if (reset_flag == 0)
1604 memset(isr_stats, 0, sizeof(*isr_stats));
1609 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1610 const char __user *user_buf,
1611 size_t count, loff_t *ppos)
1613 struct iwl_trans *trans = file->private_data;
1618 memset(buf, 0, sizeof(buf));
1619 buf_size = min(count, sizeof(buf) - 1);
1620 if (copy_from_user(buf, user_buf, buf_size))
1622 if (sscanf(buf, "%d", &csr) != 1)
1625 iwl_pcie_dump_csr(trans);
1630 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1631 char __user *user_buf,
1632 size_t count, loff_t *ppos)
1634 struct iwl_trans *trans = file->private_data;
1638 ret = iwl_dump_fh(trans, &buf);
1643 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1648 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1649 DEBUGFS_READ_FILE_OPS(fh_reg);
1650 DEBUGFS_READ_FILE_OPS(rx_queue);
1651 DEBUGFS_READ_FILE_OPS(tx_queue);
1652 DEBUGFS_WRITE_FILE_OPS(csr);
1655 * Create the debugfs files and directories
1658 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1661 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1662 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1663 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1664 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1665 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1669 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1673 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1678 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1680 static const struct iwl_trans_ops trans_ops_pcie = {
1681 .start_hw = iwl_trans_pcie_start_hw,
1682 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
1683 .fw_alive = iwl_trans_pcie_fw_alive,
1684 .start_fw = iwl_trans_pcie_start_fw,
1685 .stop_device = iwl_trans_pcie_stop_device,
1687 .d3_suspend = iwl_trans_pcie_d3_suspend,
1688 .d3_resume = iwl_trans_pcie_d3_resume,
1690 .send_cmd = iwl_trans_pcie_send_hcmd,
1692 .tx = iwl_trans_pcie_tx,
1693 .reclaim = iwl_trans_pcie_reclaim,
1695 .txq_disable = iwl_trans_pcie_txq_disable,
1696 .txq_enable = iwl_trans_pcie_txq_enable,
1698 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1700 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1702 .write8 = iwl_trans_pcie_write8,
1703 .write32 = iwl_trans_pcie_write32,
1704 .read32 = iwl_trans_pcie_read32,
1705 .read_prph = iwl_trans_pcie_read_prph,
1706 .write_prph = iwl_trans_pcie_write_prph,
1707 .read_mem = iwl_trans_pcie_read_mem,
1708 .write_mem = iwl_trans_pcie_write_mem,
1709 .configure = iwl_trans_pcie_configure,
1710 .set_pmi = iwl_trans_pcie_set_pmi,
1711 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1712 .release_nic_access = iwl_trans_pcie_release_nic_access,
1713 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1716 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1717 const struct pci_device_id *ent,
1718 const struct iwl_cfg *cfg)
1720 struct iwl_trans_pcie *trans_pcie;
1721 struct iwl_trans *trans;
1725 trans = kzalloc(sizeof(struct iwl_trans) +
1726 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1732 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1734 trans->ops = &trans_ops_pcie;
1736 trans_lockdep_init(trans);
1737 trans_pcie->trans = trans;
1738 spin_lock_init(&trans_pcie->irq_lock);
1739 spin_lock_init(&trans_pcie->reg_lock);
1740 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1742 err = pci_enable_device(pdev);
1746 if (!cfg->base_params->pcie_l1_allowed) {
1748 * W/A - seems to solve weird behavior. We need to remove this
1749 * if we don't want to stay in L1 all the time. This wastes a
1752 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1753 PCIE_LINK_STATE_L1 |
1754 PCIE_LINK_STATE_CLKPM);
1757 pci_set_master(pdev);
1759 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1761 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1763 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1765 err = pci_set_consistent_dma_mask(pdev,
1767 /* both attempts failed: */
1769 dev_err(&pdev->dev, "No suitable DMA available\n");
1770 goto out_pci_disable_device;
1774 err = pci_request_regions(pdev, DRV_NAME);
1776 dev_err(&pdev->dev, "pci_request_regions failed\n");
1777 goto out_pci_disable_device;
1780 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1781 if (!trans_pcie->hw_base) {
1782 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1784 goto out_pci_release_regions;
1787 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1788 * PCI Tx retries from interfering with C3 CPU state */
1789 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1791 trans->dev = &pdev->dev;
1792 trans_pcie->pci_dev = pdev;
1793 iwl_disable_interrupts(trans);
1795 err = pci_enable_msi(pdev);
1797 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1798 /* enable rfkill interrupt: hw bug w/a */
1799 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1800 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1801 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1802 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1806 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1807 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1808 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1809 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1811 /* Initialize the wait queue for commands */
1812 init_waitqueue_head(&trans_pcie->wait_command_queue);
1814 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1815 "iwl_cmd_pool:%s", dev_name(trans->dev));
1817 trans->dev_cmd_headroom = 0;
1818 trans->dev_cmd_pool =
1819 kmem_cache_create(trans->dev_cmd_pool_name,
1820 sizeof(struct iwl_device_cmd)
1821 + trans->dev_cmd_headroom,
1826 if (!trans->dev_cmd_pool) {
1828 goto out_pci_disable_msi;
1831 if (iwl_pcie_alloc_ict(trans))
1832 goto out_free_cmd_pool;
1834 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
1835 iwl_pcie_irq_handler,
1836 IRQF_SHARED, DRV_NAME, trans);
1838 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1842 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1847 iwl_pcie_free_ict(trans);
1849 kmem_cache_destroy(trans->dev_cmd_pool);
1850 out_pci_disable_msi:
1851 pci_disable_msi(pdev);
1852 out_pci_release_regions:
1853 pci_release_regions(pdev);
1854 out_pci_disable_device:
1855 pci_disable_device(pdev);
1859 return ERR_PTR(err);