drivers/net/wireless/iwlwifi/iwl-trans-pcie-tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/slab.h>
  31 #include <linux/sched.h>
  32
  33 #include "iwl-debug.h"
  34 #include "iwl-csr.h"
  35 #include "iwl-prph.h"
  36 #include "iwl-io.h"
  37 #include "iwl-agn-hw.h"
  38 #include "iwl-op-mode.h"
  39 #include "iwl-trans-pcie-int.h"
  40 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  41 #include "iwl-commands.h"
  42
  43 #define IWL_TX_CRC_SIZE 4
  44 #define IWL_TX_DELIMITER_SIZE 4
  45
  46 /**
  47  * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  48  */
  49 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
  50                                        struct iwl_tx_queue *txq,
  51                                        u16 byte_cnt)
  52 {
  53         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
  54         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  55         int write_ptr = txq->q.write_ptr;
  56         int txq_id = txq->q.id;
  57         u8 sec_ctl = 0;
  58         u8 sta_id = 0;
  59         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  60         __le16 bc_ent;
  61         struct iwl_tx_cmd *tx_cmd =
  62                 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
  63
  64         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
  65
  66         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
  67
  68         sta_id = tx_cmd->sta_id;
  69         sec_ctl = tx_cmd->sec_ctl;
  70
  71         switch (sec_ctl & TX_CMD_SEC_MSK) {
  72         case TX_CMD_SEC_CCM:
  73                 len += CCMP_MIC_LEN;
  74                 break;
  75         case TX_CMD_SEC_TKIP:
  76                 len += TKIP_ICV_LEN;
  77                 break;
  78         case TX_CMD_SEC_WEP:
  79                 len += WEP_IV_LEN + WEP_ICV_LEN;
  80                 break;
  81         }
  82
  83         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
  84
  85         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
  86
  87         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
  88                 scd_bc_tbl[txq_id].
  89                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
  90 }
  91
  92 /**
  93  * iwl_txq_update_write_ptr - Send new write index to hardware
  94  */
  95 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
  96 {
  97         u32 reg = 0;
  98         int txq_id = txq->q.id;
  99
 100         if (txq->need_update == 0)
 101                 return;
 102
 103         if (trans->cfg->base_params->shadow_reg_enable) {
 104                 /* shadow register enabled */
 105                 iwl_write32(trans, HBUS_TARG_WRPTR,
 106                             txq->q.write_ptr | (txq_id << 8));
 107         } else {
 108                 struct iwl_trans_pcie *trans_pcie =
 109                         IWL_TRANS_GET_PCIE_TRANS(trans);
 110                 /* if we're trying to save power */
 111                 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
 112                         /* wake up nic if it's powered down ...
 113                          * uCode will wake up, and interrupt us again, so next
 114                          * time we'll skip this part. */
 115                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 116
 117                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 118                                 IWL_DEBUG_INFO(trans,
 119                                         "Tx queue %d requesting wakeup,"
 120                                         " GP1 = 0x%x\n", txq_id, reg);
 121                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 122                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 123                                 return;
 124                         }
 125
 126                         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
 127                                      txq->q.write_ptr | (txq_id << 8));
 128
 129                 /*
 130                  * else not in power-save mode,
 131                  * uCode will never sleep when we're
 132                  * trying to tx (during RFKILL, we're not trying to tx).
 133                  */
 134                 } else
 135                         iwl_write32(trans, HBUS_TARG_WRPTR,
 136                                     txq->q.write_ptr | (txq_id << 8));
 137         }
 138         txq->need_update = 0;
 139 }
 140
 141 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 142 {
 143         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 144
 145         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 146         if (sizeof(dma_addr_t) > sizeof(u32))
 147                 addr |=
 148                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 149
 150         return addr;
 151 }
 152
 153 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 154 {
 155         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 156
 157         return le16_to_cpu(tb->hi_n_len) >> 4;
 158 }
 159
 160 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 161                                   dma_addr_t addr, u16 len)
 162 {
 163         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 164         u16 hi_n_len = len << 4;
 165
 166         put_unaligned_le32(addr, &tb->lo);
 167         if (sizeof(dma_addr_t) > sizeof(u32))
 168                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 169
 170         tb->hi_n_len = cpu_to_le16(hi_n_len);
 171
 172         tfd->num_tbs = idx + 1;
 173 }
 174
 175 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 176 {
 177         return tfd->num_tbs & 0x1f;
 178 }
 179
 180 static void iwl_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
 181                           struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
 182 {
 183         int i;
 184         int num_tbs;
 185
 186         /* Sanity check on number of chunks */
 187         num_tbs = iwl_tfd_get_num_tbs(tfd);
 188
 189         if (num_tbs >= IWL_NUM_OF_TBS) {
 190                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 191                 /* @todo issue fatal error, it is quite serious situation */
 192                 return;
 193         }
 194
 195         /* Unmap tx_cmd */
 196         if (num_tbs)
 197                 dma_unmap_single(trans->dev,
 198                                 dma_unmap_addr(meta, mapping),
 199                                 dma_unmap_len(meta, len),
 200                                 DMA_BIDIRECTIONAL);
 201
 202         /* Unmap chunks, if any. */
 203         for (i = 1; i < num_tbs; i++)
 204                 dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i),
 205                                 iwl_tfd_tb_get_len(tfd, i), dma_dir);
 206
 207         tfd->num_tbs = 0;
 208 }
 209
 210 /**
 211  * iwl_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 212  * @trans - transport private data
 213  * @txq - tx queue
 214  * @dma_dir - the direction of the DMA mapping
 215  *
 216  * Does NOT advance any TFD circular buffer read/write indexes
 217  * Does NOT free the TFD itself (which is within circular buffer)
 218  */
 219 void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 220                       enum dma_data_direction dma_dir)
 221 {
 222         struct iwl_tfd *tfd_tmp = txq->tfds;
 223
 224         /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
 225         int rd_ptr = txq->q.read_ptr;
 226         int idx = get_cmd_index(&txq->q, rd_ptr);
 227
 228         lockdep_assert_held(&txq->lock);
 229
 230         /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
 231         iwl_unmap_tfd(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr],
 232                       dma_dir);
 233
 234         /* free SKB */
 235         if (txq->entries) {
 236                 struct sk_buff *skb;
 237
 238                 skb = txq->entries[idx].skb;
 239
 240                 /* Can be called from irqs-disabled context
 241                  * If skb is not NULL, it means that the whole queue is being
 242                  * freed and that the queue is not empty - free the skb
 243                  */
 244                 if (skb) {
 245                         iwl_op_mode_free_skb(trans->op_mode, skb);
 246                         txq->entries[idx].skb = NULL;
 247                 }
 248         }
 249 }
 250
 251 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
 252                                  struct iwl_tx_queue *txq,
 253                                  dma_addr_t addr, u16 len,
 254                                  u8 reset)
 255 {
 256         struct iwl_queue *q;
 257         struct iwl_tfd *tfd, *tfd_tmp;
 258         u32 num_tbs;
 259
 260         q = &txq->q;
 261         tfd_tmp = txq->tfds;
 262         tfd = &tfd_tmp[q->write_ptr];
 263
 264         if (reset)
 265                 memset(tfd, 0, sizeof(*tfd));
 266
 267         num_tbs = iwl_tfd_get_num_tbs(tfd);
 268
 269         /* Each TFD can point to a maximum 20 Tx buffers */
 270         if (num_tbs >= IWL_NUM_OF_TBS) {
 271                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 272                         IWL_NUM_OF_TBS);
 273                 return -EINVAL;
 274         }
 275
 276         if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
 277                 return -EINVAL;
 278
 279         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 280                 IWL_ERR(trans, "Unaligned address = %llx\n",
 281                         (unsigned long long)addr);
 282
 283         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 284
 285         return 0;
 286 }
 287
 288 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
 289  * DMA services
 290  *
 291  * Theory of operation
 292  *
 293  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
 294  * of buffer descriptors, each of which points to one or more data buffers for
 295  * the device to read from or fill.  Driver and device exchange status of each
 296  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
 297  * entries in each circular buffer, to protect against confusing empty and full
 298  * queue states.
 299  *
 300  * The device reads or writes the data in the queues via the device's several
 301  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
 302  *
 303  * For Tx queue, there are low mark and high mark limits. If, after queuing
 304  * the packet for Tx, free space become < low mark, Tx queue stopped. When
 305  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
 306  * Tx queue resumed.
 307  *
 308  ***************************************************/
 309
 310 int iwl_queue_space(const struct iwl_queue *q)
 311 {
 312         int s = q->read_ptr - q->write_ptr;
 313
 314         if (q->read_ptr > q->write_ptr)
 315                 s -= q->n_bd;
 316
 317         if (s <= 0)
 318                 s += q->n_window;
 319         /* keep some reserve to not confuse empty and full situations */
 320         s -= 2;
 321         if (s < 0)
 322                 s = 0;
 323         return s;
 324 }
 325
 326 /**
 327  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 328  */
 329 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
 330 {
 331         q->n_bd = count;
 332         q->n_window = slots_num;
 333         q->id = id;
 334
 335         /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
 336          * and iwl_queue_dec_wrap are broken. */
 337         if (WARN_ON(!is_power_of_2(count)))
 338                 return -EINVAL;
 339
 340         /* slots_num must be power-of-two size, otherwise
 341          * get_cmd_index is broken. */
 342         if (WARN_ON(!is_power_of_2(slots_num)))
 343                 return -EINVAL;
 344
 345         q->low_mark = q->n_window / 4;
 346         if (q->low_mark < 4)
 347                 q->low_mark = 4;
 348
 349         q->high_mark = q->n_window / 8;
 350         if (q->high_mark < 2)
 351                 q->high_mark = 2;
 352
 353         q->write_ptr = q->read_ptr = 0;
 354
 355         return 0;
 356 }
 357
 358 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 359                                           struct iwl_tx_queue *txq)
 360 {
 361         struct iwl_trans_pcie *trans_pcie =
 362                 IWL_TRANS_GET_PCIE_TRANS(trans);
 363         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 364         int txq_id = txq->q.id;
 365         int read_ptr = txq->q.read_ptr;
 366         u8 sta_id = 0;
 367         __le16 bc_ent;
 368         struct iwl_tx_cmd *tx_cmd =
 369                 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
 370
 371         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 372
 373         if (txq_id != trans_pcie->cmd_queue)
 374                 sta_id = tx_cmd->sta_id;
 375
 376         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 377         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 378
 379         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 380                 scd_bc_tbl[txq_id].
 381                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 382 }
 383
 384 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
 385                                        u16 txq_id)
 386 {
 387         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 388         u32 tbl_dw_addr;
 389         u32 tbl_dw;
 390         u16 scd_q2ratid;
 391
 392         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 393
 394         tbl_dw_addr = trans_pcie->scd_base_addr +
 395                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
 396
 397         tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr);
 398
 399         if (txq_id & 0x1)
 400                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 401         else
 402                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 403
 404         iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw);
 405
 406         return 0;
 407 }
 408
 409 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
 410 {
 411         /* Simply stop the queue, but don't change any configuration;
 412          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 413         iwl_write_prph(trans,
 414                 SCD_QUEUE_STATUS_BITS(txq_id),
 415                 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 416                 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 417 }
 418
 419 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index)
 420 {
 421         IWL_DEBUG_TX_QUEUES(trans, "Q %d  WrPtr: %d\n", txq_id, index & 0xff);
 422         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
 423                            (index & 0xff) | (txq_id << 8));
 424         iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index);
 425 }
 426
 427 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
 428                                    struct iwl_tx_queue *txq,
 429                                    int tx_fifo_id, bool active)
 430 {
 431         int txq_id = txq->q.id;
 432
 433         iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
 434                         (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 435                         (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
 436                         (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
 437                         SCD_QUEUE_STTS_REG_MSK);
 438
 439         if (active)
 440                 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d\n",
 441                                     txq_id, tx_fifo_id);
 442         else
 443                 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
 444 }
 445
 446 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, int txq_id, int fifo,
 447                                  int sta_id, int tid, int frame_limit, u16 ssn)
 448 {
 449         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 450         unsigned long flags;
 451         u16 ra_tid = BUILD_RAxTID(sta_id, tid);
 452
 453         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
 454                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
 455
 456         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 457
 458         /* Stop this Tx queue before configuring it */
 459         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 460
 461         /* Map receiver-address / traffic-ID to this queue */
 462         iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
 463
 464         /* Set this queue as a chain-building queue */
 465         iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
 466
 467         /* enable aggregations for the queue */
 468         iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
 469
 470         /* Place first TFD at index corresponding to start sequence number.
 471          * Assumes that ssn_idx is valid (!= 0xFFF) */
 472         trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
 473         trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
 474         iwl_trans_set_wr_ptrs(trans, txq_id, ssn);
 475
 476         /* Set up Tx window size and frame limit for this queue */
 477         iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
 478                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
 479                         ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 480                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 481                         ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 482                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 483
 484         iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
 485
 486         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
 487         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
 488                                       fifo, true);
 489
 490         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 491 }
 492
 493 void iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int txq_id)
 494 {
 495         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 496
 497         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
 498                 WARN_ONCE(1, "queue %d not used", txq_id);
 499                 return;
 500         }
 501
 502         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 503
 504         iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
 505
 506         trans_pcie->txq[txq_id].q.read_ptr = 0;
 507         trans_pcie->txq[txq_id].q.write_ptr = 0;
 508         iwl_trans_set_wr_ptrs(trans, txq_id, 0);
 509
 510         iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, BIT(txq_id));
 511
 512         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
 513                                       0, false);
 514 }
 515
 516 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
 517
 518 /**
 519  * iwl_enqueue_hcmd - enqueue a uCode command
 520  * @priv: device private data point
 521  * @cmd: a point to the ucode command structure
 522  *
 523  * The function returns < 0 values to indicate the operation is
 524  * failed. On success, it turns the index (> 0) of command in the
 525  * command queue.
 526  */
 527 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 528 {
 529         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 530         struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 531         struct iwl_queue *q = &txq->q;
 532         struct iwl_device_cmd *out_cmd;
 533         struct iwl_cmd_meta *out_meta;
 534         dma_addr_t phys_addr;
 535         u32 idx;
 536         u16 copy_size, cmd_size;
 537         bool had_nocopy = false;
 538         int i;
 539         u8 *cmd_dest;
 540 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 541         const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
 542         int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
 543         int trace_idx;
 544 #endif
 545
 546         copy_size = sizeof(out_cmd->hdr);
 547         cmd_size = sizeof(out_cmd->hdr);
 548
 549         /* need one for the header if the first is NOCOPY */
 550         BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
 551
 552         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 553                 if (!cmd->len[i])
 554                         continue;
 555                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
 556                         had_nocopy = true;
 557                 } else {
 558                         /* NOCOPY must not be followed by normal! */
 559                         if (WARN_ON(had_nocopy))
 560                                 return -EINVAL;
 561                         copy_size += cmd->len[i];
 562                 }
 563                 cmd_size += cmd->len[i];
 564         }
 565
 566         /*
 567          * If any of the command structures end up being larger than
 568          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
 569          * allocated into separate TFDs, then we will need to
 570          * increase the size of the buffers.
 571          */
 572         if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
 573                 return -EINVAL;
 574
 575         spin_lock_bh(&txq->lock);
 576
 577         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
 578                 spin_unlock_bh(&txq->lock);
 579
 580                 IWL_ERR(trans, "No space in command queue\n");
 581                 iwl_op_mode_cmd_queue_full(trans->op_mode);
 582                 return -ENOSPC;
 583         }
 584
 585         idx = get_cmd_index(q, q->write_ptr);
 586         out_cmd = txq->entries[idx].cmd;
 587         out_meta = &txq->entries[idx].meta;
 588
 589         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
 590         if (cmd->flags & CMD_WANT_SKB)
 591                 out_meta->source = cmd;
 592
 593         /* set up the header */
 594
 595         out_cmd->hdr.cmd = cmd->id;
 596         out_cmd->hdr.flags = 0;
 597         out_cmd->hdr.sequence =
 598                 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
 599                                          INDEX_TO_SEQ(q->write_ptr));
 600
 601         /* and copy the data that needs to be copied */
 602
 603         cmd_dest = out_cmd->payload;
 604         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 605                 if (!cmd->len[i])
 606                         continue;
 607                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
 608                         break;
 609                 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
 610                 cmd_dest += cmd->len[i];
 611         }
 612
 613         IWL_DEBUG_HC(trans,
 614                      "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
 615                      trans_pcie_get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
 616                      out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
 617                      cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
 618
 619         phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size,
 620                                    DMA_BIDIRECTIONAL);
 621         if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
 622                 idx = -ENOMEM;
 623                 goto out;
 624         }
 625
 626         dma_unmap_addr_set(out_meta, mapping, phys_addr);
 627         dma_unmap_len_set(out_meta, len, copy_size);
 628
 629         iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, copy_size, 1);
 630 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 631         trace_bufs[0] = &out_cmd->hdr;
 632         trace_lens[0] = copy_size;
 633         trace_idx = 1;
 634 #endif
 635
 636         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 637                 if (!cmd->len[i])
 638                         continue;
 639                 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
 640                         continue;
 641                 phys_addr = dma_map_single(trans->dev, (void *)cmd->data[i],
 642                                            cmd->len[i], DMA_BIDIRECTIONAL);
 643                 if (dma_mapping_error(trans->dev, phys_addr)) {
 644                         iwl_unmap_tfd(trans, out_meta,
 645                                       &txq->tfds[q->write_ptr],
 646                                       DMA_BIDIRECTIONAL);
 647                         idx = -ENOMEM;
 648                         goto out;
 649                 }
 650
 651                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
 652                                              cmd->len[i], 0);
 653 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 654                 trace_bufs[trace_idx] = cmd->data[i];
 655                 trace_lens[trace_idx] = cmd->len[i];
 656                 trace_idx++;
 657 #endif
 658         }
 659
 660         out_meta->flags = cmd->flags;
 661
 662         txq->need_update = 1;
 663
 664         /* check that tracing gets all possible blocks */
 665         BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
 666 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 667         trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags,
 668                                trace_bufs[0], trace_lens[0],
 669                                trace_bufs[1], trace_lens[1],
 670                                trace_bufs[2], trace_lens[2]);
 671 #endif
 672
 673         /* start timer if queue currently empty */
 674         if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
 675                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
 676
 677         /* Increment and update queue's write index */
 678         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
 679         iwl_txq_update_write_ptr(trans, txq);
 680
 681  out:
 682         spin_unlock_bh(&txq->lock);
 683         return idx;
 684 }
 685
 686 static inline void iwl_queue_progress(struct iwl_trans_pcie *trans_pcie,
 687                                       struct iwl_tx_queue *txq)
 688 {
 689         if (!trans_pcie->wd_timeout)
 690                 return;
 691
 692         /*
 693          * if empty delete timer, otherwise move timer forward
 694          * since we're making progress on this queue
 695          */
 696         if (txq->q.read_ptr == txq->q.write_ptr)
 697                 del_timer(&txq->stuck_timer);
 698         else
 699                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
 700 }
 701
 702 /**
 703  * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
 704  *
 705  * When FW advances 'R' index, all entries between old and new 'R' index
 706  * need to be reclaimed. As result, some free space forms.  If there is
 707  * enough free space (> low mark), wake the stack that feeds us.
 708  */
 709 static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
 710                                    int idx)
 711 {
 712         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 713         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 714         struct iwl_queue *q = &txq->q;
 715         int nfreed = 0;
 716
 717         lockdep_assert_held(&txq->lock);
 718
 719         if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
 720                 IWL_ERR(trans,
 721                         "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
 722                         __func__, txq_id, idx, q->n_bd,
 723                         q->write_ptr, q->read_ptr);
 724                 return;
 725         }
 726
 727         for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
 728              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 729
 730                 if (nfreed++ > 0) {
 731                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
 732                                 idx, q->write_ptr, q->read_ptr);
 733                         iwl_op_mode_nic_error(trans->op_mode);
 734                 }
 735
 736         }
 737
 738         iwl_queue_progress(trans_pcie, txq);
 739 }
 740
 741 /**
 742  * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
 743  * @rxb: Rx buffer to reclaim
 744  * @handler_status: return value of the handler of the command
 745  *      (put in setup_rx_handlers)
 746  *
 747  * If an Rx buffer has an async callback associated with it the callback
 748  * will be executed.  The attached skb (if present) will only be freed
 749  * if the callback returns 1
 750  */
 751 void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb,
 752                          int handler_status)
 753 {
 754         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 755         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 756         int txq_id = SEQ_TO_QUEUE(sequence);
 757         int index = SEQ_TO_INDEX(sequence);
 758         int cmd_index;
 759         struct iwl_device_cmd *cmd;
 760         struct iwl_cmd_meta *meta;
 761         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 762         struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 763
 764         /* If a Tx command is being handled and it isn't in the actual
 765          * command queue then there a command routing bug has been introduced
 766          * in the queue management code. */
 767         if (WARN(txq_id != trans_pcie->cmd_queue,
 768                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
 769                  txq_id, trans_pcie->cmd_queue, sequence,
 770                  trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
 771                  trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
 772                 iwl_print_hex_error(trans, pkt, 32);
 773                 return;
 774         }
 775
 776         spin_lock(&txq->lock);
 777
 778         cmd_index = get_cmd_index(&txq->q, index);
 779         cmd = txq->entries[cmd_index].cmd;
 780         meta = &txq->entries[cmd_index].meta;
 781
 782         iwl_unmap_tfd(trans, meta, &txq->tfds[index], DMA_BIDIRECTIONAL);
 783
 784         /* Input error checking is done when commands are added to queue. */
 785         if (meta->flags & CMD_WANT_SKB) {
 786                 struct page *p = rxb_steal_page(rxb);
 787
 788                 meta->source->resp_pkt = pkt;
 789                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
 790                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
 791                 meta->source->handler_status = handler_status;
 792         }
 793
 794         iwl_hcmd_queue_reclaim(trans, txq_id, index);
 795
 796         if (!(meta->flags & CMD_ASYNC)) {
 797                 if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
 798                         IWL_WARN(trans,
 799                                  "HCMD_ACTIVE already clear for command %s\n",
 800                                  trans_pcie_get_cmd_string(trans_pcie,
 801                                                            cmd->hdr.cmd));
 802                 }
 803                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 804                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
 805                                trans_pcie_get_cmd_string(trans_pcie,
 806                                                          cmd->hdr.cmd));
 807                 wake_up(&trans->wait_command_queue);
 808         }
 809
 810         meta->flags = 0;
 811
 812         spin_unlock(&txq->lock);
 813 }
 814
 815 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
 816
 817 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 818 {
 819         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 820         int ret;
 821
 822         /* An asynchronous command can not expect an SKB to be set. */
 823         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
 824                 return -EINVAL;
 825
 826
 827         ret = iwl_enqueue_hcmd(trans, cmd);
 828         if (ret < 0) {
 829                 IWL_ERR(trans,
 830                         "Error sending %s: enqueue_hcmd failed: %d\n",
 831                         trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret);
 832                 return ret;
 833         }
 834         return 0;
 835 }
 836
 837 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 838 {
 839         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 840         int cmd_idx;
 841         int ret;
 842
 843         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
 844                        trans_pcie_get_cmd_string(trans_pcie, cmd->id));
 845
 846         if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
 847                                      &trans_pcie->status))) {
 848                 IWL_ERR(trans, "Command %s: a command is already active!\n",
 849                         trans_pcie_get_cmd_string(trans_pcie, cmd->id));
 850                 return -EIO;
 851         }
 852
 853         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
 854                        trans_pcie_get_cmd_string(trans_pcie, cmd->id));
 855
 856         cmd_idx = iwl_enqueue_hcmd(trans, cmd);
 857         if (cmd_idx < 0) {
 858                 ret = cmd_idx;
 859                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 860                 IWL_ERR(trans,
 861                         "Error sending %s: enqueue_hcmd failed: %d\n",
 862                         trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret);
 863                 return ret;
 864         }
 865
 866         ret = wait_event_timeout(trans->wait_command_queue,
 867                                  !test_bit(STATUS_HCMD_ACTIVE,
 868                                            &trans_pcie->status),
 869                                  HOST_COMPLETE_TIMEOUT);
 870         if (!ret) {
 871                 if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
 872                         struct iwl_tx_queue *txq =
 873                                 &trans_pcie->txq[trans_pcie->cmd_queue];
 874                         struct iwl_queue *q = &txq->q;
 875
 876                         IWL_ERR(trans,
 877                                 "Error sending %s: time out after %dms.\n",
 878                                 trans_pcie_get_cmd_string(trans_pcie, cmd->id),
 879                                 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
 880
 881                         IWL_ERR(trans,
 882                                 "Current CMD queue read_ptr %d write_ptr %d\n",
 883                                 q->read_ptr, q->write_ptr);
 884
 885                         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 886                         IWL_DEBUG_INFO(trans,
 887                                        "Clearing HCMD_ACTIVE for command %s\n",
 888                                        trans_pcie_get_cmd_string(trans_pcie,
 889                                                                  cmd->id));
 890                         ret = -ETIMEDOUT;
 891                         goto cancel;
 892                 }
 893         }
 894
 895         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
 896                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
 897                         trans_pcie_get_cmd_string(trans_pcie, cmd->id));
 898                 ret = -EIO;
 899                 goto cancel;
 900         }
 901
 902         return 0;
 903
 904 cancel:
 905         if (cmd->flags & CMD_WANT_SKB) {
 906                 /*
 907                  * Cancel the CMD_WANT_SKB flag for the cmd in the
 908                  * TX cmd queue. Otherwise in case the cmd comes
 909                  * in later, it will possibly set an invalid
 910                  * address (cmd->meta.source).
 911                  */
 912                 trans_pcie->txq[trans_pcie->cmd_queue].
 913                         entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
 914         }
 915
 916         if (cmd->resp_pkt) {
 917                 iwl_free_resp(cmd);
 918                 cmd->resp_pkt = NULL;
 919         }
 920
 921         return ret;
 922 }
 923
 924 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 925 {
 926         if (cmd->flags & CMD_ASYNC)
 927                 return iwl_send_cmd_async(trans, cmd);
 928
 929         return iwl_send_cmd_sync(trans, cmd);
 930 }
 931
 932 /* Frees buffers until index _not_ inclusive */
 933 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
 934                          struct sk_buff_head *skbs)
 935 {
 936         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 937         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 938         struct iwl_queue *q = &txq->q;
 939         int last_to_free;
 940         int freed = 0;
 941
 942         /* This function is not meant to release cmd queue*/
 943         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
 944                 return 0;
 945
 946         lockdep_assert_held(&txq->lock);
 947
 948         /*Since we free until index _not_ inclusive, the one before index is
 949          * the last we will free. This one must be used */
 950         last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
 951
 952         if ((index >= q->n_bd) ||
 953            (iwl_queue_used(q, last_to_free) == 0)) {
 954                 IWL_ERR(trans,
 955                         "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
 956                         __func__, txq_id, last_to_free, q->n_bd,
 957                         q->write_ptr, q->read_ptr);
 958                 return 0;
 959         }
 960
 961         if (WARN_ON(!skb_queue_empty(skbs)))
 962                 return 0;
 963
 964         for (;
 965              q->read_ptr != index;
 966              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 967
 968                 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
 969                         continue;
 970
 971                 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
 972
 973                 txq->entries[txq->q.read_ptr].skb = NULL;
 974
 975                 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
 976
 977                 iwl_txq_free_tfd(trans, txq, DMA_TO_DEVICE);
 978                 freed++;
 979         }
 980
 981         iwl_queue_progress(trans_pcie, txq);
 982
 983         return freed;
 984 }