1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/etherdevice.h>
45 #include <linux/if_arp.h>
47 #include <net/mac80211.h>
49 #include <asm/div64.h>
51 #define DRV_NAME "iwl4965"
56 /******************************************************************************
60 ******************************************************************************/
63 * module name, copyright, version, etc.
65 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
67 #ifdef CONFIG_IWLEGACY_DEBUG
73 #define DRV_VERSION IWLWIFI_VERSION VD
75 MODULE_DESCRIPTION(DRV_DESCRIPTION);
76 MODULE_VERSION(DRV_VERSION);
77 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78 MODULE_LICENSE("GPL");
79 MODULE_ALIAS("iwl4965");
82 il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 IL_ERR("Tx flush command to flush out all frames\n");
86 if (!test_bit(S_EXIT_PENDING, &il->status))
87 queue_work(il->workqueue, &il->tx_flush);
94 struct il_mod_params il4965_mod_params = {
97 /* the rest are 0 by default */
101 il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
105 spin_lock_irqsave(&rxq->lock, flags);
106 INIT_LIST_HEAD(&rxq->rx_free);
107 INIT_LIST_HEAD(&rxq->rx_used);
108 /* Fill the rx_used queue with _all_ of the Rx buffers */
109 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
110 /* In the reset function, these buffers may have been allocated
111 * to an SKB, so we need to unmap and free potential storage */
112 if (rxq->pool[i].page != NULL) {
113 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
114 PAGE_SIZE << il->hw_params.rx_page_order,
116 __il_free_pages(il, rxq->pool[i].page);
117 rxq->pool[i].page = NULL;
119 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
122 for (i = 0; i < RX_QUEUE_SIZE; i++)
123 rxq->queue[i] = NULL;
125 /* Set us so that we have processed and used all buffers, but have
126 * not restocked the Rx queue with fresh buffers */
127 rxq->read = rxq->write = 0;
128 rxq->write_actual = 0;
130 spin_unlock_irqrestore(&rxq->lock, flags);
134 il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
137 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
140 if (il->cfg->mod_params->amsdu_size_8K)
141 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
143 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
146 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
148 /* Reset driver's Rx queue write idx */
149 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
151 /* Tell device where to find RBD circular buffer in DRAM */
152 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
154 /* Tell device where in DRAM to update its Rx status */
155 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
158 * Direct rx interrupts to hosts
159 * Rx buffer size 4 or 8k
163 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
164 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
165 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
166 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
168 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
169 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
171 /* Set interrupt coalescing timer to default (2048 usecs) */
172 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
178 il4965_set_pwr_vmain(struct il_priv *il)
181 * (for documentation purposes)
182 * to set power to V_AUX, do:
184 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
185 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
186 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
187 ~APMG_PS_CTRL_MSK_PWR_SRC);
190 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
192 ~APMG_PS_CTRL_MSK_PWR_SRC);
196 il4965_hw_nic_init(struct il_priv *il)
199 struct il_rx_queue *rxq = &il->rxq;
203 spin_lock_irqsave(&il->lock, flags);
204 il->cfg->ops->lib->apm_ops.init(il);
206 /* Set interrupt coalescing calibration timer to default (512 usecs) */
207 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
209 spin_unlock_irqrestore(&il->lock, flags);
211 il4965_set_pwr_vmain(il);
213 il->cfg->ops->lib->apm_ops.config(il);
215 /* Allocate the RX queue, or reset if it is already allocated */
217 ret = il_rx_queue_alloc(il);
219 IL_ERR("Unable to initialize Rx queue\n");
223 il4965_rx_queue_reset(il, rxq);
225 il4965_rx_replenish(il);
227 il4965_rx_init(il, rxq);
229 spin_lock_irqsave(&il->lock, flags);
231 rxq->need_update = 1;
232 il_rx_queue_update_write_ptr(il, rxq);
234 spin_unlock_irqrestore(&il->lock, flags);
236 /* Allocate or reset and init all Tx and Command queues */
238 ret = il4965_txq_ctx_alloc(il);
242 il4965_txq_ctx_reset(il);
244 set_bit(S_INIT, &il->status);
250 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
253 il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
255 return cpu_to_le32((u32) (dma_addr >> 8));
259 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
261 * If there are slots in the RX queue that need to be restocked,
262 * and we have free pre-allocated buffers, fill the ranks as much
263 * as we can, pulling from rx_free.
265 * This moves the 'write' idx forward to catch up with 'processed', and
266 * also updates the memory address in the firmware to reference the new
270 il4965_rx_queue_restock(struct il_priv *il)
272 struct il_rx_queue *rxq = &il->rxq;
273 struct list_head *element;
274 struct il_rx_buf *rxb;
277 spin_lock_irqsave(&rxq->lock, flags);
278 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
279 /* The overwritten rxb must be a used one */
280 rxb = rxq->queue[rxq->write];
281 BUG_ON(rxb && rxb->page);
283 /* Get next free Rx buffer, remove from free list */
284 element = rxq->rx_free.next;
285 rxb = list_entry(element, struct il_rx_buf, list);
288 /* Point to Rx buffer via next RBD in circular buffer */
289 rxq->bd[rxq->write] =
290 il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
291 rxq->queue[rxq->write] = rxb;
292 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
295 spin_unlock_irqrestore(&rxq->lock, flags);
296 /* If the pre-allocated buffer pool is dropping low, schedule to
298 if (rxq->free_count <= RX_LOW_WATERMARK)
299 queue_work(il->workqueue, &il->rx_replenish);
301 /* If we've added more space for the firmware to place data, tell it.
302 * Increment device's write pointer in multiples of 8. */
303 if (rxq->write_actual != (rxq->write & ~0x7)) {
304 spin_lock_irqsave(&rxq->lock, flags);
305 rxq->need_update = 1;
306 spin_unlock_irqrestore(&rxq->lock, flags);
307 il_rx_queue_update_write_ptr(il, rxq);
312 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
314 * When moving to rx_free an SKB is allocated for the slot.
316 * Also restock the Rx queue via il_rx_queue_restock.
317 * This is called as a scheduled work item (except for during initialization)
320 il4965_rx_allocate(struct il_priv *il, gfp_t priority)
322 struct il_rx_queue *rxq = &il->rxq;
323 struct list_head *element;
324 struct il_rx_buf *rxb;
327 gfp_t gfp_mask = priority;
330 spin_lock_irqsave(&rxq->lock, flags);
331 if (list_empty(&rxq->rx_used)) {
332 spin_unlock_irqrestore(&rxq->lock, flags);
335 spin_unlock_irqrestore(&rxq->lock, flags);
337 if (rxq->free_count > RX_LOW_WATERMARK)
338 gfp_mask |= __GFP_NOWARN;
340 if (il->hw_params.rx_page_order > 0)
341 gfp_mask |= __GFP_COMP;
343 /* Alloc a new receive buffer */
344 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
347 D_INFO("alloc_pages failed, " "order: %d\n",
348 il->hw_params.rx_page_order);
350 if (rxq->free_count <= RX_LOW_WATERMARK &&
352 IL_ERR("Failed to alloc_pages with %s. "
353 "Only %u free buffers remaining.\n",
355 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
357 /* We don't reschedule replenish work here -- we will
358 * call the restock method and if it still needs
359 * more buffers it will schedule replenish */
363 spin_lock_irqsave(&rxq->lock, flags);
365 if (list_empty(&rxq->rx_used)) {
366 spin_unlock_irqrestore(&rxq->lock, flags);
367 __free_pages(page, il->hw_params.rx_page_order);
370 element = rxq->rx_used.next;
371 rxb = list_entry(element, struct il_rx_buf, list);
374 spin_unlock_irqrestore(&rxq->lock, flags);
378 /* Get physical address of the RB */
380 pci_map_page(il->pci_dev, page, 0,
381 PAGE_SIZE << il->hw_params.rx_page_order,
383 /* dma address must be no more than 36 bits */
384 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
385 /* and also 256 byte aligned! */
386 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
388 spin_lock_irqsave(&rxq->lock, flags);
390 list_add_tail(&rxb->list, &rxq->rx_free);
392 il->alloc_rxb_page++;
394 spin_unlock_irqrestore(&rxq->lock, flags);
399 il4965_rx_replenish(struct il_priv *il)
403 il4965_rx_allocate(il, GFP_KERNEL);
405 spin_lock_irqsave(&il->lock, flags);
406 il4965_rx_queue_restock(il);
407 spin_unlock_irqrestore(&il->lock, flags);
411 il4965_rx_replenish_now(struct il_priv *il)
413 il4965_rx_allocate(il, GFP_ATOMIC);
415 il4965_rx_queue_restock(il);
418 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
419 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
420 * This free routine walks the list of POOL entries and if SKB is set to
421 * non NULL it is unmapped and freed
424 il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
427 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
428 if (rxq->pool[i].page != NULL) {
429 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
430 PAGE_SIZE << il->hw_params.rx_page_order,
432 __il_free_pages(il, rxq->pool[i].page);
433 rxq->pool[i].page = NULL;
437 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
439 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
440 rxq->rb_stts, rxq->rb_stts_dma);
446 il4965_rxq_stop(struct il_priv *il)
450 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
451 il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
452 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
458 il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
463 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
464 if (rate_n_flags & RATE_MCS_HT_MSK) {
465 idx = (rate_n_flags & 0xff);
467 /* Legacy rate format, search for match in table */
469 if (band == IEEE80211_BAND_5GHZ)
470 band_offset = IL_FIRST_OFDM_RATE;
471 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
472 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
473 return idx - band_offset;
480 il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
482 /* data from PHY/DSP regarding signal strength, etc.,
483 * contents are always there, not configurable by host. */
484 struct il4965_rx_non_cfg_phy *ncphy =
485 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
487 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
491 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
492 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
496 /* Find max rssi among 3 possible receivers.
497 * These values are measured by the digital signal processor (DSP).
498 * They should stay fairly constant even as the signal strength varies,
499 * if the radio's automatic gain control (AGC) is working right.
500 * AGC value (see below) will provide the "interesting" info. */
501 for (i = 0; i < 3; i++)
502 if (valid_antennae & (1 << i))
503 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
505 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
506 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
509 /* dBm = max_rssi dB - agc dB - constant.
510 * Higher AGC (higher radio gain) means lower signal. */
511 return max_rssi - agc - IL4965_RSSI_OFFSET;
515 il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
519 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
520 RX_RES_STATUS_STATION_FOUND)
522 (RX_RES_STATUS_STATION_FOUND |
523 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
525 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
527 /* packet was not encrypted */
528 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
529 RX_RES_STATUS_SEC_TYPE_NONE)
532 /* packet was encrypted with unknown alg */
533 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
534 RX_RES_STATUS_SEC_TYPE_ERR)
537 /* decryption was not done in HW */
538 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
539 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
542 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
544 case RX_RES_STATUS_SEC_TYPE_CCMP:
545 /* alg is CCM: check MIC only */
546 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
548 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
550 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
554 case RX_RES_STATUS_SEC_TYPE_TKIP:
555 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
557 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
560 /* fall through if TTAK OK */
562 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
563 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
565 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
569 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
575 il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
576 u16 len, u32 ampdu_status, struct il_rx_buf *rxb,
577 struct ieee80211_rx_status *stats)
580 __le16 fc = hdr->frame_control;
582 /* We only process data packets if the interface is open */
583 if (unlikely(!il->is_open)) {
584 D_DROP("Dropping packet while interface is not open.\n");
588 /* In case of HW accelerated crypto and bad decryption, drop */
589 if (!il->cfg->mod_params->sw_crypto &&
590 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
593 skb = dev_alloc_skb(128);
595 IL_ERR("dev_alloc_skb failed\n");
599 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
601 il_update_stats(il, false, fc, len);
602 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
604 ieee80211_rx(il->hw, skb);
605 il->alloc_rxb_page--;
609 /* Called for N_RX (legacy ABG frames), or
610 * N_RX_MPDU (HT high-throughput N frames). */
612 il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
614 struct ieee80211_hdr *header;
615 struct ieee80211_rx_status rx_status;
616 struct il_rx_pkt *pkt = rxb_addr(rxb);
617 struct il_rx_phy_res *phy_res;
618 __le32 rx_pkt_status;
619 struct il_rx_mpdu_res_start *amsdu;
625 * N_RX and N_RX_MPDU are handled differently.
626 * N_RX: physical layer info is in this buffer
627 * N_RX_MPDU: physical layer info was sent in separate
628 * command and cached in il->last_phy_res
630 * Here we set up local variables depending on which command is
633 if (pkt->hdr.cmd == N_RX) {
634 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
636 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
637 phy_res->cfg_phy_cnt);
639 len = le16_to_cpu(phy_res->byte_count);
641 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
642 phy_res->cfg_phy_cnt + len);
643 ampdu_status = le32_to_cpu(rx_pkt_status);
645 if (!il->_4965.last_phy_res_valid) {
646 IL_ERR("MPDU frame without cached PHY data\n");
649 phy_res = &il->_4965.last_phy_res;
650 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
651 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
652 len = le16_to_cpu(amsdu->byte_count);
653 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
655 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
658 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
659 D_DROP("dsp size out of range [0,20]: %d/n",
660 phy_res->cfg_phy_cnt);
664 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
665 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
666 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
670 /* This will be used in several places later */
671 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
673 /* rx_status carries information about the packet to mac80211 */
674 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
677 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
680 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
683 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
686 /* TSF isn't reliable. In order to allow smooth user experience,
687 * this W/A doesn't propagate it to the mac80211 */
688 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU; */
690 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
692 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
693 rx_status.signal = il4965_calc_rssi(il, phy_res);
695 il_dbg_log_rx_data_frame(il, len, header);
696 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
697 (unsigned long long)rx_status.mactime);
702 * It seems that the antenna field in the phy flags value
703 * is actually a bit field. This is undefined by radiotap,
704 * it wants an actual antenna number but I always get "7"
705 * for most legacy frames I receive indicating that the
706 * same frame was received on all three RX chains.
708 * I think this field should be removed in favor of a
709 * new 802.11n radiotap field "RX chains" that is defined
713 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
714 RX_RES_PHY_FLAGS_ANTENNA_POS;
716 /* set the preamble flag if appropriate */
717 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
718 rx_status.flag |= RX_FLAG_SHORTPRE;
720 /* Set up the HT phy flags */
721 if (rate_n_flags & RATE_MCS_HT_MSK)
722 rx_status.flag |= RX_FLAG_HT;
723 if (rate_n_flags & RATE_MCS_HT40_MSK)
724 rx_status.flag |= RX_FLAG_40MHZ;
725 if (rate_n_flags & RATE_MCS_SGI_MSK)
726 rx_status.flag |= RX_FLAG_SHORT_GI;
728 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
732 /* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
733 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
735 il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
737 struct il_rx_pkt *pkt = rxb_addr(rxb);
738 il->_4965.last_phy_res_valid = true;
739 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
740 sizeof(struct il_rx_phy_res));
744 il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
745 enum ieee80211_band band, u8 is_active,
746 u8 n_probes, struct il_scan_channel *scan_ch)
748 struct ieee80211_channel *chan;
749 const struct ieee80211_supported_band *sband;
750 const struct il_channel_info *ch_info;
751 u16 passive_dwell = 0;
752 u16 active_dwell = 0;
756 sband = il_get_hw_mode(il, band);
760 active_dwell = il_get_active_dwell_time(il, band, n_probes);
761 passive_dwell = il_get_passive_dwell_time(il, band, vif);
763 if (passive_dwell <= active_dwell)
764 passive_dwell = active_dwell + 1;
766 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
767 chan = il->scan_request->channels[i];
769 if (chan->band != band)
772 channel = chan->hw_value;
773 scan_ch->channel = cpu_to_le16(channel);
775 ch_info = il_get_channel_info(il, band, channel);
776 if (!il_is_channel_valid(ch_info)) {
777 D_SCAN("Channel %d is INVALID for this band.\n",
782 if (!is_active || il_is_channel_passive(ch_info) ||
783 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
784 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
786 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
789 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
791 scan_ch->active_dwell = cpu_to_le16(active_dwell);
792 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
794 /* Set txpower levels to defaults */
795 scan_ch->dsp_atten = 110;
797 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
799 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
801 if (band == IEEE80211_BAND_5GHZ)
802 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
804 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
806 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
807 le32_to_cpu(scan_ch->type),
809 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
811 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
818 D_SCAN("total channels to scan %d\n", added);
823 il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
828 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
829 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
830 if (valid & BIT(ind)) {
838 il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
840 struct il_host_cmd cmd = {
842 .len = sizeof(struct il_scan_cmd),
843 .flags = CMD_SIZE_HUGE,
845 struct il_scan_cmd *scan;
846 struct il_rxon_context *ctx = &il->ctx;
850 enum ieee80211_band band;
852 u8 rx_ant = il->hw_params.valid_rx_ant;
854 bool is_active = false;
857 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
860 lockdep_assert_held(&il->mutex);
862 ctx = il_rxon_ctx_from_vif(vif);
866 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
869 D_SCAN("fail to allocate memory for scan\n");
874 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
876 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
877 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
879 if (il_is_any_associated(il)) {
882 u32 suspend_time = 100;
883 u32 scan_suspend_time = 100;
885 D_INFO("Scanning while associated...\n");
886 interval = vif->bss_conf.beacon_int;
888 scan->suspend_time = 0;
889 scan->max_out_time = cpu_to_le32(200 * 1024);
891 interval = suspend_time;
893 extra = (suspend_time / interval) << 22;
895 (extra | ((suspend_time % interval) * 1024));
896 scan->suspend_time = cpu_to_le32(scan_suspend_time);
897 D_SCAN("suspend_time 0x%X beacon interval %d\n",
898 scan_suspend_time, interval);
901 if (il->scan_request->n_ssids) {
903 D_SCAN("Kicking off active scan\n");
904 for (i = 0; i < il->scan_request->n_ssids; i++) {
905 /* always does wildcard anyway */
906 if (!il->scan_request->ssids[i].ssid_len)
908 scan->direct_scan[p].id = WLAN_EID_SSID;
909 scan->direct_scan[p].len =
910 il->scan_request->ssids[i].ssid_len;
911 memcpy(scan->direct_scan[p].ssid,
912 il->scan_request->ssids[i].ssid,
913 il->scan_request->ssids[i].ssid_len);
919 D_SCAN("Start passive scan.\n");
921 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
922 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
923 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
925 switch (il->scan_band) {
926 case IEEE80211_BAND_2GHZ:
927 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
929 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
930 RXON_FLG_CHANNEL_MODE_POS;
931 if (chan_mod == CHANNEL_MODE_PURE_40) {
935 rate_flags = RATE_MCS_CCK_MSK;
938 case IEEE80211_BAND_5GHZ:
942 IL_WARN("Invalid scan band\n");
947 * If active scanning is requested but a certain channel is
948 * marked passive, we can do active scanning if we detect
951 * There is an issue with some firmware versions that triggers
952 * a sysassert on a "good CRC threshold" of zero (== disabled),
953 * on a radar channel even though this means that we should NOT
956 * The "good CRC threshold" is the number of frames that we
957 * need to receive during our dwell time on a channel before
958 * sending out probes -- setting this to a huge value will
959 * mean we never reach it, but at the same time work around
960 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
961 * here instead of IL_GOOD_CRC_TH_DISABLED.
964 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
966 band = il->scan_band;
968 if (il->cfg->scan_rx_antennas[band])
969 rx_ant = il->cfg->scan_rx_antennas[band];
971 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
972 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
973 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
975 /* In power save mode use one chain, otherwise use all chains */
976 if (test_bit(S_POWER_PMI, &il->status)) {
977 /* rx_ant has been set to all valid chains previously */
979 rx_ant & ((u8) (il->chain_noise_data.active_chains));
981 active_chains = rx_ant;
983 D_SCAN("chain_noise_data.active_chains: %u\n",
984 il->chain_noise_data.active_chains);
986 rx_ant = il4965_first_antenna(active_chains);
989 /* MIMO is not used here, but value is required */
990 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
991 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
992 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
993 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
994 scan->rx_chain = cpu_to_le16(rx_chain);
997 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
998 vif->addr, il->scan_request->ie,
999 il->scan_request->ie_len,
1000 IL_MAX_SCAN_SIZE - sizeof(*scan));
1001 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1003 scan->filter_flags |=
1004 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
1006 scan->channel_count =
1007 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1008 (void *)&scan->data[cmd_len]);
1009 if (scan->channel_count == 0) {
1010 D_SCAN("channel count %d\n", scan->channel_count);
1015 le16_to_cpu(scan->tx_cmd.len) +
1016 scan->channel_count * sizeof(struct il_scan_channel);
1018 scan->len = cpu_to_le16(cmd.len);
1020 set_bit(S_SCAN_HW, &il->status);
1022 ret = il_send_cmd_sync(il, &cmd);
1024 clear_bit(S_SCAN_HW, &il->status);
1030 il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1033 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1036 return il4965_add_bssid_station(il, vif_priv->ctx,
1037 vif->bss_conf.bssid,
1038 &vif_priv->ibss_bssid_sta_id);
1039 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
1040 vif->bss_conf.bssid);
1044 il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
1046 lockdep_assert_held(&il->sta_lock);
1048 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1049 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1051 D_TX("free more than tfds_in_queue (%u:%d)\n",
1052 il->stations[sta_id].tid[tid].tfds_in_queue, freed);
1053 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1057 #define IL_TX_QUEUE_MSK 0xfffff
1060 il4965_is_single_rx_stream(struct il_priv *il)
1062 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1063 il->current_ht_config.single_chain_sufficient;
1066 #define IL_NUM_RX_CHAINS_MULTIPLE 3
1067 #define IL_NUM_RX_CHAINS_SINGLE 2
1068 #define IL_NUM_IDLE_CHAINS_DUAL 2
1069 #define IL_NUM_IDLE_CHAINS_SINGLE 1
1072 * Determine how many receiver/antenna chains to use.
1074 * More provides better reception via diversity. Fewer saves power
1075 * at the expense of throughput, but only when not in powersave to
1078 * MIMO (dual stream) requires at least 2, but works better with 3.
1079 * This does not determine *which* chains to use, just how many.
1082 il4965_get_active_rx_chain_count(struct il_priv *il)
1084 /* # of Rx chains to use when expecting MIMO. */
1085 if (il4965_is_single_rx_stream(il))
1086 return IL_NUM_RX_CHAINS_SINGLE;
1088 return IL_NUM_RX_CHAINS_MULTIPLE;
1092 * When we are in power saving mode, unless device support spatial
1093 * multiplexing power save, use the active count for rx chain count.
1096 il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1098 /* # Rx chains when idling, depending on SMPS mode */
1099 switch (il->current_ht_config.smps) {
1100 case IEEE80211_SMPS_STATIC:
1101 case IEEE80211_SMPS_DYNAMIC:
1102 return IL_NUM_IDLE_CHAINS_SINGLE;
1103 case IEEE80211_SMPS_OFF:
1106 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
1111 /* up to 4 chains */
1113 il4965_count_chain_bitmap(u32 chain_bitmap)
1116 res = (chain_bitmap & BIT(0)) >> 0;
1117 res += (chain_bitmap & BIT(1)) >> 1;
1118 res += (chain_bitmap & BIT(2)) >> 2;
1119 res += (chain_bitmap & BIT(3)) >> 3;
1124 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1126 * Selects how many and which Rx receivers/antennas/chains to use.
1127 * This should not be used for scan command ... it puts data in wrong place.
1130 il4965_set_rxon_chain(struct il_priv *il, struct il_rxon_context *ctx)
1132 bool is_single = il4965_is_single_rx_stream(il);
1133 bool is_cam = !test_bit(S_POWER_PMI, &il->status);
1134 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1138 /* Tell uCode which antennas are actually connected.
1139 * Before first association, we assume all antennas are connected.
1140 * Just after first association, il4965_chain_noise_calibration()
1141 * checks which antennas actually *are* connected. */
1142 if (il->chain_noise_data.active_chains)
1143 active_chains = il->chain_noise_data.active_chains;
1145 active_chains = il->hw_params.valid_rx_ant;
1147 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1149 /* How many receivers should we use? */
1150 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1151 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1153 /* correct rx chain count according hw settings
1154 * and chain noise calibration
1156 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1157 if (valid_rx_cnt < active_rx_cnt)
1158 active_rx_cnt = valid_rx_cnt;
1160 if (valid_rx_cnt < idle_rx_cnt)
1161 idle_rx_cnt = valid_rx_cnt;
1163 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1164 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1166 il->staging.rx_chain = cpu_to_le16(rx_chain);
1168 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
1169 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1171 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1173 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
1174 active_rx_cnt, idle_rx_cnt);
1176 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1177 active_rx_cnt < idle_rx_cnt);
1181 il4965_get_fh_string(int cmd)
1184 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1185 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1186 IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1187 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1188 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1189 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1190 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1191 IL_CMD(FH49_TSSR_TX_STATUS_REG);
1192 IL_CMD(FH49_TSSR_TX_ERROR_REG);
1199 il4965_dump_fh(struct il_priv *il, char **buf, bool display)
1202 #ifdef CONFIG_IWLEGACY_DEBUG
1206 static const u32 fh_tbl[] = {
1207 FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1208 FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1209 FH49_RSCSR_CHNL0_WPTR,
1210 FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1211 FH49_MEM_RSSR_SHARED_CTRL_REG,
1212 FH49_MEM_RSSR_RX_STATUS_REG,
1213 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1214 FH49_TSSR_TX_STATUS_REG,
1215 FH49_TSSR_TX_ERROR_REG
1217 #ifdef CONFIG_IWLEGACY_DEBUG
1219 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1220 *buf = kmalloc(bufsz, GFP_KERNEL);
1224 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
1225 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1227 scnprintf(*buf + pos, bufsz - pos,
1229 il4965_get_fh_string(fh_tbl[i]),
1230 il_rd(il, fh_tbl[i]));
1235 IL_ERR("FH register values:\n");
1236 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1237 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1238 il_rd(il, fh_tbl[i]));
1244 il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
1246 struct il_rx_pkt *pkt = rxb_addr(rxb);
1247 struct il_missed_beacon_notif *missed_beacon;
1249 missed_beacon = &pkt->u.missed_beacon;
1250 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1251 il->missed_beacon_threshold) {
1252 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1253 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1254 le32_to_cpu(missed_beacon->total_missed_becons),
1255 le32_to_cpu(missed_beacon->num_recvd_beacons),
1256 le32_to_cpu(missed_beacon->num_expected_beacons));
1257 if (!test_bit(S_SCANNING, &il->status))
1258 il4965_init_sensitivity(il);
1262 /* Calculate noise level, based on measurements during network silence just
1263 * before arriving beacon. This measurement can be done only if we know
1264 * exactly when to expect beacons, therefore only when we're associated. */
1266 il4965_rx_calc_noise(struct il_priv *il)
1268 struct stats_rx_non_phy *rx_info;
1269 int num_active_rx = 0;
1270 int total_silence = 0;
1271 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1274 rx_info = &(il->_4965.stats.rx.general);
1276 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
1278 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
1280 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
1282 if (bcn_silence_a) {
1283 total_silence += bcn_silence_a;
1286 if (bcn_silence_b) {
1287 total_silence += bcn_silence_b;
1290 if (bcn_silence_c) {
1291 total_silence += bcn_silence_c;
1295 /* Average among active antennas */
1297 last_rx_noise = (total_silence / num_active_rx) - 107;
1299 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1301 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1302 bcn_silence_b, bcn_silence_c, last_rx_noise);
1305 #ifdef CONFIG_IWLEGACY_DEBUGFS
1307 * based on the assumption of all stats counter are in DWORD
1308 * FIXME: This function is for debugging, do not deal with
1309 * the case of counters roll-over.
1312 il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
1317 u32 *delta, *max_delta;
1318 struct stats_general_common *general, *accum_general;
1319 struct stats_tx *tx, *accum_tx;
1321 prev_stats = (__le32 *) &il->_4965.stats;
1322 accum_stats = (u32 *) &il->_4965.accum_stats;
1323 size = sizeof(struct il_notif_stats);
1324 general = &il->_4965.stats.general.common;
1325 accum_general = &il->_4965.accum_stats.general.common;
1326 tx = &il->_4965.stats.tx;
1327 accum_tx = &il->_4965.accum_stats.tx;
1328 delta = (u32 *) &il->_4965.delta_stats;
1329 max_delta = (u32 *) &il->_4965.max_delta;
1331 for (i = sizeof(__le32); i < size;
1333 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1335 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
1337 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
1338 *accum_stats += *delta;
1339 if (*delta > *max_delta)
1340 *max_delta = *delta;
1344 /* reset accumulative stats for "no-counter" type stats */
1345 accum_general->temperature = general->temperature;
1346 accum_general->ttl_timestamp = general->ttl_timestamp;
1350 #define REG_RECALIB_PERIOD (60)
1353 il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
1356 struct il_rx_pkt *pkt = rxb_addr(rxb);
1358 D_RX("Statistics notification received (%d vs %d).\n",
1359 (int)sizeof(struct il_notif_stats),
1360 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1363 ((il->_4965.stats.general.common.temperature !=
1364 pkt->u.stats.general.common.temperature) ||
1365 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1366 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
1367 #ifdef CONFIG_IWLEGACY_DEBUGFS
1368 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
1371 /* TODO: reading some of stats is unneeded */
1372 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
1374 set_bit(S_STATS, &il->status);
1376 /* Reschedule the stats timer to occur in
1377 * REG_RECALIB_PERIOD seconds to ensure we get a
1378 * thermal update even if the uCode doesn't give
1380 mod_timer(&il->stats_periodic,
1381 jiffies + msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
1383 if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
1384 (pkt->hdr.cmd == N_STATS)) {
1385 il4965_rx_calc_noise(il);
1386 queue_work(il->workqueue, &il->run_time_calib_work);
1388 if (il->cfg->ops->lib->temp_ops.temperature && change)
1389 il->cfg->ops->lib->temp_ops.temperature(il);
1393 il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
1395 struct il_rx_pkt *pkt = rxb_addr(rxb);
1397 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
1398 #ifdef CONFIG_IWLEGACY_DEBUGFS
1399 memset(&il->_4965.accum_stats, 0,
1400 sizeof(struct il_notif_stats));
1401 memset(&il->_4965.delta_stats, 0,
1402 sizeof(struct il_notif_stats));
1403 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
1405 D_RX("Statistics have been cleared\n");
1407 il4965_hdl_stats(il, rxb);
1412 * mac80211 queues, ACs, hardware queues, FIFOs.
1414 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1416 * Mac80211 uses the following numbers, which we get as from it
1417 * by way of skb_get_queue_mapping(skb):
1425 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1426 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1427 * own queue per aggregation session (RA/TID combination), such queues are
1428 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1429 * order to map frames to the right queue, we also need an AC->hw queue
1430 * mapping. This is implemented here.
1432 * Due to the way hw queues are set up (by the hw specific modules like
1433 * 4965.c), the AC->hw queue mapping is the identity
1437 static const u8 tid_to_ac[] = {
1449 il4965_get_ac_from_tid(u16 tid)
1451 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1452 return tid_to_ac[tid];
1454 /* no support for TIDs 8-15 yet */
1459 il4965_get_fifo_from_tid(struct il_rxon_context *ctx, u16 tid)
1461 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1462 return ctx->ac_to_fifo[tid_to_ac[tid]];
1464 /* no support for TIDs 8-15 yet */
1469 * handle build C_TX command notification.
1472 il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1473 struct il_tx_cmd *tx_cmd,
1474 struct ieee80211_tx_info *info,
1475 struct ieee80211_hdr *hdr, u8 std_id)
1477 __le16 fc = hdr->frame_control;
1478 __le32 tx_flags = tx_cmd->tx_flags;
1480 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1481 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1482 tx_flags |= TX_CMD_FLG_ACK_MSK;
1483 if (ieee80211_is_mgmt(fc))
1484 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1485 if (ieee80211_is_probe_resp(fc) &&
1486 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1487 tx_flags |= TX_CMD_FLG_TSF_MSK;
1489 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1490 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1493 if (ieee80211_is_back_req(fc))
1494 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1496 tx_cmd->sta_id = std_id;
1497 if (ieee80211_has_morefrags(fc))
1498 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1500 if (ieee80211_is_data_qos(fc)) {
1501 u8 *qc = ieee80211_get_qos_ctl(hdr);
1502 tx_cmd->tid_tspec = qc[0] & 0xf;
1503 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1505 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1508 il_tx_cmd_protection(il, info, fc, &tx_flags);
1510 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1511 if (ieee80211_is_mgmt(fc)) {
1512 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1513 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1515 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1517 tx_cmd->timeout.pm_frame_timeout = 0;
1520 tx_cmd->driver_txop = 0;
1521 tx_cmd->tx_flags = tx_flags;
1522 tx_cmd->next_frame_len = 0;
1526 il4965_tx_cmd_build_rate(struct il_priv *il, struct il_tx_cmd *tx_cmd,
1527 struct ieee80211_tx_info *info, __le16 fc)
1529 const u8 rts_retry_limit = 60;
1532 u8 data_retry_limit;
1535 /* Set retry limit on DATA packets and Probe Responses */
1536 if (ieee80211_is_probe_resp(fc))
1537 data_retry_limit = 3;
1539 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1540 tx_cmd->data_retry_limit = data_retry_limit;
1541 /* Set retry limit on RTS packets */
1542 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
1544 /* DATA packets will use the uCode station table for rate/antenna
1546 if (ieee80211_is_data(fc)) {
1547 tx_cmd->initial_rate_idx = 0;
1548 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1553 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1554 * not really a TX rate. Thus, we use the lowest supported rate for
1555 * this band. Also use the lowest supported rate if the stored rate
1558 rate_idx = info->control.rates[0].idx;
1559 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1560 || rate_idx > RATE_COUNT_LEGACY)
1562 rate_lowest_index(&il->bands[info->band],
1564 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1565 if (info->band == IEEE80211_BAND_5GHZ)
1566 rate_idx += IL_FIRST_OFDM_RATE;
1567 /* Get PLCP rate for tx_cmd->rate_n_flags */
1568 rate_plcp = il_rates[rate_idx].plcp;
1569 /* Zero out flags for this packet */
1572 /* Set CCK flag as needed */
1573 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1574 rate_flags |= RATE_MCS_CCK_MSK;
1576 /* Set up antennas */
1577 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
1578 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
1580 /* Set the rate in the TX cmd */
1581 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
1585 il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1586 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1589 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1591 switch (keyconf->cipher) {
1592 case WLAN_CIPHER_SUITE_CCMP:
1593 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1594 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1595 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1596 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1597 D_TX("tx_cmd with AES hwcrypto\n");
1600 case WLAN_CIPHER_SUITE_TKIP:
1601 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1602 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1603 D_TX("tx_cmd with tkip hwcrypto\n");
1606 case WLAN_CIPHER_SUITE_WEP104:
1607 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1609 case WLAN_CIPHER_SUITE_WEP40:
1611 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1614 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1616 D_TX("Configuring packet for WEP encryption " "with key %d\n",
1621 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1627 * start C_TX command process
1630 il4965_tx_skb(struct il_priv *il, struct sk_buff *skb)
1632 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1633 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1634 struct ieee80211_sta *sta = info->control.sta;
1635 struct il_station_priv *sta_priv = NULL;
1636 struct il_tx_queue *txq;
1638 struct il_device_cmd *out_cmd;
1639 struct il_cmd_meta *out_meta;
1640 struct il_tx_cmd *tx_cmd;
1641 struct il_rxon_context *ctx = &il->ctx;
1643 dma_addr_t phys_addr;
1644 dma_addr_t txcmd_phys;
1645 dma_addr_t scratch_phys;
1646 u16 len, firstlen, secondlen;
1651 u8 wait_write_ptr = 0;
1654 unsigned long flags;
1655 bool is_agg = false;
1657 if (info->control.vif)
1658 ctx = il_rxon_ctx_from_vif(info->control.vif);
1660 spin_lock_irqsave(&il->lock, flags);
1661 if (il_is_rfkill(il)) {
1662 D_DROP("Dropping - RF KILL\n");
1666 fc = hdr->frame_control;
1668 #ifdef CONFIG_IWLEGACY_DEBUG
1669 if (ieee80211_is_auth(fc))
1670 D_TX("Sending AUTH frame\n");
1671 else if (ieee80211_is_assoc_req(fc))
1672 D_TX("Sending ASSOC frame\n");
1673 else if (ieee80211_is_reassoc_req(fc))
1674 D_TX("Sending REASSOC frame\n");
1677 hdr_len = ieee80211_hdrlen(fc);
1679 /* For management frames use broadcast id to do not break aggregation */
1680 if (!ieee80211_is_data(fc))
1681 sta_id = il->hw_params.bcast_id;
1683 /* Find idx into station table for destination station */
1684 sta_id = il_sta_id_or_broadcast(il, ctx, info->control.sta);
1686 if (sta_id == IL_INVALID_STATION) {
1687 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
1692 D_TX("station Id %d\n", sta_id);
1695 sta_priv = (void *)sta->drv_priv;
1697 if (sta_priv && sta_priv->asleep &&
1698 (info->flags & IEEE80211_TX_CTL_POLL_RESPONSE)) {
1700 * This sends an asynchronous command to the device,
1701 * but we can rely on it being processed before the
1702 * next frame is processed -- and the next frame to
1703 * this station is the one that will consume this
1705 * For now set the counter to just 1 since we do not
1706 * support uAPSD yet.
1708 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1711 /* FIXME: remove me ? */
1712 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1714 txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
1716 /* irqs already disabled/saved above when locking il->lock */
1717 spin_lock(&il->sta_lock);
1719 if (ieee80211_is_data_qos(fc)) {
1720 qc = ieee80211_get_qos_ctl(hdr);
1721 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1722 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1723 spin_unlock(&il->sta_lock);
1726 seq_number = il->stations[sta_id].tid[tid].seq_number;
1727 seq_number &= IEEE80211_SCTL_SEQ;
1729 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
1730 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1732 /* aggregation is on for this <sta,tid> */
1733 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1734 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1735 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1740 txq = &il->txq[txq_id];
1743 if (unlikely(il_queue_space(q) < q->high_mark)) {
1744 spin_unlock(&il->sta_lock);
1748 if (ieee80211_is_data_qos(fc)) {
1749 il->stations[sta_id].tid[tid].tfds_in_queue++;
1750 if (!ieee80211_has_morefrags(fc))
1751 il->stations[sta_id].tid[tid].seq_number = seq_number;
1754 spin_unlock(&il->sta_lock);
1756 /* Set up driver data for this TFD */
1757 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct il_tx_info));
1758 txq->txb[q->write_ptr].skb = skb;
1759 txq->txb[q->write_ptr].ctx = ctx;
1761 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1762 out_cmd = txq->cmd[q->write_ptr];
1763 out_meta = &txq->meta[q->write_ptr];
1764 tx_cmd = &out_cmd->cmd.tx;
1765 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1766 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1769 * Set up the Tx-command (not MAC!) header.
1770 * Store the chosen Tx queue and TFD idx within the sequence field;
1771 * after Tx, uCode's Tx response will return this value so driver can
1772 * locate the frame within the tx queue and do post-tx processing.
1774 out_cmd->hdr.cmd = C_TX;
1775 out_cmd->hdr.sequence =
1777 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
1779 /* Copy MAC header from skb into command buffer */
1780 memcpy(tx_cmd->hdr, hdr, hdr_len);
1782 /* Total # bytes to be transmitted */
1783 len = (u16) skb->len;
1784 tx_cmd->len = cpu_to_le16(len);
1786 if (info->control.hw_key)
1787 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1789 /* TODO need this for burst mode later on */
1790 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
1791 il_dbg_log_tx_data_frame(il, len, hdr);
1793 il4965_tx_cmd_build_rate(il, tx_cmd, info, fc);
1795 il_update_stats(il, true, fc, len);
1797 * Use the first empty entry in this queue's command buffer array
1798 * to contain the Tx command and MAC header concatenated together
1799 * (payload data will be in another buffer).
1800 * Size of this varies, due to varying MAC header length.
1801 * If end is not dword aligned, we'll have 2 extra bytes at the end
1802 * of the MAC header (device reads on dword boundaries).
1803 * We'll tell device about this padding later.
1805 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
1806 firstlen = (len + 3) & ~3;
1808 /* Tell NIC about any 2-byte padding after MAC header */
1809 if (firstlen != len)
1810 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1812 /* Physical address of this Tx command's header (not MAC header!),
1813 * within command buffer array. */
1815 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1816 PCI_DMA_BIDIRECTIONAL);
1817 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1818 dma_unmap_len_set(out_meta, len, firstlen);
1819 /* Add buffer containing Tx command and MAC(!) header to TFD's
1821 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen,
1824 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1825 txq->need_update = 1;
1828 txq->need_update = 0;
1831 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1832 * if any (802.11 null frames have no payload). */
1833 secondlen = skb->len - hdr_len;
1834 if (secondlen > 0) {
1836 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1838 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr,
1843 txcmd_phys + sizeof(struct il_cmd_header) +
1844 offsetof(struct il_tx_cmd, scratch);
1846 /* take back ownership of DMA buffer to enable update */
1847 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1848 PCI_DMA_BIDIRECTIONAL);
1849 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1850 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1852 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
1853 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1854 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1855 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
1857 /* Set up entry for this TFD in Tx byte-count array */
1858 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1859 il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq,
1860 le16_to_cpu(tx_cmd->
1863 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1864 PCI_DMA_BIDIRECTIONAL);
1866 /* Tell device the write idx *just past* this latest filled TFD */
1867 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1868 il_txq_update_write_ptr(il, txq);
1869 spin_unlock_irqrestore(&il->lock, flags);
1872 * At this point the frame is "transmitted" successfully
1873 * and we will get a TX status notification eventually,
1874 * regardless of the value of ret. "ret" only indicates
1875 * whether or not we should update the write pointer.
1879 * Avoid atomic ops if it isn't an associated client.
1880 * Also, if this is a packet for aggregation, don't
1881 * increase the counter because the ucode will stop
1882 * aggregation queues when their respective station
1885 if (sta_priv && sta_priv->client && !is_agg)
1886 atomic_inc(&sta_priv->pending_frames);
1888 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1889 if (wait_write_ptr) {
1890 spin_lock_irqsave(&il->lock, flags);
1891 txq->need_update = 1;
1892 il_txq_update_write_ptr(il, txq);
1893 spin_unlock_irqrestore(&il->lock, flags);
1895 il_stop_queue(il, txq);
1902 spin_unlock_irqrestore(&il->lock, flags);
1907 il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
1910 dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, GFP_KERNEL);
1918 il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
1920 if (unlikely(!ptr->addr))
1923 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1924 memset(ptr, 0, sizeof(*ptr));
1928 * il4965_hw_txq_ctx_free - Free TXQ Context
1930 * Destroy all TX DMA queues and structures
1933 il4965_hw_txq_ctx_free(struct il_priv *il)
1939 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1940 if (txq_id == il->cmd_queue)
1941 il_cmd_queue_free(il);
1943 il_tx_queue_free(il, txq_id);
1945 il4965_free_dma_ptr(il, &il->kw);
1947 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1949 /* free tx queue structure */
1954 * il4965_txq_ctx_alloc - allocate TX queue context
1955 * Allocate all Tx DMA structures and initialize them
1958 * @return error code
1961 il4965_txq_ctx_alloc(struct il_priv *il)
1964 int txq_id, slots_num;
1965 unsigned long flags;
1967 /* Free all tx/cmd queues and keep-warm buffer */
1968 il4965_hw_txq_ctx_free(il);
1971 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1972 il->hw_params.scd_bc_tbls_size);
1974 IL_ERR("Scheduler BC Table allocation failed\n");
1977 /* Alloc keep-warm buffer */
1978 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
1980 IL_ERR("Keep Warm allocation failed\n");
1984 /* allocate tx queue structure */
1985 ret = il_alloc_txq_mem(il);
1989 spin_lock_irqsave(&il->lock, flags);
1991 /* Turn off all Tx DMA fifos */
1992 il4965_txq_set_sched(il, 0);
1994 /* Tell NIC where to find the "keep warm" buffer */
1995 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
1997 spin_unlock_irqrestore(&il->lock, flags);
1999 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
2000 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
2003 il->cmd_queue) ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
2004 ret = il_tx_queue_init(il, &il->txq[txq_id], slots_num, txq_id);
2006 IL_ERR("Tx %d queue init failed\n", txq_id);
2014 il4965_hw_txq_ctx_free(il);
2015 il4965_free_dma_ptr(il, &il->kw);
2017 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
2023 il4965_txq_ctx_reset(struct il_priv *il)
2025 int txq_id, slots_num;
2026 unsigned long flags;
2028 spin_lock_irqsave(&il->lock, flags);
2030 /* Turn off all Tx DMA fifos */
2031 il4965_txq_set_sched(il, 0);
2033 /* Tell NIC where to find the "keep warm" buffer */
2034 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
2036 spin_unlock_irqrestore(&il->lock, flags);
2038 /* Alloc and init all Tx queues, including the command queue (#4) */
2039 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
2041 txq_id == il->cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
2042 il_tx_queue_reset(il, &il->txq[txq_id], slots_num, txq_id);
2047 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2050 il4965_txq_ctx_stop(struct il_priv *il)
2053 unsigned long flags;
2055 /* Turn off all Tx DMA fifos */
2056 spin_lock_irqsave(&il->lock, flags);
2058 il4965_txq_set_sched(il, 0);
2060 /* Stop each Tx DMA channel, and wait for it to be idle */
2061 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2062 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2064 (il, FH49_TSSR_TX_STATUS_REG,
2065 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000))
2066 IL_ERR("Failing on timeout while stopping"
2067 " DMA channel %d [0x%08x]", ch,
2068 il_rd(il, FH49_TSSR_TX_STATUS_REG));
2070 spin_unlock_irqrestore(&il->lock, flags);
2075 /* Unmap DMA from host system and free skb's */
2076 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2077 if (txq_id == il->cmd_queue)
2078 il_cmd_queue_unmap(il);
2080 il_tx_queue_unmap(il, txq_id);
2084 * Find first available (lowest unused) Tx Queue, mark it "active".
2085 * Called only when finding queue for aggregation.
2086 * Should never return anything < 7, because they should already
2087 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2090 il4965_txq_ctx_activate_free(struct il_priv *il)
2094 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2095 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2101 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2104 il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
2106 /* Simply stop the queue, but don't change any configuration;
2107 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
2108 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
2109 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2110 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
2114 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2117 il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
2123 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2126 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
2128 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2131 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2133 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2135 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2141 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2143 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2144 * i.e. it must be one of the higher queues used for aggregation
2147 il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2148 int tid, u16 ssn_idx)
2150 unsigned long flags;
2154 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2155 (IL49_FIRST_AMPDU_QUEUE +
2156 il->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
2157 IL_WARN("queue number out of range: %d, must be %d to %d\n",
2158 txq_id, IL49_FIRST_AMPDU_QUEUE,
2159 IL49_FIRST_AMPDU_QUEUE +
2160 il->cfg->base_params->num_of_ampdu_queues - 1);
2164 ra_tid = BUILD_RAxTID(sta_id, tid);
2166 /* Modify device's station table to Tx this TID */
2167 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2171 spin_lock_irqsave(&il->lock, flags);
2173 /* Stop this Tx queue before configuring it */
2174 il4965_tx_queue_stop_scheduler(il, txq_id);
2176 /* Map receiver-address / traffic-ID to this queue */
2177 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2179 /* Set this queue as a chain-building queue */
2180 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2182 /* Place first TFD at idx corresponding to start sequence number.
2183 * Assumes that ssn_idx is valid (!= 0xFFF) */
2184 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2185 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2186 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2188 /* Set up Tx win size and frame limit for this queue */
2189 il_write_targ_mem(il,
2191 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2192 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2193 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
2195 il_write_targ_mem(il,
2197 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2199 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2200 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
2202 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2204 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2205 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2207 spin_unlock_irqrestore(&il->lock, flags);
2213 il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2214 struct ieee80211_sta *sta, u16 tid, u16 * ssn)
2220 unsigned long flags;
2221 struct il_tid_data *tid_data;
2223 tx_fifo = il4965_get_fifo_from_tid(il_rxon_ctx_from_vif(vif), tid);
2224 if (unlikely(tx_fifo < 0))
2227 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
2229 sta_id = il_sta_id(sta);
2230 if (sta_id == IL_INVALID_STATION) {
2231 IL_ERR("Start AGG on invalid station\n");
2234 if (unlikely(tid >= MAX_TID_COUNT))
2237 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2238 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2242 txq_id = il4965_txq_ctx_activate_free(il);
2244 IL_ERR("No free aggregation queue available\n");
2248 spin_lock_irqsave(&il->sta_lock, flags);
2249 tid_data = &il->stations[sta_id].tid[tid];
2250 *ssn = SEQ_TO_SN(tid_data->seq_number);
2251 tid_data->agg.txq_id = txq_id;
2252 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
2253 spin_unlock_irqrestore(&il->sta_lock, flags);
2255 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
2259 spin_lock_irqsave(&il->sta_lock, flags);
2260 tid_data = &il->stations[sta_id].tid[tid];
2261 if (tid_data->tfds_in_queue == 0) {
2262 D_HT("HW queue is empty\n");
2263 tid_data->agg.state = IL_AGG_ON;
2264 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2266 D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2267 tid_data->tfds_in_queue);
2268 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2270 spin_unlock_irqrestore(&il->sta_lock, flags);
2275 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2276 * il->lock must be held by the caller
2279 il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
2281 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2282 (IL49_FIRST_AMPDU_QUEUE +
2283 il->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
2284 IL_WARN("queue number out of range: %d, must be %d to %d\n",
2285 txq_id, IL49_FIRST_AMPDU_QUEUE,
2286 IL49_FIRST_AMPDU_QUEUE +
2287 il->cfg->base_params->num_of_ampdu_queues - 1);
2291 il4965_tx_queue_stop_scheduler(il, txq_id);
2293 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2295 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2296 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2297 /* supposes that ssn_idx is valid (!= 0xFFF) */
2298 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2300 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2301 il_txq_ctx_deactivate(il, txq_id);
2302 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2308 il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2309 struct ieee80211_sta *sta, u16 tid)
2311 int tx_fifo_id, txq_id, sta_id, ssn;
2312 struct il_tid_data *tid_data;
2313 int write_ptr, read_ptr;
2314 unsigned long flags;
2316 tx_fifo_id = il4965_get_fifo_from_tid(il_rxon_ctx_from_vif(vif), tid);
2317 if (unlikely(tx_fifo_id < 0))
2320 sta_id = il_sta_id(sta);
2322 if (sta_id == IL_INVALID_STATION) {
2323 IL_ERR("Invalid station for AGG tid %d\n", tid);
2327 spin_lock_irqsave(&il->sta_lock, flags);
2329 tid_data = &il->stations[sta_id].tid[tid];
2330 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2331 txq_id = tid_data->agg.txq_id;
2333 switch (il->stations[sta_id].tid[tid].agg.state) {
2334 case IL_EMPTYING_HW_QUEUE_ADDBA:
2336 * This can happen if the peer stops aggregation
2337 * again before we've had a chance to drain the
2338 * queue we selected previously, i.e. before the
2339 * session was really started completely.
2341 D_HT("AGG stop before setup done\n");
2346 IL_WARN("Stopping AGG while state not ON or starting\n");
2349 write_ptr = il->txq[txq_id].q.write_ptr;
2350 read_ptr = il->txq[txq_id].q.read_ptr;
2352 /* The queue is not empty */
2353 if (write_ptr != read_ptr) {
2354 D_HT("Stopping a non empty AGG HW QUEUE\n");
2355 il->stations[sta_id].tid[tid].agg.state =
2356 IL_EMPTYING_HW_QUEUE_DELBA;
2357 spin_unlock_irqrestore(&il->sta_lock, flags);
2361 D_HT("HW queue is empty\n");
2363 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2365 /* do not restore/save irqs */
2366 spin_unlock(&il->sta_lock);
2367 spin_lock(&il->lock);
2370 * the only reason this call can fail is queue number out of range,
2371 * which can happen if uCode is reloaded and all the station
2372 * information are lost. if it is outside the range, there is no need
2373 * to deactivate the uCode queue, just return "success" to allow
2374 * mac80211 to clean up it own data.
2376 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2377 spin_unlock_irqrestore(&il->lock, flags);
2379 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2385 il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
2387 struct il_queue *q = &il->txq[txq_id].q;
2388 u8 *addr = il->stations[sta_id].sta.sta.addr;
2389 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
2390 struct il_rxon_context *ctx;
2394 lockdep_assert_held(&il->sta_lock);
2396 switch (il->stations[sta_id].tid[tid].agg.state) {
2397 case IL_EMPTYING_HW_QUEUE_DELBA:
2398 /* We are reclaiming the last packet of the */
2399 /* aggregated HW queue */
2400 if (txq_id == tid_data->agg.txq_id &&
2401 q->read_ptr == q->write_ptr) {
2402 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
2403 int tx_fifo = il4965_get_fifo_from_tid(ctx, tid);
2404 D_HT("HW queue empty: continue DELBA flow\n");
2405 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2406 tid_data->agg.state = IL_AGG_OFF;
2407 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
2410 case IL_EMPTYING_HW_QUEUE_ADDBA:
2411 /* We are reclaiming the last packet of the queue */
2412 if (tid_data->tfds_in_queue == 0) {
2413 D_HT("HW queue empty: continue ADDBA flow\n");
2414 tid_data->agg.state = IL_AGG_ON;
2415 ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
2424 il4965_non_agg_tx_status(struct il_priv *il, struct il_rxon_context *ctx,
2427 struct ieee80211_sta *sta;
2428 struct il_station_priv *sta_priv;
2431 sta = ieee80211_find_sta(ctx->vif, addr1);
2433 sta_priv = (void *)sta->drv_priv;
2434 /* avoid atomic ops if this isn't a client */
2435 if (sta_priv->client &&
2436 atomic_dec_return(&sta_priv->pending_frames) == 0)
2437 ieee80211_sta_block_awake(il->hw, sta, false);
2443 il4965_tx_status(struct il_priv *il, struct il_tx_info *tx_info, bool is_agg)
2445 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
2448 il4965_non_agg_tx_status(il, tx_info->ctx, hdr->addr1);
2450 ieee80211_tx_status_irqsafe(il->hw, tx_info->skb);
2454 il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
2456 struct il_tx_queue *txq = &il->txq[txq_id];
2457 struct il_queue *q = &txq->q;
2458 struct il_tx_info *tx_info;
2460 struct ieee80211_hdr *hdr;
2462 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2463 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
2464 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2465 q->write_ptr, q->read_ptr);
2469 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
2470 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2472 tx_info = &txq->txb[txq->q.read_ptr];
2474 if (WARN_ON_ONCE(tx_info->skb == NULL))
2477 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
2478 if (ieee80211_is_data_qos(hdr->frame_control))
2481 il4965_tx_status(il, tx_info,
2482 txq_id >= IL4965_FIRST_AMPDU_QUEUE);
2483 tx_info->skb = NULL;
2485 il->cfg->ops->lib->txq_free_tfd(il, txq);
2491 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2493 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2494 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2497 il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2498 struct il_compressed_ba_resp *ba_resp)
2501 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2502 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2504 struct ieee80211_tx_info *info;
2505 u64 bitmap, sent_bitmap;
2507 if (unlikely(!agg->wait_for_ba)) {
2508 if (unlikely(ba_resp->bitmap))
2509 IL_ERR("Received BA when not expected\n");
2513 /* Mark that the expected block-ack response arrived */
2514 agg->wait_for_ba = 0;
2515 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
2517 /* Calculate shift to align block-ack bits with our Tx win bits */
2518 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
2519 if (sh < 0) /* tbw something is wrong with indices */
2522 if (agg->frame_count > (64 - sh)) {
2523 D_TX_REPLY("more frames than bitmap size");
2527 /* don't use 64-bit values for now */
2528 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2530 /* check for success or failure according to the
2531 * transmitted bitmap and block-ack bitmap */
2532 sent_bitmap = bitmap & agg->bitmap;
2534 /* For each frame attempted in aggregation,
2535 * update driver's record of tx frame's status. */
2537 while (sent_bitmap) {
2538 ack = sent_bitmap & 1ULL;
2540 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2541 i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
2546 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
2548 info = IEEE80211_SKB_CB(il->txq[scd_flow].txb[agg->start_idx].skb);
2549 memset(&info->status, 0, sizeof(info->status));
2550 info->flags |= IEEE80211_TX_STAT_ACK;
2551 info->flags |= IEEE80211_TX_STAT_AMPDU;
2552 info->status.ampdu_ack_len = successes;
2553 info->status.ampdu_len = agg->frame_count;
2554 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2560 * translate ucode response to mac80211 tx status control values
2563 il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2564 struct ieee80211_tx_info *info)
2566 struct ieee80211_tx_rate *r = &info->control.rates[0];
2568 info->antenna_sel_tx =
2569 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
2570 if (rate_n_flags & RATE_MCS_HT_MSK)
2571 r->flags |= IEEE80211_TX_RC_MCS;
2572 if (rate_n_flags & RATE_MCS_GF_MSK)
2573 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2574 if (rate_n_flags & RATE_MCS_HT40_MSK)
2575 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2576 if (rate_n_flags & RATE_MCS_DUP_MSK)
2577 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2578 if (rate_n_flags & RATE_MCS_SGI_MSK)
2579 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2580 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2584 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
2586 * Handles block-acknowledge notification from device, which reports success
2587 * of frames sent via aggregation.
2590 il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
2592 struct il_rx_pkt *pkt = rxb_addr(rxb);
2593 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2594 struct il_tx_queue *txq = NULL;
2595 struct il_ht_agg *agg;
2599 unsigned long flags;
2601 /* "flow" corresponds to Tx queue */
2602 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2604 /* "ssn" is start of block-ack Tx win, corresponds to idx
2605 * (in Tx queue's circular buffer) of first TFD/frame in win */
2606 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2608 if (scd_flow >= il->hw_params.max_txq_num) {
2609 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
2613 txq = &il->txq[scd_flow];
2614 sta_id = ba_resp->sta_id;
2616 agg = &il->stations[sta_id].tid[tid].agg;
2617 if (unlikely(agg->txq_id != scd_flow)) {
2619 * FIXME: this is a uCode bug which need to be addressed,
2620 * log the information and return for now!
2621 * since it is possible happen very often and in order
2622 * not to fill the syslog, don't enable the logging by default
2624 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2625 scd_flow, agg->txq_id);
2629 /* Find idx just before block-ack win */
2630 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2632 spin_lock_irqsave(&il->sta_lock, flags);
2634 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
2635 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
2637 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2638 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2639 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2640 ba_resp->scd_flow, ba_resp->scd_ssn);
2641 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2642 (unsigned long long)agg->bitmap);
2644 /* Update driver's record of ACK vs. not for each frame in win */
2645 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2647 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2648 * block-ack win (we assume that they've been successfully
2649 * transmitted ... if not, it's too late anyway). */
2650 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2651 /* calculate mac80211 ampdu sw queue to wake */
2652 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2653 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2655 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2656 il->mac80211_registered &&
2657 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2658 il_wake_queue(il, txq);
2660 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2663 spin_unlock_irqrestore(&il->sta_lock, flags);
2666 #ifdef CONFIG_IWLEGACY_DEBUG
2668 il4965_get_tx_fail_reason(u32 status)
2670 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
2671 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
2673 switch (status & TX_STATUS_MSK) {
2674 case TX_STATUS_SUCCESS:
2676 TX_STATUS_POSTPONE(DELAY);
2677 TX_STATUS_POSTPONE(FEW_BYTES);
2678 TX_STATUS_POSTPONE(QUIET_PERIOD);
2679 TX_STATUS_POSTPONE(CALC_TTAK);
2680 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
2681 TX_STATUS_FAIL(SHORT_LIMIT);
2682 TX_STATUS_FAIL(LONG_LIMIT);
2683 TX_STATUS_FAIL(FIFO_UNDERRUN);
2684 TX_STATUS_FAIL(DRAIN_FLOW);
2685 TX_STATUS_FAIL(RFKILL_FLUSH);
2686 TX_STATUS_FAIL(LIFE_EXPIRE);
2687 TX_STATUS_FAIL(DEST_PS);
2688 TX_STATUS_FAIL(HOST_ABORTED);
2689 TX_STATUS_FAIL(BT_RETRY);
2690 TX_STATUS_FAIL(STA_INVALID);
2691 TX_STATUS_FAIL(FRAG_DROPPED);
2692 TX_STATUS_FAIL(TID_DISABLE);
2693 TX_STATUS_FAIL(FIFO_FLUSHED);
2694 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
2695 TX_STATUS_FAIL(PASSIVE_NO_RX);
2696 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
2701 #undef TX_STATUS_FAIL
2702 #undef TX_STATUS_POSTPONE
2704 #endif /* CONFIG_IWLEGACY_DEBUG */
2706 static struct il_link_quality_cmd *
2707 il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
2710 struct il_link_quality_cmd *link_cmd;
2712 __le32 rate_n_flags;
2714 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
2716 IL_ERR("Unable to allocate memory for LQ cmd.\n");
2719 /* Set up the rate scaling to start at selected rate, fall back
2720 * all the way down to 1M in IEEE order, and then spin on 1M */
2721 if (il->band == IEEE80211_BAND_5GHZ)
2726 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
2727 rate_flags |= RATE_MCS_CCK_MSK;
2730 il4965_first_antenna(il->hw_params.
2731 valid_tx_ant) << RATE_MCS_ANT_POS;
2732 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
2733 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
2734 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
2736 link_cmd->general_params.single_stream_ant_msk =
2737 il4965_first_antenna(il->hw_params.valid_tx_ant);
2739 link_cmd->general_params.dual_stream_ant_msk =
2740 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
2742 if (!link_cmd->general_params.dual_stream_ant_msk) {
2743 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
2744 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
2745 link_cmd->general_params.dual_stream_ant_msk =
2746 il->hw_params.valid_tx_ant;
2749 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
2750 link_cmd->agg_params.agg_time_limit =
2751 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
2753 link_cmd->sta_id = sta_id;
2759 * il4965_add_bssid_station - Add the special IBSS BSSID station
2764 il4965_add_bssid_station(struct il_priv *il, struct il_rxon_context *ctx,
2765 const u8 *addr, u8 *sta_id_r)
2769 struct il_link_quality_cmd *link_cmd;
2770 unsigned long flags;
2773 *sta_id_r = IL_INVALID_STATION;
2775 ret = il_add_station_common(il, ctx, addr, 0, NULL, &sta_id);
2777 IL_ERR("Unable to add station %pM\n", addr);
2784 spin_lock_irqsave(&il->sta_lock, flags);
2785 il->stations[sta_id].used |= IL_STA_LOCAL;
2786 spin_unlock_irqrestore(&il->sta_lock, flags);
2788 /* Set up default rate scaling table in device's station table */
2789 link_cmd = il4965_sta_alloc_lq(il, sta_id);
2791 IL_ERR("Unable to initialize rate scaling for station %pM.\n",
2796 ret = il_send_lq_cmd(il, ctx, link_cmd, CMD_SYNC, true);
2798 IL_ERR("Link quality command failed (%d)\n", ret);
2800 spin_lock_irqsave(&il->sta_lock, flags);
2801 il->stations[sta_id].lq = link_cmd;
2802 spin_unlock_irqrestore(&il->sta_lock, flags);
2808 il4965_static_wepkey_cmd(struct il_priv *il, struct il_rxon_context *ctx,
2812 u8 buff[sizeof(struct il_wep_cmd) +
2813 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
2814 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
2815 size_t cmd_size = sizeof(struct il_wep_cmd);
2816 struct il_host_cmd cmd = {
2821 bool not_empty = false;
2826 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
2828 for (i = 0; i < WEP_KEYS_MAX; i++) {
2829 u8 key_size = il->_4965.wep_keys[i].key_size;
2831 wep_cmd->key[i].key_idx = i;
2833 wep_cmd->key[i].key_offset = i;
2836 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
2838 wep_cmd->key[i].key_size = key_size;
2839 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
2842 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
2843 wep_cmd->num_keys = WEP_KEYS_MAX;
2845 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
2848 if (not_empty || send_if_empty)
2849 return il_send_cmd(il, &cmd);
2855 il4965_restore_default_wep_keys(struct il_priv *il, struct il_rxon_context *ctx)
2857 lockdep_assert_held(&il->mutex);
2859 return il4965_static_wepkey_cmd(il, ctx, false);
2863 il4965_remove_default_wep_key(struct il_priv *il, struct il_rxon_context *ctx,
2864 struct ieee80211_key_conf *keyconf)
2867 int idx = keyconf->keyidx;
2869 lockdep_assert_held(&il->mutex);
2871 D_WEP("Removing default WEP key: idx=%d\n", idx);
2873 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
2874 if (il_is_rfkill(il)) {
2875 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
2876 /* but keys in device are clear anyway so return success */
2879 ret = il4965_static_wepkey_cmd(il, ctx, 1);
2880 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
2886 il4965_set_default_wep_key(struct il_priv *il, struct il_rxon_context *ctx,
2887 struct ieee80211_key_conf *keyconf)
2890 int len = keyconf->keylen;
2891 int idx = keyconf->keyidx;
2893 lockdep_assert_held(&il->mutex);
2895 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
2896 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
2900 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
2901 keyconf->hw_key_idx = HW_KEY_DEFAULT;
2902 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
2904 il->_4965.wep_keys[idx].key_size = len;
2905 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
2907 ret = il4965_static_wepkey_cmd(il, ctx, false);
2909 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
2914 il4965_set_wep_dynamic_key_info(struct il_priv *il, struct il_rxon_context *ctx,
2915 struct ieee80211_key_conf *keyconf, u8 sta_id)
2917 unsigned long flags;
2918 __le16 key_flags = 0;
2919 struct il_addsta_cmd sta_cmd;
2921 lockdep_assert_held(&il->mutex);
2923 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
2925 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
2926 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
2927 key_flags &= ~STA_KEY_FLG_INVALID;
2929 if (keyconf->keylen == WEP_KEY_LEN_128)
2930 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
2932 if (sta_id == il->hw_params.bcast_id)
2933 key_flags |= STA_KEY_MULTICAST_MSK;
2935 spin_lock_irqsave(&il->sta_lock, flags);
2937 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
2938 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
2939 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
2941 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
2943 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
2946 if ((il->stations[sta_id].sta.key.
2947 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
2948 il->stations[sta_id].sta.key.key_offset =
2949 il_get_free_ucode_key_idx(il);
2950 /* else, we are overriding an existing key => no need to allocated room
2953 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
2954 "no space for a new key");
2956 il->stations[sta_id].sta.key.key_flags = key_flags;
2957 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
2958 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2960 memcpy(&sta_cmd, &il->stations[sta_id].sta,
2961 sizeof(struct il_addsta_cmd));
2962 spin_unlock_irqrestore(&il->sta_lock, flags);
2964 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2968 il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
2969 struct il_rxon_context *ctx,
2970 struct ieee80211_key_conf *keyconf, u8 sta_id)
2972 unsigned long flags;
2973 __le16 key_flags = 0;
2974 struct il_addsta_cmd sta_cmd;
2976 lockdep_assert_held(&il->mutex);
2978 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
2979 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
2980 key_flags &= ~STA_KEY_FLG_INVALID;
2982 if (sta_id == il->hw_params.bcast_id)
2983 key_flags |= STA_KEY_MULTICAST_MSK;
2985 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2987 spin_lock_irqsave(&il->sta_lock, flags);
2988 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
2989 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
2991 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
2993 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
2995 if ((il->stations[sta_id].sta.key.
2996 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
2997 il->stations[sta_id].sta.key.key_offset =
2998 il_get_free_ucode_key_idx(il);
2999 /* else, we are overriding an existing key => no need to allocated room
3002 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3003 "no space for a new key");
3005 il->stations[sta_id].sta.key.key_flags = key_flags;
3006 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3007 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3009 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3010 sizeof(struct il_addsta_cmd));
3011 spin_unlock_irqrestore(&il->sta_lock, flags);
3013 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3017 il4965_set_tkip_dynamic_key_info(struct il_priv *il,
3018 struct il_rxon_context *ctx,
3019 struct ieee80211_key_conf *keyconf, u8 sta_id)
3021 unsigned long flags;
3023 __le16 key_flags = 0;
3025 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3026 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3027 key_flags &= ~STA_KEY_FLG_INVALID;
3029 if (sta_id == il->hw_params.bcast_id)
3030 key_flags |= STA_KEY_MULTICAST_MSK;
3032 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3033 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3035 spin_lock_irqsave(&il->sta_lock, flags);
3037 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3038 il->stations[sta_id].keyinfo.keylen = 16;
3040 if ((il->stations[sta_id].sta.key.
3041 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3042 il->stations[sta_id].sta.key.key_offset =
3043 il_get_free_ucode_key_idx(il);
3044 /* else, we are overriding an existing key => no need to allocated room
3047 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3048 "no space for a new key");
3050 il->stations[sta_id].sta.key.key_flags = key_flags;
3052 /* This copy is acutally not needed: we get the key with each TX */
3053 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3055 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3057 spin_unlock_irqrestore(&il->sta_lock, flags);
3063 il4965_update_tkip_key(struct il_priv *il, struct il_rxon_context *ctx,
3064 struct ieee80211_key_conf *keyconf,
3065 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
3068 unsigned long flags;
3071 if (il_scan_cancel(il)) {
3072 /* cancel scan failed, just live w/ bad key and rely
3073 briefly on SW decryption */
3077 sta_id = il_sta_id_or_broadcast(il, ctx, sta);
3078 if (sta_id == IL_INVALID_STATION)
3081 spin_lock_irqsave(&il->sta_lock, flags);
3083 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3085 for (i = 0; i < 5; i++)
3086 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
3087 cpu_to_le16(phase1key[i]);
3089 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3090 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3092 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3094 spin_unlock_irqrestore(&il->sta_lock, flags);
3099 il4965_remove_dynamic_key(struct il_priv *il, struct il_rxon_context *ctx,
3100 struct ieee80211_key_conf *keyconf, u8 sta_id)
3102 unsigned long flags;
3105 struct il_addsta_cmd sta_cmd;
3107 lockdep_assert_held(&il->mutex);
3109 il->_4965.key_mapping_keys--;
3111 spin_lock_irqsave(&il->sta_lock, flags);
3112 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3113 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3115 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
3117 if (keyconf->keyidx != keyidx) {
3118 /* We need to remove a key with idx different that the one
3119 * in the uCode. This means that the key we need to remove has
3120 * been replaced by another one with different idx.
3121 * Don't do anything and return ok
3123 spin_unlock_irqrestore(&il->sta_lock, flags);
3127 if (il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) {
3128 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3130 spin_unlock_irqrestore(&il->sta_lock, flags);
3134 if (!test_and_clear_bit
3135 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
3136 IL_ERR("idx %d not used in uCode key table.\n",
3137 il->stations[sta_id].sta.key.key_offset);
3138 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3139 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
3140 il->stations[sta_id].sta.key.key_flags =
3141 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
3142 il->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET;
3143 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3144 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3146 if (il_is_rfkill(il)) {
3148 ("Not sending C_ADD_STA command because RFKILL enabled.\n");
3149 spin_unlock_irqrestore(&il->sta_lock, flags);
3152 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3153 sizeof(struct il_addsta_cmd));
3154 spin_unlock_irqrestore(&il->sta_lock, flags);
3156 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3160 il4965_set_dynamic_key(struct il_priv *il, struct il_rxon_context *ctx,
3161 struct ieee80211_key_conf *keyconf, u8 sta_id)
3165 lockdep_assert_held(&il->mutex);
3167 il->_4965.key_mapping_keys++;
3168 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3170 switch (keyconf->cipher) {
3171 case WLAN_CIPHER_SUITE_CCMP:
3173 il4965_set_ccmp_dynamic_key_info(il, ctx, keyconf, sta_id);
3175 case WLAN_CIPHER_SUITE_TKIP:
3177 il4965_set_tkip_dynamic_key_info(il, ctx, keyconf, sta_id);
3179 case WLAN_CIPHER_SUITE_WEP40:
3180 case WLAN_CIPHER_SUITE_WEP104:
3181 ret = il4965_set_wep_dynamic_key_info(il, ctx, keyconf, sta_id);
3184 IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3189 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3190 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
3196 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3198 * This adds the broadcast station into the driver's station table
3199 * and marks it driver active, so that it will be restored to the
3200 * device at the next best time.
3203 il4965_alloc_bcast_station(struct il_priv *il, struct il_rxon_context *ctx)
3205 struct il_link_quality_cmd *link_cmd;
3206 unsigned long flags;
3209 spin_lock_irqsave(&il->sta_lock, flags);
3210 sta_id = il_prep_station(il, ctx, il_bcast_addr, false, NULL);
3211 if (sta_id == IL_INVALID_STATION) {
3212 IL_ERR("Unable to prepare broadcast station\n");
3213 spin_unlock_irqrestore(&il->sta_lock, flags);
3218 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3219 il->stations[sta_id].used |= IL_STA_BCAST;
3220 spin_unlock_irqrestore(&il->sta_lock, flags);
3222 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3225 ("Unable to initialize rate scaling for bcast station.\n");
3229 spin_lock_irqsave(&il->sta_lock, flags);
3230 il->stations[sta_id].lq = link_cmd;
3231 spin_unlock_irqrestore(&il->sta_lock, flags);
3237 * il4965_update_bcast_station - update broadcast station's LQ command
3239 * Only used by iwl4965. Placed here to have all bcast station management
3243 il4965_update_bcast_station(struct il_priv *il, struct il_rxon_context *ctx)
3245 unsigned long flags;
3246 struct il_link_quality_cmd *link_cmd;
3247 u8 sta_id = il->hw_params.bcast_id;
3249 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3251 IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
3255 spin_lock_irqsave(&il->sta_lock, flags);
3256 if (il->stations[sta_id].lq)
3257 kfree(il->stations[sta_id].lq);
3259 D_INFO("Bcast sta rate scaling has not been initialized.\n");
3260 il->stations[sta_id].lq = link_cmd;
3261 spin_unlock_irqrestore(&il->sta_lock, flags);
3267 il4965_update_bcast_stations(struct il_priv *il)
3269 return il4965_update_bcast_station(il, &il->ctx);
3273 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3276 il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
3278 unsigned long flags;
3279 struct il_addsta_cmd sta_cmd;
3281 lockdep_assert_held(&il->mutex);
3283 /* Remove "disable" flag, to enable Tx for this TID */
3284 spin_lock_irqsave(&il->sta_lock, flags);
3285 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3286 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3287 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3288 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3289 sizeof(struct il_addsta_cmd));
3290 spin_unlock_irqrestore(&il->sta_lock, flags);
3292 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3296 il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3299 unsigned long flags;
3301 struct il_addsta_cmd sta_cmd;
3303 lockdep_assert_held(&il->mutex);
3305 sta_id = il_sta_id(sta);
3306 if (sta_id == IL_INVALID_STATION)
3309 spin_lock_irqsave(&il->sta_lock, flags);
3310 il->stations[sta_id].sta.station_flags_msk = 0;
3311 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3312 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
3313 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3314 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3315 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3316 sizeof(struct il_addsta_cmd));
3317 spin_unlock_irqrestore(&il->sta_lock, flags);
3319 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3323 il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
3325 unsigned long flags;
3327 struct il_addsta_cmd sta_cmd;
3329 lockdep_assert_held(&il->mutex);
3331 sta_id = il_sta_id(sta);
3332 if (sta_id == IL_INVALID_STATION) {
3333 IL_ERR("Invalid station for AGG tid %d\n", tid);
3337 spin_lock_irqsave(&il->sta_lock, flags);
3338 il->stations[sta_id].sta.station_flags_msk = 0;
3339 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3340 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
3341 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3342 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3343 sizeof(struct il_addsta_cmd));
3344 spin_unlock_irqrestore(&il->sta_lock, flags);
3346 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3350 il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3352 unsigned long flags;
3354 spin_lock_irqsave(&il->sta_lock, flags);
3355 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3356 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3357 il->stations[sta_id].sta.sta.modify_mask =
3358 STA_MODIFY_SLEEP_TX_COUNT_MSK;
3359 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3360 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3361 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3362 spin_unlock_irqrestore(&il->sta_lock, flags);
3367 il4965_update_chain_flags(struct il_priv *il)
3369 if (il->cfg->ops->hcmd->set_rxon_chain) {
3370 il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
3371 if (il->active.rx_chain != il->staging.rx_chain)
3372 il_commit_rxon(il, &il->ctx);
3377 il4965_clear_free_frames(struct il_priv *il)
3379 struct list_head *element;
3381 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
3383 while (!list_empty(&il->free_frames)) {
3384 element = il->free_frames.next;
3386 kfree(list_entry(element, struct il_frame, list));
3390 if (il->frames_count) {
3391 IL_WARN("%d frames still in use. Did we lose one?\n",
3393 il->frames_count = 0;
3397 static struct il_frame *
3398 il4965_get_free_frame(struct il_priv *il)
3400 struct il_frame *frame;
3401 struct list_head *element;
3402 if (list_empty(&il->free_frames)) {
3403 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3405 IL_ERR("Could not allocate frame!\n");
3413 element = il->free_frames.next;
3415 return list_entry(element, struct il_frame, list);
3419 il4965_free_frame(struct il_priv *il, struct il_frame *frame)
3421 memset(frame, 0, sizeof(*frame));
3422 list_add(&frame->list, &il->free_frames);
3426 il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3429 lockdep_assert_held(&il->mutex);
3431 if (!il->beacon_skb)
3434 if (il->beacon_skb->len > left)
3437 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
3439 return il->beacon_skb->len;
3442 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
3444 il4965_set_beacon_tim(struct il_priv *il,
3445 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3449 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3452 * The idx is relative to frame start but we start looking at the
3453 * variable-length part of the beacon.
3455 tim_idx = mgmt->u.beacon.variable - beacon;
3457 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3458 while ((tim_idx < (frame_size - 2)) &&
3459 (beacon[tim_idx] != WLAN_EID_TIM))
3460 tim_idx += beacon[tim_idx + 1] + 2;
3462 /* If TIM field was found, set variables */
3463 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3464 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
3465 tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
3467 IL_WARN("Unable to find TIM Element in beacon\n");
3471 il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
3473 struct il_tx_beacon_cmd *tx_beacon_cmd;
3478 * We have to set up the TX command, the TX Beacon command, and the
3482 lockdep_assert_held(&il->mutex);
3484 if (!il->beacon_ctx) {
3485 IL_ERR("trying to build beacon w/o beacon context!\n");
3489 /* Initialize memory */
3490 tx_beacon_cmd = &frame->u.beacon;
3491 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3493 /* Set up TX beacon contents */
3495 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3496 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
3497 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3502 /* Set up TX command fields */
3503 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
3504 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
3505 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
3506 tx_beacon_cmd->tx.tx_flags =
3507 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3508 TX_CMD_FLG_STA_RATE_MSK;
3510 /* Set up TX beacon command fields */
3511 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3514 /* Set up packet rate and flags */
3515 rate = il_get_lowest_plcp(il, il->beacon_ctx);
3516 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
3517 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
3518 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
3519 rate_flags |= RATE_MCS_CCK_MSK;
3520 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
3522 return sizeof(*tx_beacon_cmd) + frame_size;
3526 il4965_send_beacon_cmd(struct il_priv *il)
3528 struct il_frame *frame;
3529 unsigned int frame_size;
3532 frame = il4965_get_free_frame(il);
3534 IL_ERR("Could not obtain free frame buffer for beacon "
3539 frame_size = il4965_hw_get_beacon_cmd(il, frame);
3541 IL_ERR("Error configuring the beacon command\n");
3542 il4965_free_frame(il, frame);
3546 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
3548 il4965_free_frame(il, frame);
3553 static inline dma_addr_t
3554 il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
3556 struct il_tfd_tb *tb = &tfd->tbs[idx];
3558 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3559 if (sizeof(dma_addr_t) > sizeof(u32))
3561 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3568 il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
3570 struct il_tfd_tb *tb = &tfd->tbs[idx];
3572 return le16_to_cpu(tb->hi_n_len) >> 4;
3576 il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
3578 struct il_tfd_tb *tb = &tfd->tbs[idx];
3579 u16 hi_n_len = len << 4;
3581 put_unaligned_le32(addr, &tb->lo);
3582 if (sizeof(dma_addr_t) > sizeof(u32))
3583 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3585 tb->hi_n_len = cpu_to_le16(hi_n_len);
3587 tfd->num_tbs = idx + 1;
3591 il4965_tfd_get_num_tbs(struct il_tfd *tfd)
3593 return tfd->num_tbs & 0x1f;
3597 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
3598 * @il - driver ilate data
3601 * Does NOT advance any TFD circular buffer read/write idxes
3602 * Does NOT free the TFD itself (which is within circular buffer)
3605 il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
3607 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3609 struct pci_dev *dev = il->pci_dev;
3610 int idx = txq->q.read_ptr;
3614 tfd = &tfd_tmp[idx];
3616 /* Sanity check on number of chunks */
3617 num_tbs = il4965_tfd_get_num_tbs(tfd);
3619 if (num_tbs >= IL_NUM_OF_TBS) {
3620 IL_ERR("Too many chunks: %i\n", num_tbs);
3621 /* @todo issue fatal error, it is quite serious situation */
3627 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3628 dma_unmap_len(&txq->meta[idx], len),
3629 PCI_DMA_BIDIRECTIONAL);
3631 /* Unmap chunks, if any. */
3632 for (i = 1; i < num_tbs; i++)
3633 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
3634 il4965_tfd_tb_get_len(tfd, i),
3639 struct sk_buff *skb;
3641 skb = txq->txb[txq->q.read_ptr].skb;
3643 /* can be called from irqs-disabled context */
3645 dev_kfree_skb_any(skb);
3646 txq->txb[txq->q.read_ptr].skb = NULL;
3652 il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3653 dma_addr_t addr, u16 len, u8 reset, u8 pad)
3656 struct il_tfd *tfd, *tfd_tmp;
3660 tfd_tmp = (struct il_tfd *)txq->tfds;
3661 tfd = &tfd_tmp[q->write_ptr];
3664 memset(tfd, 0, sizeof(*tfd));
3666 num_tbs = il4965_tfd_get_num_tbs(tfd);
3668 /* Each TFD can point to a maximum 20 Tx buffers */
3669 if (num_tbs >= IL_NUM_OF_TBS) {
3670 IL_ERR("Error can not send more than %d chunks\n",
3675 BUG_ON(addr & ~DMA_BIT_MASK(36));
3676 if (unlikely(addr & ~IL_TX_DMA_MASK))
3677 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
3679 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
3685 * Tell nic where to find circular buffer of Tx Frame Descriptors for
3686 * given Tx queue, and enable the DMA channel used for that queue.
3688 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3689 * channels supported in hardware.
3692 il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
3694 int txq_id = txq->q.id;
3696 /* Circular buffer (TFD queue in DRAM) physical base address */
3697 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
3702 /******************************************************************************
3704 * Generic RX handler implementations
3706 ******************************************************************************/
3708 il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
3710 struct il_rx_pkt *pkt = rxb_addr(rxb);
3711 struct il_alive_resp *palive;
3712 struct delayed_work *pwork;
3714 palive = &pkt->u.alive_frame;
3716 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
3717 palive->is_valid, palive->ver_type, palive->ver_subtype);
3719 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3720 D_INFO("Initialization Alive received.\n");
3721 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
3722 sizeof(struct il_init_alive_resp));
3723 pwork = &il->init_alive_start;
3725 D_INFO("Runtime Alive received.\n");
3726 memcpy(&il->card_alive, &pkt->u.alive_frame,
3727 sizeof(struct il_alive_resp));
3728 pwork = &il->alive_start;
3731 /* We delay the ALIVE response by 5ms to
3732 * give the HW RF Kill time to activate... */
3733 if (palive->is_valid == UCODE_VALID_OK)
3734 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
3736 IL_WARN("uCode did not respond OK.\n");
3740 * il4965_bg_stats_periodic - Timer callback to queue stats
3742 * This callback is provided in order to send a stats request.
3744 * This timer function is continually reset to execute within
3745 * REG_RECALIB_PERIOD seconds since the last N_STATS
3746 * was received. We need to ensure we receive the stats in order
3747 * to update the temperature used for calibrating the TXPOWER.
3750 il4965_bg_stats_periodic(unsigned long data)
3752 struct il_priv *il = (struct il_priv *)data;
3754 if (test_bit(S_EXIT_PENDING, &il->status))
3757 /* dont send host command if rf-kill is on */
3758 if (!il_is_ready_rf(il))
3761 il_send_stats_request(il, CMD_ASYNC, false);
3765 il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
3767 struct il_rx_pkt *pkt = rxb_addr(rxb);
3768 struct il4965_beacon_notif *beacon =
3769 (struct il4965_beacon_notif *)pkt->u.raw;
3770 #ifdef CONFIG_IWLEGACY_DEBUG
3771 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
3773 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
3774 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
3775 beacon->beacon_notify_hdr.failure_frame,
3776 le32_to_cpu(beacon->ibss_mgr_status),
3777 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
3779 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
3783 il4965_perform_ct_kill_task(struct il_priv *il)
3785 unsigned long flags;
3787 D_POWER("Stop all queues\n");
3789 if (il->mac80211_registered)
3790 ieee80211_stop_queues(il->hw);
3792 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
3793 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
3794 _il_rd(il, CSR_UCODE_DRV_GP1);
3796 spin_lock_irqsave(&il->reg_lock, flags);
3797 if (!_il_grab_nic_access(il))
3798 _il_release_nic_access(il);
3799 spin_unlock_irqrestore(&il->reg_lock, flags);
3802 /* Handle notification from uCode that card's power state is changing
3803 * due to software, hardware, or critical temperature RFKILL */
3805 il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
3807 struct il_rx_pkt *pkt = rxb_addr(rxb);
3808 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3809 unsigned long status = il->status;
3811 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
3812 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3813 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
3814 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
3816 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
3818 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
3819 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3821 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3823 if (!(flags & RXON_CARD_DISABLED)) {
3824 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
3825 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3826 il_wr(il, HBUS_TARG_MBX_C,
3827 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3831 if (flags & CT_CARD_DISABLED)
3832 il4965_perform_ct_kill_task(il);
3834 if (flags & HW_CARD_DISABLED)
3835 set_bit(S_RF_KILL_HW, &il->status);
3837 clear_bit(S_RF_KILL_HW, &il->status);
3839 if (!(flags & RXON_CARD_DISABLED))
3842 if ((test_bit(S_RF_KILL_HW, &status) !=
3843 test_bit(S_RF_KILL_HW, &il->status)))
3844 wiphy_rfkill_set_hw_state(il->hw->wiphy,
3845 test_bit(S_RF_KILL_HW, &il->status));
3847 wake_up(&il->wait_command_queue);
3851 * il4965_setup_handlers - Initialize Rx handler callbacks
3853 * Setup the RX handlers for each of the reply types sent from the uCode
3856 * This function chains into the hardware specific files for them to setup
3857 * any hardware specific handlers as well.
3860 il4965_setup_handlers(struct il_priv *il)
3862 il->handlers[N_ALIVE] = il4965_hdl_alive;
3863 il->handlers[N_ERROR] = il_hdl_error;
3864 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
3865 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
3866 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
3867 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
3868 il->handlers[N_BEACON] = il4965_hdl_beacon;
3871 * The same handler is used for both the REPLY to a discrete
3872 * stats request from the host as well as for the periodic
3873 * stats notifications (after received beacons) from the uCode.
3875 il->handlers[C_STATS] = il4965_hdl_c_stats;
3876 il->handlers[N_STATS] = il4965_hdl_stats;
3878 il_setup_rx_scan_handlers(il);
3880 /* status change handler */
3881 il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
3883 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
3885 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
3886 il->handlers[N_RX_MPDU] = il4965_hdl_rx;
3888 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
3889 /* Set up hardware specific Rx handlers */
3890 il->cfg->ops->lib->handler_setup(il);
3894 * il4965_rx_handle - Main entry function for receiving responses from uCode
3896 * Uses the il->handlers callback function array to invoke
3897 * the appropriate handlers, including command responses,
3898 * frame-received notifications, and other notifications.
3901 il4965_rx_handle(struct il_priv *il)
3903 struct il_rx_buf *rxb;
3904 struct il_rx_pkt *pkt;
3905 struct il_rx_queue *rxq = &il->rxq;
3908 unsigned long flags;
3913 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
3914 * buffer that the driver may process (last buffer filled by ucode). */
3915 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
3918 /* Rx interrupt, but nothing sent from uCode */
3920 D_RX("r = %d, i = %d\n", r, i);
3922 /* calculate total frames need to be restock after handling RX */
3923 total_empty = r - rxq->write_actual;
3924 if (total_empty < 0)
3925 total_empty += RX_QUEUE_SIZE;
3927 if (total_empty > (RX_QUEUE_SIZE / 2))
3933 rxb = rxq->queue[i];
3935 /* If an RXB doesn't have a Rx queue slot associated with it,
3936 * then a bug has been introduced in the queue refilling
3937 * routines -- catch it here */
3938 BUG_ON(rxb == NULL);
3940 rxq->queue[i] = NULL;
3942 pci_unmap_page(il->pci_dev, rxb->page_dma,
3943 PAGE_SIZE << il->hw_params.rx_page_order,
3944 PCI_DMA_FROMDEVICE);
3945 pkt = rxb_addr(rxb);
3947 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
3948 len += sizeof(u32); /* account for status word */
3950 /* Reclaim a command buffer only if this packet is a response
3951 * to a (driver-originated) command.
3952 * If the packet (e.g. Rx frame) originated from uCode,
3953 * there is no command buffer to reclaim.
3954 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3955 * but apparently a few don't get set; catch them here. */
3956 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3957 (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) &&
3958 (pkt->hdr.cmd != N_RX_MPDU) &&
3959 (pkt->hdr.cmd != N_COMPRESSED_BA) &&
3960 (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX);
3962 /* Based on type of command response or notification,
3963 * handle those that need handling via function in
3964 * handlers table. See il4965_setup_handlers() */
3965 if (il->handlers[pkt->hdr.cmd]) {
3966 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
3967 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3968 il->isr_stats.handlers[pkt->hdr.cmd]++;
3969 il->handlers[pkt->hdr.cmd] (il, rxb);
3971 /* No handling needed */
3972 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
3973 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3977 * XXX: After here, we should always check rxb->page
3978 * against NULL before touching it or its virtual
3979 * memory (pkt). Because some handler might have
3980 * already taken or freed the pages.
3984 /* Invoke any callbacks, transfer the buffer to caller,
3985 * and fire off the (possibly) blocking il_send_cmd()
3986 * as we reclaim the driver command queue */
3988 il_tx_cmd_complete(il, rxb);
3990 IL_WARN("Claim null rxb?\n");
3993 /* Reuse the page if possible. For notification packets and
3994 * SKBs that fail to Rx correctly, add them back into the
3995 * rx_free list for reuse later. */
3996 spin_lock_irqsave(&rxq->lock, flags);
3997 if (rxb->page != NULL) {
3999 pci_map_page(il->pci_dev, rxb->page, 0,
4000 PAGE_SIZE << il->hw_params.
4001 rx_page_order, PCI_DMA_FROMDEVICE);
4002 list_add_tail(&rxb->list, &rxq->rx_free);
4005 list_add_tail(&rxb->list, &rxq->rx_used);
4007 spin_unlock_irqrestore(&rxq->lock, flags);
4009 i = (i + 1) & RX_QUEUE_MASK;
4010 /* If there are a lot of unused frames,
4011 * restock the Rx queue so ucode wont assert. */
4016 il4965_rx_replenish_now(il);
4022 /* Backtrack one entry */
4025 il4965_rx_replenish_now(il);
4027 il4965_rx_queue_restock(il);
4030 /* call this function to flush any scheduled tasklet */
4032 il4965_synchronize_irq(struct il_priv *il)
4034 /* wait to make sure we flush pending tasklet */
4035 synchronize_irq(il->pci_dev->irq);
4036 tasklet_kill(&il->irq_tasklet);
4040 il4965_irq_tasklet(struct il_priv *il)
4042 u32 inta, handled = 0;
4044 unsigned long flags;
4046 #ifdef CONFIG_IWLEGACY_DEBUG
4050 spin_lock_irqsave(&il->lock, flags);
4052 /* Ack/clear/reset pending uCode interrupts.
4053 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4054 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
4055 inta = _il_rd(il, CSR_INT);
4056 _il_wr(il, CSR_INT, inta);
4058 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4059 * Any new interrupts that happen after this, either while we're
4060 * in this tasklet, or later, will show up in next ISR/tasklet. */
4061 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4062 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4064 #ifdef CONFIG_IWLEGACY_DEBUG
4065 if (il_get_debug_level(il) & IL_DL_ISR) {
4066 /* just for debug */
4067 inta_mask = _il_rd(il, CSR_INT_MASK);
4068 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4069 inta_mask, inta_fh);
4073 spin_unlock_irqrestore(&il->lock, flags);
4075 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4076 * atomic, make sure that inta covers all the interrupts that
4077 * we've discovered, even if FH interrupt came in just after
4078 * reading CSR_INT. */
4079 if (inta_fh & CSR49_FH_INT_RX_MASK)
4080 inta |= CSR_INT_BIT_FH_RX;
4081 if (inta_fh & CSR49_FH_INT_TX_MASK)
4082 inta |= CSR_INT_BIT_FH_TX;
4084 /* Now service all interrupt bits discovered above. */
4085 if (inta & CSR_INT_BIT_HW_ERR) {
4086 IL_ERR("Hardware error detected. Restarting.\n");
4088 /* Tell the device to stop sending interrupts */
4089 il_disable_interrupts(il);
4092 il_irq_handle_error(il);
4094 handled |= CSR_INT_BIT_HW_ERR;
4098 #ifdef CONFIG_IWLEGACY_DEBUG
4099 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4100 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4101 if (inta & CSR_INT_BIT_SCD) {
4102 D_ISR("Scheduler finished to transmit "
4103 "the frame/frames.\n");
4104 il->isr_stats.sch++;
4107 /* Alive notification via Rx interrupt will do the real work */
4108 if (inta & CSR_INT_BIT_ALIVE) {
4109 D_ISR("Alive interrupt\n");
4110 il->isr_stats.alive++;
4114 /* Safely ignore these bits for debug checks below */
4115 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4117 /* HW RF KILL switch toggled */
4118 if (inta & CSR_INT_BIT_RF_KILL) {
4121 (_il_rd(il, CSR_GP_CNTRL) &
4122 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4125 IL_WARN("RF_KILL bit toggled to %s.\n",
4126 hw_rf_kill ? "disable radio" : "enable radio");
4128 il->isr_stats.rfkill++;
4130 /* driver only loads ucode once setting the interface up.
4131 * the driver allows loading the ucode even if the radio
4132 * is killed. Hence update the killswitch state here. The
4133 * rfkill handler will care about restarting if needed.
4135 if (!test_bit(S_ALIVE, &il->status)) {
4137 set_bit(S_RF_KILL_HW, &il->status);
4139 clear_bit(S_RF_KILL_HW, &il->status);
4140 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
4143 handled |= CSR_INT_BIT_RF_KILL;
4146 /* Chip got too hot and stopped itself */
4147 if (inta & CSR_INT_BIT_CT_KILL) {
4148 IL_ERR("Microcode CT kill error detected.\n");
4149 il->isr_stats.ctkill++;
4150 handled |= CSR_INT_BIT_CT_KILL;
4153 /* Error detected by uCode */
4154 if (inta & CSR_INT_BIT_SW_ERR) {
4155 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4158 il_irq_handle_error(il);
4159 handled |= CSR_INT_BIT_SW_ERR;
4163 * uCode wakes up after power-down sleep.
4164 * Tell device about any new tx or host commands enqueued,
4165 * and about any Rx buffers made available while asleep.
4167 if (inta & CSR_INT_BIT_WAKEUP) {
4168 D_ISR("Wakeup interrupt\n");
4169 il_rx_queue_update_write_ptr(il, &il->rxq);
4170 for (i = 0; i < il->hw_params.max_txq_num; i++)
4171 il_txq_update_write_ptr(il, &il->txq[i]);
4172 il->isr_stats.wakeup++;
4173 handled |= CSR_INT_BIT_WAKEUP;
4176 /* All uCode command responses, including Tx command responses,
4177 * Rx "responses" (frame-received notification), and other
4178 * notifications from uCode come through here*/
4179 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
4180 il4965_rx_handle(il);
4182 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4185 /* This "Tx" DMA channel is used only for loading uCode */
4186 if (inta & CSR_INT_BIT_FH_TX) {
4187 D_ISR("uCode load interrupt\n");
4189 handled |= CSR_INT_BIT_FH_TX;
4190 /* Wake up uCode load routine, now that load is complete */
4191 il->ucode_write_complete = 1;
4192 wake_up(&il->wait_command_queue);
4195 if (inta & ~handled) {
4196 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4197 il->isr_stats.unhandled++;
4200 if (inta & ~(il->inta_mask)) {
4201 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
4202 inta & ~il->inta_mask);
4203 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
4206 /* Re-enable all interrupts */
4207 /* only Re-enable if disabled by irq */
4208 if (test_bit(S_INT_ENABLED, &il->status))
4209 il_enable_interrupts(il);
4210 /* Re-enable RF_KILL if it occurred */
4211 else if (handled & CSR_INT_BIT_RF_KILL)
4212 il_enable_rfkill_int(il);
4214 #ifdef CONFIG_IWLEGACY_DEBUG
4215 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4216 inta = _il_rd(il, CSR_INT);
4217 inta_mask = _il_rd(il, CSR_INT_MASK);
4218 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4219 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4220 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4225 /*****************************************************************************
4229 *****************************************************************************/
4231 #ifdef CONFIG_IWLEGACY_DEBUG
4234 * The following adds a new attribute to the sysfs representation
4235 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4236 * used for controlling the debug level.
4238 * See the level definitions in iwl for details.
4240 * The debug_level being managed using sysfs below is a per device debug
4241 * level that is used instead of the global debug level if it (the per
4242 * device debug level) is set.
4245 il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4248 struct il_priv *il = dev_get_drvdata(d);
4249 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
4253 il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4254 const char *buf, size_t count)
4256 struct il_priv *il = dev_get_drvdata(d);
4260 ret = strict_strtoul(buf, 0, &val);
4262 IL_ERR("%s is not in hex or decimal form.\n", buf);
4264 il->debug_level = val;
4265 if (il_alloc_traffic_mem(il))
4266 IL_ERR("Not enough memory to generate traffic log\n");
4268 return strnlen(buf, count);
4271 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4272 il4965_store_debug_level);
4274 #endif /* CONFIG_IWLEGACY_DEBUG */
4277 il4965_show_temperature(struct device *d, struct device_attribute *attr,
4280 struct il_priv *il = dev_get_drvdata(d);
4282 if (!il_is_alive(il))
4285 return sprintf(buf, "%d\n", il->temperature);
4288 static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
4291 il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
4293 struct il_priv *il = dev_get_drvdata(d);
4295 if (!il_is_ready_rf(il))
4296 return sprintf(buf, "off\n");
4298 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
4302 il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4303 const char *buf, size_t count)
4305 struct il_priv *il = dev_get_drvdata(d);
4309 ret = strict_strtoul(buf, 10, &val);
4311 IL_INFO("%s is not in decimal form.\n", buf);
4313 ret = il_set_tx_power(il, val, false);
4315 IL_ERR("failed setting tx power (0x%d).\n", ret);
4322 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4323 il4965_store_tx_power);
4325 static struct attribute *il_sysfs_entries[] = {
4326 &dev_attr_temperature.attr,
4327 &dev_attr_tx_power.attr,
4328 #ifdef CONFIG_IWLEGACY_DEBUG
4329 &dev_attr_debug_level.attr,
4334 static struct attribute_group il_attribute_group = {
4335 .name = NULL, /* put in device directory */
4336 .attrs = il_sysfs_entries,
4339 /******************************************************************************
4341 * uCode download functions
4343 ******************************************************************************/
4346 il4965_dealloc_ucode_pci(struct il_priv *il)
4348 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4349 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4350 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4351 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4352 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4353 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
4357 il4965_nic_start(struct il_priv *il)
4359 /* Remove all resets to allow NIC to operate */
4360 _il_wr(il, CSR_RESET, 0);
4363 static void il4965_ucode_callback(const struct firmware *ucode_raw,
4365 static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
4367 static int __must_check
4368 il4965_request_firmware(struct il_priv *il, bool first)
4370 const char *name_pre = il->cfg->fw_name_pre;
4374 il->fw_idx = il->cfg->ucode_api_max;
4375 sprintf(tag, "%d", il->fw_idx);
4378 sprintf(tag, "%d", il->fw_idx);
4381 if (il->fw_idx < il->cfg->ucode_api_min) {
4382 IL_ERR("no suitable firmware found!\n");
4386 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
4388 D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
4390 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4391 &il->pci_dev->dev, GFP_KERNEL, il,
4392 il4965_ucode_callback);
4395 struct il4965_firmware_pieces {
4396 const void *inst, *data, *init, *init_data, *boot;
4397 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4401 il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4402 struct il4965_firmware_pieces *pieces)
4404 struct il_ucode_header *ucode = (void *)ucode_raw->data;
4405 u32 api_ver, hdr_size;
4408 il->ucode_ver = le32_to_cpu(ucode->ver);
4409 api_ver = IL_UCODE_API(il->ucode_ver);
4417 if (ucode_raw->size < hdr_size) {
4418 IL_ERR("File size too small!\n");
4421 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4422 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4423 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
4424 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
4425 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4426 src = ucode->v1.data;
4430 /* Verify size of file vs. image size info in file's header */
4431 if (ucode_raw->size !=
4432 hdr_size + pieces->inst_size + pieces->data_size +
4433 pieces->init_size + pieces->init_data_size + pieces->boot_size) {
4435 IL_ERR("uCode file size %d does not match expected size\n",
4436 (int)ucode_raw->size);
4441 src += pieces->inst_size;
4443 src += pieces->data_size;
4445 src += pieces->init_size;
4446 pieces->init_data = src;
4447 src += pieces->init_data_size;
4449 src += pieces->boot_size;
4455 * il4965_ucode_callback - callback when firmware was loaded
4457 * If loaded successfully, copies the firmware into buffers
4458 * for the card to fetch (via DMA).
4461 il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
4463 struct il_priv *il = context;
4464 struct il_ucode_header *ucode;
4466 struct il4965_firmware_pieces pieces;
4467 const unsigned int api_max = il->cfg->ucode_api_max;
4468 const unsigned int api_min = il->cfg->ucode_api_min;
4471 u32 max_probe_length = 200;
4472 u32 standard_phy_calibration_size =
4473 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
4475 memset(&pieces, 0, sizeof(pieces));
4478 if (il->fw_idx <= il->cfg->ucode_api_max)
4479 IL_ERR("request for firmware file '%s' failed.\n",
4484 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4487 /* Make sure that we got at least the API version number */
4488 if (ucode_raw->size < 4) {
4489 IL_ERR("File size way too small!\n");
4493 /* Data from ucode file: header followed by uCode images */
4494 ucode = (struct il_ucode_header *)ucode_raw->data;
4496 err = il4965_load_firmware(il, ucode_raw, &pieces);
4501 api_ver = IL_UCODE_API(il->ucode_ver);
4504 * api_ver should match the api version forming part of the
4505 * firmware filename ... but we don't check for that and only rely
4506 * on the API version read from firmware header from here on forward
4508 if (api_ver < api_min || api_ver > api_max) {
4509 IL_ERR("Driver unable to support your firmware API. "
4510 "Driver supports v%u, firmware is v%u.\n", api_max,
4515 if (api_ver != api_max)
4516 IL_ERR("Firmware has old API version. Expected v%u, "
4517 "got v%u. New firmware can be obtained "
4518 "from http://www.intellinuxwireless.org.\n", api_max,
4521 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
4522 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4523 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
4525 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4526 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4527 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
4528 IL_UCODE_SERIAL(il->ucode_ver));
4531 * For any of the failures below (before allocating pci memory)
4532 * we will try to load a version with a smaller API -- maybe the
4533 * user just got a corrupted version of the latest API.
4536 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4537 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4538 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4539 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4540 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4541 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
4543 /* Verify that uCode images will fit in card's SRAM */
4544 if (pieces.inst_size > il->hw_params.max_inst_size) {
4545 IL_ERR("uCode instr len %Zd too large to fit in\n",
4550 if (pieces.data_size > il->hw_params.max_data_size) {
4551 IL_ERR("uCode data len %Zd too large to fit in\n",
4556 if (pieces.init_size > il->hw_params.max_inst_size) {
4557 IL_ERR("uCode init instr len %Zd too large to fit in\n",
4562 if (pieces.init_data_size > il->hw_params.max_data_size) {
4563 IL_ERR("uCode init data len %Zd too large to fit in\n",
4564 pieces.init_data_size);
4568 if (pieces.boot_size > il->hw_params.max_bsm_size) {
4569 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
4574 /* Allocate ucode buffers for card's bus-master loading ... */
4576 /* Runtime instructions and 2 copies of data:
4577 * 1) unmodified from disk
4578 * 2) backup cache for save/restore during power-downs */
4579 il->ucode_code.len = pieces.inst_size;
4580 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
4582 il->ucode_data.len = pieces.data_size;
4583 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
4585 il->ucode_data_backup.len = pieces.data_size;
4586 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
4588 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4589 !il->ucode_data_backup.v_addr)
4592 /* Initialization instructions and data */
4593 if (pieces.init_size && pieces.init_data_size) {
4594 il->ucode_init.len = pieces.init_size;
4595 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
4597 il->ucode_init_data.len = pieces.init_data_size;
4598 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
4600 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
4604 /* Bootstrap (instructions only, no data) */
4605 if (pieces.boot_size) {
4606 il->ucode_boot.len = pieces.boot_size;
4607 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
4609 if (!il->ucode_boot.v_addr)
4613 /* Now that we can no longer fail, copy information */
4615 il->sta_key_max_num = STA_KEY_MAX_NUM;
4617 /* Copy images into buffers for card's bus-master reads ... */
4619 /* Runtime instructions (first block of data in file) */
4620 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
4622 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
4624 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
4625 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
4629 * NOTE: Copy into backup buffer will be done in il_up()
4631 D_INFO("Copying (but not loading) uCode data len %Zd\n",
4633 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4634 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
4636 /* Initialization instructions */
4637 if (pieces.init_size) {
4638 D_INFO("Copying (but not loading) init instr len %Zd\n",
4640 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
4643 /* Initialization data */
4644 if (pieces.init_data_size) {
4645 D_INFO("Copying (but not loading) init data len %Zd\n",
4646 pieces.init_data_size);
4647 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
4648 pieces.init_data_size);
4651 /* Bootstrap instructions */
4652 D_INFO("Copying (but not loading) boot instr len %Zd\n",
4654 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
4657 * figure out the offset of chain noise reset and gain commands
4658 * base on the size of standard phy calibration commands table size
4660 il->_4965.phy_calib_chain_noise_reset_cmd =
4661 standard_phy_calibration_size;
4662 il->_4965.phy_calib_chain_noise_gain_cmd =
4663 standard_phy_calibration_size + 1;
4665 /**************************************************
4666 * This is still part of probe() in a sense...
4668 * 9. Setup and register with mac80211 and debugfs
4669 **************************************************/
4670 err = il4965_mac_setup_register(il, max_probe_length);
4674 err = il_dbgfs_register(il, DRV_NAME);
4676 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4679 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
4681 IL_ERR("failed to create sysfs device attributes\n");
4685 /* We have our copies now, allow OS release its copies */
4686 release_firmware(ucode_raw);
4687 complete(&il->_4965.firmware_loading_complete);
4691 /* try next, if any */
4692 if (il4965_request_firmware(il, false))
4694 release_firmware(ucode_raw);
4698 IL_ERR("failed to allocate pci memory\n");
4699 il4965_dealloc_ucode_pci(il);
4701 complete(&il->_4965.firmware_loading_complete);
4702 device_release_driver(&il->pci_dev->dev);
4703 release_firmware(ucode_raw);
4706 static const char *const desc_lookup_text[] = {
4711 "NMI_INTERRUPT_WDG",
4715 "HW_ERROR_TUNE_LOCK",
4716 "HW_ERROR_TEMPERATURE",
4717 "ILLEGAL_CHAN_FREQ",
4720 "NMI_INTERRUPT_HOST",
4721 "NMI_INTERRUPT_ACTION_PT",
4722 "NMI_INTERRUPT_UNKNOWN",
4723 "UCODE_VERSION_MISMATCH",
4724 "HW_ERROR_ABS_LOCK",
4725 "HW_ERROR_CAL_LOCK_FAIL",
4726 "NMI_INTERRUPT_INST_ACTION_PT",
4727 "NMI_INTERRUPT_DATA_ACTION_PT",
4729 "NMI_INTERRUPT_TRM",
4730 "NMI_INTERRUPT_BREAK_POINT",
4740 } advanced_lookup[] = {
4742 "NMI_INTERRUPT_WDG", 0x34}, {
4743 "SYSASSERT", 0x35}, {
4744 "UCODE_VERSION_MISMATCH", 0x37}, {
4745 "BAD_COMMAND", 0x38}, {
4746 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
4747 "FATAL_ERROR", 0x3D}, {
4748 "NMI_TRM_HW_ERR", 0x46}, {
4749 "NMI_INTERRUPT_TRM", 0x4C}, {
4750 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
4751 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
4752 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
4753 "NMI_INTERRUPT_HOST", 0x66}, {
4754 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
4755 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
4756 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
4757 "ADVANCED_SYSASSERT", 0},};
4760 il4965_desc_lookup(u32 num)
4763 int max = ARRAY_SIZE(desc_lookup_text);
4766 return desc_lookup_text[num];
4768 max = ARRAY_SIZE(advanced_lookup) - 1;
4769 for (i = 0; i < max; i++) {
4770 if (advanced_lookup[i].num == num)
4773 return advanced_lookup[i].name;
4776 #define ERROR_START_OFFSET (1 * sizeof(u32))
4777 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
4780 il4965_dump_nic_error_log(struct il_priv *il)
4783 u32 desc, time, count, base, data1;
4784 u32 blink1, blink2, ilink1, ilink2;
4787 if (il->ucode_type == UCODE_INIT)
4788 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
4790 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
4792 if (!il->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
4793 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
4794 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
4798 count = il_read_targ_mem(il, base);
4800 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4801 IL_ERR("Start IWL Error Log Dump:\n");
4802 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
4805 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
4806 il->isr_stats.err_code = desc;
4807 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
4808 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
4809 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
4810 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
4811 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
4812 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
4813 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
4814 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
4815 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
4816 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
4819 "data1 data2 line\n");
4820 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
4821 il4965_desc_lookup(desc), desc, time, data1, data2, line);
4822 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
4823 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
4824 blink2, ilink1, ilink2, hcmd);
4828 il4965_rf_kill_ct_config(struct il_priv *il)
4830 struct il_ct_kill_config cmd;
4831 unsigned long flags;
4834 spin_lock_irqsave(&il->lock, flags);
4835 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
4836 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
4837 spin_unlock_irqrestore(&il->lock, flags);
4839 cmd.critical_temperature_R =
4840 cpu_to_le32(il->hw_params.ct_kill_threshold);
4842 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
4844 IL_ERR("C_CT_KILL_CONFIG failed\n");
4846 D_INFO("C_CT_KILL_CONFIG " "succeeded, "
4847 "critical temperature is %d\n",
4848 il->hw_params.ct_kill_threshold);
4851 static const s8 default_queue_to_tx_fifo[] = {
4861 #define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
4864 il4965_alive_notify(struct il_priv *il)
4867 unsigned long flags;
4871 spin_lock_irqsave(&il->lock, flags);
4873 /* Clear 4965's internal Tx Scheduler data base */
4874 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
4875 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
4876 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
4877 il_write_targ_mem(il, a, 0);
4878 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
4879 il_write_targ_mem(il, a, 0);
4883 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
4885 il_write_targ_mem(il, a, 0);
4887 /* Tel 4965 where to find Tx byte count tables */
4888 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
4890 /* Enable DMA channel */
4891 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
4892 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
4893 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
4894 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
4896 /* Update FH chicken bits */
4897 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
4898 il_wr(il, FH49_TX_CHICKEN_BITS_REG,
4899 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
4901 /* Disable chain mode for all queues */
4902 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
4904 /* Initialize each Tx queue (including the command queue) */
4905 for (i = 0; i < il->hw_params.max_txq_num; i++) {
4907 /* TFD circular buffer read/write idxes */
4908 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
4909 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
4911 /* Max Tx Window size for Scheduler-ACK mode */
4912 il_write_targ_mem(il,
4914 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
4916 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4917 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4920 il_write_targ_mem(il,
4922 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
4925 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
4926 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4929 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
4930 (1 << il->hw_params.max_txq_num) - 1);
4932 /* Activate all Tx DMA/FIFO channels */
4933 il4965_txq_set_sched(il, IL_MASK(0, 6));
4935 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
4937 /* make sure all queue are not stopped */
4938 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
4939 for (i = 0; i < 4; i++)
4940 atomic_set(&il->queue_stop_count[i], 0);
4942 /* reset to 0 to enable all the queue first */
4943 il->txq_ctx_active_msk = 0;
4944 /* Map each Tx/cmd queue to its corresponding fifo */
4945 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
4947 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
4948 int ac = default_queue_to_tx_fifo[i];
4950 il_txq_ctx_activate(il, i);
4952 if (ac == IL_TX_FIFO_UNUSED)
4955 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
4958 spin_unlock_irqrestore(&il->lock, flags);
4964 * il4965_alive_start - called after N_ALIVE notification received
4965 * from protocol/runtime uCode (initialization uCode's
4966 * Alive gets handled by il_init_alive_start()).
4969 il4965_alive_start(struct il_priv *il)
4972 struct il_rxon_context *ctx = &il->ctx;
4974 D_INFO("Runtime Alive received.\n");
4976 if (il->card_alive.is_valid != UCODE_VALID_OK) {
4977 /* We had an error bringing up the hardware, so take it
4978 * all the way back down so we can try again */
4979 D_INFO("Alive failed.\n");
4983 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
4984 * This is a paranoid check, because we would not have gotten the
4985 * "runtime" alive if code weren't properly loaded. */
4986 if (il4965_verify_ucode(il)) {
4987 /* Runtime instruction load was bad;
4988 * take it all the way back down so we can try again */
4989 D_INFO("Bad runtime uCode load.\n");
4993 ret = il4965_alive_notify(il);
4995 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
4999 /* After the ALIVE response, we can send host commands to the uCode */
5000 set_bit(S_ALIVE, &il->status);
5002 /* Enable watchdog to monitor the driver tx queues */
5003 il_setup_watchdog(il);
5005 if (il_is_rfkill(il))
5008 ieee80211_wake_queues(il->hw);
5010 il->active_rate = RATES_MASK;
5012 if (il_is_associated(il)) {
5013 struct il_rxon_cmd *active_rxon =
5014 (struct il_rxon_cmd *)&il->active;
5015 /* apply any changes in staging */
5016 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
5017 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5019 /* Initialize our rx_config data */
5020 il_connection_init_rx_config(il, &il->ctx);
5022 if (il->cfg->ops->hcmd->set_rxon_chain)
5023 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
5026 /* Configure bluetooth coexistence if enabled */
5027 il_send_bt_config(il);
5029 il4965_reset_run_time_calib(il);
5031 set_bit(S_READY, &il->status);
5033 /* Configure the adapter for unassociated operation */
5034 il_commit_rxon(il, ctx);
5036 /* At this point, the NIC is initialized and operational */
5037 il4965_rf_kill_ct_config(il);
5039 D_INFO("ALIVE processing complete.\n");
5040 wake_up(&il->wait_command_queue);
5042 il_power_update_mode(il, true);
5043 D_INFO("Updated power mode\n");
5048 queue_work(il->workqueue, &il->restart);
5051 static void il4965_cancel_deferred_work(struct il_priv *il);
5054 __il4965_down(struct il_priv *il)
5056 unsigned long flags;
5059 D_INFO(DRV_NAME " is going down\n");
5061 il_scan_cancel_timeout(il, 200);
5063 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
5065 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
5066 * to prevent rearm timer */
5067 del_timer_sync(&il->watchdog);
5069 il_clear_ucode_stations(il, NULL);
5071 /* FIXME: race conditions ? */
5072 spin_lock_irq(&il->sta_lock);
5074 * Remove all key information that is not stored as part
5075 * of station information since mac80211 may not have had
5076 * a chance to remove all the keys. When device is
5077 * reconfigured by mac80211 after an error all keys will
5080 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5081 il->_4965.key_mapping_keys = 0;
5082 spin_unlock_irq(&il->sta_lock);
5084 il_dealloc_bcast_stations(il);
5085 il_clear_driver_stations(il);
5087 /* Unblock any waiting calls */
5088 wake_up_all(&il->wait_command_queue);
5090 /* Wipe out the EXIT_PENDING status bit if we are not actually
5091 * exiting the module */
5093 clear_bit(S_EXIT_PENDING, &il->status);
5095 /* stop and reset the on-board processor */
5096 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
5098 /* tell the device to stop sending interrupts */
5099 spin_lock_irqsave(&il->lock, flags);
5100 il_disable_interrupts(il);
5101 spin_unlock_irqrestore(&il->lock, flags);
5102 il4965_synchronize_irq(il);
5104 if (il->mac80211_registered)
5105 ieee80211_stop_queues(il->hw);
5107 /* If we have not previously called il_init() then
5108 * clear all bits but the RF Kill bit and return */
5109 if (!il_is_init(il)) {
5111 test_bit(S_RF_KILL_HW,
5113 status) << S_RF_KILL_HW |
5114 test_bit(S_GEO_CONFIGURED,
5116 status) << S_GEO_CONFIGURED |
5117 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5121 /* ...otherwise clear out all the status bits but the RF Kill
5122 * bit and continue taking the NIC down. */
5124 test_bit(S_RF_KILL_HW,
5125 &il->status) << S_RF_KILL_HW | test_bit(S_GEO_CONFIGURED,
5128 S_GEO_CONFIGURED | test_bit(S_FW_ERROR,
5130 status) << S_FW_ERROR |
5131 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5133 il4965_txq_ctx_stop(il);
5134 il4965_rxq_stop(il);
5136 /* Power-down device's busmaster DMA clocks */
5137 il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
5140 /* Make sure (redundant) we've released our request to stay awake */
5141 il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5143 /* Stop the device, and put it in low power state */
5147 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
5149 dev_kfree_skb(il->beacon_skb);
5150 il->beacon_skb = NULL;
5152 /* clear out any free frames */
5153 il4965_clear_free_frames(il);
5157 il4965_down(struct il_priv *il)
5159 mutex_lock(&il->mutex);
5161 mutex_unlock(&il->mutex);
5163 il4965_cancel_deferred_work(il);
5166 #define HW_READY_TIMEOUT (50)
5169 il4965_set_hw_ready(struct il_priv *il)
5173 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
5174 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
5176 /* See if we got it */
5178 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5179 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5180 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, HW_READY_TIMEOUT);
5181 if (ret != -ETIMEDOUT)
5182 il->hw_ready = true;
5184 il->hw_ready = false;
5186 D_INFO("hardware %s\n", (il->hw_ready == 1) ? "ready" : "not ready");
5191 il4965_prepare_card_hw(struct il_priv *il)
5195 D_INFO("il4965_prepare_card_hw enter\n");
5197 ret = il4965_set_hw_ready(il);
5201 /* If HW is not ready, prepare the conditions to check again */
5202 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
5205 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5206 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5207 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
5209 /* HW should be ready by now, check again. */
5210 if (ret != -ETIMEDOUT)
5211 il4965_set_hw_ready(il);
5216 #define MAX_HW_RESTARTS 5
5219 __il4965_up(struct il_priv *il)
5224 if (test_bit(S_EXIT_PENDING, &il->status)) {
5225 IL_WARN("Exit pending; will not bring the NIC up\n");
5229 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
5230 IL_ERR("ucode not available for device bringup\n");
5234 ret = il4965_alloc_bcast_station(il, &il->ctx);
5236 il_dealloc_bcast_stations(il);
5240 il4965_prepare_card_hw(il);
5242 if (!il->hw_ready) {
5243 IL_WARN("Exit HW not ready\n");
5247 /* If platform's RF_KILL switch is NOT set to KILL */
5248 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5249 clear_bit(S_RF_KILL_HW, &il->status);
5251 set_bit(S_RF_KILL_HW, &il->status);
5253 if (il_is_rfkill(il)) {
5254 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
5256 il_enable_interrupts(il);
5257 IL_WARN("Radio disabled by HW RF Kill switch\n");
5261 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5263 /* must be initialised before il_hw_nic_init */
5264 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
5266 ret = il4965_hw_nic_init(il);
5268 IL_ERR("Unable to init nic\n");
5272 /* make sure rfkill handshake bits are cleared */
5273 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5274 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5276 /* clear (again), then enable host interrupts */
5277 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5278 il_enable_interrupts(il);
5280 /* really make sure rfkill handshake bits are cleared */
5281 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5282 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5284 /* Copy original ucode data image from disk into backup cache.
5285 * This will be used to initialize the on-board processor's
5286 * data SRAM for a clean start when the runtime program first loads. */
5287 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5288 il->ucode_data.len);
5290 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5292 /* load bootstrap state machine,
5293 * load bootstrap program into processor's memory,
5294 * prepare to load the "initialize" uCode */
5295 ret = il->cfg->ops->lib->load_ucode(il);
5298 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
5302 /* start card; "initialize" will load runtime ucode */
5303 il4965_nic_start(il);
5305 D_INFO(DRV_NAME " is coming up\n");
5310 set_bit(S_EXIT_PENDING, &il->status);
5312 clear_bit(S_EXIT_PENDING, &il->status);
5314 /* tried to restart and config the device for as long as our
5315 * patience could withstand */
5316 IL_ERR("Unable to initialize device after %d attempts.\n", i);
5320 /*****************************************************************************
5322 * Workqueue callbacks
5324 *****************************************************************************/
5327 il4965_bg_init_alive_start(struct work_struct *data)
5329 struct il_priv *il =
5330 container_of(data, struct il_priv, init_alive_start.work);
5332 mutex_lock(&il->mutex);
5333 if (test_bit(S_EXIT_PENDING, &il->status))
5336 il->cfg->ops->lib->init_alive_start(il);
5338 mutex_unlock(&il->mutex);
5342 il4965_bg_alive_start(struct work_struct *data)
5344 struct il_priv *il =
5345 container_of(data, struct il_priv, alive_start.work);
5347 mutex_lock(&il->mutex);
5348 if (test_bit(S_EXIT_PENDING, &il->status))
5351 il4965_alive_start(il);
5353 mutex_unlock(&il->mutex);
5357 il4965_bg_run_time_calib_work(struct work_struct *work)
5359 struct il_priv *il = container_of(work, struct il_priv,
5360 run_time_calib_work);
5362 mutex_lock(&il->mutex);
5364 if (test_bit(S_EXIT_PENDING, &il->status) ||
5365 test_bit(S_SCANNING, &il->status)) {
5366 mutex_unlock(&il->mutex);
5370 if (il->start_calib) {
5371 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5372 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
5375 mutex_unlock(&il->mutex);
5379 il4965_bg_restart(struct work_struct *data)
5381 struct il_priv *il = container_of(data, struct il_priv, restart);
5383 if (test_bit(S_EXIT_PENDING, &il->status))
5386 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
5387 mutex_lock(&il->mutex);
5393 mutex_unlock(&il->mutex);
5394 il4965_cancel_deferred_work(il);
5395 ieee80211_restart_hw(il->hw);
5399 mutex_lock(&il->mutex);
5400 if (test_bit(S_EXIT_PENDING, &il->status)) {
5401 mutex_unlock(&il->mutex);
5406 mutex_unlock(&il->mutex);
5411 il4965_bg_rx_replenish(struct work_struct *data)
5413 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
5415 if (test_bit(S_EXIT_PENDING, &il->status))
5418 mutex_lock(&il->mutex);
5419 il4965_rx_replenish(il);
5420 mutex_unlock(&il->mutex);
5423 /*****************************************************************************
5425 * mac80211 entry point functions
5427 *****************************************************************************/
5429 #define UCODE_READY_TIMEOUT (4 * HZ)
5432 * Not a mac80211 entry point function, but it fits in with all the
5433 * other mac80211 functions grouped here.
5436 il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
5439 struct ieee80211_hw *hw = il->hw;
5441 hw->rate_control_algorithm = "iwl-4965-rs";
5443 /* Tell mac80211 our characteristics */
5445 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION |
5446 IEEE80211_HW_NEED_DTIM_PERIOD | IEEE80211_HW_SPECTRUM_MGMT |
5447 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5449 if (il->cfg->sku & IL_SKU_N)
5451 IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
5452 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
5454 hw->sta_data_size = sizeof(struct il_station_priv);
5455 hw->vif_data_size = sizeof(struct il_vif_priv);
5457 hw->wiphy->interface_modes =
5458 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
5461 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS;
5464 * For now, disable PS by default because it affects
5465 * RX performance significantly.
5467 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5469 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5470 /* we create the 802.11 header and a zero-length SSID element */
5471 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5473 /* Default value; 4 EDCA QOS priorities */
5476 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
5478 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5479 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5480 &il->bands[IEEE80211_BAND_2GHZ];
5481 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5482 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5483 &il->bands[IEEE80211_BAND_5GHZ];
5487 ret = ieee80211_register_hw(il->hw);
5489 IL_ERR("Failed to register hw (error %d)\n", ret);
5492 il->mac80211_registered = 1;
5498 il4965_mac_start(struct ieee80211_hw *hw)
5500 struct il_priv *il = hw->priv;
5503 D_MAC80211("enter\n");
5505 /* we should be verifying the device is ready to be opened */
5506 mutex_lock(&il->mutex);
5507 ret = __il4965_up(il);
5508 mutex_unlock(&il->mutex);
5513 if (il_is_rfkill(il))
5516 D_INFO("Start UP work done.\n");
5518 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5519 * mac80211 will not be run successfully. */
5520 ret = wait_event_timeout(il->wait_command_queue,
5521 test_bit(S_READY, &il->status),
5522 UCODE_READY_TIMEOUT);
5524 if (!test_bit(S_READY, &il->status)) {
5525 IL_ERR("START_ALIVE timeout after %dms.\n",
5526 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5531 il4965_led_enable(il);
5535 D_MAC80211("leave\n");
5540 il4965_mac_stop(struct ieee80211_hw *hw)
5542 struct il_priv *il = hw->priv;
5544 D_MAC80211("enter\n");
5553 flush_workqueue(il->workqueue);
5555 /* User space software may expect getting rfkill changes
5556 * even if interface is down */
5557 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5558 il_enable_rfkill_int(il);
5560 D_MAC80211("leave\n");
5564 il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
5566 struct il_priv *il = hw->priv;
5568 D_MACDUMP("enter\n");
5570 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
5571 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
5573 if (il4965_tx_skb(il, skb))
5574 dev_kfree_skb_any(skb);
5576 D_MACDUMP("leave\n");
5580 il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5581 struct ieee80211_key_conf *keyconf,
5582 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
5584 struct il_priv *il = hw->priv;
5585 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
5587 D_MAC80211("enter\n");
5589 il4965_update_tkip_key(il, vif_priv->ctx, keyconf, sta, iv32,
5592 D_MAC80211("leave\n");
5596 il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5597 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5598 struct ieee80211_key_conf *key)
5600 struct il_priv *il = hw->priv;
5601 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
5602 struct il_rxon_context *ctx = vif_priv->ctx;
5605 bool is_default_wep_key = false;
5607 D_MAC80211("enter\n");
5609 if (il->cfg->mod_params->sw_crypto) {
5610 D_MAC80211("leave - hwcrypto disabled\n");
5614 sta_id = il_sta_id_or_broadcast(il, vif_priv->ctx, sta);
5615 if (sta_id == IL_INVALID_STATION)
5618 mutex_lock(&il->mutex);
5619 il_scan_cancel_timeout(il, 100);
5622 * If we are getting WEP group key and we didn't receive any key mapping
5623 * so far, we are in legacy wep mode (group key only), otherwise we are
5625 * In legacy wep mode, we use another host command to the uCode.
5627 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
5628 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
5630 is_default_wep_key = !il->_4965.key_mapping_keys;
5632 is_default_wep_key =
5633 (key->hw_key_idx == HW_KEY_DEFAULT);
5638 if (is_default_wep_key)
5640 il4965_set_default_wep_key(il, vif_priv->ctx, key);
5643 il4965_set_dynamic_key(il, vif_priv->ctx, key,
5646 D_MAC80211("enable hwcrypto key\n");
5649 if (is_default_wep_key)
5650 ret = il4965_remove_default_wep_key(il, ctx, key);
5652 ret = il4965_remove_dynamic_key(il, ctx, key, sta_id);
5654 D_MAC80211("disable hwcrypto key\n");
5660 mutex_unlock(&il->mutex);
5661 D_MAC80211("leave\n");
5667 il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5668 enum ieee80211_ampdu_mlme_action action,
5669 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5672 struct il_priv *il = hw->priv;
5675 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
5677 if (!(il->cfg->sku & IL_SKU_N))
5680 mutex_lock(&il->mutex);
5683 case IEEE80211_AMPDU_RX_START:
5685 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
5687 case IEEE80211_AMPDU_RX_STOP:
5689 ret = il4965_sta_rx_agg_stop(il, sta, tid);
5690 if (test_bit(S_EXIT_PENDING, &il->status))
5693 case IEEE80211_AMPDU_TX_START:
5695 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
5697 case IEEE80211_AMPDU_TX_STOP:
5699 ret = il4965_tx_agg_stop(il, vif, sta, tid);
5700 if (test_bit(S_EXIT_PENDING, &il->status))
5703 case IEEE80211_AMPDU_TX_OPERATIONAL:
5707 mutex_unlock(&il->mutex);
5713 il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5714 struct ieee80211_sta *sta)
5716 struct il_priv *il = hw->priv;
5717 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
5718 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
5719 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
5723 D_INFO("received request to add station %pM\n", sta->addr);
5724 mutex_lock(&il->mutex);
5725 D_INFO("proceeding to add station %pM\n", sta->addr);
5726 sta_priv->common.sta_id = IL_INVALID_STATION;
5728 atomic_set(&sta_priv->pending_frames, 0);
5731 il_add_station_common(il, vif_priv->ctx, sta->addr, is_ap, sta,
5734 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
5735 /* Should we return success if return code is EEXIST ? */
5736 mutex_unlock(&il->mutex);
5740 sta_priv->common.sta_id = sta_id;
5742 /* Initialize rate scaling */
5743 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
5744 il4965_rs_rate_init(il, sta, sta_id);
5745 mutex_unlock(&il->mutex);
5751 il4965_mac_channel_switch(struct ieee80211_hw *hw,
5752 struct ieee80211_channel_switch *ch_switch)
5754 struct il_priv *il = hw->priv;
5755 const struct il_channel_info *ch_info;
5756 struct ieee80211_conf *conf = &hw->conf;
5757 struct ieee80211_channel *channel = ch_switch->channel;
5758 struct il_ht_config *ht_conf = &il->current_ht_config;
5760 struct il_rxon_context *ctx = &il->ctx;
5763 D_MAC80211("enter\n");
5765 mutex_lock(&il->mutex);
5767 if (il_is_rfkill(il))
5770 if (test_bit(S_EXIT_PENDING, &il->status) ||
5771 test_bit(S_SCANNING, &il->status) ||
5772 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
5775 if (!il_is_associated(il))
5778 if (!il->cfg->ops->lib->set_channel_switch)
5781 ch = channel->hw_value;
5782 if (le16_to_cpu(il->active.channel) == ch)
5785 ch_info = il_get_channel_info(il, channel->band, ch);
5786 if (!il_is_channel_valid(ch_info)) {
5787 D_MAC80211("invalid channel\n");
5791 spin_lock_irq(&il->lock);
5793 il->current_ht_config.smps = conf->smps_mode;
5795 /* Configure HT40 channels */
5796 il->ht.enabled = conf_is_ht(conf);
5797 if (il->ht.enabled) {
5798 if (conf_is_ht40_minus(conf)) {
5799 il->ht.extension_chan_offset =
5800 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
5801 il->ht.is_40mhz = true;
5802 } else if (conf_is_ht40_plus(conf)) {
5803 il->ht.extension_chan_offset =
5804 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
5805 il->ht.is_40mhz = true;
5807 il->ht.extension_chan_offset =
5808 IEEE80211_HT_PARAM_CHA_SEC_NONE;
5809 il->ht.is_40mhz = false;
5812 il->ht.is_40mhz = false;
5814 if ((le16_to_cpu(il->staging.channel) != ch))
5815 il->staging.flags = 0;
5817 il_set_rxon_channel(il, channel, ctx);
5818 il_set_rxon_ht(il, ht_conf);
5819 il_set_flags_for_band(il, ctx, channel->band, ctx->vif);
5821 spin_unlock_irq(&il->lock);
5825 * at this point, staging_rxon has the
5826 * configuration for channel switch
5828 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
5829 il->switch_channel = cpu_to_le16(ch);
5830 if (il->cfg->ops->lib->set_channel_switch(il, ch_switch)) {
5831 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
5832 il->switch_channel = 0;
5833 ieee80211_chswitch_done(ctx->vif, false);
5837 mutex_unlock(&il->mutex);
5838 D_MAC80211("leave\n");
5842 il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
5843 unsigned int *total_flags, u64 multicast)
5845 struct il_priv *il = hw->priv;
5846 __le32 filter_or = 0, filter_nand = 0;
5848 #define CHK(test, flag) do { \
5849 if (*total_flags & (test)) \
5850 filter_or |= (flag); \
5852 filter_nand |= (flag); \
5855 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
5858 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
5859 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
5860 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
5861 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
5865 mutex_lock(&il->mutex);
5867 il->staging.filter_flags &= ~filter_nand;
5868 il->staging.filter_flags |= filter_or;
5871 * Not committing directly because hardware can perform a scan,
5872 * but we'll eventually commit the filter flags change anyway.
5875 mutex_unlock(&il->mutex);
5878 * Receiving all multicast frames is always enabled by the
5879 * default flags setup in il_connection_init_rx_config()
5880 * since we currently do not support programming multicast
5881 * filters into the device.
5884 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
5885 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
5888 /*****************************************************************************
5890 * driver setup and teardown
5892 *****************************************************************************/
5895 il4965_bg_txpower_work(struct work_struct *work)
5897 struct il_priv *il = container_of(work, struct il_priv,
5900 mutex_lock(&il->mutex);
5902 /* If a scan happened to start before we got here
5903 * then just return; the stats notification will
5904 * kick off another scheduled work to compensate for
5905 * any temperature delta we missed here. */
5906 if (test_bit(S_EXIT_PENDING, &il->status) ||
5907 test_bit(S_SCANNING, &il->status))
5910 /* Regardless of if we are associated, we must reconfigure the
5911 * TX power since frames can be sent on non-radar channels while
5913 il->cfg->ops->lib->send_tx_power(il);
5915 /* Update last_temperature to keep is_calib_needed from running
5916 * when it isn't needed... */
5917 il->last_temperature = il->temperature;
5919 mutex_unlock(&il->mutex);
5923 il4965_setup_deferred_work(struct il_priv *il)
5925 il->workqueue = create_singlethread_workqueue(DRV_NAME);
5927 init_waitqueue_head(&il->wait_command_queue);
5929 INIT_WORK(&il->restart, il4965_bg_restart);
5930 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
5931 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
5932 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
5933 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
5935 il_setup_scan_deferred_work(il);
5937 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
5939 init_timer(&il->stats_periodic);
5940 il->stats_periodic.data = (unsigned long)il;
5941 il->stats_periodic.function = il4965_bg_stats_periodic;
5943 init_timer(&il->watchdog);
5944 il->watchdog.data = (unsigned long)il;
5945 il->watchdog.function = il_bg_watchdog;
5947 tasklet_init(&il->irq_tasklet,
5948 (void (*)(unsigned long))il4965_irq_tasklet,
5953 il4965_cancel_deferred_work(struct il_priv *il)
5955 cancel_work_sync(&il->txpower_work);
5956 cancel_delayed_work_sync(&il->init_alive_start);
5957 cancel_delayed_work(&il->alive_start);
5958 cancel_work_sync(&il->run_time_calib_work);
5960 il_cancel_scan_deferred_work(il);
5962 del_timer_sync(&il->stats_periodic);
5966 il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
5970 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
5971 rates[i].bitrate = il_rates[i].ieee * 5;
5972 rates[i].hw_value = i; /* Rate scaling will work on idxes */
5973 rates[i].hw_value_short = i;
5975 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
5977 * If CCK != 1M then set short preamble rate flag.
5980 (il_rates[i].plcp ==
5981 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
5987 * Acquire il->lock before calling this function !
5990 il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
5992 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
5993 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
5997 il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
5998 int tx_fifo_id, int scd_retry)
6000 int txq_id = txq->q.id;
6002 /* Find out whether to activate Tx queue */
6003 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
6005 /* Set up and activate */
6006 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
6007 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6008 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6009 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6010 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6011 IL49_SCD_QUEUE_STTS_REG_MSK);
6013 txq->sched_retry = scd_retry;
6015 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
6016 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
6020 il4965_init_drv(struct il_priv *il)
6024 spin_lock_init(&il->sta_lock);
6025 spin_lock_init(&il->hcmd_lock);
6027 INIT_LIST_HEAD(&il->free_frames);
6029 mutex_init(&il->mutex);
6031 il->ieee_channels = NULL;
6032 il->ieee_rates = NULL;
6033 il->band = IEEE80211_BAND_2GHZ;
6035 il->iw_mode = NL80211_IFTYPE_STATION;
6036 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6037 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
6039 /* initialize force reset */
6040 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
6042 /* Choose which receivers/antennas to use */
6043 if (il->cfg->ops->hcmd->set_rxon_chain)
6044 il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
6046 il_init_scan_params(il);
6048 ret = il_init_channel_map(il);
6050 IL_ERR("initializing regulatory failed: %d\n", ret);
6054 ret = il_init_geos(il);
6056 IL_ERR("initializing geos failed: %d\n", ret);
6057 goto err_free_channel_map;
6059 il4965_init_hw_rates(il, il->ieee_rates);
6063 err_free_channel_map:
6064 il_free_channel_map(il);
6070 il4965_uninit_drv(struct il_priv *il)
6072 il4965_calib_free_results(il);
6074 il_free_channel_map(il);
6075 kfree(il->scan_cmd);
6079 il4965_hw_detect(struct il_priv *il)
6081 il->hw_rev = _il_rd(il, CSR_HW_REV);
6082 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
6083 il->rev_id = il->pci_dev->revision;
6084 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
6088 il4965_set_hw_params(struct il_priv *il)
6090 il->hw_params.bcast_id = IL4965_BROADCAST_ID;
6091 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6092 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6093 if (il->cfg->mod_params->amsdu_size_8K)
6094 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
6096 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
6098 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
6100 if (il->cfg->mod_params->disable_11n)
6101 il->cfg->sku &= ~IL_SKU_N;
6103 /* Device-specific setup */
6104 return il->cfg->ops->lib->set_hw_params(il);
6107 static const u8 il4965_bss_ac_to_fifo[] = {
6114 static const u8 il4965_bss_ac_to_queue[] = {
6119 il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
6123 struct ieee80211_hw *hw;
6124 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
6125 unsigned long flags;
6128 /************************
6129 * 1. Allocating HW data
6130 ************************/
6132 hw = il_alloc_all(cfg);
6138 /* At this point both hw and il are allocated. */
6140 il->ctx.always_active = true;
6141 il->ctx.is_active = true;
6142 il->ctx.ac_to_fifo = il4965_bss_ac_to_fifo;
6143 il->ctx.ac_to_queue = il4965_bss_ac_to_queue;
6145 SET_IEEE80211_DEV(hw, &pdev->dev);
6147 D_INFO("*** LOAD DRIVER ***\n");
6150 il->inta_mask = CSR_INI_SET_MASK;
6152 if (il_alloc_traffic_mem(il))
6153 IL_ERR("Not enough memory to generate traffic log\n");
6155 /**************************
6156 * 2. Initializing PCI bus
6157 **************************/
6158 pci_disable_link_state(pdev,
6159 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6160 PCIE_LINK_STATE_CLKPM);
6162 if (pci_enable_device(pdev)) {
6164 goto out_ieee80211_free_hw;
6167 pci_set_master(pdev);
6169 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6171 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6173 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6176 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6177 /* both attempts failed: */
6179 IL_WARN("No suitable DMA available.\n");
6180 goto out_pci_disable_device;
6184 err = pci_request_regions(pdev, DRV_NAME);
6186 goto out_pci_disable_device;
6188 pci_set_drvdata(pdev, il);
6190 /***********************
6191 * 3. Read REV register
6192 ***********************/
6193 il->hw_base = pci_iomap(pdev, 0, 0);
6196 goto out_pci_release_regions;
6199 D_INFO("pci_resource_len = 0x%08llx\n",
6200 (unsigned long long)pci_resource_len(pdev, 0));
6201 D_INFO("pci_resource_base = %p\n", il->hw_base);
6203 /* these spin locks will be used in apm_ops.init and EEPROM access
6204 * we should init now
6206 spin_lock_init(&il->reg_lock);
6207 spin_lock_init(&il->lock);
6210 * stop and reset the on-board processor just in case it is in a
6211 * strange state ... like being left stranded by a primary kernel
6212 * and this is now the kdump kernel trying to start up
6214 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
6216 il4965_hw_detect(il);
6217 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
6219 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6220 * PCI Tx retries from interfering with C3 CPU state */
6221 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6223 il4965_prepare_card_hw(il);
6224 if (!il->hw_ready) {
6225 IL_WARN("Failed, HW not ready\n");
6232 /* Read the EEPROM */
6233 err = il_eeprom_init(il);
6235 IL_ERR("Unable to init EEPROM\n");
6238 err = il4965_eeprom_check_version(il);
6240 goto out_free_eeprom;
6243 goto out_free_eeprom;
6245 /* extract MAC Address */
6246 il4965_eeprom_get_mac(il, il->addresses[0].addr);
6247 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
6248 il->hw->wiphy->addresses = il->addresses;
6249 il->hw->wiphy->n_addresses = 1;
6251 /************************
6252 * 5. Setup HW constants
6253 ************************/
6254 if (il4965_set_hw_params(il)) {
6255 IL_ERR("failed to set hw parameters\n");
6256 goto out_free_eeprom;
6259 /*******************
6261 *******************/
6263 err = il4965_init_drv(il);
6265 goto out_free_eeprom;
6266 /* At this point both hw and il are initialized. */
6268 /********************
6270 ********************/
6271 spin_lock_irqsave(&il->lock, flags);
6272 il_disable_interrupts(il);
6273 spin_unlock_irqrestore(&il->lock, flags);
6275 pci_enable_msi(il->pci_dev);
6277 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
6279 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
6280 goto out_disable_msi;
6283 il4965_setup_deferred_work(il);
6284 il4965_setup_handlers(il);
6286 /*********************************************
6287 * 8. Enable interrupts and read RFKILL state
6288 *********************************************/
6290 /* enable rfkill interrupt: hw bug w/a */
6291 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
6292 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6293 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
6294 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
6297 il_enable_rfkill_int(il);
6299 /* If platform's RF_KILL switch is NOT set to KILL */
6300 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6301 clear_bit(S_RF_KILL_HW, &il->status);
6303 set_bit(S_RF_KILL_HW, &il->status);
6305 wiphy_rfkill_set_hw_state(il->hw->wiphy,
6306 test_bit(S_RF_KILL_HW, &il->status));
6308 il_power_initialize(il);
6310 init_completion(&il->_4965.firmware_loading_complete);
6312 err = il4965_request_firmware(il, true);
6314 goto out_destroy_workqueue;
6318 out_destroy_workqueue:
6319 destroy_workqueue(il->workqueue);
6320 il->workqueue = NULL;
6321 free_irq(il->pci_dev->irq, il);
6323 pci_disable_msi(il->pci_dev);
6324 il4965_uninit_drv(il);
6328 pci_iounmap(pdev, il->hw_base);
6329 out_pci_release_regions:
6330 pci_set_drvdata(pdev, NULL);
6331 pci_release_regions(pdev);
6332 out_pci_disable_device:
6333 pci_disable_device(pdev);
6334 out_ieee80211_free_hw:
6335 il_free_traffic_mem(il);
6336 ieee80211_free_hw(il->hw);
6341 static void __devexit
6342 il4965_pci_remove(struct pci_dev *pdev)
6344 struct il_priv *il = pci_get_drvdata(pdev);
6345 unsigned long flags;
6350 wait_for_completion(&il->_4965.firmware_loading_complete);
6352 D_INFO("*** UNLOAD DRIVER ***\n");
6354 il_dbgfs_unregister(il);
6355 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
6357 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6358 * to be called and il4965_down since we are removing the device
6359 * we need to set S_EXIT_PENDING bit.
6361 set_bit(S_EXIT_PENDING, &il->status);
6365 if (il->mac80211_registered) {
6366 ieee80211_unregister_hw(il->hw);
6367 il->mac80211_registered = 0;
6373 * Make sure device is reset to low power before unloading driver.
6374 * This may be redundant with il4965_down(), but there are paths to
6375 * run il4965_down() without calling apm_ops.stop(), and there are
6376 * paths to avoid running il4965_down() at all before leaving driver.
6377 * This (inexpensive) call *makes sure* device is reset.
6381 /* make sure we flush any pending irq or
6382 * tasklet for the driver
6384 spin_lock_irqsave(&il->lock, flags);
6385 il_disable_interrupts(il);
6386 spin_unlock_irqrestore(&il->lock, flags);
6388 il4965_synchronize_irq(il);
6390 il4965_dealloc_ucode_pci(il);
6393 il4965_rx_queue_free(il, &il->rxq);
6394 il4965_hw_txq_ctx_free(il);
6398 /*netif_stop_queue(dev); */
6399 flush_workqueue(il->workqueue);
6401 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
6402 * il->workqueue... so we can't take down the workqueue
6404 destroy_workqueue(il->workqueue);
6405 il->workqueue = NULL;
6406 il_free_traffic_mem(il);
6408 free_irq(il->pci_dev->irq, il);
6409 pci_disable_msi(il->pci_dev);
6410 pci_iounmap(pdev, il->hw_base);
6411 pci_release_regions(pdev);
6412 pci_disable_device(pdev);
6413 pci_set_drvdata(pdev, NULL);
6415 il4965_uninit_drv(il);
6417 dev_kfree_skb(il->beacon_skb);
6419 ieee80211_free_hw(il->hw);
6423 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
6424 * must be called under il->lock and mac access
6427 il4965_txq_set_sched(struct il_priv *il, u32 mask)
6429 il_wr_prph(il, IL49_SCD_TXFACT, mask);
6432 /*****************************************************************************
6434 * driver and module entry point
6436 *****************************************************************************/
6438 /* Hardware specific file defines the PCI IDs table for that hardware module */
6439 static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
6440 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6441 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
6444 MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
6446 static struct pci_driver il4965_driver = {
6448 .id_table = il4965_hw_card_ids,
6449 .probe = il4965_pci_probe,
6450 .remove = __devexit_p(il4965_pci_remove),
6451 .driver.pm = IL_LEGACY_PM_OPS,
6459 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6460 pr_info(DRV_COPYRIGHT "\n");
6462 ret = il4965_rate_control_register();
6464 pr_err("Unable to register rate control algorithm: %d\n", ret);
6468 ret = pci_register_driver(&il4965_driver);
6470 pr_err("Unable to initialize PCI module\n");
6471 goto error_register;
6477 il4965_rate_control_unregister();
6484 pci_unregister_driver(&il4965_driver);
6485 il4965_rate_control_unregister();
6488 module_exit(il4965_exit);
6489 module_init(il4965_init);
6491 #ifdef CONFIG_IWLEGACY_DEBUG
6492 module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
6493 MODULE_PARM_DESC(debug, "debug output mask");
6496 module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
6497 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
6498 module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
6499 MODULE_PARM_DESC(queues_num, "number of hw queues.");
6500 module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
6501 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
6502 module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6504 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
6505 module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
6506 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");