drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 Intel Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of version 2 of the GNU General Public License as
  15  * published by the Free Software Foundation.
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  17  * This program is distributed in the hope that it will be useful, but
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  30  *
  31  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  34  * Copyright(c) 2018 Intel Corporation
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  48  *    contributors may be used to endorse or promote products derived
  49  *    from this software without specific prior written permission.
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  54  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  55  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  60  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  61  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62  *
  63  *****************************************************************************/
  64 #include <linux/pci.h>
  65 #include <linux/pci-aspm.h>
  66 #include <linux/interrupt.h>
  67 #include <linux/debugfs.h>
  68 #include <linux/sched.h>
  69 #include <linux/bitops.h>
  70 #include <linux/gfp.h>
  71 #include <linux/vmalloc.h>
  72 #include <linux/pm_runtime.h>
  73 #include <linux/module.h>
  74 #include <linux/wait.h>
  75
  76 #include "iwl-drv.h"
  77 #include "iwl-trans.h"
  78 #include "iwl-csr.h"
  79 #include "iwl-prph.h"
  80 #include "iwl-scd.h"
  81 #include "iwl-agn-hw.h"
  82 #include "fw/error-dump.h"
  83 #include "fw/dbg.h"
  84 #include "internal.h"
  85 #include "iwl-fh.h"
  86
  87 /* extended range in FW SRAM */
  88 #define IWL_FW_MEM_EXTENDED_START       0x40000
  89 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  90
  91 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
  92 {
  93 #define PCI_DUMP_SIZE   64
  94 #define PREFIX_LEN      32
  95         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  96         struct pci_dev *pdev = trans_pcie->pci_dev;
  97         u32 i, pos, alloc_size, *ptr, *buf;
  98         char *prefix;
  99
 100         if (trans_pcie->pcie_dbg_dumped_once)
 101                 return;
 102
 103         /* Should be a multiple of 4 */
 104         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
 105         /* Alloc a max size buffer */
 106         if (PCI_ERR_ROOT_ERR_SRC +  4 > PCI_DUMP_SIZE)
 107                 alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
 108         else
 109                 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
 110         buf = kmalloc(alloc_size, GFP_ATOMIC);
 111         if (!buf)
 112                 return;
 113         prefix = (char *)buf + alloc_size - PREFIX_LEN;
 114
 115         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
 116
 117         /* Print wifi device registers */
 118         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 119         IWL_ERR(trans, "iwlwifi device config registers:\n");
 120         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 121                 if (pci_read_config_dword(pdev, i, ptr))
 122                         goto err_read;
 123         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 124
 125         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
 126         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 127                 *ptr = iwl_read32(trans, i);
 128         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 129
 130         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 131         if (pos) {
 132                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
 133                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
 134                         if (pci_read_config_dword(pdev, pos + i, ptr))
 135                                 goto err_read;
 136                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
 137                                32, 4, buf, i, 0);
 138         }
 139
 140         /* Print parent device registers next */
 141         if (!pdev->bus->self)
 142                 goto out;
 143
 144         pdev = pdev->bus->self;
 145         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 146
 147         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
 148                 pci_name(pdev));
 149         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 150                 if (pci_read_config_dword(pdev, i, ptr))
 151                         goto err_read;
 152         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 153
 154         /* Print root port AER registers */
 155         pos = 0;
 156         pdev = pcie_find_root_port(pdev);
 157         if (pdev)
 158                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 159         if (pos) {
 160                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
 161                         pci_name(pdev));
 162                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 163                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
 164                         if (pci_read_config_dword(pdev, pos + i, ptr))
 165                                 goto err_read;
 166                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
 167                                4, buf, i, 0);
 168         }
 169         goto out;
 170
 171 err_read:
 172         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 173         IWL_ERR(trans, "Read failed at 0x%X\n", i);
 174 out:
 175         trans_pcie->pcie_dbg_dumped_once = 1;
 176         kfree(buf);
 177 }
 178
 179 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
 180 {
 181         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 182         iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
 183                     BIT(trans->cfg->csr->flag_sw_reset));
 184         usleep_range(5000, 6000);
 185 }
 186
 187 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
 188 {
 189         int i;
 190
 191         for (i = 0; i < trans->num_blocks; i++) {
 192                 dma_free_coherent(trans->dev, trans->fw_mon[i].size,
 193                                   trans->fw_mon[i].block,
 194                                   trans->fw_mon[i].physical);
 195                 trans->fw_mon[i].block = NULL;
 196                 trans->fw_mon[i].physical = 0;
 197                 trans->fw_mon[i].size = 0;
 198                 trans->num_blocks--;
 199         }
 200 }
 201
 202 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
 203                                             u8 max_power, u8 min_power)
 204 {
 205         void *cpu_addr = NULL;
 206         dma_addr_t phys = 0;
 207         u32 size = 0;
 208         u8 power;
 209
 210         for (power = max_power; power >= min_power; power--) {
 211                 size = BIT(power);
 212                 cpu_addr = dma_alloc_coherent(trans->dev, size, &phys,
 213                                               GFP_KERNEL | __GFP_NOWARN |
 214                                               __GFP_ZERO | __GFP_COMP);
 215                 if (!cpu_addr)
 216                         continue;
 217
 218                 IWL_INFO(trans,
 219                          "Allocated 0x%08x bytes for firmware monitor.\n",
 220                          size);
 221                 break;
 222         }
 223
 224         if (WARN_ON_ONCE(!cpu_addr))
 225                 return;
 226
 227         if (power != max_power)
 228                 IWL_ERR(trans,
 229                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 230                         (unsigned long)BIT(power - 10),
 231                         (unsigned long)BIT(max_power - 10));
 232
 233         trans->fw_mon[trans->num_blocks].block = cpu_addr;
 234         trans->fw_mon[trans->num_blocks].physical = phys;
 235         trans->fw_mon[trans->num_blocks].size = size;
 236         trans->num_blocks++;
 237 }
 238
 239 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 240 {
 241         if (!max_power) {
 242                 /* default max_power is maximum */
 243                 max_power = 26;
 244         } else {
 245                 max_power += 11;
 246         }
 247
 248         if (WARN(max_power > 26,
 249                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 250                  max_power))
 251                 return;
 252
 253         /*
 254          * This function allocats the default fw monitor.
 255          * The optional additional ones will be allocated in runtime
 256          */
 257         if (trans->num_blocks)
 258                 return;
 259
 260         iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
 261 }
 262
 263 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 264 {
 265         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 266                     ((reg & 0x0000ffff) | (2 << 28)));
 267         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 268 }
 269
 270 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 271 {
 272         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 273         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 274                     ((reg & 0x0000ffff) | (3 << 28)));
 275 }
 276
 277 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 278 {
 279         if (trans->cfg->apmg_not_supported)
 280                 return;
 281
 282         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 283                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 284                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 285                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 286         else
 287                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 288                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 289                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 290 }
 291
 292 /* PCI registers */
 293 #define PCI_CFG_RETRY_TIMEOUT   0x041
 294
 295 void iwl_pcie_apm_config(struct iwl_trans *trans)
 296 {
 297         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 298         u16 lctl;
 299         u16 cap;
 300
 301         /*
 302          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 303          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 304          * If so (likely), disable L0S, so device moves directly L0->L1;
 305          *    costs negligible amount of power savings.
 306          * If not (unlikely), enable L0S, so there is at least some
 307          *    power savings, even without L1.
 308          */
 309         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 310         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 311                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 312         else
 313                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 314         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 315
 316         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 317         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 318         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 319                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 320                         trans->ltr_enabled ? "En" : "Dis");
 321 }
 322
 323 /*
 324  * Start up NIC's basic functionality after it has been reset
 325  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 326  * NOTE:  This does not load uCode nor start the embedded processor
 327  */
 328 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 329 {
 330         int ret;
 331
 332         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 333
 334         /*
 335          * Use "set_bit" below rather than "write", to preserve any hardware
 336          * bits already set by default after reset.
 337          */
 338
 339         /* Disable L0S exit timer (platform NMI Work/Around) */
 340         if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
 341                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 342                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 343
 344         /*
 345          * Disable L0s without affecting L1;
 346          *  don't wait for ICH L0s (ICH bug W/A)
 347          */
 348         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 349                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 350
 351         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 352         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 353
 354         /*
 355          * Enable HAP INTA (interrupt from management bus) to
 356          * wake device's PCI Express link L1a -> L0s
 357          */
 358         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 359                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 360
 361         iwl_pcie_apm_config(trans);
 362
 363         /* Configure analog phase-lock-loop before activating to D0A */
 364         if (trans->cfg->base_params->pll_cfg)
 365                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 366
 367         /*
 368          * Set "initialization complete" bit to move adapter from
 369          * D0U* --> D0A* (powered-up active) state.
 370          */
 371         iwl_set_bit(trans, CSR_GP_CNTRL,
 372                     BIT(trans->cfg->csr->flag_init_done));
 373
 374         /*
 375          * Wait for clock stabilization; once stabilized, access to
 376          * device-internal resources is supported, e.g. iwl_write_prph()
 377          * and accesses to uCode SRAM.
 378          */
 379         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 380                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 381                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 382                            25000);
 383         if (ret < 0) {
 384                 IWL_ERR(trans, "Failed to init the card\n");
 385                 return ret;
 386         }
 387
 388         if (trans->cfg->host_interrupt_operation_mode) {
 389                 /*
 390                  * This is a bit of an abuse - This is needed for 7260 / 3160
 391                  * only check host_interrupt_operation_mode even if this is
 392                  * not related to host_interrupt_operation_mode.
 393                  *
 394                  * Enable the oscillator to count wake up time for L1 exit. This
 395                  * consumes slightly more power (100uA) - but allows to be sure
 396                  * that we wake up from L1 on time.
 397                  *
 398                  * This looks weird: read twice the same register, discard the
 399                  * value, set a bit, and yet again, read that same register
 400                  * just to discard the value. But that's the way the hardware
 401                  * seems to like it.
 402                  */
 403                 iwl_read_prph(trans, OSC_CLK);
 404                 iwl_read_prph(trans, OSC_CLK);
 405                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 406                 iwl_read_prph(trans, OSC_CLK);
 407                 iwl_read_prph(trans, OSC_CLK);
 408         }
 409
 410         /*
 411          * Enable DMA clock and wait for it to stabilize.
 412          *
 413          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 414          * bits do not disable clocks.  This preserves any hardware
 415          * bits already set by default in "CLK_CTRL_REG" after reset.
 416          */
 417         if (!trans->cfg->apmg_not_supported) {
 418                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 419                                APMG_CLK_VAL_DMA_CLK_RQT);
 420                 udelay(20);
 421
 422                 /* Disable L1-Active */
 423                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 424                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 425
 426                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 427                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 428                                APMG_RTC_INT_STT_RFKILL);
 429         }
 430
 431         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 432
 433         return 0;
 434 }
 435
 436 /*
 437  * Enable LP XTAL to avoid HW bug where device may consume much power if
 438  * FW is not loaded after device reset. LP XTAL is disabled by default
 439  * after device HW reset. Do it only if XTAL is fed by internal source.
 440  * Configure device's "persistence" mode to avoid resetting XTAL again when
 441  * SHRD_HW_RST occurs in S3.
 442  */
 443 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 444 {
 445         int ret;
 446         u32 apmg_gp1_reg;
 447         u32 apmg_xtal_cfg_reg;
 448         u32 dl_cfg_reg;
 449
 450         /* Force XTAL ON */
 451         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 452                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 453
 454         iwl_trans_pcie_sw_reset(trans);
 455
 456         /*
 457          * Set "initialization complete" bit to move adapter from
 458          * D0U* --> D0A* (powered-up active) state.
 459          */
 460         iwl_set_bit(trans, CSR_GP_CNTRL,
 461                     BIT(trans->cfg->csr->flag_init_done));
 462
 463         /*
 464          * Wait for clock stabilization; once stabilized, access to
 465          * device-internal resources is possible.
 466          */
 467         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 468                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 469                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 470                            25000);
 471         if (WARN_ON(ret < 0)) {
 472                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 473                 /* Release XTAL ON request */
 474                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 475                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 476                 return;
 477         }
 478
 479         /*
 480          * Clear "disable persistence" to avoid LP XTAL resetting when
 481          * SHRD_HW_RST is applied in S3.
 482          */
 483         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 484                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 485
 486         /*
 487          * Force APMG XTAL to be active to prevent its disabling by HW
 488          * caused by APMG idle state.
 489          */
 490         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 491                                                     SHR_APMG_XTAL_CFG_REG);
 492         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 493                                  apmg_xtal_cfg_reg |
 494                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 495
 496         iwl_trans_pcie_sw_reset(trans);
 497
 498         /* Enable LP XTAL by indirect access through CSR */
 499         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 500         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 501                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 502                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 503
 504         /* Clear delay line clock power up */
 505         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 506         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 507                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 508
 509         /*
 510          * Enable persistence mode to avoid LP XTAL resetting when
 511          * SHRD_HW_RST is applied in S3.
 512          */
 513         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 514                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 515
 516         /*
 517          * Clear "initialization complete" bit to move adapter from
 518          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 519          */
 520         iwl_clear_bit(trans, CSR_GP_CNTRL,
 521                       BIT(trans->cfg->csr->flag_init_done));
 522
 523         /* Activates XTAL resources monitor */
 524         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 525                                  CSR_MONITOR_XTAL_RESOURCES);
 526
 527         /* Release XTAL ON request */
 528         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 529                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 530         udelay(10);
 531
 532         /* Release APMG XTAL */
 533         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 534                                  apmg_xtal_cfg_reg &
 535                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 536 }
 537
 538 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 539 {
 540         int ret;
 541
 542         /* stop device's busmaster DMA activity */
 543         iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
 544                     BIT(trans->cfg->csr->flag_stop_master));
 545
 546         ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset,
 547                            BIT(trans->cfg->csr->flag_master_dis),
 548                            BIT(trans->cfg->csr->flag_master_dis), 100);
 549         if (ret < 0)
 550                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 551
 552         IWL_DEBUG_INFO(trans, "stop master\n");
 553 }
 554
 555 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 556 {
 557         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 558
 559         if (op_mode_leave) {
 560                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 561                         iwl_pcie_apm_init(trans);
 562
 563                 /* inform ME that we are leaving */
 564                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 565                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 566                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 567                 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
 568                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 569                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 570                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 571                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 572                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 573                         mdelay(1);
 574                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 575                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 576                 }
 577                 mdelay(5);
 578         }
 579
 580         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 581
 582         /* Stop device's DMA activity */
 583         iwl_pcie_apm_stop_master(trans);
 584
 585         if (trans->cfg->lp_xtal_workaround) {
 586                 iwl_pcie_apm_lp_xtal_enable(trans);
 587                 return;
 588         }
 589
 590         iwl_trans_pcie_sw_reset(trans);
 591
 592         /*
 593          * Clear "initialization complete" bit to move adapter from
 594          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 595          */
 596         iwl_clear_bit(trans, CSR_GP_CNTRL,
 597                       BIT(trans->cfg->csr->flag_init_done));
 598 }
 599
 600 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 601 {
 602         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 603         int ret;
 604
 605         /* nic_init */
 606         spin_lock(&trans_pcie->irq_lock);
 607         ret = iwl_pcie_apm_init(trans);
 608         spin_unlock(&trans_pcie->irq_lock);
 609
 610         if (ret)
 611                 return ret;
 612
 613         iwl_pcie_set_pwr(trans, false);
 614
 615         iwl_op_mode_nic_config(trans->op_mode);
 616
 617         /* Allocate the RX queue, or reset if it is already allocated */
 618         iwl_pcie_rx_init(trans);
 619
 620         /* Allocate or reset and init all Tx and Command queues */
 621         if (iwl_pcie_tx_init(trans))
 622                 return -ENOMEM;
 623
 624         if (trans->cfg->base_params->shadow_reg_enable) {
 625                 /* enable shadow regs in HW */
 626                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 627                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 628         }
 629
 630         return 0;
 631 }
 632
 633 #define HW_READY_TIMEOUT (50)
 634
 635 /* Note: returns poll_bit return value, which is >= 0 if success */
 636 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 637 {
 638         int ret;
 639
 640         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 641                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 642
 643         /* See if we got it */
 644         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 645                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 646                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 647                            HW_READY_TIMEOUT);
 648
 649         if (ret >= 0)
 650                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 651
 652         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 653         return ret;
 654 }
 655
 656 /* Note: returns standard 0/-ERROR code */
 657 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 658 {
 659         int ret;
 660         int t = 0;
 661         int iter;
 662
 663         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 664
 665         ret = iwl_pcie_set_hw_ready(trans);
 666         /* If the card is ready, exit 0 */
 667         if (ret >= 0)
 668                 return 0;
 669
 670         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 671                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 672         usleep_range(1000, 2000);
 673
 674         for (iter = 0; iter < 10; iter++) {
 675                 /* If HW is not ready, prepare the conditions to check again */
 676                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 677                             CSR_HW_IF_CONFIG_REG_PREPARE);
 678
 679                 do {
 680                         ret = iwl_pcie_set_hw_ready(trans);
 681                         if (ret >= 0)
 682                                 return 0;
 683
 684                         usleep_range(200, 1000);
 685                         t += 200;
 686                 } while (t < 150000);
 687                 msleep(25);
 688         }
 689
 690         IWL_ERR(trans, "Couldn't prepare the card\n");
 691
 692         return ret;
 693 }
 694
 695 /*
 696  * ucode
 697  */
 698 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 699                                             u32 dst_addr, dma_addr_t phy_addr,
 700                                             u32 byte_cnt)
 701 {
 702         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 703                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 704
 705         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 706                     dst_addr);
 707
 708         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 709                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 710
 711         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 712                     (iwl_get_dma_hi_addr(phy_addr)
 713                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 714
 715         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 716                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 717                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 718                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 719
 720         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 721                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 722                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 723                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 724 }
 725
 726 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 727                                         u32 dst_addr, dma_addr_t phy_addr,
 728                                         u32 byte_cnt)
 729 {
 730         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 731         unsigned long flags;
 732         int ret;
 733
 734         trans_pcie->ucode_write_complete = false;
 735
 736         if (!iwl_trans_grab_nic_access(trans, &flags))
 737                 return -EIO;
 738
 739         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 740                                         byte_cnt);
 741         iwl_trans_release_nic_access(trans, &flags);
 742
 743         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 744                                  trans_pcie->ucode_write_complete, 5 * HZ);
 745         if (!ret) {
 746                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 747                 iwl_trans_pcie_dump_regs(trans);
 748                 return -ETIMEDOUT;
 749         }
 750
 751         return 0;
 752 }
 753
 754 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 755                             const struct fw_desc *section)
 756 {
 757         u8 *v_addr;
 758         dma_addr_t p_addr;
 759         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 760         int ret = 0;
 761
 762         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 763                      section_num);
 764
 765         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 766                                     GFP_KERNEL | __GFP_NOWARN);
 767         if (!v_addr) {
 768                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 769                 chunk_sz = PAGE_SIZE;
 770                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 771                                             &p_addr, GFP_KERNEL);
 772                 if (!v_addr)
 773                         return -ENOMEM;
 774         }
 775
 776         for (offset = 0; offset < section->len; offset += chunk_sz) {
 777                 u32 copy_size, dst_addr;
 778                 bool extended_addr = false;
 779
 780                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 781                 dst_addr = section->offset + offset;
 782
 783                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 784                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 785                         extended_addr = true;
 786
 787                 if (extended_addr)
 788                         iwl_set_bits_prph(trans, LMPM_CHICK,
 789                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 790
 791                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 792                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 793                                                    copy_size);
 794
 795                 if (extended_addr)
 796                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 797                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 798
 799                 if (ret) {
 800                         IWL_ERR(trans,
 801                                 "Could not load the [%d] uCode section\n",
 802                                 section_num);
 803                         break;
 804                 }
 805         }
 806
 807         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 808         return ret;
 809 }
 810
 811 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 812                                            const struct fw_img *image,
 813                                            int cpu,
 814                                            int *first_ucode_section)
 815 {
 816         int shift_param;
 817         int i, ret = 0, sec_num = 0x1;
 818         u32 val, last_read_idx = 0;
 819
 820         if (cpu == 1) {
 821                 shift_param = 0;
 822                 *first_ucode_section = 0;
 823         } else {
 824                 shift_param = 16;
 825                 (*first_ucode_section)++;
 826         }
 827
 828         for (i = *first_ucode_section; i < image->num_sec; i++) {
 829                 last_read_idx = i;
 830
 831                 /*
 832                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 833                  * CPU1 to CPU2.
 834                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 835                  * CPU2 non paged to CPU2 paging sec.
 836                  */
 837                 if (!image->sec[i].data ||
 838                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 839                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 840                         IWL_DEBUG_FW(trans,
 841                                      "Break since Data not valid or Empty section, sec = %d\n",
 842                                      i);
 843                         break;
 844                 }
 845
 846                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 847                 if (ret)
 848                         return ret;
 849
 850                 /* Notify ucode of loaded section number and status */
 851                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 852                 val = val | (sec_num << shift_param);
 853                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 854
 855                 sec_num = (sec_num << 1) | 0x1;
 856         }
 857
 858         *first_ucode_section = last_read_idx;
 859
 860         iwl_enable_interrupts(trans);
 861
 862         if (trans->cfg->use_tfh) {
 863                 if (cpu == 1)
 864                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 865                                        0xFFFF);
 866                 else
 867                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 868                                        0xFFFFFFFF);
 869         } else {
 870                 if (cpu == 1)
 871                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 872                                            0xFFFF);
 873                 else
 874                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 875                                            0xFFFFFFFF);
 876         }
 877
 878         return 0;
 879 }
 880
 881 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 882                                       const struct fw_img *image,
 883                                       int cpu,
 884                                       int *first_ucode_section)
 885 {
 886         int i, ret = 0;
 887         u32 last_read_idx = 0;
 888
 889         if (cpu == 1)
 890                 *first_ucode_section = 0;
 891         else
 892                 (*first_ucode_section)++;
 893
 894         for (i = *first_ucode_section; i < image->num_sec; i++) {
 895                 last_read_idx = i;
 896
 897                 /*
 898                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 899                  * CPU1 to CPU2.
 900                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 901                  * CPU2 non paged to CPU2 paging sec.
 902                  */
 903                 if (!image->sec[i].data ||
 904                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 905                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 906                         IWL_DEBUG_FW(trans,
 907                                      "Break since Data not valid or Empty section, sec = %d\n",
 908                                      i);
 909                         break;
 910                 }
 911
 912                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 913                 if (ret)
 914                         return ret;
 915         }
 916
 917         *first_ucode_section = last_read_idx;
 918
 919         return 0;
 920 }
 921
 922 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 923 {
 924         const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv;
 925         int i;
 926
 927         if (trans->ini_valid) {
 928                 if (!trans->num_blocks)
 929                         return;
 930
 931                 iwl_write_prph(trans, MON_BUFF_BASE_ADDR_VER2,
 932                                trans->fw_mon[0].physical >>
 933                                MON_BUFF_SHIFT_VER2);
 934                 iwl_write_prph(trans, MON_BUFF_END_ADDR_VER2,
 935                                (trans->fw_mon[0].physical +
 936                                 trans->fw_mon[0].size - 256) >>
 937                                MON_BUFF_SHIFT_VER2);
 938                 return;
 939         }
 940
 941         IWL_INFO(trans, "Applying debug destination %s\n",
 942                  get_fw_dbg_mode_string(dest->monitor_mode));
 943
 944         if (dest->monitor_mode == EXTERNAL_MODE)
 945                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 946         else
 947                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 948
 949         for (i = 0; i < trans->dbg_n_dest_reg; i++) {
 950                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 951                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 952
 953                 switch (dest->reg_ops[i].op) {
 954                 case CSR_ASSIGN:
 955                         iwl_write32(trans, addr, val);
 956                         break;
 957                 case CSR_SETBIT:
 958                         iwl_set_bit(trans, addr, BIT(val));
 959                         break;
 960                 case CSR_CLEARBIT:
 961                         iwl_clear_bit(trans, addr, BIT(val));
 962                         break;
 963                 case PRPH_ASSIGN:
 964                         iwl_write_prph(trans, addr, val);
 965                         break;
 966                 case PRPH_SETBIT:
 967                         iwl_set_bits_prph(trans, addr, BIT(val));
 968                         break;
 969                 case PRPH_CLEARBIT:
 970                         iwl_clear_bits_prph(trans, addr, BIT(val));
 971                         break;
 972                 case PRPH_BLOCKBIT:
 973                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 974                                 IWL_ERR(trans,
 975                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 976                                         val, addr);
 977                                 goto monitor;
 978                         }
 979                         break;
 980                 default:
 981                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 982                                 dest->reg_ops[i].op);
 983                         break;
 984                 }
 985         }
 986
 987 monitor:
 988         if (dest->monitor_mode == EXTERNAL_MODE && trans->fw_mon[0].size) {
 989                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 990                                trans->fw_mon[0].physical >> dest->base_shift);
 991                 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 992                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 993                                        (trans->fw_mon[0].physical +
 994                                         trans->fw_mon[0].size - 256) >>
 995                                                 dest->end_shift);
 996                 else
 997                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 998                                        (trans->fw_mon[0].physical +
 999                                         trans->fw_mon[0].size) >>
1000                                                 dest->end_shift);
1001         }
1002 }
1003
1004 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
1005                                 const struct fw_img *image)
1006 {
1007         int ret = 0;
1008         int first_ucode_section;
1009
1010         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1011                      image->is_dual_cpus ? "Dual" : "Single");
1012
1013         /* load to FW the binary non secured sections of CPU1 */
1014         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1015         if (ret)
1016                 return ret;
1017
1018         if (image->is_dual_cpus) {
1019                 /* set CPU2 header address */
1020                 iwl_write_prph(trans,
1021                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1022                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1023
1024                 /* load to FW the binary sections of CPU2 */
1025                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1026                                                  &first_ucode_section);
1027                 if (ret)
1028                         return ret;
1029         }
1030
1031         /* supported for 7000 only for the moment */
1032         if (iwlwifi_mod_params.fw_monitor &&
1033             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1034                 iwl_pcie_alloc_fw_monitor(trans, 0);
1035
1036                 if (trans->fw_mon[0].size) {
1037                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1038                                        trans->fw_mon[0].physical >> 4);
1039                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
1040                                        (trans->fw_mon[0].physical +
1041                                         trans->fw_mon[0].size) >> 4);
1042                 }
1043         } else if (iwl_pcie_dbg_on(trans)) {
1044                 iwl_pcie_apply_destination(trans);
1045         }
1046
1047         iwl_enable_interrupts(trans);
1048
1049         /* release CPU reset */
1050         iwl_write32(trans, CSR_RESET, 0);
1051
1052         return 0;
1053 }
1054
1055 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1056                                           const struct fw_img *image)
1057 {
1058         int ret = 0;
1059         int first_ucode_section;
1060
1061         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1062                      image->is_dual_cpus ? "Dual" : "Single");
1063
1064         if (iwl_pcie_dbg_on(trans))
1065                 iwl_pcie_apply_destination(trans);
1066
1067         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1068                         iwl_read_prph(trans, WFPM_GP2));
1069
1070         /*
1071          * Set default value. On resume reading the values that were
1072          * zeored can provide debug data on the resume flow.
1073          * This is for debugging only and has no functional impact.
1074          */
1075         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1076
1077         /* configure the ucode to be ready to get the secured image */
1078         /* release CPU reset */
1079         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1080
1081         /* load to FW the binary Secured sections of CPU1 */
1082         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1083                                               &first_ucode_section);
1084         if (ret)
1085                 return ret;
1086
1087         /* load to FW the binary sections of CPU2 */
1088         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1089                                                &first_ucode_section);
1090 }
1091
1092 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1093 {
1094         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1095         bool hw_rfkill = iwl_is_rfkill_set(trans);
1096         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1097         bool report;
1098
1099         if (hw_rfkill) {
1100                 set_bit(STATUS_RFKILL_HW, &trans->status);
1101                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1102         } else {
1103                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1104                 if (trans_pcie->opmode_down)
1105                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1106         }
1107
1108         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1109
1110         if (prev != report)
1111                 iwl_trans_pcie_rf_kill(trans, report);
1112
1113         return hw_rfkill;
1114 }
1115
1116 struct iwl_causes_list {
1117         u32 cause_num;
1118         u32 mask_reg;
1119         u8 addr;
1120 };
1121
1122 static struct iwl_causes_list causes_list[] = {
1123         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1124         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1125         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1126         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1127         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1128         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1129         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1130         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1131         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1132         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1133         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1134         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1135         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1136         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1137 };
1138
1139 static struct iwl_causes_list causes_list_v2[] = {
1140         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1141         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1142         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1143         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1144         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1145         {MSIX_HW_INT_CAUSES_REG_IPC,            CSR_MSIX_HW_INT_MASK_AD, 0x11},
1146         {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2,      CSR_MSIX_HW_INT_MASK_AD, 0x15},
1147         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1148         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1149         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1150         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1151         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1152         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1153         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1154 };
1155
1156 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1157 {
1158         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1159         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1160         int i, arr_size =
1161                 (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1162                 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2);
1163
1164         /*
1165          * Access all non RX causes and map them to the default irq.
1166          * In case we are missing at least one interrupt vector,
1167          * the first interrupt vector will serve non-RX and FBQ causes.
1168          */
1169         for (i = 0; i < arr_size; i++) {
1170                 struct iwl_causes_list *causes =
1171                         (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1172                         causes_list : causes_list_v2;
1173
1174                 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1175                 iwl_clear_bit(trans, causes[i].mask_reg,
1176                               causes[i].cause_num);
1177         }
1178 }
1179
1180 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1181 {
1182         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1183         u32 offset =
1184                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1185         u32 val, idx;
1186
1187         /*
1188          * The first RX queue - fallback queue, which is designated for
1189          * management frame, command responses etc, is always mapped to the
1190          * first interrupt vector. The other RX queues are mapped to
1191          * the other (N - 2) interrupt vectors.
1192          */
1193         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1194         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1195                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1196                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1197                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1198         }
1199         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1200
1201         val = MSIX_FH_INT_CAUSES_Q(0);
1202         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1203                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1204         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1205
1206         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1207                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1208 }
1209
1210 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1211 {
1212         struct iwl_trans *trans = trans_pcie->trans;
1213
1214         if (!trans_pcie->msix_enabled) {
1215                 if (trans->cfg->mq_rx_supported &&
1216                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1217                         iwl_write_prph(trans, UREG_CHICK,
1218                                        UREG_CHICK_MSI_ENABLE);
1219                 return;
1220         }
1221         /*
1222          * The IVAR table needs to be configured again after reset,
1223          * but if the device is disabled, we can't write to
1224          * prph.
1225          */
1226         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1227                 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1228
1229         /*
1230          * Each cause from the causes list above and the RX causes is
1231          * represented as a byte in the IVAR table. The first nibble
1232          * represents the bound interrupt vector of the cause, the second
1233          * represents no auto clear for this cause. This will be set if its
1234          * interrupt vector is bound to serve other causes.
1235          */
1236         iwl_pcie_map_rx_causes(trans);
1237
1238         iwl_pcie_map_non_rx_causes(trans);
1239 }
1240
1241 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1242 {
1243         struct iwl_trans *trans = trans_pcie->trans;
1244
1245         iwl_pcie_conf_msix_hw(trans_pcie);
1246
1247         if (!trans_pcie->msix_enabled)
1248                 return;
1249
1250         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1251         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1252         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1253         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1254 }
1255
1256 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1257 {
1258         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1259
1260         lockdep_assert_held(&trans_pcie->mutex);
1261
1262         if (trans_pcie->is_down)
1263                 return;
1264
1265         trans_pcie->is_down = true;
1266
1267         /* Stop dbgc before stopping device */
1268         _iwl_fw_dbg_stop_recording(trans, NULL);
1269
1270         /* tell the device to stop sending interrupts */
1271         iwl_disable_interrupts(trans);
1272
1273         /* device going down, Stop using ICT table */
1274         iwl_pcie_disable_ict(trans);
1275
1276         /*
1277          * If a HW restart happens during firmware loading,
1278          * then the firmware loading might call this function
1279          * and later it might be called again due to the
1280          * restart. So don't process again if the device is
1281          * already dead.
1282          */
1283         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1284                 IWL_DEBUG_INFO(trans,
1285                                "DEVICE_ENABLED bit was set and is now cleared\n");
1286                 iwl_pcie_tx_stop(trans);
1287                 iwl_pcie_rx_stop(trans);
1288
1289                 /* Power-down device's busmaster DMA clocks */
1290                 if (!trans->cfg->apmg_not_supported) {
1291                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1292                                        APMG_CLK_VAL_DMA_CLK_RQT);
1293                         udelay(5);
1294                 }
1295         }
1296
1297         /* Make sure (redundant) we've released our request to stay awake */
1298         iwl_clear_bit(trans, CSR_GP_CNTRL,
1299                       BIT(trans->cfg->csr->flag_mac_access_req));
1300
1301         /* Stop the device, and put it in low power state */
1302         iwl_pcie_apm_stop(trans, false);
1303
1304         iwl_trans_pcie_sw_reset(trans);
1305
1306         /*
1307          * Upon stop, the IVAR table gets erased, so msi-x won't
1308          * work. This causes a bug in RF-KILL flows, since the interrupt
1309          * that enables radio won't fire on the correct irq, and the
1310          * driver won't be able to handle the interrupt.
1311          * Configure the IVAR table again after reset.
1312          */
1313         iwl_pcie_conf_msix_hw(trans_pcie);
1314
1315         /*
1316          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1317          * This is a bug in certain verions of the hardware.
1318          * Certain devices also keep sending HW RF kill interrupt all
1319          * the time, unless the interrupt is ACKed even if the interrupt
1320          * should be masked. Re-ACK all the interrupts here.
1321          */
1322         iwl_disable_interrupts(trans);
1323
1324         /* clear all status bits */
1325         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1326         clear_bit(STATUS_INT_ENABLED, &trans->status);
1327         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1328
1329         /*
1330          * Even if we stop the HW, we still want the RF kill
1331          * interrupt
1332          */
1333         iwl_enable_rfkill_int(trans);
1334
1335         /* re-take ownership to prevent other users from stealing the device */
1336         iwl_pcie_prepare_card_hw(trans);
1337 }
1338
1339 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1340 {
1341         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1342
1343         if (trans_pcie->msix_enabled) {
1344                 int i;
1345
1346                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1347                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1348         } else {
1349                 synchronize_irq(trans_pcie->pci_dev->irq);
1350         }
1351 }
1352
1353 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1354                                    const struct fw_img *fw, bool run_in_rfkill)
1355 {
1356         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1357         bool hw_rfkill;
1358         int ret;
1359
1360         /* This may fail if AMT took ownership of the device */
1361         if (iwl_pcie_prepare_card_hw(trans)) {
1362                 IWL_WARN(trans, "Exit HW not ready\n");
1363                 ret = -EIO;
1364                 goto out;
1365         }
1366
1367         iwl_enable_rfkill_int(trans);
1368
1369         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1370
1371         /*
1372          * We enabled the RF-Kill interrupt and the handler may very
1373          * well be running. Disable the interrupts to make sure no other
1374          * interrupt can be fired.
1375          */
1376         iwl_disable_interrupts(trans);
1377
1378         /* Make sure it finished running */
1379         iwl_pcie_synchronize_irqs(trans);
1380
1381         mutex_lock(&trans_pcie->mutex);
1382
1383         /* If platform's RF_KILL switch is NOT set to KILL */
1384         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1385         if (hw_rfkill && !run_in_rfkill) {
1386                 ret = -ERFKILL;
1387                 goto out;
1388         }
1389
1390         /* Someone called stop_device, don't try to start_fw */
1391         if (trans_pcie->is_down) {
1392                 IWL_WARN(trans,
1393                          "Can't start_fw since the HW hasn't been started\n");
1394                 ret = -EIO;
1395                 goto out;
1396         }
1397
1398         /* make sure rfkill handshake bits are cleared */
1399         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1400         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1401                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1402
1403         /* clear (again), then enable host interrupts */
1404         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1405
1406         ret = iwl_pcie_nic_init(trans);
1407         if (ret) {
1408                 IWL_ERR(trans, "Unable to init nic\n");
1409                 goto out;
1410         }
1411
1412         /*
1413          * Now, we load the firmware and don't want to be interrupted, even
1414          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1415          * FH_TX interrupt which is needed to load the firmware). If the
1416          * RF-Kill switch is toggled, we will find out after having loaded
1417          * the firmware and return the proper value to the caller.
1418          */
1419         iwl_enable_fw_load_int(trans);
1420
1421         /* really make sure rfkill handshake bits are cleared */
1422         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1423         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1424
1425         /* Load the given image to the HW */
1426         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1427                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1428         else
1429                 ret = iwl_pcie_load_given_ucode(trans, fw);
1430
1431         /* re-check RF-Kill state since we may have missed the interrupt */
1432         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1433         if (hw_rfkill && !run_in_rfkill)
1434                 ret = -ERFKILL;
1435
1436 out:
1437         mutex_unlock(&trans_pcie->mutex);
1438         return ret;
1439 }
1440
1441 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1442 {
1443         iwl_pcie_reset_ict(trans);
1444         iwl_pcie_tx_start(trans, scd_addr);
1445 }
1446
1447 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1448                                        bool was_in_rfkill)
1449 {
1450         bool hw_rfkill;
1451
1452         /*
1453          * Check again since the RF kill state may have changed while
1454          * all the interrupts were disabled, in this case we couldn't
1455          * receive the RF kill interrupt and update the state in the
1456          * op_mode.
1457          * Don't call the op_mode if the rkfill state hasn't changed.
1458          * This allows the op_mode to call stop_device from the rfkill
1459          * notification without endless recursion. Under very rare
1460          * circumstances, we might have a small recursion if the rfkill
1461          * state changed exactly now while we were called from stop_device.
1462          * This is very unlikely but can happen and is supported.
1463          */
1464         hw_rfkill = iwl_is_rfkill_set(trans);
1465         if (hw_rfkill) {
1466                 set_bit(STATUS_RFKILL_HW, &trans->status);
1467                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1468         } else {
1469                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1470                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1471         }
1472         if (hw_rfkill != was_in_rfkill)
1473                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1474 }
1475
1476 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1477 {
1478         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1479         bool was_in_rfkill;
1480
1481         mutex_lock(&trans_pcie->mutex);
1482         trans_pcie->opmode_down = true;
1483         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1484         _iwl_trans_pcie_stop_device(trans, low_power);
1485         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1486         mutex_unlock(&trans_pcie->mutex);
1487 }
1488
1489 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1490 {
1491         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1492                 IWL_TRANS_GET_PCIE_TRANS(trans);
1493
1494         lockdep_assert_held(&trans_pcie->mutex);
1495
1496         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1497                  state ? "disabled" : "enabled");
1498         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1499                 if (trans->cfg->gen2)
1500                         _iwl_trans_pcie_gen2_stop_device(trans, true);
1501                 else
1502                         _iwl_trans_pcie_stop_device(trans, true);
1503         }
1504 }
1505
1506 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1507                                       bool reset)
1508 {
1509         if (!reset) {
1510                 /* Enable persistence mode to avoid reset */
1511                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1512                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1513         }
1514
1515         iwl_disable_interrupts(trans);
1516
1517         /*
1518          * in testing mode, the host stays awake and the
1519          * hardware won't be reset (not even partially)
1520          */
1521         if (test)
1522                 return;
1523
1524         iwl_pcie_disable_ict(trans);
1525
1526         iwl_pcie_synchronize_irqs(trans);
1527
1528         iwl_clear_bit(trans, CSR_GP_CNTRL,
1529                       BIT(trans->cfg->csr->flag_mac_access_req));
1530         iwl_clear_bit(trans, CSR_GP_CNTRL,
1531                       BIT(trans->cfg->csr->flag_init_done));
1532
1533         iwl_pcie_enable_rx_wake(trans, false);
1534
1535         if (reset) {
1536                 /*
1537                  * reset TX queues -- some of their registers reset during S3
1538                  * so if we don't reset everything here the D3 image would try
1539                  * to execute some invalid memory upon resume
1540                  */
1541                 iwl_trans_pcie_tx_reset(trans);
1542         }
1543
1544         iwl_pcie_set_pwr(trans, true);
1545 }
1546
1547 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1548                                     enum iwl_d3_status *status,
1549                                     bool test,  bool reset)
1550 {
1551         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1552         u32 val;
1553         int ret;
1554
1555         if (test) {
1556                 iwl_enable_interrupts(trans);
1557                 *status = IWL_D3_STATUS_ALIVE;
1558                 return 0;
1559         }
1560
1561         iwl_pcie_enable_rx_wake(trans, true);
1562
1563         iwl_set_bit(trans, CSR_GP_CNTRL,
1564                     BIT(trans->cfg->csr->flag_mac_access_req));
1565         iwl_set_bit(trans, CSR_GP_CNTRL,
1566                     BIT(trans->cfg->csr->flag_init_done));
1567
1568         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1569                 udelay(2);
1570
1571         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1572                            BIT(trans->cfg->csr->flag_mac_clock_ready),
1573                            BIT(trans->cfg->csr->flag_mac_clock_ready),
1574                            25000);
1575         if (ret < 0) {
1576                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1577                 return ret;
1578         }
1579
1580         /*
1581          * Reconfigure IVAR table in case of MSIX or reset ict table in
1582          * MSI mode since HW reset erased it.
1583          * Also enables interrupts - none will happen as
1584          * the device doesn't know we're waking it up, only when
1585          * the opmode actually tells it after this call.
1586          */
1587         iwl_pcie_conf_msix_hw(trans_pcie);
1588         if (!trans_pcie->msix_enabled)
1589                 iwl_pcie_reset_ict(trans);
1590         iwl_enable_interrupts(trans);
1591
1592         iwl_pcie_set_pwr(trans, false);
1593
1594         if (!reset) {
1595                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1596                               BIT(trans->cfg->csr->flag_mac_access_req));
1597         } else {
1598                 iwl_trans_pcie_tx_reset(trans);
1599
1600                 ret = iwl_pcie_rx_init(trans);
1601                 if (ret) {
1602                         IWL_ERR(trans,
1603                                 "Failed to resume the device (RX reset)\n");
1604                         return ret;
1605                 }
1606         }
1607
1608         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1609                         iwl_read_prph(trans, WFPM_GP2));
1610
1611         val = iwl_read32(trans, CSR_RESET);
1612         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1613                 *status = IWL_D3_STATUS_RESET;
1614         else
1615                 *status = IWL_D3_STATUS_ALIVE;
1616
1617         return 0;
1618 }
1619
1620 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1621                                         struct iwl_trans *trans)
1622 {
1623         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1624         int max_irqs, num_irqs, i, ret;
1625         u16 pci_cmd;
1626
1627         if (!trans->cfg->mq_rx_supported)
1628                 goto enable_msi;
1629
1630         max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
1631         for (i = 0; i < max_irqs; i++)
1632                 trans_pcie->msix_entries[i].entry = i;
1633
1634         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1635                                          MSIX_MIN_INTERRUPT_VECTORS,
1636                                          max_irqs);
1637         if (num_irqs < 0) {
1638                 IWL_DEBUG_INFO(trans,
1639                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1640                                num_irqs);
1641                 goto enable_msi;
1642         }
1643         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1644
1645         IWL_DEBUG_INFO(trans,
1646                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1647                        num_irqs);
1648
1649         /*
1650          * In case the OS provides fewer interrupts than requested, different
1651          * causes will share the same interrupt vector as follows:
1652          * One interrupt less: non rx causes shared with FBQ.
1653          * Two interrupts less: non rx causes shared with FBQ and RSS.
1654          * More than two interrupts: we will use fewer RSS queues.
1655          */
1656         if (num_irqs <= max_irqs - 2) {
1657                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1658                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1659                         IWL_SHARED_IRQ_FIRST_RSS;
1660         } else if (num_irqs == max_irqs - 1) {
1661                 trans_pcie->trans->num_rx_queues = num_irqs;
1662                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1663         } else {
1664                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1665         }
1666         WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1667
1668         trans_pcie->alloc_vecs = num_irqs;
1669         trans_pcie->msix_enabled = true;
1670         return;
1671
1672 enable_msi:
1673         ret = pci_enable_msi(pdev);
1674         if (ret) {
1675                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1676                 /* enable rfkill interrupt: hw bug w/a */
1677                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1678                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1679                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1680                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1681                 }
1682         }
1683 }
1684
1685 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1686 {
1687         int iter_rx_q, i, ret, cpu, offset;
1688         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1689
1690         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1691         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1692         offset = 1 + i;
1693         for (; i < iter_rx_q ; i++) {
1694                 /*
1695                  * Get the cpu prior to the place to search
1696                  * (i.e. return will be > i - 1).
1697                  */
1698                 cpu = cpumask_next(i - offset, cpu_online_mask);
1699                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1700                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1701                                             &trans_pcie->affinity_mask[i]);
1702                 if (ret)
1703                         IWL_ERR(trans_pcie->trans,
1704                                 "Failed to set affinity mask for IRQ %d\n",
1705                                 i);
1706         }
1707 }
1708
1709 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1710                                       struct iwl_trans_pcie *trans_pcie)
1711 {
1712         int i;
1713
1714         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1715                 int ret;
1716                 struct msix_entry *msix_entry;
1717                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1718
1719                 if (!qname)
1720                         return -ENOMEM;
1721
1722                 msix_entry = &trans_pcie->msix_entries[i];
1723                 ret = devm_request_threaded_irq(&pdev->dev,
1724                                                 msix_entry->vector,
1725                                                 iwl_pcie_msix_isr,
1726                                                 (i == trans_pcie->def_irq) ?
1727                                                 iwl_pcie_irq_msix_handler :
1728                                                 iwl_pcie_irq_rx_msix_handler,
1729                                                 IRQF_SHARED,
1730                                                 qname,
1731                                                 msix_entry);
1732                 if (ret) {
1733                         IWL_ERR(trans_pcie->trans,
1734                                 "Error allocating IRQ %d\n", i);
1735
1736                         return ret;
1737                 }
1738         }
1739         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1740
1741         return 0;
1742 }
1743
1744 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1745 {
1746         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1747         u32 hpm;
1748         int err;
1749
1750         lockdep_assert_held(&trans_pcie->mutex);
1751
1752         err = iwl_pcie_prepare_card_hw(trans);
1753         if (err) {
1754                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1755                 return err;
1756         }
1757
1758         hpm = iwl_trans_read_prph(trans, HPM_DEBUG);
1759         if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1760                 if (iwl_trans_read_prph(trans, PREG_PRPH_WPROT_0) &
1761                     PREG_WFPM_ACCESS) {
1762                         IWL_ERR(trans,
1763                                 "Error, can not clear persistence bit\n");
1764                         return -EPERM;
1765                 }
1766                 iwl_trans_write_prph(trans, HPM_DEBUG, hpm & ~PERSISTENCE_BIT);
1767         }
1768
1769         iwl_trans_pcie_sw_reset(trans);
1770
1771         err = iwl_pcie_apm_init(trans);
1772         if (err)
1773                 return err;
1774
1775         iwl_pcie_init_msix(trans_pcie);
1776
1777         /* From now on, the op_mode will be kept updated about RF kill state */
1778         iwl_enable_rfkill_int(trans);
1779
1780         trans_pcie->opmode_down = false;
1781
1782         /* Set is_down to false here so that...*/
1783         trans_pcie->is_down = false;
1784
1785         /* ...rfkill can call stop_device and set it false if needed */
1786         iwl_pcie_check_hw_rf_kill(trans);
1787
1788         /* Make sure we sync here, because we'll need full access later */
1789         if (low_power)
1790                 pm_runtime_resume(trans->dev);
1791
1792         return 0;
1793 }
1794
1795 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1796 {
1797         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1798         int ret;
1799
1800         mutex_lock(&trans_pcie->mutex);
1801         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1802         mutex_unlock(&trans_pcie->mutex);
1803
1804         return ret;
1805 }
1806
1807 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1808 {
1809         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1810
1811         mutex_lock(&trans_pcie->mutex);
1812
1813         /* disable interrupts - don't enable HW RF kill interrupt */
1814         iwl_disable_interrupts(trans);
1815
1816         iwl_pcie_apm_stop(trans, true);
1817
1818         iwl_disable_interrupts(trans);
1819
1820         iwl_pcie_disable_ict(trans);
1821
1822         mutex_unlock(&trans_pcie->mutex);
1823
1824         iwl_pcie_synchronize_irqs(trans);
1825 }
1826
1827 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1828 {
1829         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1830 }
1831
1832 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1833 {
1834         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1835 }
1836
1837 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1838 {
1839         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1840 }
1841
1842 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1843 {
1844         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1845                 return 0x00FFFFFF;
1846         else
1847                 return 0x000FFFFF;
1848 }
1849
1850 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1851 {
1852         u32 mask = iwl_trans_pcie_prph_msk(trans);
1853
1854         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1855                                ((reg & mask) | (3 << 24)));
1856         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1857 }
1858
1859 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1860                                       u32 val)
1861 {
1862         u32 mask = iwl_trans_pcie_prph_msk(trans);
1863
1864         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1865                                ((addr & mask) | (3 << 24)));
1866         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1867 }
1868
1869 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1870                                      const struct iwl_trans_config *trans_cfg)
1871 {
1872         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1873
1874         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1875         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1876         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1877         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1878                 trans_pcie->n_no_reclaim_cmds = 0;
1879         else
1880                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1881         if (trans_pcie->n_no_reclaim_cmds)
1882                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1883                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1884
1885         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1886         trans_pcie->rx_page_order =
1887                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1888
1889         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1890         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1891         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1892
1893         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1894         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1895
1896         trans->command_groups = trans_cfg->command_groups;
1897         trans->command_groups_size = trans_cfg->command_groups_size;
1898
1899         /* Initialize NAPI here - it should be before registering to mac80211
1900          * in the opmode but after the HW struct is allocated.
1901          * As this function may be called again in some corner cases don't
1902          * do anything if NAPI was already initialized.
1903          */
1904         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1905                 init_dummy_netdev(&trans_pcie->napi_dev);
1906 }
1907
1908 void iwl_trans_pcie_free(struct iwl_trans *trans)
1909 {
1910         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1911         int i;
1912
1913         iwl_pcie_synchronize_irqs(trans);
1914
1915         if (trans->cfg->gen2)
1916                 iwl_pcie_gen2_tx_free(trans);
1917         else
1918                 iwl_pcie_tx_free(trans);
1919         iwl_pcie_rx_free(trans);
1920
1921         if (trans_pcie->rba.alloc_wq) {
1922                 destroy_workqueue(trans_pcie->rba.alloc_wq);
1923                 trans_pcie->rba.alloc_wq = NULL;
1924         }
1925
1926         if (trans_pcie->msix_enabled) {
1927                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1928                         irq_set_affinity_hint(
1929                                 trans_pcie->msix_entries[i].vector,
1930                                 NULL);
1931                 }
1932
1933                 trans_pcie->msix_enabled = false;
1934         } else {
1935                 iwl_pcie_free_ict(trans);
1936         }
1937
1938         iwl_pcie_free_fw_monitor(trans);
1939
1940         for_each_possible_cpu(i) {
1941                 struct iwl_tso_hdr_page *p =
1942                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1943
1944                 if (p->page)
1945                         __free_page(p->page);
1946         }
1947
1948         free_percpu(trans_pcie->tso_hdr_page);
1949         mutex_destroy(&trans_pcie->mutex);
1950         iwl_trans_free(trans);
1951 }
1952
1953 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1954 {
1955         if (state)
1956                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1957         else
1958                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1959 }
1960
1961 struct iwl_trans_pcie_removal {
1962         struct pci_dev *pdev;
1963         struct work_struct work;
1964 };
1965
1966 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
1967 {
1968         struct iwl_trans_pcie_removal *removal =
1969                 container_of(wk, struct iwl_trans_pcie_removal, work);
1970         struct pci_dev *pdev = removal->pdev;
1971         char *prop[] = {"EVENT=INACCESSIBLE", NULL};
1972
1973         dev_err(&pdev->dev, "Device gone - attempting removal\n");
1974         kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
1975         pci_lock_rescan_remove();
1976         pci_dev_put(pdev);
1977         pci_stop_and_remove_bus_device(pdev);
1978         pci_unlock_rescan_remove();
1979
1980         kfree(removal);
1981         module_put(THIS_MODULE);
1982 }
1983
1984 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1985                                            unsigned long *flags)
1986 {
1987         int ret;
1988         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1989
1990         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1991
1992         if (trans_pcie->cmd_hold_nic_awake)
1993                 goto out;
1994
1995         /* this bit wakes up the NIC */
1996         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1997                                  BIT(trans->cfg->csr->flag_mac_access_req));
1998         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1999                 udelay(2);
2000
2001         /*
2002          * These bits say the device is running, and should keep running for
2003          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2004          * but they do not indicate that embedded SRAM is restored yet;
2005          * HW with volatile SRAM must save/restore contents to/from
2006          * host DRAM when sleeping/waking for power-saving.
2007          * Each direction takes approximately 1/4 millisecond; with this
2008          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2009          * series of register accesses are expected (e.g. reading Event Log),
2010          * to keep device from sleeping.
2011          *
2012          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2013          * SRAM is okay/restored.  We don't check that here because this call
2014          * is just for hardware register access; but GP1 MAC_SLEEP
2015          * check is a good idea before accessing the SRAM of HW with
2016          * volatile SRAM (e.g. reading Event Log).
2017          *
2018          * 5000 series and later (including 1000 series) have non-volatile SRAM,
2019          * and do not save/restore SRAM when power cycling.
2020          */
2021         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2022                            BIT(trans->cfg->csr->flag_val_mac_access_en),
2023                            (BIT(trans->cfg->csr->flag_mac_clock_ready) |
2024                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2025         if (unlikely(ret < 0)) {
2026                 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2027
2028                 WARN_ONCE(1,
2029                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2030                           cntrl);
2031
2032                 iwl_trans_pcie_dump_regs(trans);
2033
2034                 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2035                         struct iwl_trans_pcie_removal *removal;
2036
2037                         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2038                                 goto err;
2039
2040                         IWL_ERR(trans, "Device gone - scheduling removal!\n");
2041
2042                         /*
2043                          * get a module reference to avoid doing this
2044                          * while unloading anyway and to avoid
2045                          * scheduling a work with code that's being
2046                          * removed.
2047                          */
2048                         if (!try_module_get(THIS_MODULE)) {
2049                                 IWL_ERR(trans,
2050                                         "Module is being unloaded - abort\n");
2051                                 goto err;
2052                         }
2053
2054                         removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2055                         if (!removal) {
2056                                 module_put(THIS_MODULE);
2057                                 goto err;
2058                         }
2059                         /*
2060                          * we don't need to clear this flag, because
2061                          * the trans will be freed and reallocated.
2062                         */
2063                         set_bit(STATUS_TRANS_DEAD, &trans->status);
2064
2065                         removal->pdev = to_pci_dev(trans->dev);
2066                         INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2067                         pci_dev_get(removal->pdev);
2068                         schedule_work(&removal->work);
2069                 } else {
2070                         iwl_write32(trans, CSR_RESET,
2071                                     CSR_RESET_REG_FLAG_FORCE_NMI);
2072                 }
2073
2074 err:
2075                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2076                 return false;
2077         }
2078
2079 out:
2080         /*
2081          * Fool sparse by faking we release the lock - sparse will
2082          * track nic_access anyway.
2083          */
2084         __release(&trans_pcie->reg_lock);
2085         return true;
2086 }
2087
2088 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2089                                               unsigned long *flags)
2090 {
2091         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2092
2093         lockdep_assert_held(&trans_pcie->reg_lock);
2094
2095         /*
2096          * Fool sparse by faking we acquiring the lock - sparse will
2097          * track nic_access anyway.
2098          */
2099         __acquire(&trans_pcie->reg_lock);
2100
2101         if (trans_pcie->cmd_hold_nic_awake)
2102                 goto out;
2103
2104         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2105                                    BIT(trans->cfg->csr->flag_mac_access_req));
2106         /*
2107          * Above we read the CSR_GP_CNTRL register, which will flush
2108          * any previous writes, but we need the write that clears the
2109          * MAC_ACCESS_REQ bit to be performed before any other writes
2110          * scheduled on different CPUs (after we drop reg_lock).
2111          */
2112         mmiowb();
2113 out:
2114         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2115 }
2116
2117 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2118                                    void *buf, int dwords)
2119 {
2120         unsigned long flags;
2121         int offs, ret = 0;
2122         u32 *vals = buf;
2123
2124         if (iwl_trans_grab_nic_access(trans, &flags)) {
2125                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2126                 for (offs = 0; offs < dwords; offs++)
2127                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
2128                 iwl_trans_release_nic_access(trans, &flags);
2129         } else {
2130                 ret = -EBUSY;
2131         }
2132         return ret;
2133 }
2134
2135 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2136                                     const void *buf, int dwords)
2137 {
2138         unsigned long flags;
2139         int offs, ret = 0;
2140         const u32 *vals = buf;
2141
2142         if (iwl_trans_grab_nic_access(trans, &flags)) {
2143                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2144                 for (offs = 0; offs < dwords; offs++)
2145                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2146                                     vals ? vals[offs] : 0);
2147                 iwl_trans_release_nic_access(trans, &flags);
2148         } else {
2149                 ret = -EBUSY;
2150         }
2151         return ret;
2152 }
2153
2154 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2155                                             unsigned long txqs,
2156                                             bool freeze)
2157 {
2158         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2159         int queue;
2160
2161         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2162                 struct iwl_txq *txq = trans_pcie->txq[queue];
2163                 unsigned long now;
2164
2165                 spin_lock_bh(&txq->lock);
2166
2167                 now = jiffies;
2168
2169                 if (txq->frozen == freeze)
2170                         goto next_queue;
2171
2172                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2173                                     freeze ? "Freezing" : "Waking", queue);
2174
2175                 txq->frozen = freeze;
2176
2177                 if (txq->read_ptr == txq->write_ptr)
2178                         goto next_queue;
2179
2180                 if (freeze) {
2181                         if (unlikely(time_after(now,
2182                                                 txq->stuck_timer.expires))) {
2183                                 /*
2184                                  * The timer should have fired, maybe it is
2185                                  * spinning right now on the lock.
2186                                  */
2187                                 goto next_queue;
2188                         }
2189                         /* remember how long until the timer fires */
2190                         txq->frozen_expiry_remainder =
2191                                 txq->stuck_timer.expires - now;
2192                         del_timer(&txq->stuck_timer);
2193                         goto next_queue;
2194                 }
2195
2196                 /*
2197                  * Wake a non-empty queue -> arm timer with the
2198                  * remainder before it froze
2199                  */
2200                 mod_timer(&txq->stuck_timer,
2201                           now + txq->frozen_expiry_remainder);
2202
2203 next_queue:
2204                 spin_unlock_bh(&txq->lock);
2205         }
2206 }
2207
2208 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2209 {
2210         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2211         int i;
2212
2213         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2214                 struct iwl_txq *txq = trans_pcie->txq[i];
2215
2216                 if (i == trans_pcie->cmd_queue)
2217                         continue;
2218
2219                 spin_lock_bh(&txq->lock);
2220
2221                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2222                         txq->block--;
2223                         if (!txq->block) {
2224                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2225                                             txq->write_ptr | (i << 8));
2226                         }
2227                 } else if (block) {
2228                         txq->block++;
2229                 }
2230
2231                 spin_unlock_bh(&txq->lock);
2232         }
2233 }
2234
2235 #define IWL_FLUSH_WAIT_MS       2000
2236
2237 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2238 {
2239         u32 txq_id = txq->id;
2240         u32 status;
2241         bool active;
2242         u8 fifo;
2243
2244         if (trans->cfg->use_tfh) {
2245                 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2246                         txq->read_ptr, txq->write_ptr);
2247                 /* TODO: access new SCD registers and dump them */
2248                 return;
2249         }
2250
2251         status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2252         fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2253         active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2254
2255         IWL_ERR(trans,
2256                 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2257                 txq_id, active ? "" : "in", fifo,
2258                 jiffies_to_msecs(txq->wd_timeout),
2259                 txq->read_ptr, txq->write_ptr,
2260                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2261                         (trans->cfg->base_params->max_tfd_queue_size - 1),
2262                 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2263                         (trans->cfg->base_params->max_tfd_queue_size - 1),
2264                 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2265 }
2266
2267 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2268                                        struct iwl_trans_rxq_dma_data *data)
2269 {
2270         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2271
2272         if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2273                 return -EINVAL;
2274
2275         data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2276         data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2277         data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2278         data->fr_bd_wid = 0;
2279
2280         return 0;
2281 }
2282
2283 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2284 {
2285         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2286         struct iwl_txq *txq;
2287         unsigned long now = jiffies;
2288         u8 wr_ptr;
2289
2290         /* Make sure the NIC is still alive in the bus */
2291         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2292                 return -ENODEV;
2293
2294         if (!test_bit(txq_idx, trans_pcie->queue_used))
2295                 return -EINVAL;
2296
2297         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2298         txq = trans_pcie->txq[txq_idx];
2299         wr_ptr = READ_ONCE(txq->write_ptr);
2300
2301         while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
2302                !time_after(jiffies,
2303                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2304                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2305
2306                 if (WARN_ONCE(wr_ptr != write_ptr,
2307                               "WR pointer moved while flushing %d -> %d\n",
2308                               wr_ptr, write_ptr))
2309                         return -ETIMEDOUT;
2310                 usleep_range(1000, 2000);
2311         }
2312
2313         if (txq->read_ptr != txq->write_ptr) {
2314                 IWL_ERR(trans,
2315                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2316                 iwl_trans_pcie_log_scd_error(trans, txq);
2317                 return -ETIMEDOUT;
2318         }
2319
2320         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2321
2322         return 0;
2323 }
2324
2325 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2326 {
2327         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2328         int cnt;
2329         int ret = 0;
2330
2331         /* waiting for all the tx frames complete might take a while */
2332         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2333
2334                 if (cnt == trans_pcie->cmd_queue)
2335                         continue;
2336                 if (!test_bit(cnt, trans_pcie->queue_used))
2337                         continue;
2338                 if (!(BIT(cnt) & txq_bm))
2339                         continue;
2340
2341                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2342                 if (ret)
2343                         break;
2344         }
2345
2346         return ret;
2347 }
2348
2349 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2350                                          u32 mask, u32 value)
2351 {
2352         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2353         unsigned long flags;
2354
2355         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2356         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2357         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2358 }
2359
2360 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2361 {
2362         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2363
2364         if (iwlwifi_mod_params.d0i3_disable)
2365                 return;
2366
2367         pm_runtime_get(&trans_pcie->pci_dev->dev);
2368
2369 #ifdef CONFIG_PM
2370         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2371                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2372 #endif /* CONFIG_PM */
2373 }
2374
2375 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2376 {
2377         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2378
2379         if (iwlwifi_mod_params.d0i3_disable)
2380                 return;
2381
2382         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2383         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2384
2385 #ifdef CONFIG_PM
2386         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2387                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2388 #endif /* CONFIG_PM */
2389 }
2390
2391 static const char *get_csr_string(int cmd)
2392 {
2393 #define IWL_CMD(x) case x: return #x
2394         switch (cmd) {
2395         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2396         IWL_CMD(CSR_INT_COALESCING);
2397         IWL_CMD(CSR_INT);
2398         IWL_CMD(CSR_INT_MASK);
2399         IWL_CMD(CSR_FH_INT_STATUS);
2400         IWL_CMD(CSR_GPIO_IN);
2401         IWL_CMD(CSR_RESET);
2402         IWL_CMD(CSR_GP_CNTRL);
2403         IWL_CMD(CSR_HW_REV);
2404         IWL_CMD(CSR_EEPROM_REG);
2405         IWL_CMD(CSR_EEPROM_GP);
2406         IWL_CMD(CSR_OTP_GP_REG);
2407         IWL_CMD(CSR_GIO_REG);
2408         IWL_CMD(CSR_GP_UCODE_REG);
2409         IWL_CMD(CSR_GP_DRIVER_REG);
2410         IWL_CMD(CSR_UCODE_DRV_GP1);
2411         IWL_CMD(CSR_UCODE_DRV_GP2);
2412         IWL_CMD(CSR_LED_REG);
2413         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2414         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2415         IWL_CMD(CSR_ANA_PLL_CFG);
2416         IWL_CMD(CSR_HW_REV_WA_REG);
2417         IWL_CMD(CSR_MONITOR_STATUS_REG);
2418         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2419         default:
2420                 return "UNKNOWN";
2421         }
2422 #undef IWL_CMD
2423 }
2424
2425 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2426 {
2427         int i;
2428         static const u32 csr_tbl[] = {
2429                 CSR_HW_IF_CONFIG_REG,
2430                 CSR_INT_COALESCING,
2431                 CSR_INT,
2432                 CSR_INT_MASK,
2433                 CSR_FH_INT_STATUS,
2434                 CSR_GPIO_IN,
2435                 CSR_RESET,
2436                 CSR_GP_CNTRL,
2437                 CSR_HW_REV,
2438                 CSR_EEPROM_REG,
2439                 CSR_EEPROM_GP,
2440                 CSR_OTP_GP_REG,
2441                 CSR_GIO_REG,
2442                 CSR_GP_UCODE_REG,
2443                 CSR_GP_DRIVER_REG,
2444                 CSR_UCODE_DRV_GP1,
2445                 CSR_UCODE_DRV_GP2,
2446                 CSR_LED_REG,
2447                 CSR_DRAM_INT_TBL_REG,
2448                 CSR_GIO_CHICKEN_BITS,
2449                 CSR_ANA_PLL_CFG,
2450                 CSR_MONITOR_STATUS_REG,
2451                 CSR_HW_REV_WA_REG,
2452                 CSR_DBG_HPET_MEM_REG
2453         };
2454         IWL_ERR(trans, "CSR values:\n");
2455         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2456                 "CSR_INT_PERIODIC_REG)\n");
2457         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2458                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2459                         get_csr_string(csr_tbl[i]),
2460                         iwl_read32(trans, csr_tbl[i]));
2461         }
2462 }
2463
2464 #ifdef CONFIG_IWLWIFI_DEBUGFS
2465 /* create and remove of files */
2466 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2467         if (!debugfs_create_file(#name, mode, parent, trans,            \
2468                                  &iwl_dbgfs_##name##_ops))              \
2469                 goto err;                                               \
2470 } while (0)
2471
2472 /* file operation */
2473 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2474 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2475         .read = iwl_dbgfs_##name##_read,                                \
2476         .open = simple_open,                                            \
2477         .llseek = generic_file_llseek,                                  \
2478 };
2479
2480 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2481 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2482         .write = iwl_dbgfs_##name##_write,                              \
2483         .open = simple_open,                                            \
2484         .llseek = generic_file_llseek,                                  \
2485 };
2486
2487 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2488 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2489         .write = iwl_dbgfs_##name##_write,                              \
2490         .read = iwl_dbgfs_##name##_read,                                \
2491         .open = simple_open,                                            \
2492         .llseek = generic_file_llseek,                                  \
2493 };
2494
2495 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2496                                        char __user *user_buf,
2497                                        size_t count, loff_t *ppos)
2498 {
2499         struct iwl_trans *trans = file->private_data;
2500         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2501         struct iwl_txq *txq;
2502         char *buf;
2503         int pos = 0;
2504         int cnt;
2505         int ret;
2506         size_t bufsz;
2507
2508         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2509
2510         if (!trans_pcie->txq_memory)
2511                 return -EAGAIN;
2512
2513         buf = kzalloc(bufsz, GFP_KERNEL);
2514         if (!buf)
2515                 return -ENOMEM;
2516
2517         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2518                 txq = trans_pcie->txq[cnt];
2519                 pos += scnprintf(buf + pos, bufsz - pos,
2520                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2521                                 cnt, txq->read_ptr, txq->write_ptr,
2522                                 !!test_bit(cnt, trans_pcie->queue_used),
2523                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2524                                  txq->need_update, txq->frozen,
2525                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2526         }
2527         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2528         kfree(buf);
2529         return ret;
2530 }
2531
2532 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2533                                        char __user *user_buf,
2534                                        size_t count, loff_t *ppos)
2535 {
2536         struct iwl_trans *trans = file->private_data;
2537         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2538         char *buf;
2539         int pos = 0, i, ret;
2540         size_t bufsz = sizeof(buf);
2541
2542         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2543
2544         if (!trans_pcie->rxq)
2545                 return -EAGAIN;
2546
2547         buf = kzalloc(bufsz, GFP_KERNEL);
2548         if (!buf)
2549                 return -ENOMEM;
2550
2551         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2552                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2553
2554                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2555                                  i);
2556                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2557                                  rxq->read);
2558                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2559                                  rxq->write);
2560                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2561                                  rxq->write_actual);
2562                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2563                                  rxq->need_update);
2564                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2565                                  rxq->free_count);
2566                 if (rxq->rb_stts) {
2567                         u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2568                                                                      rxq));
2569                         pos += scnprintf(buf + pos, bufsz - pos,
2570                                          "\tclosed_rb_num: %u\n",
2571                                          r & 0x0FFF);
2572                 } else {
2573                         pos += scnprintf(buf + pos, bufsz - pos,
2574                                          "\tclosed_rb_num: Not Allocated\n");
2575                 }
2576         }
2577         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2578         kfree(buf);
2579
2580         return ret;
2581 }
2582
2583 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2584                                         char __user *user_buf,
2585                                         size_t count, loff_t *ppos)
2586 {
2587         struct iwl_trans *trans = file->private_data;
2588         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2589         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2590
2591         int pos = 0;
2592         char *buf;
2593         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2594         ssize_t ret;
2595
2596         buf = kzalloc(bufsz, GFP_KERNEL);
2597         if (!buf)
2598                 return -ENOMEM;
2599
2600         pos += scnprintf(buf + pos, bufsz - pos,
2601                         "Interrupt Statistics Report:\n");
2602
2603         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2604                 isr_stats->hw);
2605         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2606                 isr_stats->sw);
2607         if (isr_stats->sw || isr_stats->hw) {
2608                 pos += scnprintf(buf + pos, bufsz - pos,
2609                         "\tLast Restarting Code:  0x%X\n",
2610                         isr_stats->err_code);
2611         }
2612 #ifdef CONFIG_IWLWIFI_DEBUG
2613         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2614                 isr_stats->sch);
2615         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2616                 isr_stats->alive);
2617 #endif
2618         pos += scnprintf(buf + pos, bufsz - pos,
2619                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2620
2621         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2622                 isr_stats->ctkill);
2623
2624         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2625                 isr_stats->wakeup);
2626
2627         pos += scnprintf(buf + pos, bufsz - pos,
2628                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2629
2630         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2631                 isr_stats->tx);
2632
2633         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2634                 isr_stats->unhandled);
2635
2636         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2637         kfree(buf);
2638         return ret;
2639 }
2640
2641 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2642                                          const char __user *user_buf,
2643                                          size_t count, loff_t *ppos)
2644 {
2645         struct iwl_trans *trans = file->private_data;
2646         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2647         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2648         u32 reset_flag;
2649         int ret;
2650
2651         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2652         if (ret)
2653                 return ret;
2654         if (reset_flag == 0)
2655                 memset(isr_stats, 0, sizeof(*isr_stats));
2656
2657         return count;
2658 }
2659
2660 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2661                                    const char __user *user_buf,
2662                                    size_t count, loff_t *ppos)
2663 {
2664         struct iwl_trans *trans = file->private_data;
2665
2666         iwl_pcie_dump_csr(trans);
2667
2668         return count;
2669 }
2670
2671 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2672                                      char __user *user_buf,
2673                                      size_t count, loff_t *ppos)
2674 {
2675         struct iwl_trans *trans = file->private_data;
2676         char *buf = NULL;
2677         ssize_t ret;
2678
2679         ret = iwl_dump_fh(trans, &buf);
2680         if (ret < 0)
2681                 return ret;
2682         if (!buf)
2683                 return -EINVAL;
2684         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2685         kfree(buf);
2686         return ret;
2687 }
2688
2689 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2690                                      char __user *user_buf,
2691                                      size_t count, loff_t *ppos)
2692 {
2693         struct iwl_trans *trans = file->private_data;
2694         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2695         char buf[100];
2696         int pos;
2697
2698         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2699                         trans_pcie->debug_rfkill,
2700                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2701                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2702
2703         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2704 }
2705
2706 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2707                                       const char __user *user_buf,
2708                                       size_t count, loff_t *ppos)
2709 {
2710         struct iwl_trans *trans = file->private_data;
2711         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2712         bool old = trans_pcie->debug_rfkill;
2713         int ret;
2714
2715         ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2716         if (ret)
2717                 return ret;
2718         if (old == trans_pcie->debug_rfkill)
2719                 return count;
2720         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2721                  old, trans_pcie->debug_rfkill);
2722         iwl_pcie_handle_rfkill_irq(trans);
2723
2724         return count;
2725 }
2726
2727 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2728                                        struct file *file)
2729 {
2730         struct iwl_trans *trans = inode->i_private;
2731         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2732
2733         if (!trans->dbg_dest_tlv ||
2734             trans->dbg_dest_tlv->monitor_mode != EXTERNAL_MODE) {
2735                 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2736                 return -ENOENT;
2737         }
2738
2739         if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2740                 return -EBUSY;
2741
2742         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2743         return simple_open(inode, file);
2744 }
2745
2746 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2747                                           struct file *file)
2748 {
2749         struct iwl_trans_pcie *trans_pcie =
2750                 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2751
2752         if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2753                 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2754         return 0;
2755 }
2756
2757 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2758                                   void *buf, ssize_t *size,
2759                                   ssize_t *bytes_copied)
2760 {
2761         int buf_size_left = count - *bytes_copied;
2762
2763         buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2764         if (*size > buf_size_left)
2765                 *size = buf_size_left;
2766
2767         *size -= copy_to_user(user_buf, buf, *size);
2768         *bytes_copied += *size;
2769
2770         if (buf_size_left == *size)
2771                 return true;
2772         return false;
2773 }
2774
2775 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2776                                            char __user *user_buf,
2777                                            size_t count, loff_t *ppos)
2778 {
2779         struct iwl_trans *trans = file->private_data;
2780         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2781         void *cpu_addr = (void *)trans->fw_mon[0].block, *curr_buf;
2782         struct cont_rec *data = &trans_pcie->fw_mon_data;
2783         u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2784         ssize_t size, bytes_copied = 0;
2785         bool b_full;
2786
2787         if (trans->dbg_dest_tlv) {
2788                 write_ptr_addr =
2789                         le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2790                 wrap_cnt_addr = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2791         } else {
2792                 write_ptr_addr = MON_BUFF_WRPTR;
2793                 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2794         }
2795
2796         if (unlikely(!trans->dbg_rec_on))
2797                 return 0;
2798
2799         mutex_lock(&data->mutex);
2800         if (data->state ==
2801             IWL_FW_MON_DBGFS_STATE_DISABLED) {
2802                 mutex_unlock(&data->mutex);
2803                 return 0;
2804         }
2805
2806         /* write_ptr position in bytes rather then DW */
2807         write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2808         wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2809
2810         if (data->prev_wrap_cnt == wrap_cnt) {
2811                 size = write_ptr - data->prev_wr_ptr;
2812                 curr_buf = cpu_addr + data->prev_wr_ptr;
2813                 b_full = iwl_write_to_user_buf(user_buf, count,
2814                                                curr_buf, &size,
2815                                                &bytes_copied);
2816                 data->prev_wr_ptr += size;
2817
2818         } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2819                    write_ptr < data->prev_wr_ptr) {
2820                 size = trans->fw_mon[0].size - data->prev_wr_ptr;
2821                 curr_buf = cpu_addr + data->prev_wr_ptr;
2822                 b_full = iwl_write_to_user_buf(user_buf, count,
2823                                                curr_buf, &size,
2824                                                &bytes_copied);
2825                 data->prev_wr_ptr += size;
2826
2827                 if (!b_full) {
2828                         size = write_ptr;
2829                         b_full = iwl_write_to_user_buf(user_buf, count,
2830                                                        cpu_addr, &size,
2831                                                        &bytes_copied);
2832                         data->prev_wr_ptr = size;
2833                         data->prev_wrap_cnt++;
2834                 }
2835         } else {
2836                 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2837                     write_ptr > data->prev_wr_ptr)
2838                         IWL_WARN(trans,
2839                                  "write pointer passed previous write pointer, start copying from the beginning\n");
2840                 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2841                                    data->prev_wr_ptr == 0))
2842                         IWL_WARN(trans,
2843                                  "monitor data is out of sync, start copying from the beginning\n");
2844
2845                 size = write_ptr;
2846                 b_full = iwl_write_to_user_buf(user_buf, count,
2847                                                cpu_addr, &size,
2848                                                &bytes_copied);
2849                 data->prev_wr_ptr = size;
2850                 data->prev_wrap_cnt = wrap_cnt;
2851         }
2852
2853         mutex_unlock(&data->mutex);
2854
2855         return bytes_copied;
2856 }
2857
2858 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2859 DEBUGFS_READ_FILE_OPS(fh_reg);
2860 DEBUGFS_READ_FILE_OPS(rx_queue);
2861 DEBUGFS_READ_FILE_OPS(tx_queue);
2862 DEBUGFS_WRITE_FILE_OPS(csr);
2863 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2864
2865 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2866         .read = iwl_dbgfs_monitor_data_read,
2867         .open = iwl_dbgfs_monitor_data_open,
2868         .release = iwl_dbgfs_monitor_data_release,
2869 };
2870
2871 /* Create the debugfs files and directories */
2872 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2873 {
2874         struct dentry *dir = trans->dbgfs_dir;
2875
2876         DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2877         DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2878         DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2879         DEBUGFS_ADD_FILE(csr, dir, 0200);
2880         DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2881         DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2882         DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
2883         return 0;
2884
2885 err:
2886         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2887         return -ENOMEM;
2888 }
2889
2890 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2891 {
2892         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2893         struct cont_rec *data = &trans_pcie->fw_mon_data;
2894
2895         mutex_lock(&data->mutex);
2896         data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2897         mutex_unlock(&data->mutex);
2898 }
2899 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2900
2901 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2902 {
2903         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2904         u32 cmdlen = 0;
2905         int i;
2906
2907         for (i = 0; i < trans_pcie->max_tbs; i++)
2908                 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2909
2910         return cmdlen;
2911 }
2912
2913 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2914                                    struct iwl_fw_error_dump_data **data,
2915                                    int allocated_rb_nums)
2916 {
2917         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2918         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2919         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2920         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2921         u32 i, r, j, rb_len = 0;
2922
2923         spin_lock(&rxq->lock);
2924
2925         r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
2926
2927         for (i = rxq->read, j = 0;
2928              i != r && j < allocated_rb_nums;
2929              i = (i + 1) & RX_QUEUE_MASK, j++) {
2930                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2931                 struct iwl_fw_error_dump_rb *rb;
2932
2933                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2934                                DMA_FROM_DEVICE);
2935
2936                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2937
2938                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2939                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2940                 rb = (void *)(*data)->data;
2941                 rb->index = cpu_to_le32(i);
2942                 memcpy(rb->data, page_address(rxb->page), max_len);
2943                 /* remap the page for the free benefit */
2944                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2945                                                      max_len,
2946                                                      DMA_FROM_DEVICE);
2947
2948                 *data = iwl_fw_error_next_data(*data);
2949         }
2950
2951         spin_unlock(&rxq->lock);
2952
2953         return rb_len;
2954 }
2955 #define IWL_CSR_TO_DUMP (0x250)
2956
2957 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2958                                    struct iwl_fw_error_dump_data **data)
2959 {
2960         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2961         __le32 *val;
2962         int i;
2963
2964         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2965         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2966         val = (void *)(*data)->data;
2967
2968         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2969                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2970
2971         *data = iwl_fw_error_next_data(*data);
2972
2973         return csr_len;
2974 }
2975
2976 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2977                                        struct iwl_fw_error_dump_data **data)
2978 {
2979         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2980         unsigned long flags;
2981         __le32 *val;
2982         int i;
2983
2984         if (!iwl_trans_grab_nic_access(trans, &flags))
2985                 return 0;
2986
2987         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2988         (*data)->len = cpu_to_le32(fh_regs_len);
2989         val = (void *)(*data)->data;
2990
2991         if (!trans->cfg->gen2)
2992                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2993                      i += sizeof(u32))
2994                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2995         else
2996                 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2997                      i += sizeof(u32))
2998                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2999                                                                       i));
3000
3001         iwl_trans_release_nic_access(trans, &flags);
3002
3003         *data = iwl_fw_error_next_data(*data);
3004
3005         return sizeof(**data) + fh_regs_len;
3006 }
3007
3008 static u32
3009 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3010                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3011                                  u32 monitor_len)
3012 {
3013         u32 buf_size_in_dwords = (monitor_len >> 2);
3014         u32 *buffer = (u32 *)fw_mon_data->data;
3015         unsigned long flags;
3016         u32 i;
3017
3018         if (!iwl_trans_grab_nic_access(trans, &flags))
3019                 return 0;
3020
3021         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3022         for (i = 0; i < buf_size_in_dwords; i++)
3023                 buffer[i] = iwl_read_prph_no_grab(trans,
3024                                 MON_DMARB_RD_DATA_ADDR);
3025         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3026
3027         iwl_trans_release_nic_access(trans, &flags);
3028
3029         return monitor_len;
3030 }
3031
3032 static void
3033 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3034                              struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3035 {
3036         u32 base, write_ptr, wrap_cnt;
3037
3038         /* If there was a dest TLV - use the values from there */
3039         if (trans->ini_valid) {
3040                 base = MON_BUFF_BASE_ADDR_VER2;
3041                 write_ptr = MON_BUFF_WRPTR_VER2;
3042                 wrap_cnt = MON_BUFF_CYCLE_CNT_VER2;
3043         } else if (trans->dbg_dest_tlv) {
3044                 write_ptr = le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
3045                 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
3046                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3047         } else {
3048                 base = MON_BUFF_BASE_ADDR;
3049                 write_ptr = MON_BUFF_WRPTR;
3050                 wrap_cnt = MON_BUFF_CYCLE_CNT;
3051         }
3052         fw_mon_data->fw_mon_wr_ptr =
3053                 cpu_to_le32(iwl_read_prph(trans, write_ptr));
3054         fw_mon_data->fw_mon_cycle_cnt =
3055                 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3056         fw_mon_data->fw_mon_base_ptr =
3057                 cpu_to_le32(iwl_read_prph(trans, base));
3058 }
3059
3060 static u32
3061 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3062                             struct iwl_fw_error_dump_data **data,
3063                             u32 monitor_len)
3064 {
3065         u32 len = 0;
3066
3067         if ((trans->num_blocks &&
3068              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
3069              (trans->dbg_dest_tlv && !trans->ini_valid) ||
3070              (trans->ini_valid && trans->num_blocks)) {
3071                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3072
3073                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3074                 fw_mon_data = (void *)(*data)->data;
3075
3076                 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3077
3078                 len += sizeof(**data) + sizeof(*fw_mon_data);
3079                 if (trans->num_blocks) {
3080                         memcpy(fw_mon_data->data,
3081                                trans->fw_mon[0].block,
3082                                trans->fw_mon[0].size);
3083
3084                         monitor_len = trans->fw_mon[0].size;
3085                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
3086                         u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3087                         /*
3088                          * Update pointers to reflect actual values after
3089                          * shifting
3090                          */
3091                         if (trans->dbg_dest_tlv->version) {
3092                                 base = (iwl_read_prph(trans, base) &
3093                                         IWL_LDBG_M2S_BUF_BA_MSK) <<
3094                                        trans->dbg_dest_tlv->base_shift;
3095                                 base *= IWL_M2S_UNIT_SIZE;
3096                                 base += trans->cfg->smem_offset;
3097                         } else {
3098                                 base = iwl_read_prph(trans, base) <<
3099                                        trans->dbg_dest_tlv->base_shift;
3100                         }
3101
3102                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
3103                                            monitor_len / sizeof(u32));
3104                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
3105                         monitor_len =
3106                                 iwl_trans_pci_dump_marbh_monitor(trans,
3107                                                                  fw_mon_data,
3108                                                                  monitor_len);
3109                 } else {
3110                         /* Didn't match anything - output no monitor data */
3111                         monitor_len = 0;
3112                 }
3113
3114                 len += monitor_len;
3115                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3116         }
3117
3118         return len;
3119 }
3120
3121 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, int *len)
3122 {
3123         if (trans->num_blocks) {
3124                 *len += sizeof(struct iwl_fw_error_dump_data) +
3125                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3126                         trans->fw_mon[0].size;
3127                 return trans->fw_mon[0].size;
3128         } else if (trans->dbg_dest_tlv) {
3129                 u32 base, end, cfg_reg, monitor_len;
3130
3131                 if (trans->dbg_dest_tlv->version == 1) {
3132                         cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3133                         cfg_reg = iwl_read_prph(trans, cfg_reg);
3134                         base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3135                                 trans->dbg_dest_tlv->base_shift;
3136                         base *= IWL_M2S_UNIT_SIZE;
3137                         base += trans->cfg->smem_offset;
3138
3139                         monitor_len =
3140                                 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3141                                 trans->dbg_dest_tlv->end_shift;
3142                         monitor_len *= IWL_M2S_UNIT_SIZE;
3143                 } else {
3144                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3145                         end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
3146
3147                         base = iwl_read_prph(trans, base) <<
3148                                trans->dbg_dest_tlv->base_shift;
3149                         end = iwl_read_prph(trans, end) <<
3150                               trans->dbg_dest_tlv->end_shift;
3151
3152                         /* Make "end" point to the actual end */
3153                         if (trans->cfg->device_family >=
3154                             IWL_DEVICE_FAMILY_8000 ||
3155                             trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
3156                                 end += (1 << trans->dbg_dest_tlv->end_shift);
3157                         monitor_len = end - base;
3158                 }
3159                 *len += sizeof(struct iwl_fw_error_dump_data) +
3160                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3161                         monitor_len;
3162                 return monitor_len;
3163         }
3164         return 0;
3165 }
3166
3167 static struct iwl_trans_dump_data
3168 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3169                           u32 dump_mask)
3170 {
3171         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3172         struct iwl_fw_error_dump_data *data;
3173         struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
3174         struct iwl_fw_error_dump_txcmd *txcmd;
3175         struct iwl_trans_dump_data *dump_data;
3176         u32 len, num_rbs = 0;
3177         u32 monitor_len;
3178         int i, ptr;
3179         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3180                         !trans->cfg->mq_rx_supported &&
3181                         dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3182
3183         if (!dump_mask)
3184                 return NULL;
3185
3186         /* transport dump header */
3187         len = sizeof(*dump_data);
3188
3189         /* host commands */
3190         len += sizeof(*data) +
3191                 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
3192
3193         /* FW monitor */
3194         monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3195
3196         if (dump_mask == BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) {
3197                 dump_data = vzalloc(len);
3198                 if (!dump_data)
3199                         return NULL;
3200
3201                 data = (void *)dump_data->data;
3202                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3203                 dump_data->len = len;
3204
3205                 return dump_data;
3206         }
3207
3208         /* CSR registers */
3209         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3210                 len += sizeof(*data) + IWL_CSR_TO_DUMP;
3211
3212         /* FH registers */
3213         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3214                 if (trans->cfg->gen2)
3215                         len += sizeof(*data) +
3216                                (FH_MEM_UPPER_BOUND_GEN2 -
3217                                 FH_MEM_LOWER_BOUND_GEN2);
3218                 else
3219                         len += sizeof(*data) +
3220                                (FH_MEM_UPPER_BOUND -
3221                                 FH_MEM_LOWER_BOUND);
3222         }
3223
3224         if (dump_rbs) {
3225                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3226                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3227                 /* RBs */
3228                 num_rbs =
3229                         le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3230                         & 0x0FFF;
3231                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3232                 len += num_rbs * (sizeof(*data) +
3233                                   sizeof(struct iwl_fw_error_dump_rb) +
3234                                   (PAGE_SIZE << trans_pcie->rx_page_order));
3235         }
3236
3237         /* Paged memory for gen2 HW */
3238         if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3239                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
3240                         len += sizeof(*data) +
3241                                sizeof(struct iwl_fw_error_dump_paging) +
3242                                trans_pcie->init_dram.paging[i].size;
3243
3244         dump_data = vzalloc(len);
3245         if (!dump_data)
3246                 return NULL;
3247
3248         len = 0;
3249         data = (void *)dump_data->data;
3250
3251         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) {
3252                 u16 tfd_size = trans_pcie->tfd_size;
3253
3254                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3255                 txcmd = (void *)data->data;
3256                 spin_lock_bh(&cmdq->lock);
3257                 ptr = cmdq->write_ptr;
3258                 for (i = 0; i < cmdq->n_window; i++) {
3259                         u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
3260                         u32 caplen, cmdlen;
3261
3262                         cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3263                                                            cmdq->tfds +
3264                                                            tfd_size * ptr);
3265                         caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3266
3267                         if (cmdlen) {
3268                                 len += sizeof(*txcmd) + caplen;
3269                                 txcmd->cmdlen = cpu_to_le32(cmdlen);
3270                                 txcmd->caplen = cpu_to_le32(caplen);
3271                                 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3272                                        caplen);
3273                                 txcmd = (void *)((u8 *)txcmd->data + caplen);
3274                         }
3275
3276                         ptr = iwl_queue_dec_wrap(trans, ptr);
3277                 }
3278                 spin_unlock_bh(&cmdq->lock);
3279
3280                 data->len = cpu_to_le32(len);
3281                 len += sizeof(*data);
3282                 data = iwl_fw_error_next_data(data);
3283         }
3284
3285         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3286                 len += iwl_trans_pcie_dump_csr(trans, &data);
3287         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3288                 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3289         if (dump_rbs)
3290                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3291
3292         /* Paged memory for gen2 HW */
3293         if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3294                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
3295                         struct iwl_fw_error_dump_paging *paging;
3296                         dma_addr_t addr =
3297                                 trans_pcie->init_dram.paging[i].physical;
3298                         u32 page_len = trans_pcie->init_dram.paging[i].size;
3299
3300                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3301                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
3302                         paging = (void *)data->data;
3303                         paging->index = cpu_to_le32(i);
3304                         dma_sync_single_for_cpu(trans->dev, addr, page_len,
3305                                                 DMA_BIDIRECTIONAL);
3306                         memcpy(paging->data,
3307                                trans_pcie->init_dram.paging[i].block, page_len);
3308                         data = iwl_fw_error_next_data(data);
3309
3310                         len += sizeof(*data) + sizeof(*paging) + page_len;
3311                 }
3312         }
3313         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3314                 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3315
3316         dump_data->len = len;
3317
3318         return dump_data;
3319 }
3320
3321 #ifdef CONFIG_PM_SLEEP
3322 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3323 {
3324         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3325             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3326                 return iwl_pci_fw_enter_d0i3(trans);
3327
3328         return 0;
3329 }
3330
3331 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3332 {
3333         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3334             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3335                 iwl_pci_fw_exit_d0i3(trans);
3336 }
3337 #endif /* CONFIG_PM_SLEEP */
3338
3339 #define IWL_TRANS_COMMON_OPS                                            \
3340         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3341         .write8 = iwl_trans_pcie_write8,                                \
3342         .write32 = iwl_trans_pcie_write32,                              \
3343         .read32 = iwl_trans_pcie_read32,                                \
3344         .read_prph = iwl_trans_pcie_read_prph,                          \
3345         .write_prph = iwl_trans_pcie_write_prph,                        \
3346         .read_mem = iwl_trans_pcie_read_mem,                            \
3347         .write_mem = iwl_trans_pcie_write_mem,                          \
3348         .configure = iwl_trans_pcie_configure,                          \
3349         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3350         .sw_reset = iwl_trans_pcie_sw_reset,                            \
3351         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3352         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3353         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3354         .ref = iwl_trans_pcie_ref,                                      \
3355         .unref = iwl_trans_pcie_unref,                                  \
3356         .dump_data = iwl_trans_pcie_dump_data,                          \
3357         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3358         .d3_resume = iwl_trans_pcie_d3_resume
3359
3360 #ifdef CONFIG_PM_SLEEP
3361 #define IWL_TRANS_PM_OPS                                                \
3362         .suspend = iwl_trans_pcie_suspend,                              \
3363         .resume = iwl_trans_pcie_resume,
3364 #else
3365 #define IWL_TRANS_PM_OPS
3366 #endif /* CONFIG_PM_SLEEP */
3367
3368 static const struct iwl_trans_ops trans_ops_pcie = {
3369         IWL_TRANS_COMMON_OPS,
3370         IWL_TRANS_PM_OPS
3371         .start_hw = iwl_trans_pcie_start_hw,
3372         .fw_alive = iwl_trans_pcie_fw_alive,
3373         .start_fw = iwl_trans_pcie_start_fw,
3374         .stop_device = iwl_trans_pcie_stop_device,
3375
3376         .send_cmd = iwl_trans_pcie_send_hcmd,
3377
3378         .tx = iwl_trans_pcie_tx,
3379         .reclaim = iwl_trans_pcie_reclaim,
3380
3381         .txq_disable = iwl_trans_pcie_txq_disable,
3382         .txq_enable = iwl_trans_pcie_txq_enable,
3383
3384         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3385
3386         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3387
3388         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3389         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3390 #ifdef CONFIG_IWLWIFI_DEBUGFS
3391         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3392 #endif
3393 };
3394
3395 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3396         IWL_TRANS_COMMON_OPS,
3397         IWL_TRANS_PM_OPS
3398         .start_hw = iwl_trans_pcie_start_hw,
3399         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3400         .start_fw = iwl_trans_pcie_gen2_start_fw,
3401         .stop_device = iwl_trans_pcie_gen2_stop_device,
3402
3403         .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3404
3405         .tx = iwl_trans_pcie_gen2_tx,
3406         .reclaim = iwl_trans_pcie_reclaim,
3407
3408         .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3409         .txq_free = iwl_trans_pcie_dyn_txq_free,
3410         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3411         .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3412 #ifdef CONFIG_IWLWIFI_DEBUGFS
3413         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3414 #endif
3415 };
3416
3417 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3418                                        const struct pci_device_id *ent,
3419                                        const struct iwl_cfg *cfg)
3420 {
3421         struct iwl_trans_pcie *trans_pcie;
3422         struct iwl_trans *trans;
3423         int ret, addr_size;
3424
3425         ret = pcim_enable_device(pdev);
3426         if (ret)
3427                 return ERR_PTR(ret);
3428
3429         if (cfg->gen2)
3430                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3431                                         &pdev->dev, cfg, &trans_ops_pcie_gen2);
3432         else
3433                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3434                                         &pdev->dev, cfg, &trans_ops_pcie);
3435         if (!trans)
3436                 return ERR_PTR(-ENOMEM);
3437
3438         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3439
3440         trans_pcie->trans = trans;
3441         trans_pcie->opmode_down = true;
3442         spin_lock_init(&trans_pcie->irq_lock);
3443         spin_lock_init(&trans_pcie->reg_lock);
3444         mutex_init(&trans_pcie->mutex);
3445         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3446         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3447         if (!trans_pcie->tso_hdr_page) {
3448                 ret = -ENOMEM;
3449                 goto out_no_pci;
3450         }
3451
3452
3453         if (!cfg->base_params->pcie_l1_allowed) {
3454                 /*
3455                  * W/A - seems to solve weird behavior. We need to remove this
3456                  * if we don't want to stay in L1 all the time. This wastes a
3457                  * lot of power.
3458                  */
3459                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3460                                        PCIE_LINK_STATE_L1 |
3461                                        PCIE_LINK_STATE_CLKPM);
3462         }
3463
3464         trans_pcie->def_rx_queue = 0;
3465
3466         if (cfg->use_tfh) {
3467                 addr_size = 64;
3468                 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3469                 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3470         } else {
3471                 addr_size = 36;
3472                 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3473                 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3474         }
3475         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3476
3477         pci_set_master(pdev);
3478
3479         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3480         if (!ret)
3481                 ret = pci_set_consistent_dma_mask(pdev,
3482                                                   DMA_BIT_MASK(addr_size));
3483         if (ret) {
3484                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3485                 if (!ret)
3486                         ret = pci_set_consistent_dma_mask(pdev,
3487                                                           DMA_BIT_MASK(32));
3488                 /* both attempts failed: */
3489                 if (ret) {
3490                         dev_err(&pdev->dev, "No suitable DMA available\n");
3491                         goto out_no_pci;
3492                 }
3493         }
3494
3495         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3496         if (ret) {
3497                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3498                 goto out_no_pci;
3499         }
3500
3501         trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3502         if (!trans_pcie->hw_base) {
3503                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3504                 ret = -ENODEV;
3505                 goto out_no_pci;
3506         }
3507
3508         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3509          * PCI Tx retries from interfering with C3 CPU state */
3510         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3511
3512         trans_pcie->pci_dev = pdev;
3513         iwl_disable_interrupts(trans);
3514
3515         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3516         if (trans->hw_rev == 0xffffffff) {
3517                 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3518                 ret = -EIO;
3519                 goto out_no_pci;
3520         }
3521
3522         /*
3523          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3524          * changed, and now the revision step also includes bit 0-1 (no more
3525          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3526          * in the old format.
3527          */
3528         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
3529                 unsigned long flags;
3530
3531                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3532                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3533
3534                 ret = iwl_pcie_prepare_card_hw(trans);
3535                 if (ret) {
3536                         IWL_WARN(trans, "Exit HW not ready\n");
3537                         goto out_no_pci;
3538                 }
3539
3540                 /*
3541                  * in-order to recognize C step driver should read chip version
3542                  * id located at the AUX bus MISC address space.
3543                  */
3544                 iwl_set_bit(trans, CSR_GP_CNTRL,
3545                             BIT(trans->cfg->csr->flag_init_done));
3546                 udelay(2);
3547
3548                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3549                                    BIT(trans->cfg->csr->flag_mac_clock_ready),
3550                                    BIT(trans->cfg->csr->flag_mac_clock_ready),
3551                                    25000);
3552                 if (ret < 0) {
3553                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3554                         goto out_no_pci;
3555                 }
3556
3557                 if (iwl_trans_grab_nic_access(trans, &flags)) {
3558                         u32 hw_step;
3559
3560                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3561                         hw_step |= ENABLE_WFPM;
3562                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3563                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3564                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3565                         if (hw_step == 0x3)
3566                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3567                                                 (SILICON_C_STEP << 2);
3568                         iwl_trans_release_nic_access(trans, &flags);
3569                 }
3570         }
3571
3572         /*
3573          * 9000-series integrated A-step has a problem with suspend/resume
3574          * and sometimes even causes the whole platform to get stuck. This
3575          * workaround makes the hardware not go into the problematic state.
3576          */
3577         if (trans->cfg->integrated &&
3578             trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3579             CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3580                 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3581                             CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3582
3583 #if IS_ENABLED(CONFIG_IWLMVM)
3584         trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3585
3586         if (cfg == &iwl22000_2ax_cfg_hr) {
3587                 if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3588                     CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
3589                         trans->cfg = &iwl22000_2ax_cfg_hr;
3590                 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3591                            CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) {
3592                         trans->cfg = &iwl22000_2ax_cfg_jf;
3593                 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3594                            CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) {
3595                         IWL_ERR(trans, "RF ID HRCDB is not supported\n");
3596                         ret = -EINVAL;
3597                         goto out_no_pci;
3598                 } else {
3599                         IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n",
3600                                 CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id));
3601                         ret = -EINVAL;
3602                         goto out_no_pci;
3603                 }
3604         } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3605                    CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
3606                 u32 hw_status;
3607
3608                 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3609                 if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP)
3610                         /*
3611                         * b step fw is the same for physical card and fpga
3612                         */
3613                         trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0;
3614                 else if ((hw_status & UMAG_GEN_HW_IS_FPGA) &&
3615                          CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) {
3616                         trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0;
3617                 } else {
3618                         /*
3619                         * a step no FPGA
3620                         */
3621                         trans->cfg = &iwl22000_2ac_cfg_hr;
3622                 }
3623         }
3624 #endif
3625
3626         iwl_pcie_set_interrupt_capa(pdev, trans);
3627         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3628         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3629                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3630
3631         /* Initialize the wait queue for commands */
3632         init_waitqueue_head(&trans_pcie->wait_command_queue);
3633
3634         init_waitqueue_head(&trans_pcie->d0i3_waitq);
3635
3636         if (trans_pcie->msix_enabled) {
3637                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3638                 if (ret)
3639                         goto out_no_pci;
3640          } else {
3641                 ret = iwl_pcie_alloc_ict(trans);
3642                 if (ret)
3643                         goto out_no_pci;
3644
3645                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3646                                                 iwl_pcie_isr,
3647                                                 iwl_pcie_irq_handler,
3648                                                 IRQF_SHARED, DRV_NAME, trans);
3649                 if (ret) {
3650                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3651                         goto out_free_ict;
3652                 }
3653                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3654          }
3655
3656         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3657                                                    WQ_HIGHPRI | WQ_UNBOUND, 1);
3658         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3659
3660 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3661         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3662 #else
3663         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3664 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3665
3666 #ifdef CONFIG_IWLWIFI_DEBUGFS
3667         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3668         mutex_init(&trans_pcie->fw_mon_data.mutex);
3669 #endif
3670
3671         return trans;
3672
3673 out_free_ict:
3674         iwl_pcie_free_ict(trans);
3675 out_no_pci:
3676         free_percpu(trans_pcie->tso_hdr_page);
3677         iwl_trans_free(trans);
3678         return ERR_PTR(ret);
3679 }