drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
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   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
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  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 - 2019 Intel Corporation
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  32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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  52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  61  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62  *
  63  *****************************************************************************/
  64 #include <linux/pci.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70 #include <linux/vmalloc.h>
  71 #include <linux/module.h>
  72 #include <linux/wait.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-scd.h"
  79 #include "iwl-agn-hw.h"
  80 #include "fw/error-dump.h"
  81 #include "fw/dbg.h"
  82 #include "internal.h"
  83 #include "iwl-fh.h"
  84
  85 /* extended range in FW SRAM */
  86 #define IWL_FW_MEM_EXTENDED_START       0x40000
  87 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  88
  89 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
  90 {
  91 #define PCI_DUMP_SIZE           352
  92 #define PCI_MEM_DUMP_SIZE       64
  93 #define PCI_PARENT_DUMP_SIZE    524
  94 #define PREFIX_LEN              32
  95         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  96         struct pci_dev *pdev = trans_pcie->pci_dev;
  97         u32 i, pos, alloc_size, *ptr, *buf;
  98         char *prefix;
  99
 100         if (trans_pcie->pcie_dbg_dumped_once)
 101                 return;
 102
 103         /* Should be a multiple of 4 */
 104         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
 105         BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
 106         BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
 107
 108         /* Alloc a max size buffer */
 109         alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
 110         alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
 111         alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
 112         alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
 113
 114         buf = kmalloc(alloc_size, GFP_ATOMIC);
 115         if (!buf)
 116                 return;
 117         prefix = (char *)buf + alloc_size - PREFIX_LEN;
 118
 119         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
 120
 121         /* Print wifi device registers */
 122         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 123         IWL_ERR(trans, "iwlwifi device config registers:\n");
 124         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 125                 if (pci_read_config_dword(pdev, i, ptr))
 126                         goto err_read;
 127         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 128
 129         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
 130         for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
 131                 *ptr = iwl_read32(trans, i);
 132         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 133
 134         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 135         if (pos) {
 136                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
 137                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
 138                         if (pci_read_config_dword(pdev, pos + i, ptr))
 139                                 goto err_read;
 140                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
 141                                32, 4, buf, i, 0);
 142         }
 143
 144         /* Print parent device registers next */
 145         if (!pdev->bus->self)
 146                 goto out;
 147
 148         pdev = pdev->bus->self;
 149         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 150
 151         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
 152                 pci_name(pdev));
 153         for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
 154                 if (pci_read_config_dword(pdev, i, ptr))
 155                         goto err_read;
 156         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 157
 158         /* Print root port AER registers */
 159         pos = 0;
 160         pdev = pcie_find_root_port(pdev);
 161         if (pdev)
 162                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 163         if (pos) {
 164                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
 165                         pci_name(pdev));
 166                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 167                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
 168                         if (pci_read_config_dword(pdev, pos + i, ptr))
 169                                 goto err_read;
 170                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
 171                                4, buf, i, 0);
 172         }
 173         goto out;
 174
 175 err_read:
 176         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 177         IWL_ERR(trans, "Read failed at 0x%X\n", i);
 178 out:
 179         trans_pcie->pcie_dbg_dumped_once = 1;
 180         kfree(buf);
 181 }
 182
 183 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
 184 {
 185         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 186         iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
 187                     BIT(trans->trans_cfg->csr->flag_sw_reset));
 188         usleep_range(5000, 6000);
 189 }
 190
 191 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
 192 {
 193         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 194
 195         if (!fw_mon->size)
 196                 return;
 197
 198         dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
 199                           fw_mon->physical);
 200
 201         fw_mon->block = NULL;
 202         fw_mon->physical = 0;
 203         fw_mon->size = 0;
 204 }
 205
 206 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
 207                                             u8 max_power, u8 min_power)
 208 {
 209         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 210         void *block = NULL;
 211         dma_addr_t physical = 0;
 212         u32 size = 0;
 213         u8 power;
 214
 215         if (fw_mon->size)
 216                 return;
 217
 218         for (power = max_power; power >= min_power; power--) {
 219                 size = BIT(power);
 220                 block = dma_alloc_coherent(trans->dev, size, &physical,
 221                                            GFP_KERNEL | __GFP_NOWARN);
 222                 if (!block)
 223                         continue;
 224
 225                 IWL_INFO(trans,
 226                          "Allocated 0x%08x bytes for firmware monitor.\n",
 227                          size);
 228                 break;
 229         }
 230
 231         if (WARN_ON_ONCE(!block))
 232                 return;
 233
 234         if (power != max_power)
 235                 IWL_ERR(trans,
 236                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 237                         (unsigned long)BIT(power - 10),
 238                         (unsigned long)BIT(max_power - 10));
 239
 240         fw_mon->block = block;
 241         fw_mon->physical = physical;
 242         fw_mon->size = size;
 243 }
 244
 245 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 246 {
 247         if (!max_power) {
 248                 /* default max_power is maximum */
 249                 max_power = 26;
 250         } else {
 251                 max_power += 11;
 252         }
 253
 254         if (WARN(max_power > 26,
 255                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 256                  max_power))
 257                 return;
 258
 259         if (trans->dbg.fw_mon.size)
 260                 return;
 261
 262         iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
 263 }
 264
 265 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 266 {
 267         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 268                     ((reg & 0x0000ffff) | (2 << 28)));
 269         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 270 }
 271
 272 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 273 {
 274         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 275         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 276                     ((reg & 0x0000ffff) | (3 << 28)));
 277 }
 278
 279 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 280 {
 281         if (trans->cfg->apmg_not_supported)
 282                 return;
 283
 284         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 285                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 286                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 287                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 288         else
 289                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 290                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 291                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 292 }
 293
 294 /* PCI registers */
 295 #define PCI_CFG_RETRY_TIMEOUT   0x041
 296
 297 void iwl_pcie_apm_config(struct iwl_trans *trans)
 298 {
 299         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 300         u16 lctl;
 301         u16 cap;
 302
 303         /*
 304          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 305          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 306          * If so (likely), disable L0S, so device moves directly L0->L1;
 307          *    costs negligible amount of power savings.
 308          * If not (unlikely), enable L0S, so there is at least some
 309          *    power savings, even without L1.
 310          */
 311         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 312         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 313                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 314         else
 315                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 316         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 317
 318         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 319         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 320         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 321                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 322                         trans->ltr_enabled ? "En" : "Dis");
 323 }
 324
 325 /*
 326  * Start up NIC's basic functionality after it has been reset
 327  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 328  * NOTE:  This does not load uCode nor start the embedded processor
 329  */
 330 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 331 {
 332         int ret;
 333
 334         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 335
 336         /*
 337          * Use "set_bit" below rather than "write", to preserve any hardware
 338          * bits already set by default after reset.
 339          */
 340
 341         /* Disable L0S exit timer (platform NMI Work/Around) */
 342         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
 343                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 344                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 345
 346         /*
 347          * Disable L0s without affecting L1;
 348          *  don't wait for ICH L0s (ICH bug W/A)
 349          */
 350         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 351                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 352
 353         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 354         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 355
 356         /*
 357          * Enable HAP INTA (interrupt from management bus) to
 358          * wake device's PCI Express link L1a -> L0s
 359          */
 360         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 361                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 362
 363         iwl_pcie_apm_config(trans);
 364
 365         /* Configure analog phase-lock-loop before activating to D0A */
 366         if (trans->trans_cfg->base_params->pll_cfg)
 367                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 368
 369         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
 370         if (ret)
 371                 return ret;
 372
 373         if (trans->cfg->host_interrupt_operation_mode) {
 374                 /*
 375                  * This is a bit of an abuse - This is needed for 7260 / 3160
 376                  * only check host_interrupt_operation_mode even if this is
 377                  * not related to host_interrupt_operation_mode.
 378                  *
 379                  * Enable the oscillator to count wake up time for L1 exit. This
 380                  * consumes slightly more power (100uA) - but allows to be sure
 381                  * that we wake up from L1 on time.
 382                  *
 383                  * This looks weird: read twice the same register, discard the
 384                  * value, set a bit, and yet again, read that same register
 385                  * just to discard the value. But that's the way the hardware
 386                  * seems to like it.
 387                  */
 388                 iwl_read_prph(trans, OSC_CLK);
 389                 iwl_read_prph(trans, OSC_CLK);
 390                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 391                 iwl_read_prph(trans, OSC_CLK);
 392                 iwl_read_prph(trans, OSC_CLK);
 393         }
 394
 395         /*
 396          * Enable DMA clock and wait for it to stabilize.
 397          *
 398          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 399          * bits do not disable clocks.  This preserves any hardware
 400          * bits already set by default in "CLK_CTRL_REG" after reset.
 401          */
 402         if (!trans->cfg->apmg_not_supported) {
 403                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 404                                APMG_CLK_VAL_DMA_CLK_RQT);
 405                 udelay(20);
 406
 407                 /* Disable L1-Active */
 408                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 409                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 410
 411                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 412                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 413                                APMG_RTC_INT_STT_RFKILL);
 414         }
 415
 416         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 417
 418         return 0;
 419 }
 420
 421 /*
 422  * Enable LP XTAL to avoid HW bug where device may consume much power if
 423  * FW is not loaded after device reset. LP XTAL is disabled by default
 424  * after device HW reset. Do it only if XTAL is fed by internal source.
 425  * Configure device's "persistence" mode to avoid resetting XTAL again when
 426  * SHRD_HW_RST occurs in S3.
 427  */
 428 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 429 {
 430         int ret;
 431         u32 apmg_gp1_reg;
 432         u32 apmg_xtal_cfg_reg;
 433         u32 dl_cfg_reg;
 434
 435         /* Force XTAL ON */
 436         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 437                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 438
 439         iwl_trans_pcie_sw_reset(trans);
 440
 441         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
 442         if (WARN_ON(ret)) {
 443                 /* Release XTAL ON request */
 444                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 445                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 446                 return;
 447         }
 448
 449         /*
 450          * Clear "disable persistence" to avoid LP XTAL resetting when
 451          * SHRD_HW_RST is applied in S3.
 452          */
 453         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 454                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 455
 456         /*
 457          * Force APMG XTAL to be active to prevent its disabling by HW
 458          * caused by APMG idle state.
 459          */
 460         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 461                                                     SHR_APMG_XTAL_CFG_REG);
 462         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 463                                  apmg_xtal_cfg_reg |
 464                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 465
 466         iwl_trans_pcie_sw_reset(trans);
 467
 468         /* Enable LP XTAL by indirect access through CSR */
 469         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 470         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 471                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 472                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 473
 474         /* Clear delay line clock power up */
 475         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 476         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 477                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 478
 479         /*
 480          * Enable persistence mode to avoid LP XTAL resetting when
 481          * SHRD_HW_RST is applied in S3.
 482          */
 483         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 484                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 485
 486         /*
 487          * Clear "initialization complete" bit to move adapter from
 488          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 489          */
 490         iwl_clear_bit(trans, CSR_GP_CNTRL,
 491                       BIT(trans->trans_cfg->csr->flag_init_done));
 492
 493         /* Activates XTAL resources monitor */
 494         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 495                                  CSR_MONITOR_XTAL_RESOURCES);
 496
 497         /* Release XTAL ON request */
 498         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 499                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 500         udelay(10);
 501
 502         /* Release APMG XTAL */
 503         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 504                                  apmg_xtal_cfg_reg &
 505                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 506 }
 507
 508 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 509 {
 510         int ret;
 511
 512         /* stop device's busmaster DMA activity */
 513         iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
 514                     BIT(trans->trans_cfg->csr->flag_stop_master));
 515
 516         ret = iwl_poll_bit(trans, trans->trans_cfg->csr->addr_sw_reset,
 517                            BIT(trans->trans_cfg->csr->flag_master_dis),
 518                            BIT(trans->trans_cfg->csr->flag_master_dis), 100);
 519         if (ret < 0)
 520                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 521
 522         IWL_DEBUG_INFO(trans, "stop master\n");
 523 }
 524
 525 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 526 {
 527         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 528
 529         if (op_mode_leave) {
 530                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 531                         iwl_pcie_apm_init(trans);
 532
 533                 /* inform ME that we are leaving */
 534                 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
 535                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 536                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 537                 else if (trans->trans_cfg->device_family >=
 538                          IWL_DEVICE_FAMILY_8000) {
 539                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 540                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 541                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 542                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 543                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 544                         mdelay(1);
 545                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 546                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 547                 }
 548                 mdelay(5);
 549         }
 550
 551         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 552
 553         /* Stop device's DMA activity */
 554         iwl_pcie_apm_stop_master(trans);
 555
 556         if (trans->cfg->lp_xtal_workaround) {
 557                 iwl_pcie_apm_lp_xtal_enable(trans);
 558                 return;
 559         }
 560
 561         iwl_trans_pcie_sw_reset(trans);
 562
 563         /*
 564          * Clear "initialization complete" bit to move adapter from
 565          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 566          */
 567         iwl_clear_bit(trans, CSR_GP_CNTRL,
 568                       BIT(trans->trans_cfg->csr->flag_init_done));
 569 }
 570
 571 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 572 {
 573         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 574         int ret;
 575
 576         /* nic_init */
 577         spin_lock(&trans_pcie->irq_lock);
 578         ret = iwl_pcie_apm_init(trans);
 579         spin_unlock(&trans_pcie->irq_lock);
 580
 581         if (ret)
 582                 return ret;
 583
 584         iwl_pcie_set_pwr(trans, false);
 585
 586         iwl_op_mode_nic_config(trans->op_mode);
 587
 588         /* Allocate the RX queue, or reset if it is already allocated */
 589         iwl_pcie_rx_init(trans);
 590
 591         /* Allocate or reset and init all Tx and Command queues */
 592         if (iwl_pcie_tx_init(trans))
 593                 return -ENOMEM;
 594
 595         if (trans->trans_cfg->base_params->shadow_reg_enable) {
 596                 /* enable shadow regs in HW */
 597                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 598                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 599         }
 600
 601         return 0;
 602 }
 603
 604 #define HW_READY_TIMEOUT (50)
 605
 606 /* Note: returns poll_bit return value, which is >= 0 if success */
 607 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 608 {
 609         int ret;
 610
 611         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 612                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 613
 614         /* See if we got it */
 615         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 616                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 617                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 618                            HW_READY_TIMEOUT);
 619
 620         if (ret >= 0)
 621                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 622
 623         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 624         return ret;
 625 }
 626
 627 /* Note: returns standard 0/-ERROR code */
 628 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 629 {
 630         int ret;
 631         int t = 0;
 632         int iter;
 633
 634         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 635
 636         ret = iwl_pcie_set_hw_ready(trans);
 637         /* If the card is ready, exit 0 */
 638         if (ret >= 0)
 639                 return 0;
 640
 641         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 642                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 643         usleep_range(1000, 2000);
 644
 645         for (iter = 0; iter < 10; iter++) {
 646                 /* If HW is not ready, prepare the conditions to check again */
 647                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 648                             CSR_HW_IF_CONFIG_REG_PREPARE);
 649
 650                 do {
 651                         ret = iwl_pcie_set_hw_ready(trans);
 652                         if (ret >= 0)
 653                                 return 0;
 654
 655                         usleep_range(200, 1000);
 656                         t += 200;
 657                 } while (t < 150000);
 658                 msleep(25);
 659         }
 660
 661         IWL_ERR(trans, "Couldn't prepare the card\n");
 662
 663         return ret;
 664 }
 665
 666 /*
 667  * ucode
 668  */
 669 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 670                                             u32 dst_addr, dma_addr_t phy_addr,
 671                                             u32 byte_cnt)
 672 {
 673         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 674                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 675
 676         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 677                     dst_addr);
 678
 679         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 680                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 681
 682         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 683                     (iwl_get_dma_hi_addr(phy_addr)
 684                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 685
 686         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 687                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 688                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 689                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 690
 691         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 692                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 693                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 694                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 695 }
 696
 697 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 698                                         u32 dst_addr, dma_addr_t phy_addr,
 699                                         u32 byte_cnt)
 700 {
 701         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 702         unsigned long flags;
 703         int ret;
 704
 705         trans_pcie->ucode_write_complete = false;
 706
 707         if (!iwl_trans_grab_nic_access(trans, &flags))
 708                 return -EIO;
 709
 710         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 711                                         byte_cnt);
 712         iwl_trans_release_nic_access(trans, &flags);
 713
 714         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 715                                  trans_pcie->ucode_write_complete, 5 * HZ);
 716         if (!ret) {
 717                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 718                 iwl_trans_pcie_dump_regs(trans);
 719                 return -ETIMEDOUT;
 720         }
 721
 722         return 0;
 723 }
 724
 725 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 726                             const struct fw_desc *section)
 727 {
 728         u8 *v_addr;
 729         dma_addr_t p_addr;
 730         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 731         int ret = 0;
 732
 733         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 734                      section_num);
 735
 736         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 737                                     GFP_KERNEL | __GFP_NOWARN);
 738         if (!v_addr) {
 739                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 740                 chunk_sz = PAGE_SIZE;
 741                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 742                                             &p_addr, GFP_KERNEL);
 743                 if (!v_addr)
 744                         return -ENOMEM;
 745         }
 746
 747         for (offset = 0; offset < section->len; offset += chunk_sz) {
 748                 u32 copy_size, dst_addr;
 749                 bool extended_addr = false;
 750
 751                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 752                 dst_addr = section->offset + offset;
 753
 754                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 755                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 756                         extended_addr = true;
 757
 758                 if (extended_addr)
 759                         iwl_set_bits_prph(trans, LMPM_CHICK,
 760                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 761
 762                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 763                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 764                                                    copy_size);
 765
 766                 if (extended_addr)
 767                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 768                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 769
 770                 if (ret) {
 771                         IWL_ERR(trans,
 772                                 "Could not load the [%d] uCode section\n",
 773                                 section_num);
 774                         break;
 775                 }
 776         }
 777
 778         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 779         return ret;
 780 }
 781
 782 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 783                                            const struct fw_img *image,
 784                                            int cpu,
 785                                            int *first_ucode_section)
 786 {
 787         int shift_param;
 788         int i, ret = 0, sec_num = 0x1;
 789         u32 val, last_read_idx = 0;
 790
 791         if (cpu == 1) {
 792                 shift_param = 0;
 793                 *first_ucode_section = 0;
 794         } else {
 795                 shift_param = 16;
 796                 (*first_ucode_section)++;
 797         }
 798
 799         for (i = *first_ucode_section; i < image->num_sec; i++) {
 800                 last_read_idx = i;
 801
 802                 /*
 803                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 804                  * CPU1 to CPU2.
 805                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 806                  * CPU2 non paged to CPU2 paging sec.
 807                  */
 808                 if (!image->sec[i].data ||
 809                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 810                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 811                         IWL_DEBUG_FW(trans,
 812                                      "Break since Data not valid or Empty section, sec = %d\n",
 813                                      i);
 814                         break;
 815                 }
 816
 817                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 818                 if (ret)
 819                         return ret;
 820
 821                 /* Notify ucode of loaded section number and status */
 822                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 823                 val = val | (sec_num << shift_param);
 824                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 825
 826                 sec_num = (sec_num << 1) | 0x1;
 827         }
 828
 829         *first_ucode_section = last_read_idx;
 830
 831         iwl_enable_interrupts(trans);
 832
 833         if (trans->trans_cfg->use_tfh) {
 834                 if (cpu == 1)
 835                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 836                                        0xFFFF);
 837                 else
 838                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 839                                        0xFFFFFFFF);
 840         } else {
 841                 if (cpu == 1)
 842                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 843                                            0xFFFF);
 844                 else
 845                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 846                                            0xFFFFFFFF);
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 853                                       const struct fw_img *image,
 854                                       int cpu,
 855                                       int *first_ucode_section)
 856 {
 857         int i, ret = 0;
 858         u32 last_read_idx = 0;
 859
 860         if (cpu == 1)
 861                 *first_ucode_section = 0;
 862         else
 863                 (*first_ucode_section)++;
 864
 865         for (i = *first_ucode_section; i < image->num_sec; i++) {
 866                 last_read_idx = i;
 867
 868                 /*
 869                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 870                  * CPU1 to CPU2.
 871                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 872                  * CPU2 non paged to CPU2 paging sec.
 873                  */
 874                 if (!image->sec[i].data ||
 875                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 876                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 877                         IWL_DEBUG_FW(trans,
 878                                      "Break since Data not valid or Empty section, sec = %d\n",
 879                                      i);
 880                         break;
 881                 }
 882
 883                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 884                 if (ret)
 885                         return ret;
 886         }
 887
 888         *first_ucode_section = last_read_idx;
 889
 890         return 0;
 891 }
 892
 893 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
 894 {
 895         enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
 896         struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
 897                 &trans->dbg.fw_mon_cfg[alloc_id];
 898         struct iwl_dram_data *frag;
 899
 900         if (!iwl_trans_dbg_ini_valid(trans))
 901                 return;
 902
 903         if (le32_to_cpu(fw_mon_cfg->buf_location) ==
 904             IWL_FW_INI_LOCATION_SRAM_PATH) {
 905                 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
 906                 /* set sram monitor by enabling bit 7 */
 907                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 908                             CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
 909
 910                 return;
 911         }
 912
 913         if (le32_to_cpu(fw_mon_cfg->buf_location) !=
 914             IWL_FW_INI_LOCATION_DRAM_PATH ||
 915             !trans->dbg.fw_mon_ini[alloc_id].num_frags)
 916                 return;
 917
 918         frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
 919
 920         IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
 921                      alloc_id);
 922
 923         iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
 924                             frag->physical >> MON_BUFF_SHIFT_VER2);
 925         iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
 926                             (frag->physical + frag->size - 256) >>
 927                             MON_BUFF_SHIFT_VER2);
 928 }
 929
 930 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 931 {
 932         const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
 933         const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 934         int i;
 935
 936         if (iwl_trans_dbg_ini_valid(trans)) {
 937                 iwl_pcie_apply_destination_ini(trans);
 938                 return;
 939         }
 940
 941         IWL_INFO(trans, "Applying debug destination %s\n",
 942                  get_fw_dbg_mode_string(dest->monitor_mode));
 943
 944         if (dest->monitor_mode == EXTERNAL_MODE)
 945                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 946         else
 947                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 948
 949         for (i = 0; i < trans->dbg.n_dest_reg; i++) {
 950                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 951                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 952
 953                 switch (dest->reg_ops[i].op) {
 954                 case CSR_ASSIGN:
 955                         iwl_write32(trans, addr, val);
 956                         break;
 957                 case CSR_SETBIT:
 958                         iwl_set_bit(trans, addr, BIT(val));
 959                         break;
 960                 case CSR_CLEARBIT:
 961                         iwl_clear_bit(trans, addr, BIT(val));
 962                         break;
 963                 case PRPH_ASSIGN:
 964                         iwl_write_prph(trans, addr, val);
 965                         break;
 966                 case PRPH_SETBIT:
 967                         iwl_set_bits_prph(trans, addr, BIT(val));
 968                         break;
 969                 case PRPH_CLEARBIT:
 970                         iwl_clear_bits_prph(trans, addr, BIT(val));
 971                         break;
 972                 case PRPH_BLOCKBIT:
 973                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 974                                 IWL_ERR(trans,
 975                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 976                                         val, addr);
 977                                 goto monitor;
 978                         }
 979                         break;
 980                 default:
 981                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 982                                 dest->reg_ops[i].op);
 983                         break;
 984                 }
 985         }
 986
 987 monitor:
 988         if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
 989                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 990                                fw_mon->physical >> dest->base_shift);
 991                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 992                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 993                                        (fw_mon->physical + fw_mon->size -
 994                                         256) >> dest->end_shift);
 995                 else
 996                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 997                                        (fw_mon->physical + fw_mon->size) >>
 998                                        dest->end_shift);
 999         }
1000 }
1001
1002 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
1003                                 const struct fw_img *image)
1004 {
1005         int ret = 0;
1006         int first_ucode_section;
1007
1008         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1009                      image->is_dual_cpus ? "Dual" : "Single");
1010
1011         /* load to FW the binary non secured sections of CPU1 */
1012         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1013         if (ret)
1014                 return ret;
1015
1016         if (image->is_dual_cpus) {
1017                 /* set CPU2 header address */
1018                 iwl_write_prph(trans,
1019                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1020                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1021
1022                 /* load to FW the binary sections of CPU2 */
1023                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1024                                                  &first_ucode_section);
1025                 if (ret)
1026                         return ret;
1027         }
1028
1029         /* supported for 7000 only for the moment */
1030         if (iwlwifi_mod_params.fw_monitor &&
1031             trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1032                 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
1033
1034                 iwl_pcie_alloc_fw_monitor(trans, 0);
1035                 if (fw_mon->size) {
1036                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1037                                        fw_mon->physical >> 4);
1038                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
1039                                        (fw_mon->physical + fw_mon->size) >> 4);
1040                 }
1041         } else if (iwl_pcie_dbg_on(trans)) {
1042                 iwl_pcie_apply_destination(trans);
1043         }
1044
1045         iwl_enable_interrupts(trans);
1046
1047         /* release CPU reset */
1048         iwl_write32(trans, CSR_RESET, 0);
1049
1050         return 0;
1051 }
1052
1053 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1054                                           const struct fw_img *image)
1055 {
1056         int ret = 0;
1057         int first_ucode_section;
1058
1059         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1060                      image->is_dual_cpus ? "Dual" : "Single");
1061
1062         if (iwl_pcie_dbg_on(trans))
1063                 iwl_pcie_apply_destination(trans);
1064
1065         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1066                         iwl_read_prph(trans, WFPM_GP2));
1067
1068         /*
1069          * Set default value. On resume reading the values that were
1070          * zeored can provide debug data on the resume flow.
1071          * This is for debugging only and has no functional impact.
1072          */
1073         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1074
1075         /* configure the ucode to be ready to get the secured image */
1076         /* release CPU reset */
1077         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1078
1079         /* load to FW the binary Secured sections of CPU1 */
1080         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1081                                               &first_ucode_section);
1082         if (ret)
1083                 return ret;
1084
1085         /* load to FW the binary sections of CPU2 */
1086         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1087                                                &first_ucode_section);
1088 }
1089
1090 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1091 {
1092         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1093         bool hw_rfkill = iwl_is_rfkill_set(trans);
1094         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1095         bool report;
1096
1097         if (hw_rfkill) {
1098                 set_bit(STATUS_RFKILL_HW, &trans->status);
1099                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1100         } else {
1101                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1102                 if (trans_pcie->opmode_down)
1103                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1104         }
1105
1106         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1107
1108         if (prev != report)
1109                 iwl_trans_pcie_rf_kill(trans, report);
1110
1111         return hw_rfkill;
1112 }
1113
1114 struct iwl_causes_list {
1115         u32 cause_num;
1116         u32 mask_reg;
1117         u8 addr;
1118 };
1119
1120 static struct iwl_causes_list causes_list[] = {
1121         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1122         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1123         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1124         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1125         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1126         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1127         {MSIX_HW_INT_CAUSES_REG_IML,            CSR_MSIX_HW_INT_MASK_AD, 0x12},
1128         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1129         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1130         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1131         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1132         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1133         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1134         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1135         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1136 };
1137
1138 static struct iwl_causes_list causes_list_v2[] = {
1139         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1140         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1141         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1142         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1143         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1144         {MSIX_HW_INT_CAUSES_REG_IPC,            CSR_MSIX_HW_INT_MASK_AD, 0x11},
1145         {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2,      CSR_MSIX_HW_INT_MASK_AD, 0x15},
1146         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1147         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1148         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1149         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1150         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1151         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1152         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1153 };
1154
1155 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1156 {
1157         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1158         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1159         int i, arr_size =
1160                 (trans->trans_cfg->device_family != IWL_DEVICE_FAMILY_22560) ?
1161                 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2);
1162
1163         /*
1164          * Access all non RX causes and map them to the default irq.
1165          * In case we are missing at least one interrupt vector,
1166          * the first interrupt vector will serve non-RX and FBQ causes.
1167          */
1168         for (i = 0; i < arr_size; i++) {
1169                 struct iwl_causes_list *causes =
1170                         (trans->trans_cfg->device_family !=
1171                          IWL_DEVICE_FAMILY_22560) ?
1172                         causes_list : causes_list_v2;
1173
1174                 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1175                 iwl_clear_bit(trans, causes[i].mask_reg,
1176                               causes[i].cause_num);
1177         }
1178 }
1179
1180 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1181 {
1182         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1183         u32 offset =
1184                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1185         u32 val, idx;
1186
1187         /*
1188          * The first RX queue - fallback queue, which is designated for
1189          * management frame, command responses etc, is always mapped to the
1190          * first interrupt vector. The other RX queues are mapped to
1191          * the other (N - 2) interrupt vectors.
1192          */
1193         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1194         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1195                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1196                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1197                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1198         }
1199         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1200
1201         val = MSIX_FH_INT_CAUSES_Q(0);
1202         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1203                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1204         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1205
1206         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1207                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1208 }
1209
1210 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1211 {
1212         struct iwl_trans *trans = trans_pcie->trans;
1213
1214         if (!trans_pcie->msix_enabled) {
1215                 if (trans->trans_cfg->mq_rx_supported &&
1216                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1217                         iwl_write_umac_prph(trans, UREG_CHICK,
1218                                             UREG_CHICK_MSI_ENABLE);
1219                 return;
1220         }
1221         /*
1222          * The IVAR table needs to be configured again after reset,
1223          * but if the device is disabled, we can't write to
1224          * prph.
1225          */
1226         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1227                 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1228
1229         /*
1230          * Each cause from the causes list above and the RX causes is
1231          * represented as a byte in the IVAR table. The first nibble
1232          * represents the bound interrupt vector of the cause, the second
1233          * represents no auto clear for this cause. This will be set if its
1234          * interrupt vector is bound to serve other causes.
1235          */
1236         iwl_pcie_map_rx_causes(trans);
1237
1238         iwl_pcie_map_non_rx_causes(trans);
1239 }
1240
1241 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1242 {
1243         struct iwl_trans *trans = trans_pcie->trans;
1244
1245         iwl_pcie_conf_msix_hw(trans_pcie);
1246
1247         if (!trans_pcie->msix_enabled)
1248                 return;
1249
1250         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1251         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1252         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1253         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1254 }
1255
1256 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1257 {
1258         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1259
1260         lockdep_assert_held(&trans_pcie->mutex);
1261
1262         if (trans_pcie->is_down)
1263                 return;
1264
1265         trans_pcie->is_down = true;
1266
1267         /* tell the device to stop sending interrupts */
1268         iwl_disable_interrupts(trans);
1269
1270         /* device going down, Stop using ICT table */
1271         iwl_pcie_disable_ict(trans);
1272
1273         /*
1274          * If a HW restart happens during firmware loading,
1275          * then the firmware loading might call this function
1276          * and later it might be called again due to the
1277          * restart. So don't process again if the device is
1278          * already dead.
1279          */
1280         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1281                 IWL_DEBUG_INFO(trans,
1282                                "DEVICE_ENABLED bit was set and is now cleared\n");
1283                 iwl_pcie_tx_stop(trans);
1284                 iwl_pcie_rx_stop(trans);
1285
1286                 /* Power-down device's busmaster DMA clocks */
1287                 if (!trans->cfg->apmg_not_supported) {
1288                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1289                                        APMG_CLK_VAL_DMA_CLK_RQT);
1290                         udelay(5);
1291                 }
1292         }
1293
1294         /* Make sure (redundant) we've released our request to stay awake */
1295         iwl_clear_bit(trans, CSR_GP_CNTRL,
1296                       BIT(trans->trans_cfg->csr->flag_mac_access_req));
1297
1298         /* Stop the device, and put it in low power state */
1299         iwl_pcie_apm_stop(trans, false);
1300
1301         iwl_trans_pcie_sw_reset(trans);
1302
1303         /*
1304          * Upon stop, the IVAR table gets erased, so msi-x won't
1305          * work. This causes a bug in RF-KILL flows, since the interrupt
1306          * that enables radio won't fire on the correct irq, and the
1307          * driver won't be able to handle the interrupt.
1308          * Configure the IVAR table again after reset.
1309          */
1310         iwl_pcie_conf_msix_hw(trans_pcie);
1311
1312         /*
1313          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1314          * This is a bug in certain verions of the hardware.
1315          * Certain devices also keep sending HW RF kill interrupt all
1316          * the time, unless the interrupt is ACKed even if the interrupt
1317          * should be masked. Re-ACK all the interrupts here.
1318          */
1319         iwl_disable_interrupts(trans);
1320
1321         /* clear all status bits */
1322         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1323         clear_bit(STATUS_INT_ENABLED, &trans->status);
1324         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1325
1326         /*
1327          * Even if we stop the HW, we still want the RF kill
1328          * interrupt
1329          */
1330         iwl_enable_rfkill_int(trans);
1331
1332         /* re-take ownership to prevent other users from stealing the device */
1333         iwl_pcie_prepare_card_hw(trans);
1334 }
1335
1336 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1337 {
1338         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1339
1340         if (trans_pcie->msix_enabled) {
1341                 int i;
1342
1343                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1344                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1345         } else {
1346                 synchronize_irq(trans_pcie->pci_dev->irq);
1347         }
1348 }
1349
1350 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1351                                    const struct fw_img *fw, bool run_in_rfkill)
1352 {
1353         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1354         bool hw_rfkill;
1355         int ret;
1356
1357         /* This may fail if AMT took ownership of the device */
1358         if (iwl_pcie_prepare_card_hw(trans)) {
1359                 IWL_WARN(trans, "Exit HW not ready\n");
1360                 ret = -EIO;
1361                 goto out;
1362         }
1363
1364         iwl_enable_rfkill_int(trans);
1365
1366         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1367
1368         /*
1369          * We enabled the RF-Kill interrupt and the handler may very
1370          * well be running. Disable the interrupts to make sure no other
1371          * interrupt can be fired.
1372          */
1373         iwl_disable_interrupts(trans);
1374
1375         /* Make sure it finished running */
1376         iwl_pcie_synchronize_irqs(trans);
1377
1378         mutex_lock(&trans_pcie->mutex);
1379
1380         /* If platform's RF_KILL switch is NOT set to KILL */
1381         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1382         if (hw_rfkill && !run_in_rfkill) {
1383                 ret = -ERFKILL;
1384                 goto out;
1385         }
1386
1387         /* Someone called stop_device, don't try to start_fw */
1388         if (trans_pcie->is_down) {
1389                 IWL_WARN(trans,
1390                          "Can't start_fw since the HW hasn't been started\n");
1391                 ret = -EIO;
1392                 goto out;
1393         }
1394
1395         /* make sure rfkill handshake bits are cleared */
1396         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1397         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1398                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1399
1400         /* clear (again), then enable host interrupts */
1401         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1402
1403         ret = iwl_pcie_nic_init(trans);
1404         if (ret) {
1405                 IWL_ERR(trans, "Unable to init nic\n");
1406                 goto out;
1407         }
1408
1409         /*
1410          * Now, we load the firmware and don't want to be interrupted, even
1411          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1412          * FH_TX interrupt which is needed to load the firmware). If the
1413          * RF-Kill switch is toggled, we will find out after having loaded
1414          * the firmware and return the proper value to the caller.
1415          */
1416         iwl_enable_fw_load_int(trans);
1417
1418         /* really make sure rfkill handshake bits are cleared */
1419         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1420         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1421
1422         /* Load the given image to the HW */
1423         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1424                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1425         else
1426                 ret = iwl_pcie_load_given_ucode(trans, fw);
1427
1428         /* re-check RF-Kill state since we may have missed the interrupt */
1429         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1430         if (hw_rfkill && !run_in_rfkill)
1431                 ret = -ERFKILL;
1432
1433 out:
1434         mutex_unlock(&trans_pcie->mutex);
1435         return ret;
1436 }
1437
1438 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1439 {
1440         iwl_pcie_reset_ict(trans);
1441         iwl_pcie_tx_start(trans, scd_addr);
1442 }
1443
1444 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1445                                        bool was_in_rfkill)
1446 {
1447         bool hw_rfkill;
1448
1449         /*
1450          * Check again since the RF kill state may have changed while
1451          * all the interrupts were disabled, in this case we couldn't
1452          * receive the RF kill interrupt and update the state in the
1453          * op_mode.
1454          * Don't call the op_mode if the rkfill state hasn't changed.
1455          * This allows the op_mode to call stop_device from the rfkill
1456          * notification without endless recursion. Under very rare
1457          * circumstances, we might have a small recursion if the rfkill
1458          * state changed exactly now while we were called from stop_device.
1459          * This is very unlikely but can happen and is supported.
1460          */
1461         hw_rfkill = iwl_is_rfkill_set(trans);
1462         if (hw_rfkill) {
1463                 set_bit(STATUS_RFKILL_HW, &trans->status);
1464                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1465         } else {
1466                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1467                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1468         }
1469         if (hw_rfkill != was_in_rfkill)
1470                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1471 }
1472
1473 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1474 {
1475         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1476         bool was_in_rfkill;
1477
1478         mutex_lock(&trans_pcie->mutex);
1479         trans_pcie->opmode_down = true;
1480         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1481         _iwl_trans_pcie_stop_device(trans);
1482         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1483         mutex_unlock(&trans_pcie->mutex);
1484 }
1485
1486 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1487 {
1488         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1489                 IWL_TRANS_GET_PCIE_TRANS(trans);
1490
1491         lockdep_assert_held(&trans_pcie->mutex);
1492
1493         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1494                  state ? "disabled" : "enabled");
1495         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1496                 if (trans->trans_cfg->gen2)
1497                         _iwl_trans_pcie_gen2_stop_device(trans);
1498                 else
1499                         _iwl_trans_pcie_stop_device(trans);
1500         }
1501 }
1502
1503 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1504                                   bool test, bool reset)
1505 {
1506         iwl_disable_interrupts(trans);
1507
1508         /*
1509          * in testing mode, the host stays awake and the
1510          * hardware won't be reset (not even partially)
1511          */
1512         if (test)
1513                 return;
1514
1515         iwl_pcie_disable_ict(trans);
1516
1517         iwl_pcie_synchronize_irqs(trans);
1518
1519         iwl_clear_bit(trans, CSR_GP_CNTRL,
1520                       BIT(trans->trans_cfg->csr->flag_mac_access_req));
1521         iwl_clear_bit(trans, CSR_GP_CNTRL,
1522                       BIT(trans->trans_cfg->csr->flag_init_done));
1523
1524         if (reset) {
1525                 /*
1526                  * reset TX queues -- some of their registers reset during S3
1527                  * so if we don't reset everything here the D3 image would try
1528                  * to execute some invalid memory upon resume
1529                  */
1530                 iwl_trans_pcie_tx_reset(trans);
1531         }
1532
1533         iwl_pcie_set_pwr(trans, true);
1534 }
1535
1536 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1537                                      bool reset)
1538 {
1539         int ret;
1540         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1541
1542         /*
1543          * Family IWL_DEVICE_FAMILY_AX210 and above persist mode is set by FW.
1544          */
1545         if (!reset && trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
1546                 /* Enable persistence mode to avoid reset */
1547                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1548                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1549         }
1550
1551         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1552                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1553                                     UREG_DOORBELL_TO_ISR6_SUSPEND);
1554
1555                 ret = wait_event_timeout(trans_pcie->sx_waitq,
1556                                          trans_pcie->sx_complete, 2 * HZ);
1557                 /*
1558                  * Invalidate it toward resume.
1559                  */
1560                 trans_pcie->sx_complete = false;
1561
1562                 if (!ret) {
1563                         IWL_ERR(trans, "Timeout entering D3\n");
1564                         return -ETIMEDOUT;
1565                 }
1566         }
1567         iwl_pcie_d3_complete_suspend(trans, test, reset);
1568
1569         return 0;
1570 }
1571
1572 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1573                                     enum iwl_d3_status *status,
1574                                     bool test,  bool reset)
1575 {
1576         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1577         u32 val;
1578         int ret;
1579
1580         if (test) {
1581                 iwl_enable_interrupts(trans);
1582                 *status = IWL_D3_STATUS_ALIVE;
1583                 goto out;
1584         }
1585
1586         iwl_set_bit(trans, CSR_GP_CNTRL,
1587                     BIT(trans->trans_cfg->csr->flag_mac_access_req));
1588
1589         ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1590         if (ret)
1591                 return ret;
1592
1593         /*
1594          * Reconfigure IVAR table in case of MSIX or reset ict table in
1595          * MSI mode since HW reset erased it.
1596          * Also enables interrupts - none will happen as
1597          * the device doesn't know we're waking it up, only when
1598          * the opmode actually tells it after this call.
1599          */
1600         iwl_pcie_conf_msix_hw(trans_pcie);
1601         if (!trans_pcie->msix_enabled)
1602                 iwl_pcie_reset_ict(trans);
1603         iwl_enable_interrupts(trans);
1604
1605         iwl_pcie_set_pwr(trans, false);
1606
1607         if (!reset) {
1608                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1609                               BIT(trans->trans_cfg->csr->flag_mac_access_req));
1610         } else {
1611                 iwl_trans_pcie_tx_reset(trans);
1612
1613                 ret = iwl_pcie_rx_init(trans);
1614                 if (ret) {
1615                         IWL_ERR(trans,
1616                                 "Failed to resume the device (RX reset)\n");
1617                         return ret;
1618                 }
1619         }
1620
1621         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1622                         iwl_read_umac_prph(trans, WFPM_GP2));
1623
1624         val = iwl_read32(trans, CSR_RESET);
1625         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1626                 *status = IWL_D3_STATUS_RESET;
1627         else
1628                 *status = IWL_D3_STATUS_ALIVE;
1629
1630 out:
1631         if (*status == IWL_D3_STATUS_ALIVE &&
1632             trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1633                 trans_pcie->sx_complete = false;
1634                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1635                                     UREG_DOORBELL_TO_ISR6_RESUME);
1636
1637                 ret = wait_event_timeout(trans_pcie->sx_waitq,
1638                                          trans_pcie->sx_complete, 2 * HZ);
1639                 /*
1640                  * Invalidate it toward next suspend.
1641                  */
1642                 trans_pcie->sx_complete = false;
1643
1644                 if (!ret) {
1645                         IWL_ERR(trans, "Timeout exiting D3\n");
1646                         return -ETIMEDOUT;
1647                 }
1648         }
1649         return 0;
1650 }
1651
1652 static void
1653 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1654                             struct iwl_trans *trans,
1655                             const struct iwl_cfg_trans_params *cfg_trans)
1656 {
1657         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1658         int max_irqs, num_irqs, i, ret;
1659         u16 pci_cmd;
1660
1661         if (!cfg_trans->mq_rx_supported)
1662                 goto enable_msi;
1663
1664         max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
1665         for (i = 0; i < max_irqs; i++)
1666                 trans_pcie->msix_entries[i].entry = i;
1667
1668         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1669                                          MSIX_MIN_INTERRUPT_VECTORS,
1670                                          max_irqs);
1671         if (num_irqs < 0) {
1672                 IWL_DEBUG_INFO(trans,
1673                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1674                                num_irqs);
1675                 goto enable_msi;
1676         }
1677         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1678
1679         IWL_DEBUG_INFO(trans,
1680                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1681                        num_irqs);
1682
1683         /*
1684          * In case the OS provides fewer interrupts than requested, different
1685          * causes will share the same interrupt vector as follows:
1686          * One interrupt less: non rx causes shared with FBQ.
1687          * Two interrupts less: non rx causes shared with FBQ and RSS.
1688          * More than two interrupts: we will use fewer RSS queues.
1689          */
1690         if (num_irqs <= max_irqs - 2) {
1691                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1692                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1693                         IWL_SHARED_IRQ_FIRST_RSS;
1694         } else if (num_irqs == max_irqs - 1) {
1695                 trans_pcie->trans->num_rx_queues = num_irqs;
1696                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1697         } else {
1698                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1699         }
1700         WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1701
1702         trans_pcie->alloc_vecs = num_irqs;
1703         trans_pcie->msix_enabled = true;
1704         return;
1705
1706 enable_msi:
1707         ret = pci_enable_msi(pdev);
1708         if (ret) {
1709                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1710                 /* enable rfkill interrupt: hw bug w/a */
1711                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1712                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1713                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1714                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1715                 }
1716         }
1717 }
1718
1719 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1720 {
1721         int iter_rx_q, i, ret, cpu, offset;
1722         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1723
1724         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1725         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1726         offset = 1 + i;
1727         for (; i < iter_rx_q ; i++) {
1728                 /*
1729                  * Get the cpu prior to the place to search
1730                  * (i.e. return will be > i - 1).
1731                  */
1732                 cpu = cpumask_next(i - offset, cpu_online_mask);
1733                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1734                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1735                                             &trans_pcie->affinity_mask[i]);
1736                 if (ret)
1737                         IWL_ERR(trans_pcie->trans,
1738                                 "Failed to set affinity mask for IRQ %d\n",
1739                                 i);
1740         }
1741 }
1742
1743 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1744                                       struct iwl_trans_pcie *trans_pcie)
1745 {
1746         int i;
1747
1748         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1749                 int ret;
1750                 struct msix_entry *msix_entry;
1751                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1752
1753                 if (!qname)
1754                         return -ENOMEM;
1755
1756                 msix_entry = &trans_pcie->msix_entries[i];
1757                 ret = devm_request_threaded_irq(&pdev->dev,
1758                                                 msix_entry->vector,
1759                                                 iwl_pcie_msix_isr,
1760                                                 (i == trans_pcie->def_irq) ?
1761                                                 iwl_pcie_irq_msix_handler :
1762                                                 iwl_pcie_irq_rx_msix_handler,
1763                                                 IRQF_SHARED,
1764                                                 qname,
1765                                                 msix_entry);
1766                 if (ret) {
1767                         IWL_ERR(trans_pcie->trans,
1768                                 "Error allocating IRQ %d\n", i);
1769
1770                         return ret;
1771                 }
1772         }
1773         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1774
1775         return 0;
1776 }
1777
1778 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1779 {
1780         u32 hpm, wprot;
1781
1782         switch (trans->trans_cfg->device_family) {
1783         case IWL_DEVICE_FAMILY_9000:
1784                 wprot = PREG_PRPH_WPROT_9000;
1785                 break;
1786         case IWL_DEVICE_FAMILY_22000:
1787                 wprot = PREG_PRPH_WPROT_22000;
1788                 break;
1789         default:
1790                 return 0;
1791         }
1792
1793         hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1794         if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1795                 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1796
1797                 if (wprot_val & PREG_WFPM_ACCESS) {
1798                         IWL_ERR(trans,
1799                                 "Error, can not clear persistence bit\n");
1800                         return -EPERM;
1801                 }
1802                 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1803                                             hpm & ~PERSISTENCE_BIT);
1804         }
1805
1806         return 0;
1807 }
1808
1809 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1810 {
1811         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1812         int err;
1813
1814         lockdep_assert_held(&trans_pcie->mutex);
1815
1816         err = iwl_pcie_prepare_card_hw(trans);
1817         if (err) {
1818                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1819                 return err;
1820         }
1821
1822         err = iwl_trans_pcie_clear_persistence_bit(trans);
1823         if (err)
1824                 return err;
1825
1826         iwl_trans_pcie_sw_reset(trans);
1827
1828         err = iwl_pcie_apm_init(trans);
1829         if (err)
1830                 return err;
1831
1832         iwl_pcie_init_msix(trans_pcie);
1833
1834         /* From now on, the op_mode will be kept updated about RF kill state */
1835         iwl_enable_rfkill_int(trans);
1836
1837         trans_pcie->opmode_down = false;
1838
1839         /* Set is_down to false here so that...*/
1840         trans_pcie->is_down = false;
1841
1842         /* ...rfkill can call stop_device and set it false if needed */
1843         iwl_pcie_check_hw_rf_kill(trans);
1844
1845         return 0;
1846 }
1847
1848 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1849 {
1850         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1851         int ret;
1852
1853         mutex_lock(&trans_pcie->mutex);
1854         ret = _iwl_trans_pcie_start_hw(trans);
1855         mutex_unlock(&trans_pcie->mutex);
1856
1857         return ret;
1858 }
1859
1860 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1861 {
1862         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1863
1864         mutex_lock(&trans_pcie->mutex);
1865
1866         /* disable interrupts - don't enable HW RF kill interrupt */
1867         iwl_disable_interrupts(trans);
1868
1869         iwl_pcie_apm_stop(trans, true);
1870
1871         iwl_disable_interrupts(trans);
1872
1873         iwl_pcie_disable_ict(trans);
1874
1875         mutex_unlock(&trans_pcie->mutex);
1876
1877         iwl_pcie_synchronize_irqs(trans);
1878 }
1879
1880 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1881 {
1882         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1883 }
1884
1885 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1886 {
1887         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1888 }
1889
1890 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1891 {
1892         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1893 }
1894
1895 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1896 {
1897         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1898                 return 0x00FFFFFF;
1899         else
1900                 return 0x000FFFFF;
1901 }
1902
1903 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1904 {
1905         u32 mask = iwl_trans_pcie_prph_msk(trans);
1906
1907         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1908                                ((reg & mask) | (3 << 24)));
1909         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1910 }
1911
1912 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1913                                       u32 val)
1914 {
1915         u32 mask = iwl_trans_pcie_prph_msk(trans);
1916
1917         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1918                                ((addr & mask) | (3 << 24)));
1919         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1920 }
1921
1922 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1923                                      const struct iwl_trans_config *trans_cfg)
1924 {
1925         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1926
1927         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1928         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1929         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1930         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1931                 trans_pcie->n_no_reclaim_cmds = 0;
1932         else
1933                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1934         if (trans_pcie->n_no_reclaim_cmds)
1935                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1936                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1937
1938         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1939         trans_pcie->rx_page_order =
1940                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1941
1942         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1943         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1944         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1945
1946         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1947         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1948
1949         trans->command_groups = trans_cfg->command_groups;
1950         trans->command_groups_size = trans_cfg->command_groups_size;
1951
1952         /* Initialize NAPI here - it should be before registering to mac80211
1953          * in the opmode but after the HW struct is allocated.
1954          * As this function may be called again in some corner cases don't
1955          * do anything if NAPI was already initialized.
1956          */
1957         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1958                 init_dummy_netdev(&trans_pcie->napi_dev);
1959 }
1960
1961 void iwl_trans_pcie_free(struct iwl_trans *trans)
1962 {
1963         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1964         int i;
1965
1966         iwl_pcie_synchronize_irqs(trans);
1967
1968         if (trans->trans_cfg->gen2)
1969                 iwl_pcie_gen2_tx_free(trans);
1970         else
1971                 iwl_pcie_tx_free(trans);
1972         iwl_pcie_rx_free(trans);
1973
1974         if (trans_pcie->rba.alloc_wq) {
1975                 destroy_workqueue(trans_pcie->rba.alloc_wq);
1976                 trans_pcie->rba.alloc_wq = NULL;
1977         }
1978
1979         if (trans_pcie->msix_enabled) {
1980                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1981                         irq_set_affinity_hint(
1982                                 trans_pcie->msix_entries[i].vector,
1983                                 NULL);
1984                 }
1985
1986                 trans_pcie->msix_enabled = false;
1987         } else {
1988                 iwl_pcie_free_ict(trans);
1989         }
1990
1991         iwl_pcie_free_fw_monitor(trans);
1992
1993         for_each_possible_cpu(i) {
1994                 struct iwl_tso_hdr_page *p =
1995                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1996
1997                 if (p->page)
1998                         __free_page(p->page);
1999         }
2000
2001         free_percpu(trans_pcie->tso_hdr_page);
2002         mutex_destroy(&trans_pcie->mutex);
2003         iwl_trans_free(trans);
2004 }
2005
2006 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2007 {
2008         if (state)
2009                 set_bit(STATUS_TPOWER_PMI, &trans->status);
2010         else
2011                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
2012 }
2013
2014 struct iwl_trans_pcie_removal {
2015         struct pci_dev *pdev;
2016         struct work_struct work;
2017 };
2018
2019 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2020 {
2021         struct iwl_trans_pcie_removal *removal =
2022                 container_of(wk, struct iwl_trans_pcie_removal, work);
2023         struct pci_dev *pdev = removal->pdev;
2024         static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
2025
2026         dev_err(&pdev->dev, "Device gone - attempting removal\n");
2027         kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2028         pci_lock_rescan_remove();
2029         pci_dev_put(pdev);
2030         pci_stop_and_remove_bus_device(pdev);
2031         pci_unlock_rescan_remove();
2032
2033         kfree(removal);
2034         module_put(THIS_MODULE);
2035 }
2036
2037 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
2038                                            unsigned long *flags)
2039 {
2040         int ret;
2041         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2042
2043         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
2044
2045         if (trans_pcie->cmd_hold_nic_awake)
2046                 goto out;
2047
2048         /* this bit wakes up the NIC */
2049         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
2050                                  BIT(trans->trans_cfg->csr->flag_mac_access_req));
2051         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2052                 udelay(2);
2053
2054         /*
2055          * These bits say the device is running, and should keep running for
2056          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2057          * but they do not indicate that embedded SRAM is restored yet;
2058          * HW with volatile SRAM must save/restore contents to/from
2059          * host DRAM when sleeping/waking for power-saving.
2060          * Each direction takes approximately 1/4 millisecond; with this
2061          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2062          * series of register accesses are expected (e.g. reading Event Log),
2063          * to keep device from sleeping.
2064          *
2065          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2066          * SRAM is okay/restored.  We don't check that here because this call
2067          * is just for hardware register access; but GP1 MAC_SLEEP
2068          * check is a good idea before accessing the SRAM of HW with
2069          * volatile SRAM (e.g. reading Event Log).
2070          *
2071          * 5000 series and later (including 1000 series) have non-volatile SRAM,
2072          * and do not save/restore SRAM when power cycling.
2073          */
2074         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2075                            BIT(trans->trans_cfg->csr->flag_val_mac_access_en),
2076                            (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) |
2077                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2078         if (unlikely(ret < 0)) {
2079                 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2080
2081                 WARN_ONCE(1,
2082                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2083                           cntrl);
2084
2085                 iwl_trans_pcie_dump_regs(trans);
2086
2087                 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2088                         struct iwl_trans_pcie_removal *removal;
2089
2090                         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2091                                 goto err;
2092
2093                         IWL_ERR(trans, "Device gone - scheduling removal!\n");
2094
2095                         /*
2096                          * get a module reference to avoid doing this
2097                          * while unloading anyway and to avoid
2098                          * scheduling a work with code that's being
2099                          * removed.
2100                          */
2101                         if (!try_module_get(THIS_MODULE)) {
2102                                 IWL_ERR(trans,
2103                                         "Module is being unloaded - abort\n");
2104                                 goto err;
2105                         }
2106
2107                         removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2108                         if (!removal) {
2109                                 module_put(THIS_MODULE);
2110                                 goto err;
2111                         }
2112                         /*
2113                          * we don't need to clear this flag, because
2114                          * the trans will be freed and reallocated.
2115                         */
2116                         set_bit(STATUS_TRANS_DEAD, &trans->status);
2117
2118                         removal->pdev = to_pci_dev(trans->dev);
2119                         INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2120                         pci_dev_get(removal->pdev);
2121                         schedule_work(&removal->work);
2122                 } else {
2123                         iwl_write32(trans, CSR_RESET,
2124                                     CSR_RESET_REG_FLAG_FORCE_NMI);
2125                 }
2126
2127 err:
2128                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2129                 return false;
2130         }
2131
2132 out:
2133         /*
2134          * Fool sparse by faking we release the lock - sparse will
2135          * track nic_access anyway.
2136          */
2137         __release(&trans_pcie->reg_lock);
2138         return true;
2139 }
2140
2141 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2142                                               unsigned long *flags)
2143 {
2144         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2145
2146         lockdep_assert_held(&trans_pcie->reg_lock);
2147
2148         /*
2149          * Fool sparse by faking we acquiring the lock - sparse will
2150          * track nic_access anyway.
2151          */
2152         __acquire(&trans_pcie->reg_lock);
2153
2154         if (trans_pcie->cmd_hold_nic_awake)
2155                 goto out;
2156
2157         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2158                                    BIT(trans->trans_cfg->csr->flag_mac_access_req));
2159         /*
2160          * Above we read the CSR_GP_CNTRL register, which will flush
2161          * any previous writes, but we need the write that clears the
2162          * MAC_ACCESS_REQ bit to be performed before any other writes
2163          * scheduled on different CPUs (after we drop reg_lock).
2164          */
2165 out:
2166         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2167 }
2168
2169 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2170                                    void *buf, int dwords)
2171 {
2172         unsigned long flags;
2173         int offs, ret = 0;
2174         u32 *vals = buf;
2175
2176         if (iwl_trans_grab_nic_access(trans, &flags)) {
2177                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
2178                 for (offs = 0; offs < dwords; offs++)
2179                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
2180                 iwl_trans_release_nic_access(trans, &flags);
2181         } else {
2182                 ret = -EBUSY;
2183         }
2184         return ret;
2185 }
2186
2187 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2188                                     const void *buf, int dwords)
2189 {
2190         unsigned long flags;
2191         int offs, ret = 0;
2192         const u32 *vals = buf;
2193
2194         if (iwl_trans_grab_nic_access(trans, &flags)) {
2195                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2196                 for (offs = 0; offs < dwords; offs++)
2197                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2198                                     vals ? vals[offs] : 0);
2199                 iwl_trans_release_nic_access(trans, &flags);
2200         } else {
2201                 ret = -EBUSY;
2202         }
2203         return ret;
2204 }
2205
2206 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2207                                             unsigned long txqs,
2208                                             bool freeze)
2209 {
2210         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2211         int queue;
2212
2213         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2214                 struct iwl_txq *txq = trans_pcie->txq[queue];
2215                 unsigned long now;
2216
2217                 spin_lock_bh(&txq->lock);
2218
2219                 now = jiffies;
2220
2221                 if (txq->frozen == freeze)
2222                         goto next_queue;
2223
2224                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2225                                     freeze ? "Freezing" : "Waking", queue);
2226
2227                 txq->frozen = freeze;
2228
2229                 if (txq->read_ptr == txq->write_ptr)
2230                         goto next_queue;
2231
2232                 if (freeze) {
2233                         if (unlikely(time_after(now,
2234                                                 txq->stuck_timer.expires))) {
2235                                 /*
2236                                  * The timer should have fired, maybe it is
2237                                  * spinning right now on the lock.
2238                                  */
2239                                 goto next_queue;
2240                         }
2241                         /* remember how long until the timer fires */
2242                         txq->frozen_expiry_remainder =
2243                                 txq->stuck_timer.expires - now;
2244                         del_timer(&txq->stuck_timer);
2245                         goto next_queue;
2246                 }
2247
2248                 /*
2249                  * Wake a non-empty queue -> arm timer with the
2250                  * remainder before it froze
2251                  */
2252                 mod_timer(&txq->stuck_timer,
2253                           now + txq->frozen_expiry_remainder);
2254
2255 next_queue:
2256                 spin_unlock_bh(&txq->lock);
2257         }
2258 }
2259
2260 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2261 {
2262         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2263         int i;
2264
2265         for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
2266                 struct iwl_txq *txq = trans_pcie->txq[i];
2267
2268                 if (i == trans_pcie->cmd_queue)
2269                         continue;
2270
2271                 spin_lock_bh(&txq->lock);
2272
2273                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2274                         txq->block--;
2275                         if (!txq->block) {
2276                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2277                                             txq->write_ptr | (i << 8));
2278                         }
2279                 } else if (block) {
2280                         txq->block++;
2281                 }
2282
2283                 spin_unlock_bh(&txq->lock);
2284         }
2285 }
2286
2287 #define IWL_FLUSH_WAIT_MS       2000
2288
2289 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2290 {
2291         u32 txq_id = txq->id;
2292         u32 status;
2293         bool active;
2294         u8 fifo;
2295
2296         if (trans->trans_cfg->use_tfh) {
2297                 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2298                         txq->read_ptr, txq->write_ptr);
2299                 /* TODO: access new SCD registers and dump them */
2300                 return;
2301         }
2302
2303         status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2304         fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2305         active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2306
2307         IWL_ERR(trans,
2308                 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2309                 txq_id, active ? "" : "in", fifo,
2310                 jiffies_to_msecs(txq->wd_timeout),
2311                 txq->read_ptr, txq->write_ptr,
2312                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2313                         (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2314                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2315                         (trans->trans_cfg->base_params->max_tfd_queue_size - 1),
2316                         iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2317 }
2318
2319 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2320                                        struct iwl_trans_rxq_dma_data *data)
2321 {
2322         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2323
2324         if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2325                 return -EINVAL;
2326
2327         data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2328         data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2329         data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2330         data->fr_bd_wid = 0;
2331
2332         return 0;
2333 }
2334
2335 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2336 {
2337         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2338         struct iwl_txq *txq;
2339         unsigned long now = jiffies;
2340         bool overflow_tx;
2341         u8 wr_ptr;
2342
2343         /* Make sure the NIC is still alive in the bus */
2344         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2345                 return -ENODEV;
2346
2347         if (!test_bit(txq_idx, trans_pcie->queue_used))
2348                 return -EINVAL;
2349
2350         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2351         txq = trans_pcie->txq[txq_idx];
2352
2353         spin_lock_bh(&txq->lock);
2354         overflow_tx = txq->overflow_tx ||
2355                       !skb_queue_empty(&txq->overflow_q);
2356         spin_unlock_bh(&txq->lock);
2357
2358         wr_ptr = READ_ONCE(txq->write_ptr);
2359
2360         while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2361                 overflow_tx) &&
2362                !time_after(jiffies,
2363                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2364                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2365
2366                 /*
2367                  * If write pointer moved during the wait, warn only
2368                  * if the TX came from op mode. In case TX came from
2369                  * trans layer (overflow TX) don't warn.
2370                  */
2371                 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2372                               "WR pointer moved while flushing %d -> %d\n",
2373                               wr_ptr, write_ptr))
2374                         return -ETIMEDOUT;
2375                 wr_ptr = write_ptr;
2376
2377                 usleep_range(1000, 2000);
2378
2379                 spin_lock_bh(&txq->lock);
2380                 overflow_tx = txq->overflow_tx ||
2381                               !skb_queue_empty(&txq->overflow_q);
2382                 spin_unlock_bh(&txq->lock);
2383         }
2384
2385         if (txq->read_ptr != txq->write_ptr) {
2386                 IWL_ERR(trans,
2387                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2388                 iwl_trans_pcie_log_scd_error(trans, txq);
2389                 return -ETIMEDOUT;
2390         }
2391
2392         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2393
2394         return 0;
2395 }
2396
2397 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2398 {
2399         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2400         int cnt;
2401         int ret = 0;
2402
2403         /* waiting for all the tx frames complete might take a while */
2404         for (cnt = 0;
2405              cnt < trans->trans_cfg->base_params->num_of_queues;
2406              cnt++) {
2407
2408                 if (cnt == trans_pcie->cmd_queue)
2409                         continue;
2410                 if (!test_bit(cnt, trans_pcie->queue_used))
2411                         continue;
2412                 if (!(BIT(cnt) & txq_bm))
2413                         continue;
2414
2415                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2416                 if (ret)
2417                         break;
2418         }
2419
2420         return ret;
2421 }
2422
2423 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2424                                          u32 mask, u32 value)
2425 {
2426         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2427         unsigned long flags;
2428
2429         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2430         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2431         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2432 }
2433
2434 static const char *get_csr_string(int cmd)
2435 {
2436 #define IWL_CMD(x) case x: return #x
2437         switch (cmd) {
2438         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2439         IWL_CMD(CSR_INT_COALESCING);
2440         IWL_CMD(CSR_INT);
2441         IWL_CMD(CSR_INT_MASK);
2442         IWL_CMD(CSR_FH_INT_STATUS);
2443         IWL_CMD(CSR_GPIO_IN);
2444         IWL_CMD(CSR_RESET);
2445         IWL_CMD(CSR_GP_CNTRL);
2446         IWL_CMD(CSR_HW_REV);
2447         IWL_CMD(CSR_EEPROM_REG);
2448         IWL_CMD(CSR_EEPROM_GP);
2449         IWL_CMD(CSR_OTP_GP_REG);
2450         IWL_CMD(CSR_GIO_REG);
2451         IWL_CMD(CSR_GP_UCODE_REG);
2452         IWL_CMD(CSR_GP_DRIVER_REG);
2453         IWL_CMD(CSR_UCODE_DRV_GP1);
2454         IWL_CMD(CSR_UCODE_DRV_GP2);
2455         IWL_CMD(CSR_LED_REG);
2456         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2457         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2458         IWL_CMD(CSR_ANA_PLL_CFG);
2459         IWL_CMD(CSR_HW_REV_WA_REG);
2460         IWL_CMD(CSR_MONITOR_STATUS_REG);
2461         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2462         default:
2463                 return "UNKNOWN";
2464         }
2465 #undef IWL_CMD
2466 }
2467
2468 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2469 {
2470         int i;
2471         static const u32 csr_tbl[] = {
2472                 CSR_HW_IF_CONFIG_REG,
2473                 CSR_INT_COALESCING,
2474                 CSR_INT,
2475                 CSR_INT_MASK,
2476                 CSR_FH_INT_STATUS,
2477                 CSR_GPIO_IN,
2478                 CSR_RESET,
2479                 CSR_GP_CNTRL,
2480                 CSR_HW_REV,
2481                 CSR_EEPROM_REG,
2482                 CSR_EEPROM_GP,
2483                 CSR_OTP_GP_REG,
2484                 CSR_GIO_REG,
2485                 CSR_GP_UCODE_REG,
2486                 CSR_GP_DRIVER_REG,
2487                 CSR_UCODE_DRV_GP1,
2488                 CSR_UCODE_DRV_GP2,
2489                 CSR_LED_REG,
2490                 CSR_DRAM_INT_TBL_REG,
2491                 CSR_GIO_CHICKEN_BITS,
2492                 CSR_ANA_PLL_CFG,
2493                 CSR_MONITOR_STATUS_REG,
2494                 CSR_HW_REV_WA_REG,
2495                 CSR_DBG_HPET_MEM_REG
2496         };
2497         IWL_ERR(trans, "CSR values:\n");
2498         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2499                 "CSR_INT_PERIODIC_REG)\n");
2500         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2501                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2502                         get_csr_string(csr_tbl[i]),
2503                         iwl_read32(trans, csr_tbl[i]));
2504         }
2505 }
2506
2507 #ifdef CONFIG_IWLWIFI_DEBUGFS
2508 /* create and remove of files */
2509 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2510         debugfs_create_file(#name, mode, parent, trans,                 \
2511                             &iwl_dbgfs_##name##_ops);                   \
2512 } while (0)
2513
2514 /* file operation */
2515 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2516 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2517         .read = iwl_dbgfs_##name##_read,                                \
2518         .open = simple_open,                                            \
2519         .llseek = generic_file_llseek,                                  \
2520 };
2521
2522 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2523 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2524         .write = iwl_dbgfs_##name##_write,                              \
2525         .open = simple_open,                                            \
2526         .llseek = generic_file_llseek,                                  \
2527 };
2528
2529 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2530 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2531         .write = iwl_dbgfs_##name##_write,                              \
2532         .read = iwl_dbgfs_##name##_read,                                \
2533         .open = simple_open,                                            \
2534         .llseek = generic_file_llseek,                                  \
2535 };
2536
2537 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2538                                        char __user *user_buf,
2539                                        size_t count, loff_t *ppos)
2540 {
2541         struct iwl_trans *trans = file->private_data;
2542         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2543         struct iwl_txq *txq;
2544         char *buf;
2545         int pos = 0;
2546         int cnt;
2547         int ret;
2548         size_t bufsz;
2549
2550         bufsz = sizeof(char) * 75 *
2551                 trans->trans_cfg->base_params->num_of_queues;
2552
2553         if (!trans_pcie->txq_memory)
2554                 return -EAGAIN;
2555
2556         buf = kzalloc(bufsz, GFP_KERNEL);
2557         if (!buf)
2558                 return -ENOMEM;
2559
2560         for (cnt = 0;
2561              cnt < trans->trans_cfg->base_params->num_of_queues;
2562              cnt++) {
2563                 txq = trans_pcie->txq[cnt];
2564                 pos += scnprintf(buf + pos, bufsz - pos,
2565                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2566                                 cnt, txq->read_ptr, txq->write_ptr,
2567                                 !!test_bit(cnt, trans_pcie->queue_used),
2568                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2569                                  txq->need_update, txq->frozen,
2570                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2571         }
2572         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2573         kfree(buf);
2574         return ret;
2575 }
2576
2577 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2578                                        char __user *user_buf,
2579                                        size_t count, loff_t *ppos)
2580 {
2581         struct iwl_trans *trans = file->private_data;
2582         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2583         char *buf;
2584         int pos = 0, i, ret;
2585         size_t bufsz = sizeof(buf);
2586
2587         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2588
2589         if (!trans_pcie->rxq)
2590                 return -EAGAIN;
2591
2592         buf = kzalloc(bufsz, GFP_KERNEL);
2593         if (!buf)
2594                 return -ENOMEM;
2595
2596         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2597                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2598
2599                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2600                                  i);
2601                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2602                                  rxq->read);
2603                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2604                                  rxq->write);
2605                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2606                                  rxq->write_actual);
2607                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2608                                  rxq->need_update);
2609                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2610                                  rxq->free_count);
2611                 if (rxq->rb_stts) {
2612                         u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2613                                                                      rxq));
2614                         pos += scnprintf(buf + pos, bufsz - pos,
2615                                          "\tclosed_rb_num: %u\n",
2616                                          r & 0x0FFF);
2617                 } else {
2618                         pos += scnprintf(buf + pos, bufsz - pos,
2619                                          "\tclosed_rb_num: Not Allocated\n");
2620                 }
2621         }
2622         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2623         kfree(buf);
2624
2625         return ret;
2626 }
2627
2628 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2629                                         char __user *user_buf,
2630                                         size_t count, loff_t *ppos)
2631 {
2632         struct iwl_trans *trans = file->private_data;
2633         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2634         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2635
2636         int pos = 0;
2637         char *buf;
2638         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2639         ssize_t ret;
2640
2641         buf = kzalloc(bufsz, GFP_KERNEL);
2642         if (!buf)
2643                 return -ENOMEM;
2644
2645         pos += scnprintf(buf + pos, bufsz - pos,
2646                         "Interrupt Statistics Report:\n");
2647
2648         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2649                 isr_stats->hw);
2650         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2651                 isr_stats->sw);
2652         if (isr_stats->sw || isr_stats->hw) {
2653                 pos += scnprintf(buf + pos, bufsz - pos,
2654                         "\tLast Restarting Code:  0x%X\n",
2655                         isr_stats->err_code);
2656         }
2657 #ifdef CONFIG_IWLWIFI_DEBUG
2658         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2659                 isr_stats->sch);
2660         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2661                 isr_stats->alive);
2662 #endif
2663         pos += scnprintf(buf + pos, bufsz - pos,
2664                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2665
2666         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2667                 isr_stats->ctkill);
2668
2669         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2670                 isr_stats->wakeup);
2671
2672         pos += scnprintf(buf + pos, bufsz - pos,
2673                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2674
2675         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2676                 isr_stats->tx);
2677
2678         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2679                 isr_stats->unhandled);
2680
2681         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2682         kfree(buf);
2683         return ret;
2684 }
2685
2686 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2687                                          const char __user *user_buf,
2688                                          size_t count, loff_t *ppos)
2689 {
2690         struct iwl_trans *trans = file->private_data;
2691         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2692         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2693         u32 reset_flag;
2694         int ret;
2695
2696         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2697         if (ret)
2698                 return ret;
2699         if (reset_flag == 0)
2700                 memset(isr_stats, 0, sizeof(*isr_stats));
2701
2702         return count;
2703 }
2704
2705 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2706                                    const char __user *user_buf,
2707                                    size_t count, loff_t *ppos)
2708 {
2709         struct iwl_trans *trans = file->private_data;
2710
2711         iwl_pcie_dump_csr(trans);
2712
2713         return count;
2714 }
2715
2716 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2717                                      char __user *user_buf,
2718                                      size_t count, loff_t *ppos)
2719 {
2720         struct iwl_trans *trans = file->private_data;
2721         char *buf = NULL;
2722         ssize_t ret;
2723
2724         ret = iwl_dump_fh(trans, &buf);
2725         if (ret < 0)
2726                 return ret;
2727         if (!buf)
2728                 return -EINVAL;
2729         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2730         kfree(buf);
2731         return ret;
2732 }
2733
2734 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2735                                      char __user *user_buf,
2736                                      size_t count, loff_t *ppos)
2737 {
2738         struct iwl_trans *trans = file->private_data;
2739         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2740         char buf[100];
2741         int pos;
2742
2743         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2744                         trans_pcie->debug_rfkill,
2745                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2746                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2747
2748         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2749 }
2750
2751 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2752                                       const char __user *user_buf,
2753                                       size_t count, loff_t *ppos)
2754 {
2755         struct iwl_trans *trans = file->private_data;
2756         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2757         bool new_value;
2758         int ret;
2759
2760         ret = kstrtobool_from_user(user_buf, count, &new_value);
2761         if (ret)
2762                 return ret;
2763         if (new_value == trans_pcie->debug_rfkill)
2764                 return count;
2765         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2766                  trans_pcie->debug_rfkill, new_value);
2767         trans_pcie->debug_rfkill = new_value;
2768         iwl_pcie_handle_rfkill_irq(trans);
2769
2770         return count;
2771 }
2772
2773 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2774                                        struct file *file)
2775 {
2776         struct iwl_trans *trans = inode->i_private;
2777         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2778
2779         if (!trans->dbg.dest_tlv ||
2780             trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2781                 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2782                 return -ENOENT;
2783         }
2784
2785         if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2786                 return -EBUSY;
2787
2788         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2789         return simple_open(inode, file);
2790 }
2791
2792 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2793                                           struct file *file)
2794 {
2795         struct iwl_trans_pcie *trans_pcie =
2796                 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2797
2798         if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2799                 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2800         return 0;
2801 }
2802
2803 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2804                                   void *buf, ssize_t *size,
2805                                   ssize_t *bytes_copied)
2806 {
2807         int buf_size_left = count - *bytes_copied;
2808
2809         buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2810         if (*size > buf_size_left)
2811                 *size = buf_size_left;
2812
2813         *size -= copy_to_user(user_buf, buf, *size);
2814         *bytes_copied += *size;
2815
2816         if (buf_size_left == *size)
2817                 return true;
2818         return false;
2819 }
2820
2821 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2822                                            char __user *user_buf,
2823                                            size_t count, loff_t *ppos)
2824 {
2825         struct iwl_trans *trans = file->private_data;
2826         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2827         void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
2828         struct cont_rec *data = &trans_pcie->fw_mon_data;
2829         u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2830         ssize_t size, bytes_copied = 0;
2831         bool b_full;
2832
2833         if (trans->dbg.dest_tlv) {
2834                 write_ptr_addr =
2835                         le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2836                 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
2837         } else {
2838                 write_ptr_addr = MON_BUFF_WRPTR;
2839                 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2840         }
2841
2842         if (unlikely(!trans->dbg.rec_on))
2843                 return 0;
2844
2845         mutex_lock(&data->mutex);
2846         if (data->state ==
2847             IWL_FW_MON_DBGFS_STATE_DISABLED) {
2848                 mutex_unlock(&data->mutex);
2849                 return 0;
2850         }
2851
2852         /* write_ptr position in bytes rather then DW */
2853         write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2854         wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2855
2856         if (data->prev_wrap_cnt == wrap_cnt) {
2857                 size = write_ptr - data->prev_wr_ptr;
2858                 curr_buf = cpu_addr + data->prev_wr_ptr;
2859                 b_full = iwl_write_to_user_buf(user_buf, count,
2860                                                curr_buf, &size,
2861                                                &bytes_copied);
2862                 data->prev_wr_ptr += size;
2863
2864         } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2865                    write_ptr < data->prev_wr_ptr) {
2866                 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
2867                 curr_buf = cpu_addr + data->prev_wr_ptr;
2868                 b_full = iwl_write_to_user_buf(user_buf, count,
2869                                                curr_buf, &size,
2870                                                &bytes_copied);
2871                 data->prev_wr_ptr += size;
2872
2873                 if (!b_full) {
2874                         size = write_ptr;
2875                         b_full = iwl_write_to_user_buf(user_buf, count,
2876                                                        cpu_addr, &size,
2877                                                        &bytes_copied);
2878                         data->prev_wr_ptr = size;
2879                         data->prev_wrap_cnt++;
2880                 }
2881         } else {
2882                 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2883                     write_ptr > data->prev_wr_ptr)
2884                         IWL_WARN(trans,
2885                                  "write pointer passed previous write pointer, start copying from the beginning\n");
2886                 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2887                                    data->prev_wr_ptr == 0))
2888                         IWL_WARN(trans,
2889                                  "monitor data is out of sync, start copying from the beginning\n");
2890
2891                 size = write_ptr;
2892                 b_full = iwl_write_to_user_buf(user_buf, count,
2893                                                cpu_addr, &size,
2894                                                &bytes_copied);
2895                 data->prev_wr_ptr = size;
2896                 data->prev_wrap_cnt = wrap_cnt;
2897         }
2898
2899         mutex_unlock(&data->mutex);
2900
2901         return bytes_copied;
2902 }
2903
2904 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2905 DEBUGFS_READ_FILE_OPS(fh_reg);
2906 DEBUGFS_READ_FILE_OPS(rx_queue);
2907 DEBUGFS_READ_FILE_OPS(tx_queue);
2908 DEBUGFS_WRITE_FILE_OPS(csr);
2909 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2910
2911 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2912         .read = iwl_dbgfs_monitor_data_read,
2913         .open = iwl_dbgfs_monitor_data_open,
2914         .release = iwl_dbgfs_monitor_data_release,
2915 };
2916
2917 /* Create the debugfs files and directories */
2918 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2919 {
2920         struct dentry *dir = trans->dbgfs_dir;
2921
2922         DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2923         DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2924         DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2925         DEBUGFS_ADD_FILE(csr, dir, 0200);
2926         DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2927         DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2928         DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
2929 }
2930
2931 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2932 {
2933         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2934         struct cont_rec *data = &trans_pcie->fw_mon_data;
2935
2936         mutex_lock(&data->mutex);
2937         data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2938         mutex_unlock(&data->mutex);
2939 }
2940 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2941
2942 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2943 {
2944         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2945         u32 cmdlen = 0;
2946         int i;
2947
2948         for (i = 0; i < trans_pcie->max_tbs; i++)
2949                 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2950
2951         return cmdlen;
2952 }
2953
2954 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2955                                    struct iwl_fw_error_dump_data **data,
2956                                    int allocated_rb_nums)
2957 {
2958         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2959         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2960         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2961         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2962         u32 i, r, j, rb_len = 0;
2963
2964         spin_lock(&rxq->lock);
2965
2966         r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
2967
2968         for (i = rxq->read, j = 0;
2969              i != r && j < allocated_rb_nums;
2970              i = (i + 1) & RX_QUEUE_MASK, j++) {
2971                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2972                 struct iwl_fw_error_dump_rb *rb;
2973
2974                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2975                                DMA_FROM_DEVICE);
2976
2977                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2978
2979                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2980                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2981                 rb = (void *)(*data)->data;
2982                 rb->index = cpu_to_le32(i);
2983                 memcpy(rb->data, page_address(rxb->page), max_len);
2984                 /* remap the page for the free benefit */
2985                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2986                                                      max_len,
2987                                                      DMA_FROM_DEVICE);
2988
2989                 *data = iwl_fw_error_next_data(*data);
2990         }
2991
2992         spin_unlock(&rxq->lock);
2993
2994         return rb_len;
2995 }
2996 #define IWL_CSR_TO_DUMP (0x250)
2997
2998 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2999                                    struct iwl_fw_error_dump_data **data)
3000 {
3001         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3002         __le32 *val;
3003         int i;
3004
3005         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3006         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3007         val = (void *)(*data)->data;
3008
3009         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3010                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3011
3012         *data = iwl_fw_error_next_data(*data);
3013
3014         return csr_len;
3015 }
3016
3017 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3018                                        struct iwl_fw_error_dump_data **data)
3019 {
3020         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3021         unsigned long flags;
3022         __le32 *val;
3023         int i;
3024
3025         if (!iwl_trans_grab_nic_access(trans, &flags))
3026                 return 0;
3027
3028         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3029         (*data)->len = cpu_to_le32(fh_regs_len);
3030         val = (void *)(*data)->data;
3031
3032         if (!trans->trans_cfg->gen2)
3033                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3034                      i += sizeof(u32))
3035                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3036         else
3037                 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3038                      i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3039                      i += sizeof(u32))
3040                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3041                                                                       i));
3042
3043         iwl_trans_release_nic_access(trans, &flags);
3044
3045         *data = iwl_fw_error_next_data(*data);
3046
3047         return sizeof(**data) + fh_regs_len;
3048 }
3049
3050 static u32
3051 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3052                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3053                                  u32 monitor_len)
3054 {
3055         u32 buf_size_in_dwords = (monitor_len >> 2);
3056         u32 *buffer = (u32 *)fw_mon_data->data;
3057         unsigned long flags;
3058         u32 i;
3059
3060         if (!iwl_trans_grab_nic_access(trans, &flags))
3061                 return 0;
3062
3063         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3064         for (i = 0; i < buf_size_in_dwords; i++)
3065                 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3066                                                        MON_DMARB_RD_DATA_ADDR);
3067         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3068
3069         iwl_trans_release_nic_access(trans, &flags);
3070
3071         return monitor_len;
3072 }
3073
3074 static void
3075 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3076                              struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3077 {
3078         u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3079
3080         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3081                 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3082                 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3083                 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3084                 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3085         } else if (trans->dbg.dest_tlv) {
3086                 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3087                 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3088                 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3089         } else {
3090                 base = MON_BUFF_BASE_ADDR;
3091                 write_ptr = MON_BUFF_WRPTR;
3092                 wrap_cnt = MON_BUFF_CYCLE_CNT;
3093         }
3094
3095         write_ptr_val = iwl_read_prph(trans, write_ptr);
3096         fw_mon_data->fw_mon_cycle_cnt =
3097                 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3098         fw_mon_data->fw_mon_base_ptr =
3099                 cpu_to_le32(iwl_read_prph(trans, base));
3100         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3101                 fw_mon_data->fw_mon_base_high_ptr =
3102                         cpu_to_le32(iwl_read_prph(trans, base_high));
3103                 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3104         }
3105         fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3106 }
3107
3108 static u32
3109 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3110                             struct iwl_fw_error_dump_data **data,
3111                             u32 monitor_len)
3112 {
3113         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3114         u32 len = 0;
3115
3116         if (trans->dbg.dest_tlv ||
3117             (fw_mon->size &&
3118              (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3119               trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3120                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3121
3122                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3123                 fw_mon_data = (void *)(*data)->data;
3124
3125                 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3126
3127                 len += sizeof(**data) + sizeof(*fw_mon_data);
3128                 if (fw_mon->size) {
3129                         memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3130                         monitor_len = fw_mon->size;
3131                 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3132                         u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3133                         /*
3134                          * Update pointers to reflect actual values after
3135                          * shifting
3136                          */
3137                         if (trans->dbg.dest_tlv->version) {
3138                                 base = (iwl_read_prph(trans, base) &
3139                                         IWL_LDBG_M2S_BUF_BA_MSK) <<
3140                                        trans->dbg.dest_tlv->base_shift;
3141                                 base *= IWL_M2S_UNIT_SIZE;
3142                                 base += trans->cfg->smem_offset;
3143                         } else {
3144                                 base = iwl_read_prph(trans, base) <<
3145                                        trans->dbg.dest_tlv->base_shift;
3146                         }
3147
3148                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
3149                                            monitor_len / sizeof(u32));
3150                 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3151                         monitor_len =
3152                                 iwl_trans_pci_dump_marbh_monitor(trans,
3153                                                                  fw_mon_data,
3154                                                                  monitor_len);
3155                 } else {
3156                         /* Didn't match anything - output no monitor data */
3157                         monitor_len = 0;
3158                 }
3159
3160                 len += monitor_len;
3161                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3162         }
3163
3164         return len;
3165 }
3166
3167 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3168 {
3169         if (trans->dbg.fw_mon.size) {
3170                 *len += sizeof(struct iwl_fw_error_dump_data) +
3171                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3172                         trans->dbg.fw_mon.size;
3173                 return trans->dbg.fw_mon.size;
3174         } else if (trans->dbg.dest_tlv) {
3175                 u32 base, end, cfg_reg, monitor_len;
3176
3177                 if (trans->dbg.dest_tlv->version == 1) {
3178                         cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3179                         cfg_reg = iwl_read_prph(trans, cfg_reg);
3180                         base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3181                                 trans->dbg.dest_tlv->base_shift;
3182                         base *= IWL_M2S_UNIT_SIZE;
3183                         base += trans->cfg->smem_offset;
3184
3185                         monitor_len =
3186                                 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3187                                 trans->dbg.dest_tlv->end_shift;
3188                         monitor_len *= IWL_M2S_UNIT_SIZE;
3189                 } else {
3190                         base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3191                         end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3192
3193                         base = iwl_read_prph(trans, base) <<
3194                                trans->dbg.dest_tlv->base_shift;
3195                         end = iwl_read_prph(trans, end) <<
3196                               trans->dbg.dest_tlv->end_shift;
3197
3198                         /* Make "end" point to the actual end */
3199                         if (trans->trans_cfg->device_family >=
3200                             IWL_DEVICE_FAMILY_8000 ||
3201                             trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3202                                 end += (1 << trans->dbg.dest_tlv->end_shift);
3203                         monitor_len = end - base;
3204                 }
3205                 *len += sizeof(struct iwl_fw_error_dump_data) +
3206                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3207                         monitor_len;
3208                 return monitor_len;
3209         }
3210         return 0;
3211 }
3212
3213 static struct iwl_trans_dump_data
3214 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3215                           u32 dump_mask)
3216 {
3217         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3218         struct iwl_fw_error_dump_data *data;
3219         struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
3220         struct iwl_fw_error_dump_txcmd *txcmd;
3221         struct iwl_trans_dump_data *dump_data;
3222         u32 len, num_rbs = 0, monitor_len = 0;
3223         int i, ptr;
3224         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3225                         !trans->trans_cfg->mq_rx_supported &&
3226                         dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3227
3228         if (!dump_mask)
3229                 return NULL;
3230
3231         /* transport dump header */
3232         len = sizeof(*dump_data);
3233
3234         /* host commands */
3235         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3236                 len += sizeof(*data) +
3237                         cmdq->n_window * (sizeof(*txcmd) +
3238                                           TFD_MAX_PAYLOAD_SIZE);
3239
3240         /* FW monitor */
3241         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3242                 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3243
3244         /* CSR registers */
3245         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3246                 len += sizeof(*data) + IWL_CSR_TO_DUMP;
3247
3248         /* FH registers */
3249         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3250                 if (trans->trans_cfg->gen2)
3251                         len += sizeof(*data) +
3252                                (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3253                                 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3254                 else
3255                         len += sizeof(*data) +
3256                                (FH_MEM_UPPER_BOUND -
3257                                 FH_MEM_LOWER_BOUND);
3258         }
3259
3260         if (dump_rbs) {
3261                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3262                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3263                 /* RBs */
3264                 num_rbs =
3265                         le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3266                         & 0x0FFF;
3267                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3268                 len += num_rbs * (sizeof(*data) +
3269                                   sizeof(struct iwl_fw_error_dump_rb) +
3270                                   (PAGE_SIZE << trans_pcie->rx_page_order));
3271         }
3272
3273         /* Paged memory for gen2 HW */
3274         if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3275                 for (i = 0; i < trans->init_dram.paging_cnt; i++)
3276                         len += sizeof(*data) +
3277                                sizeof(struct iwl_fw_error_dump_paging) +
3278                                trans->init_dram.paging[i].size;
3279
3280         dump_data = vzalloc(len);
3281         if (!dump_data)
3282                 return NULL;
3283
3284         len = 0;
3285         data = (void *)dump_data->data;
3286
3287         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3288                 u16 tfd_size = trans_pcie->tfd_size;
3289
3290                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3291                 txcmd = (void *)data->data;
3292                 spin_lock_bh(&cmdq->lock);
3293                 ptr = cmdq->write_ptr;
3294                 for (i = 0; i < cmdq->n_window; i++) {
3295                         u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
3296                         u32 caplen, cmdlen;
3297
3298                         cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3299                                                            cmdq->tfds +
3300                                                            tfd_size * ptr);
3301                         caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3302
3303                         if (cmdlen) {
3304                                 len += sizeof(*txcmd) + caplen;
3305                                 txcmd->cmdlen = cpu_to_le32(cmdlen);
3306                                 txcmd->caplen = cpu_to_le32(caplen);
3307                                 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3308                                        caplen);
3309                                 txcmd = (void *)((u8 *)txcmd->data + caplen);
3310                         }
3311
3312                         ptr = iwl_queue_dec_wrap(trans, ptr);
3313                 }
3314                 spin_unlock_bh(&cmdq->lock);
3315
3316                 data->len = cpu_to_le32(len);
3317                 len += sizeof(*data);
3318                 data = iwl_fw_error_next_data(data);
3319         }
3320
3321         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3322                 len += iwl_trans_pcie_dump_csr(trans, &data);
3323         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3324                 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3325         if (dump_rbs)
3326                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3327
3328         /* Paged memory for gen2 HW */
3329         if (trans->trans_cfg->gen2 &&
3330             dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3331                 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3332                         struct iwl_fw_error_dump_paging *paging;
3333                         u32 page_len = trans->init_dram.paging[i].size;
3334
3335                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3336                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
3337                         paging = (void *)data->data;
3338                         paging->index = cpu_to_le32(i);
3339                         memcpy(paging->data,
3340                                trans->init_dram.paging[i].block, page_len);
3341                         data = iwl_fw_error_next_data(data);
3342
3343                         len += sizeof(*data) + sizeof(*paging) + page_len;
3344                 }
3345         }
3346         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3347                 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3348
3349         dump_data->len = len;
3350
3351         return dump_data;
3352 }
3353
3354 #ifdef CONFIG_PM_SLEEP
3355 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3356 {
3357         return 0;
3358 }
3359
3360 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3361 {
3362 }
3363 #endif /* CONFIG_PM_SLEEP */
3364
3365 #define IWL_TRANS_COMMON_OPS                                            \
3366         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3367         .write8 = iwl_trans_pcie_write8,                                \
3368         .write32 = iwl_trans_pcie_write32,                              \
3369         .read32 = iwl_trans_pcie_read32,                                \
3370         .read_prph = iwl_trans_pcie_read_prph,                          \
3371         .write_prph = iwl_trans_pcie_write_prph,                        \
3372         .read_mem = iwl_trans_pcie_read_mem,                            \
3373         .write_mem = iwl_trans_pcie_write_mem,                          \
3374         .configure = iwl_trans_pcie_configure,                          \
3375         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3376         .sw_reset = iwl_trans_pcie_sw_reset,                            \
3377         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3378         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3379         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3380         .dump_data = iwl_trans_pcie_dump_data,                          \
3381         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3382         .d3_resume = iwl_trans_pcie_d3_resume,                          \
3383         .sync_nmi = iwl_trans_pcie_sync_nmi
3384
3385 #ifdef CONFIG_PM_SLEEP
3386 #define IWL_TRANS_PM_OPS                                                \
3387         .suspend = iwl_trans_pcie_suspend,                              \
3388         .resume = iwl_trans_pcie_resume,
3389 #else
3390 #define IWL_TRANS_PM_OPS
3391 #endif /* CONFIG_PM_SLEEP */
3392
3393 static const struct iwl_trans_ops trans_ops_pcie = {
3394         IWL_TRANS_COMMON_OPS,
3395         IWL_TRANS_PM_OPS
3396         .start_hw = iwl_trans_pcie_start_hw,
3397         .fw_alive = iwl_trans_pcie_fw_alive,
3398         .start_fw = iwl_trans_pcie_start_fw,
3399         .stop_device = iwl_trans_pcie_stop_device,
3400
3401         .send_cmd = iwl_trans_pcie_send_hcmd,
3402
3403         .tx = iwl_trans_pcie_tx,
3404         .reclaim = iwl_trans_pcie_reclaim,
3405
3406         .txq_disable = iwl_trans_pcie_txq_disable,
3407         .txq_enable = iwl_trans_pcie_txq_enable,
3408
3409         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3410
3411         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3412
3413         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3414         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3415 #ifdef CONFIG_IWLWIFI_DEBUGFS
3416         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3417 #endif
3418 };
3419
3420 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3421         IWL_TRANS_COMMON_OPS,
3422         IWL_TRANS_PM_OPS
3423         .start_hw = iwl_trans_pcie_start_hw,
3424         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3425         .start_fw = iwl_trans_pcie_gen2_start_fw,
3426         .stop_device = iwl_trans_pcie_gen2_stop_device,
3427
3428         .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3429
3430         .tx = iwl_trans_pcie_gen2_tx,
3431         .reclaim = iwl_trans_pcie_reclaim,
3432
3433         .set_q_ptrs = iwl_trans_pcie_set_q_ptrs,
3434
3435         .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3436         .txq_free = iwl_trans_pcie_dyn_txq_free,
3437         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3438         .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3439 #ifdef CONFIG_IWLWIFI_DEBUGFS
3440         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3441 #endif
3442 };
3443
3444 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3445                                const struct pci_device_id *ent,
3446                                const struct iwl_cfg_trans_params *cfg_trans)
3447 {
3448         struct iwl_trans_pcie *trans_pcie;
3449         struct iwl_trans *trans;
3450         int ret, addr_size;
3451
3452         ret = pcim_enable_device(pdev);
3453         if (ret)
3454                 return ERR_PTR(ret);
3455
3456         if (cfg_trans->gen2)
3457                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3458                                         &pdev->dev, &trans_ops_pcie_gen2);
3459         else
3460                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3461                                         &pdev->dev, &trans_ops_pcie);
3462
3463         if (!trans)
3464                 return ERR_PTR(-ENOMEM);
3465
3466         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3467
3468         trans_pcie->trans = trans;
3469         trans_pcie->opmode_down = true;
3470         spin_lock_init(&trans_pcie->irq_lock);
3471         spin_lock_init(&trans_pcie->reg_lock);
3472         mutex_init(&trans_pcie->mutex);
3473         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3474         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3475         if (!trans_pcie->tso_hdr_page) {
3476                 ret = -ENOMEM;
3477                 goto out_no_pci;
3478         }
3479         trans_pcie->debug_rfkill = -1;
3480
3481         if (!cfg_trans->base_params->pcie_l1_allowed) {
3482                 /*
3483                  * W/A - seems to solve weird behavior. We need to remove this
3484                  * if we don't want to stay in L1 all the time. This wastes a
3485                  * lot of power.
3486                  */
3487                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3488                                        PCIE_LINK_STATE_L1 |
3489                                        PCIE_LINK_STATE_CLKPM);
3490         }
3491
3492         trans_pcie->def_rx_queue = 0;
3493
3494         if (cfg_trans->use_tfh) {
3495                 addr_size = 64;
3496                 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3497                 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3498         } else {
3499                 addr_size = 36;
3500                 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3501                 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3502         }
3503         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3504
3505         pci_set_master(pdev);
3506
3507         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3508         if (!ret)
3509                 ret = pci_set_consistent_dma_mask(pdev,
3510                                                   DMA_BIT_MASK(addr_size));
3511         if (ret) {
3512                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3513                 if (!ret)
3514                         ret = pci_set_consistent_dma_mask(pdev,
3515                                                           DMA_BIT_MASK(32));
3516                 /* both attempts failed: */
3517                 if (ret) {
3518                         dev_err(&pdev->dev, "No suitable DMA available\n");
3519                         goto out_no_pci;
3520                 }
3521         }
3522
3523         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3524         if (ret) {
3525                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3526                 goto out_no_pci;
3527         }
3528
3529         trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3530         if (!trans_pcie->hw_base) {
3531                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3532                 ret = -ENODEV;
3533                 goto out_no_pci;
3534         }
3535
3536         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3537          * PCI Tx retries from interfering with C3 CPU state */
3538         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3539
3540         trans_pcie->pci_dev = pdev;
3541         iwl_disable_interrupts(trans);
3542
3543         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3544         if (trans->hw_rev == 0xffffffff) {
3545                 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3546                 ret = -EIO;
3547                 goto out_no_pci;
3548         }
3549
3550         /*
3551          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3552          * changed, and now the revision step also includes bit 0-1 (no more
3553          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3554          * in the old format.
3555          */
3556         if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) {
3557                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3558                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3559
3560                 ret = iwl_pcie_prepare_card_hw(trans);
3561                 if (ret) {
3562                         IWL_WARN(trans, "Exit HW not ready\n");
3563                         goto out_no_pci;
3564                 }
3565
3566                 /*
3567                  * in-order to recognize C step driver should read chip version
3568                  * id located at the AUX bus MISC address space.
3569                  */
3570                 ret = iwl_finish_nic_init(trans, cfg_trans);
3571                 if (ret)
3572                         goto out_no_pci;
3573
3574         }
3575
3576         IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3577
3578         iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3579         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3580         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3581                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3582
3583         /* Initialize the wait queue for commands */
3584         init_waitqueue_head(&trans_pcie->wait_command_queue);
3585
3586         init_waitqueue_head(&trans_pcie->sx_waitq);
3587
3588         if (trans_pcie->msix_enabled) {
3589                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3590                 if (ret)
3591                         goto out_no_pci;
3592          } else {
3593                 ret = iwl_pcie_alloc_ict(trans);
3594                 if (ret)
3595                         goto out_no_pci;
3596
3597                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3598                                                 iwl_pcie_isr,
3599                                                 iwl_pcie_irq_handler,
3600                                                 IRQF_SHARED, DRV_NAME, trans);
3601                 if (ret) {
3602                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3603                         goto out_free_ict;
3604                 }
3605                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3606          }
3607
3608         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3609                                                    WQ_HIGHPRI | WQ_UNBOUND, 1);
3610         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3611
3612 #ifdef CONFIG_IWLWIFI_DEBUGFS
3613         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3614         mutex_init(&trans_pcie->fw_mon_data.mutex);
3615 #endif
3616
3617         iwl_dbg_tlv_init(trans);
3618
3619         return trans;
3620
3621 out_free_ict:
3622         iwl_pcie_free_ict(trans);
3623 out_no_pci:
3624         free_percpu(trans_pcie->tso_hdr_page);
3625         iwl_trans_free(trans);
3626         return ERR_PTR(ret);
3627 }
3628
3629 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3630 {
3631         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3632         unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
3633         bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
3634         u32 inta_addr, sw_err_bit;
3635
3636         if (trans_pcie->msix_enabled) {
3637                 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3638                 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3639         } else {
3640                 inta_addr = CSR_INT;
3641                 sw_err_bit = CSR_INT_BIT_SW_ERR;
3642         }
3643
3644         /* if the interrupts were already disabled, there is no point in
3645          * calling iwl_disable_interrupts
3646          */
3647         if (interrupts_enabled)
3648                 iwl_disable_interrupts(trans);
3649
3650         iwl_force_nmi(trans);
3651         while (time_after(timeout, jiffies)) {
3652                 u32 inta_hw = iwl_read32(trans, inta_addr);
3653
3654                 /* Error detected by uCode */
3655                 if (inta_hw & sw_err_bit) {
3656                         /* Clear causes register */
3657                         iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
3658                         break;
3659                 }
3660
3661                 mdelay(1);
3662         }
3663
3664         /* enable interrupts only if there were already enabled before this
3665          * function to avoid a case were the driver enable interrupts before
3666          * proper configurations were made
3667          */
3668         if (interrupts_enabled)
3669                 iwl_enable_interrupts(trans);
3670
3671         iwl_trans_fw_error(trans);
3672 }