1 /******************************************************************************
3 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
6 * Portions of this file are derived from the ipw3945 project, as well
7 * as portions of the ieee80211 subsystem header files.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
22 * The full GNU General Public License is included in this distribution in the
23 * file called LICENSE.
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *****************************************************************************/
30 #ifndef __iwl_trans_int_pcie_h__
31 #define __iwl_trans_int_pcie_h__
33 #include <linux/spinlock.h>
34 #include <linux/interrupt.h>
35 #include <linux/skbuff.h>
36 #include <linux/wait.h>
37 #include <linux/pci.h>
38 #include <linux/timer.h>
42 #include "iwl-trans.h"
43 #include "iwl-debug.h"
45 #include "iwl-op-mode.h"
47 /* We need 2 entries for the TX command and header, and another one might
48 * be needed for potential data in the SKB's head. The remaining ones can
51 #define IWL_PCIE_MAX_FRAGS (IWL_NUM_OF_TBS - 3)
54 * RX related structures and functions
56 #define RX_NUM_QUEUES 1
57 #define RX_POST_REQ_ALLOC 2
58 #define RX_CLAIM_REQ_ALLOC 8
59 #define RX_POOL_SIZE ((RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC) * RX_NUM_QUEUES)
60 #define RX_PENDING_WATERMARK 16
64 /*This file includes the declaration that are internal to the
67 struct iwl_rx_mem_buffer {
70 struct list_head list;
74 * struct isr_statistics - interrupt statistics
77 struct isr_statistics {
92 * struct iwl_rxq - Rx queue
93 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
94 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
95 * @read: Shared index to newest available Rx buffer
96 * @write: Shared index to oldest written Rx packet
97 * @free_count: Number of pre-allocated buffers in rx_free
98 * @used_count: Number of RBDs handled to allocator to use for allocation
100 * @rx_free: list of RBDs with allocated RB ready for use
101 * @rx_used: list of RBDs with no RB attached
102 * @need_update: flag to indicate we need to update read/write index
103 * @rb_stts: driver's pointer to receive buffer status
104 * @rb_stts_dma: bus address of receive buffer status
106 * @queue: actual rx queue
108 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
118 struct list_head rx_free;
119 struct list_head rx_used;
121 struct iwl_rb_status *rb_stts;
122 dma_addr_t rb_stts_dma;
124 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
128 * struct iwl_rb_allocator - Rx allocator
129 * @pool: initial pool of allocator
130 * @req_pending: number of requests the allcator had not processed yet
131 * @req_ready: number of requests honored and ready for claiming
132 * @rbd_allocated: RBDs with pages allocated and ready to be handled to
133 * the queue. This is a list of &struct iwl_rx_mem_buffer
134 * @rbd_empty: RBDs with no page attached for allocator use. This is a list
135 * of &struct iwl_rx_mem_buffer
136 * @lock: protects the rbd_allocated and rbd_empty lists
137 * @alloc_wq: work queue for background calls
138 * @rx_alloc: work struct for background calls
140 struct iwl_rb_allocator {
141 struct iwl_rx_mem_buffer pool[RX_POOL_SIZE];
142 atomic_t req_pending;
144 struct list_head rbd_allocated;
145 struct list_head rbd_empty;
147 struct workqueue_struct *alloc_wq;
148 struct work_struct rx_alloc;
158 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
159 * @index -- current index
161 static inline int iwl_queue_inc_wrap(int index)
163 return ++index & (TFD_QUEUE_SIZE_MAX - 1);
167 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
168 * @index -- current index
170 static inline int iwl_queue_dec_wrap(int index)
172 return --index & (TFD_QUEUE_SIZE_MAX - 1);
175 struct iwl_cmd_meta {
176 /* only for SYNC commands, iff the reply skb is wanted */
177 struct iwl_host_cmd *source;
182 * Generic queue structure
184 * Contains common data for Rx and Tx queues.
186 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
187 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
188 * there might be HW changes in the future). For the normal TX
189 * queues, n_window, which is the size of the software queue data
190 * is also 256; however, for the command queue, n_window is only
191 * 32 since we don't need so many commands pending. Since the HW
192 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result,
193 * the software buffers (in the variables @meta, @txb in struct
194 * iwl_txq) only have 32 entries, while the HW buffers (@tfds in
195 * the same struct) have 256.
196 * This means that we end up with the following:
197 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
198 * SW entries: | 0 | ... | 31 |
199 * where N is a number between 0 and 7. This means that the SW
200 * data is a window overlayed over the HW queue.
203 int write_ptr; /* 1-st empty entry (index) host_w*/
204 int read_ptr; /* last used entry (index) host_r*/
205 /* use for monitoring and recovering the stuck queue */
206 dma_addr_t dma_addr; /* physical addr for BD's */
207 int n_window; /* safe queue window */
209 int low_mark; /* low watermark, resume queue if free
210 * space more than this */
211 int high_mark; /* high watermark, stop queue if free
212 * space less than this */
215 #define TFD_TX_CMD_SLOTS 256
216 #define TFD_CMD_SLOTS 32
219 * The FH will write back to the first TB only, so we need
220 * to copy some data into the buffer regardless of whether
221 * it should be mapped or not. This indicates how big the
222 * first TB must be to include the scratch buffer. Since
223 * the scratch is 4 bytes at offset 12, it's 16 now. If we
224 * make it bigger then allocations will be bigger and copy
225 * slower, so that's probably not useful.
227 #define IWL_HCMD_SCRATCHBUF_SIZE 16
229 struct iwl_pcie_txq_entry {
230 struct iwl_device_cmd *cmd;
232 /* buffer to free after command completes */
233 const void *free_buf;
234 struct iwl_cmd_meta meta;
237 struct iwl_pcie_txq_scratch_buf {
238 struct iwl_cmd_header hdr;
244 * struct iwl_txq - Tx Queue for DMA
245 * @q: generic Rx/Tx queue descriptor
246 * @tfds: transmit frame descriptors (DMA memory)
247 * @scratchbufs: start of command headers, including scratch buffers, for
248 * the writeback -- this is DMA memory and an array holding one buffer
249 * for each command on the queue
250 * @scratchbufs_dma: DMA address for the scratchbufs start
251 * @entries: transmit entries (driver state)
253 * @stuck_timer: timer that fires if queue gets stuck
254 * @trans_pcie: pointer back to transport (for timer)
255 * @need_update: indicates need to update read/write index
256 * @active: stores if queue is active
257 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
258 * @wd_timeout: queue watchdog timeout (jiffies) - per queue
259 * @frozen: tx stuck queue timer is frozen
260 * @frozen_expiry_remainder: remember how long until the timer fires
262 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
263 * descriptors) and required locking structures.
267 struct iwl_tfd *tfds;
268 struct iwl_pcie_txq_scratch_buf *scratchbufs;
269 dma_addr_t scratchbufs_dma;
270 struct iwl_pcie_txq_entry *entries;
272 unsigned long frozen_expiry_remainder;
273 struct timer_list stuck_timer;
274 struct iwl_trans_pcie *trans_pcie;
280 unsigned long wd_timeout;
281 struct sk_buff_head overflow_q;
284 static inline dma_addr_t
285 iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
287 return txq->scratchbufs_dma +
288 sizeof(struct iwl_pcie_txq_scratch_buf) * idx;
291 struct iwl_tso_hdr_page {
297 * struct iwl_trans_pcie - PCIe transport specific data
298 * @rxq: all the RX queue data
299 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
300 * @rba: allocator for RX replenishing
301 * @drv - pointer to iwl_drv
302 * @trans: pointer to the generic transport area
303 * @scd_base_addr: scheduler sram base address in SRAM
304 * @scd_bc_tbls: pointer to the byte count table of the scheduler
305 * @kw: keep warm address
306 * @pci_dev: basic pci-network driver stuff
307 * @hw_base: pci hardware address support
308 * @ucode_write_complete: indicates that the ucode has been copied.
309 * @ucode_write_waitq: wait queue for uCode load
310 * @cmd_queue - command queue number
311 * @rx_buf_size: Rx buffer size
312 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
313 * @scd_set_active: should the transport configure the SCD for HCMD queue
314 * @wide_cmd_header: true when ucode supports wide command header format
315 * @sw_csum_tx: if true, then the transport will compute the csum of the TXed
317 * @rx_page_order: page order for receive buffer size
318 * @reg_lock: protect hw register access
319 * @mutex: to protect stop_device / start_fw / start_hw
320 * @cmd_in_flight: true when we have a host command in flight
321 * @fw_mon_phys: physical address of the buffer for the firmware monitor
322 * @fw_mon_page: points to the first page of the buffer for the firmware monitor
323 * @fw_mon_size: size of the buffer for the firmware monitor
325 struct iwl_trans_pcie {
327 struct iwl_rx_mem_buffer rx_pool[RX_QUEUE_SIZE];
328 struct iwl_rb_allocator rba;
329 struct iwl_trans *trans;
332 struct net_device napi_dev;
333 struct napi_struct napi;
335 struct __percpu iwl_tso_hdr_page *tso_hdr_page;
339 dma_addr_t ict_tbl_dma;
343 struct isr_statistics isr_stats;
349 struct iwl_dma_ptr scd_bc_tbls;
350 struct iwl_dma_ptr kw;
353 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
354 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
356 /* PCI bus related data */
357 struct pci_dev *pci_dev;
358 void __iomem *hw_base;
360 bool ucode_write_complete;
361 wait_queue_head_t ucode_write_waitq;
362 wait_queue_head_t wait_command_queue;
366 unsigned int cmd_q_wdg_timeout;
367 u8 n_no_reclaim_cmds;
368 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
370 enum iwl_amsdu_size rx_buf_size;
373 bool wide_cmd_header;
377 /*protect hw register */
379 bool cmd_hold_nic_awake;
380 bool ref_cmd_in_flight;
382 /* protect ref counter */
386 dma_addr_t fw_mon_phys;
387 struct page *fw_mon_page;
391 static inline struct iwl_trans_pcie *
392 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
394 return (void *)trans->trans_specific;
397 static inline struct iwl_trans *
398 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
400 return container_of((void *)trans_pcie, struct iwl_trans,
405 * Convention: trans API functions: iwl_trans_pcie_XXX
406 * Other functions: iwl_pcie_XXX
408 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
409 const struct pci_device_id *ent,
410 const struct iwl_cfg *cfg);
411 void iwl_trans_pcie_free(struct iwl_trans *trans);
413 /*****************************************************
415 ******************************************************/
416 int iwl_pcie_rx_init(struct iwl_trans *trans);
417 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
418 int iwl_pcie_rx_stop(struct iwl_trans *trans);
419 void iwl_pcie_rx_free(struct iwl_trans *trans);
421 /*****************************************************
422 * ICT - interrupt handling
423 ******************************************************/
424 irqreturn_t iwl_pcie_isr(int irq, void *data);
425 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
426 void iwl_pcie_free_ict(struct iwl_trans *trans);
427 void iwl_pcie_reset_ict(struct iwl_trans *trans);
428 void iwl_pcie_disable_ict(struct iwl_trans *trans);
430 /*****************************************************
432 ******************************************************/
433 int iwl_pcie_tx_init(struct iwl_trans *trans);
434 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
435 int iwl_pcie_tx_stop(struct iwl_trans *trans);
436 void iwl_pcie_tx_free(struct iwl_trans *trans);
437 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
438 const struct iwl_trans_txq_scd_cfg *cfg,
439 unsigned int wdg_timeout);
440 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
442 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
443 struct iwl_device_cmd *dev_cmd, int txq_id);
444 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
445 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
446 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
447 struct iwl_rx_cmd_buffer *rxb);
448 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
449 struct sk_buff_head *skbs);
450 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
452 void iwl_trans_pcie_ref(struct iwl_trans *trans);
453 void iwl_trans_pcie_unref(struct iwl_trans *trans);
455 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
457 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
459 return le16_to_cpu(tb->hi_n_len) >> 4;
462 /*****************************************************
464 ******************************************************/
465 void iwl_pcie_dump_csr(struct iwl_trans *trans);
467 /*****************************************************
469 ******************************************************/
470 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
472 clear_bit(STATUS_INT_ENABLED, &trans->status);
474 /* disable interrupts from uCode/NIC to host */
475 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
477 /* acknowledge/clear/reset any interrupts still pending
478 * from uCode or flow handler (Rx/Tx DMA) */
479 iwl_write32(trans, CSR_INT, 0xffffffff);
480 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
481 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
484 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
488 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
489 set_bit(STATUS_INT_ENABLED, &trans->status);
490 trans_pcie->inta_mask = CSR_INI_SET_MASK;
491 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
494 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
496 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
498 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
499 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
500 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
503 static inline void iwl_wake_queue(struct iwl_trans *trans,
506 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
508 if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
509 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
510 iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
514 static inline void iwl_stop_queue(struct iwl_trans *trans,
517 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
519 if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
520 iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
521 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
523 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
527 static inline bool iwl_queue_used(const struct iwl_queue *q, int i)
529 return q->write_ptr >= q->read_ptr ?
530 (i >= q->read_ptr && i < q->write_ptr) :
531 !(i < q->read_ptr && i >= q->write_ptr);
534 static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
536 return index & (q->n_window - 1);
539 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
541 return !(iwl_read32(trans, CSR_GP_CNTRL) &
542 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
545 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
546 u32 reg, u32 mask, u32 value)
550 #ifdef CONFIG_IWLWIFI_DEBUG
551 WARN_ON_ONCE(value & ~mask);
554 v = iwl_read32(trans, reg);
557 iwl_write32(trans, reg, v);
560 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
563 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
566 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
569 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
572 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
574 #ifdef CONFIG_IWLWIFI_DEBUGFS
575 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
577 static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
583 #endif /* __iwl_trans_int_pcie_h__ */