1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2018-2024 Intel Corporation
5 #include <linux/firmware.h>
8 #include "iwl-dbg-tlv.h"
10 #include "fw/runtime.h"
13 * enum iwl_dbg_tlv_type - debug TLV types
14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV
15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV
16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV
17 * @IWL_DBG_TLV_TYPE_REGION: region TLV
18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV
19 * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV
20 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs
22 enum iwl_dbg_tlv_type {
23 IWL_DBG_TLV_TYPE_DEBUG_INFO =
24 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE,
25 IWL_DBG_TLV_TYPE_BUF_ALLOC,
26 IWL_DBG_TLV_TYPE_HCMD,
27 IWL_DBG_TLV_TYPE_REGION,
28 IWL_DBG_TLV_TYPE_TRIGGER,
29 IWL_DBG_TLV_TYPE_CONF_SET,
34 * struct iwl_dbg_tlv_ver_data - debug TLV version struct
35 * @min_ver: min version supported
36 * @max_ver: max version supported
38 struct iwl_dbg_tlv_ver_data {
44 * struct iwl_dbg_tlv_timer_node - timer node struct
45 * @list: list of &struct iwl_dbg_tlv_timer_node
47 * @fwrt: &struct iwl_fw_runtime
48 * @tlv: TLV attach to the timer node
50 struct iwl_dbg_tlv_timer_node {
51 struct list_head list;
52 struct timer_list timer;
53 struct iwl_fw_runtime *fwrt;
54 struct iwl_ucode_tlv *tlv;
57 static const struct iwl_dbg_tlv_ver_data
58 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = {
59 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,},
60 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,},
61 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,},
62 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 3,},
63 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,},
64 [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,},
67 static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv,
68 struct list_head *list)
70 u32 len = le32_to_cpu(tlv->length);
71 struct iwl_dbg_tlv_node *node;
73 node = kzalloc(sizeof(*node) + len, GFP_KERNEL);
77 memcpy(&node->tlv, tlv, sizeof(node->tlv));
78 memcpy(node->tlv.data, tlv->data, len);
79 list_add_tail(&node->list, list);
84 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv)
86 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
87 u32 type = le32_to_cpu(tlv->type);
88 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
89 u32 ver = le32_to_cpu(hdr->version);
91 if (ver < dbg_ver_table[tlv_idx].min_ver ||
92 ver > dbg_ver_table[tlv_idx].max_ver)
98 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
99 const struct iwl_ucode_tlv *tlv)
101 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data;
103 if (le32_to_cpu(tlv->length) != sizeof(*debug_info))
106 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
107 debug_info->debug_cfg_name);
109 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list);
112 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
113 const struct iwl_ucode_tlv *tlv)
115 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data;
119 if (le32_to_cpu(tlv->length) != sizeof(*alloc))
122 buf_location = le32_to_cpu(alloc->buf_location);
123 alloc_id = le32_to_cpu(alloc->alloc_id);
125 if (buf_location == IWL_FW_INI_LOCATION_INVALID ||
126 buf_location >= IWL_FW_INI_LOCATION_NUM)
129 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID ||
130 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
133 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH &&
134 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
137 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH &&
138 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
141 if (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH &&
142 alloc->req_size == 0) {
143 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n");
147 trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
152 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n",
153 alloc_id, buf_location);
157 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
158 const struct iwl_ucode_tlv *tlv)
160 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data;
161 u32 tp = le32_to_cpu(hcmd->time_point);
163 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd))
166 /* Host commands can not be sent in early time point since the FW
169 if (tp == IWL_FW_INI_TIME_POINT_INVALID ||
170 tp >= IWL_FW_INI_TIME_POINT_NUM ||
171 tp == IWL_FW_INI_TIME_POINT_EARLY) {
173 "WRT: Invalid time point %u for host command TLV\n",
178 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list);
181 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
182 const struct iwl_ucode_tlv *tlv)
184 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data;
185 struct iwl_ucode_tlv **active_reg;
186 u32 id = le32_to_cpu(reg->id);
188 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length);
191 * The higher part of the ID from version 2 is debug policy.
192 * The id will be only lsb 16 bits, so mask it out.
194 if (le32_to_cpu(reg->hdr.version) >= 2)
195 id &= IWL_FW_INI_REGION_ID_MASK;
197 if (le32_to_cpu(tlv->length) < sizeof(*reg))
200 /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */
201 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n",
202 IWL_FW_INI_MAX_NAME, reg->name);
204 if (id >= IWL_FW_INI_MAX_REGION_ID) {
205 IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
209 if (type <= IWL_FW_INI_REGION_INVALID ||
210 type >= IWL_FW_INI_REGION_NUM) {
211 IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
215 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG &&
216 !trans->ops->read_config32) {
217 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type);
221 if (type == IWL_FW_INI_REGION_INTERNAL_BUFFER) {
222 trans->dbg.imr_data.sram_addr =
223 le32_to_cpu(reg->internal_buffer.base_addr);
224 trans->dbg.imr_data.sram_size =
225 le32_to_cpu(reg->internal_buffer.size);
229 active_reg = &trans->dbg.active_regions[id];
231 IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
236 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL);
240 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
245 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
246 const struct iwl_ucode_tlv *tlv)
248 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data;
249 struct iwl_fw_ini_trigger_tlv *dup_trig;
250 u32 tp = le32_to_cpu(trig->time_point);
251 u32 rf = le32_to_cpu(trig->reset_fw);
252 struct iwl_ucode_tlv *dup = NULL;
255 if (le32_to_cpu(tlv->length) < sizeof(*trig))
258 if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
259 tp >= IWL_FW_INI_TIME_POINT_NUM) {
261 "WRT: Invalid time point %u for trigger TLV\n",
267 "WRT: time point %u for trigger TLV with reset_fw %u\n",
269 trans->dbg.last_tp_resetfw = 0xFF;
270 if (!le32_to_cpu(trig->occurrences)) {
271 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length),
275 dup_trig = (void *)dup->data;
276 dup_trig->occurrences = cpu_to_le32(-1);
280 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
286 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans,
287 const struct iwl_ucode_tlv *tlv)
289 const struct iwl_fw_ini_conf_set_tlv *conf_set = (const void *)tlv->data;
290 u32 tp = le32_to_cpu(conf_set->time_point);
291 u32 type = le32_to_cpu(conf_set->set_type);
293 if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
294 tp >= IWL_FW_INI_TIME_POINT_NUM) {
296 "WRT: Invalid time point %u for config set TLV\n", tp);
300 if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID ||
301 type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) {
303 "WRT: Invalid config set type %u for config set TLV\n", type);
307 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list);
310 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
311 const struct iwl_ucode_tlv *tlv) = {
312 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info,
313 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc,
314 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd,
315 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region,
316 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger,
317 [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set,
320 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv,
323 enum iwl_ini_cfg_state *cfg_state = ext ?
324 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
325 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
331 if (le32_to_cpu(tlv->length) < sizeof(*hdr))
334 type = le32_to_cpu(tlv->type);
335 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
336 domain = le32_to_cpu(hdr->domain);
338 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON &&
339 !(domain & trans->dbg.domains_bitmap)) {
341 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n",
342 domain, trans->dbg.domains_bitmap);
346 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) {
347 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
351 if (!iwl_dbg_tlv_ver_support(tlv)) {
352 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
353 le32_to_cpu(hdr->version));
357 ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
360 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n",
365 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED)
366 *cfg_state = IWL_INI_CFG_STATE_LOADED;
371 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED;
374 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
376 struct list_head *timer_list = &trans->dbg.periodic_trig_list;
377 struct iwl_dbg_tlv_timer_node *node, *tmp;
379 list_for_each_entry_safe(node, tmp, timer_list, list) {
380 timer_shutdown_sync(&node->timer);
381 list_del(&node->list);
385 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers);
387 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
388 enum iwl_fw_ini_allocation_id alloc_id)
390 struct iwl_fw_mon *fw_mon;
393 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID ||
394 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
397 fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
399 for (i = 0; i < fw_mon->num_frags; i++) {
400 struct iwl_dram_data *frag = &fw_mon->frags[i];
402 dma_free_coherent(trans->dev, frag->size, frag->block,
410 kfree(fw_mon->frags);
411 fw_mon->frags = NULL;
412 fw_mon->num_frags = 0;
415 void iwl_dbg_tlv_free(struct iwl_trans *trans)
417 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp;
420 iwl_dbg_tlv_del_timers(trans);
422 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
423 struct iwl_ucode_tlv **active_reg =
424 &trans->dbg.active_regions[i];
430 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
431 &trans->dbg.debug_info_tlv_list, list) {
432 list_del(&tlv_node->list);
436 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
437 struct iwl_dbg_tlv_time_point_data *tp =
438 &trans->dbg.time_point[i];
440 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list,
442 list_del(&tlv_node->list);
446 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list,
448 list_del(&tlv_node->list);
452 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
453 &tp->active_trig_list, list) {
454 list_del(&tlv_node->list);
458 list_for_each_entry_safe(tlv_node, tlv_node_tmp,
459 &tp->config_list, list) {
460 list_del(&tlv_node->list);
466 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
467 iwl_dbg_tlv_fragments_free(trans, i);
470 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
473 const struct iwl_ucode_tlv *tlv;
476 while (len >= sizeof(*tlv)) {
478 tlv = (const void *)data;
480 tlv_len = le32_to_cpu(tlv->length);
483 IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
487 len -= ALIGN(tlv_len, 4);
488 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
490 iwl_dbg_tlv_alloc(trans, tlv, true);
496 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
498 const struct firmware *fw;
499 const char *yoyo_bin = "iwl-debug-yoyo.bin";
502 if (!iwlwifi_mod_params.enable_ini ||
503 trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000)
506 res = firmware_request_nowarn(&fw, yoyo_bin, dev);
507 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin);
512 trans->dbg.yoyo_bin_loaded = true;
514 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
516 release_firmware(fw);
519 void iwl_dbg_tlv_init(struct iwl_trans *trans)
523 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
524 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
526 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
527 struct iwl_dbg_tlv_time_point_data *tp =
528 &trans->dbg.time_point[i];
530 INIT_LIST_HEAD(&tp->trig_list);
531 INIT_LIST_HEAD(&tp->hcmd_list);
532 INIT_LIST_HEAD(&tp->active_trig_list);
533 INIT_LIST_HEAD(&tp->config_list);
537 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
538 struct iwl_dram_data *frag, u32 pages)
543 if (!frag || frag->size || !pages)
547 * We try to allocate as many pages as we can, starting with
548 * the requested amount and going down until we can allocate
549 * something. Because of DIV_ROUND_UP(), pages will never go
550 * down to 0 and stop the loop, so stop when pages reaches 1,
551 * which is too small anyway.
554 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
556 GFP_KERNEL | __GFP_NOWARN);
560 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
563 pages = DIV_ROUND_UP(pages, 2);
569 frag->physical = physical;
571 frag->size = pages * PAGE_SIZE;
576 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
577 enum iwl_fw_ini_allocation_id alloc_id)
579 struct iwl_fw_mon *fw_mon;
580 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
581 u32 num_frags, remain_pages, frag_pages;
584 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
585 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
588 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
589 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
591 if (fw_mon->num_frags) {
592 for (i = 0; i < fw_mon->num_frags; i++)
593 memset(fw_mon->frags[i].block, 0,
594 fw_mon->frags[i].size);
598 if (fw_mon_cfg->buf_location !=
599 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH))
602 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num);
603 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
604 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
607 } else if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ &&
608 alloc_id > IWL_FW_INI_ALLOCATION_ID_DBGC3) {
612 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size),
614 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS);
615 num_frags = min_t(u32, num_frags, remain_pages);
616 frag_pages = DIV_ROUND_UP(remain_pages, num_frags);
618 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL);
622 for (i = 0; i < num_frags; i++) {
623 int pages = min_t(u32, frag_pages, remain_pages);
626 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n",
627 alloc_id, i, pages * PAGE_SIZE);
629 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
632 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) -
633 (remain_pages * PAGE_SIZE);
635 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) {
636 iwl_dbg_tlv_fragments_free(fwrt->trans,
643 remain_pages -= pages;
650 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
651 enum iwl_fw_ini_allocation_id alloc_id)
653 struct iwl_fw_mon *fw_mon;
654 u32 remain_frags, num_commands;
655 int i, fw_mon_idx = 0;
657 if (!fw_has_capa(&fwrt->fw->ucode_capa,
658 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP))
661 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
662 alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
665 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
666 IWL_FW_INI_LOCATION_DRAM_PATH)
669 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
671 /* the first fragment of DBGC1 is given to the FW via register
674 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
677 remain_frags = fw_mon->num_frags - fw_mon_idx;
681 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
683 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
686 for (i = 0; i < num_commands; i++) {
687 u32 num_frags = min_t(u32, remain_frags,
688 BUF_ALLOC_MAX_NUM_FRAGS);
689 struct iwl_buf_alloc_cmd data = {
690 .alloc_id = cpu_to_le32(alloc_id),
691 .num_frags = cpu_to_le32(num_frags),
693 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH),
695 struct iwl_host_cmd hcmd = {
696 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION),
698 .len[0] = sizeof(data),
699 .flags = CMD_SEND_IN_RFKILL,
703 for (j = 0; j < num_frags; j++) {
704 struct iwl_buf_alloc_frag *frag = &data.frags[j];
705 struct iwl_dram_data *fw_mon_frag =
706 &fw_mon->frags[fw_mon_idx++];
708 frag->addr = cpu_to_le64(fw_mon_frag->physical);
709 frag->size = cpu_to_le32(fw_mon_frag->size);
711 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
715 remain_frags -= num_frags;
721 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
725 if (fw_has_capa(&fwrt->fw->ucode_capa,
726 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT))
729 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
730 ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
733 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n",
738 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt,
739 enum iwl_fw_ini_allocation_id alloc_id,
740 struct iwl_dram_info *dram_info)
742 struct iwl_fw_mon *fw_mon;
743 u32 remain_frags, num_frags;
744 int j, fw_mon_idx = 0;
745 struct iwl_buf_alloc_cmd *data;
747 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
748 IWL_FW_INI_LOCATION_DRAM_PATH) {
749 IWL_DEBUG_FW(fwrt, "WRT: alloc_id %u location is not in DRAM_PATH\n",
754 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
756 /* the first fragment of DBGC1 is given to the FW via register
759 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
762 remain_frags = fw_mon->num_frags - fw_mon_idx;
766 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
767 data = &dram_info->dram_frags[alloc_id - 1];
768 data->alloc_id = cpu_to_le32(alloc_id);
769 data->num_frags = cpu_to_le32(num_frags);
770 data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH);
772 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n",
773 cpu_to_le32(alloc_id), cpu_to_le32(num_frags));
775 for (j = 0; j < num_frags; j++) {
776 struct iwl_buf_alloc_frag *frag = &data->frags[j];
777 struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++];
779 frag->addr = cpu_to_le64(fw_mon_frag->physical);
780 frag->size = cpu_to_le32(fw_mon_frag->size);
781 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n");
782 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n",
783 j, cpu_to_le64(fw_mon_frag->physical),
784 cpu_to_le32(fw_mon_frag->size));
789 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt)
792 bool dram_alloc = false;
793 struct iwl_dram_data *frags =
794 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0];
795 struct iwl_dram_info *dram_info;
797 if (!frags || !frags->block)
800 dram_info = frags->block;
802 if (!fw_has_capa(&fwrt->fw->ucode_capa,
803 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT))
806 memset(dram_info, 0, sizeof(*dram_info));
808 for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1;
809 i < IWL_FW_INI_ALLOCATION_NUM; i++) {
810 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location ==
811 IWL_FW_INI_LOCATION_INVALID)
814 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info);
819 "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n",
824 dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD);
825 dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD);
829 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
830 struct list_head *hcmd_list)
832 struct iwl_dbg_tlv_node *node;
834 list_for_each_entry(node, hcmd_list, list) {
835 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data;
836 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd;
837 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd);
838 struct iwl_host_cmd cmd = {
839 .id = WIDE_ID(hcmd_data->group, hcmd_data->id),
840 .len = { hcmd_len, },
841 .data = { hcmd_data->data, },
844 iwl_trans_send_cmd(fwrt->trans, &cmd);
848 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,
849 struct list_head *conf_list)
851 struct iwl_dbg_tlv_node *node;
853 list_for_each_entry(node, conf_list, list) {
854 struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data;
855 u32 count, address, value;
856 u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8;
857 u32 type = le32_to_cpu(config_list->set_type);
858 u32 offset = le32_to_cpu(config_list->addr_offset);
861 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: {
862 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
863 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n");
864 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n");
867 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len);
868 for (count = 0; count < len; count++) {
869 address = le32_to_cpu(config_list->addr_val[count].address);
870 value = le32_to_cpu(config_list->addr_val[count].value);
871 iwl_trans_write_prph(fwrt->trans, address + offset, value);
873 iwl_trans_release_nic_access(fwrt->trans);
876 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: {
877 for (count = 0; count < len; count++) {
878 address = le32_to_cpu(config_list->addr_val[count].address);
879 value = le32_to_cpu(config_list->addr_val[count].value);
880 iwl_trans_write_mem32(fwrt->trans, address + offset, value);
881 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n",
882 count, address, value);
886 case IWL_FW_INI_CONFIG_SET_TYPE_CSR: {
887 for (count = 0; count < len; count++) {
888 address = le32_to_cpu(config_list->addr_val[count].address);
889 value = le32_to_cpu(config_list->addr_val[count].value);
890 iwl_write32(fwrt->trans, address + offset, value);
891 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n",
892 count, address, value);
896 case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: {
897 struct iwl_dbgc1_info dram_info = {};
898 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0];
899 __le64 dram_base_addr;
907 dram_base_addr = cpu_to_le64(frags->physical);
908 dram_size = cpu_to_le32(frags->size);
909 dram_addr = le64_to_cpu(dram_base_addr);
911 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n",
912 dram_base_addr, dram_size);
913 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n",
914 le32_to_cpu(config_list->addr_offset));
915 for (count = 0; count < len; count++) {
916 address = le32_to_cpu(config_list->addr_val[count].address);
917 dram_info.dbgc1_add_lsb =
918 cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400);
919 dram_info.dbgc1_add_msb =
920 cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32);
921 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400);
922 ret = iwl_trans_write_mem(fwrt->trans,
923 address + offset, &dram_info, 4);
925 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n");
931 case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: {
932 u32 debug_token_config =
933 le32_to_cpu(config_list->addr_val[0].value);
935 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n",
937 fwrt->trans->dbg.ucode_preset = debug_token_config;
946 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t)
948 struct iwl_dbg_tlv_timer_node *timer_node =
949 from_timer(timer_node, t, timer);
950 struct iwl_fwrt_dump_data dump_data = {
951 .trig = (void *)timer_node->tlv->data,
955 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false);
956 if (!ret || ret == -EBUSY) {
957 u32 occur = le32_to_cpu(dump_data.trig->occurrences);
958 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]);
963 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval));
967 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
969 struct iwl_dbg_tlv_node *node;
970 struct list_head *trig_list =
971 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
973 list_for_each_entry(node, trig_list, list) {
974 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data;
975 struct iwl_dbg_tlv_timer_node *timer_node;
976 u32 occur = le32_to_cpu(trig->occurrences), collect_interval;
977 u32 min_interval = 100;
982 /* make sure there is at least one dword of data for the
985 if (le32_to_cpu(node->tlv.length) <
986 sizeof(*trig) + sizeof(__le32)) {
988 "WRT: Invalid periodic trigger data was not given\n");
992 if (le32_to_cpu(trig->data[0]) < min_interval) {
994 "WRT: Override min interval from %u to %u msec\n",
995 le32_to_cpu(trig->data[0]), min_interval);
996 trig->data[0] = cpu_to_le32(min_interval);
999 collect_interval = le32_to_cpu(trig->data[0]);
1001 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL);
1004 "WRT: Failed to allocate periodic trigger\n");
1008 timer_node->fwrt = fwrt;
1009 timer_node->tlv = &node->tlv;
1010 timer_setup(&timer_node->timer,
1011 iwl_dbg_tlv_periodic_trig_handler, 0);
1013 list_add_tail(&timer_node->list,
1014 &fwrt->trans->dbg.periodic_trig_list);
1016 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
1018 mod_timer(&timer_node->timer,
1019 jiffies + msecs_to_jiffies(collect_interval));
1023 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new,
1024 const struct iwl_ucode_tlv *old)
1026 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data;
1027 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data;
1028 const __le32 *new_data = new_trig->data, *old_data = old_trig->data;
1029 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data);
1030 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data);
1033 for (i = 0; i < new_dwords_num; i++) {
1036 for (j = 0; j < old_dwords_num; j++) {
1037 if (new_data[i] == old_data[j]) {
1049 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
1050 struct iwl_ucode_tlv *trig_tlv,
1051 struct iwl_dbg_tlv_node *node)
1053 struct iwl_ucode_tlv *node_tlv = &node->tlv;
1054 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data;
1055 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
1056 u32 policy = le32_to_cpu(trig->apply_policy);
1057 u32 size = le32_to_cpu(trig_tlv->length);
1058 u32 trig_data_len = size - sizeof(*trig);
1061 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) {
1062 u32 data_len = le32_to_cpu(node_tlv->length) -
1066 "WRT: Appending trigger data (time point %u)\n",
1067 le32_to_cpu(trig->time_point));
1073 "WRT: Overriding trigger data (time point %u)\n",
1074 le32_to_cpu(trig->time_point));
1077 if (size != le32_to_cpu(node_tlv->length)) {
1078 struct list_head *prev = node->list.prev;
1079 struct iwl_dbg_tlv_node *tmp;
1081 list_del(&node->list);
1083 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL);
1086 "WRT: No memory to override trigger (time point %u)\n",
1087 le32_to_cpu(trig->time_point));
1089 list_add(&node->list, prev);
1094 list_add(&tmp->list, prev);
1095 node_tlv = &tmp->tlv;
1096 node_trig = (void *)node_tlv->data;
1099 memcpy((u8 *)node_trig->data + offset, trig->data, trig_data_len);
1100 node_tlv->length = cpu_to_le32(size);
1102 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) {
1104 "WRT: Overriding trigger configuration (time point %u)\n",
1105 le32_to_cpu(trig->time_point));
1107 /* the first 11 dwords are configuration related */
1108 memcpy(node_trig, trig, sizeof(__le32) * 11);
1111 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) {
1113 "WRT: Overriding trigger regions (time point %u)\n",
1114 le32_to_cpu(trig->time_point));
1116 node_trig->regions_mask = trig->regions_mask;
1119 "WRT: Appending trigger regions (time point %u)\n",
1120 le32_to_cpu(trig->time_point));
1122 node_trig->regions_mask |= trig->regions_mask;
1129 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
1130 struct list_head *trig_list,
1131 struct iwl_ucode_tlv *trig_tlv)
1133 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
1134 struct iwl_dbg_tlv_node *node, *match = NULL;
1135 u32 policy = le32_to_cpu(trig->apply_policy);
1137 list_for_each_entry(node, trig_list, list) {
1138 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT))
1141 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) ||
1142 is_trig_data_contained(trig_tlv, &node->tlv)) {
1149 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
1150 le32_to_cpu(trig->time_point));
1151 return iwl_dbg_tlv_add(trig_tlv, trig_list);
1154 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
1158 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
1159 struct iwl_dbg_tlv_time_point_data *tp)
1161 struct iwl_dbg_tlv_node *node;
1162 struct list_head *trig_list = &tp->trig_list;
1163 struct list_head *active_trig_list = &tp->active_trig_list;
1165 list_for_each_entry(node, trig_list, list) {
1166 struct iwl_ucode_tlv *tlv = &node->tlv;
1168 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
1172 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
1173 struct iwl_fwrt_dump_data *dump_data,
1174 union iwl_dbg_tlv_tp_data *tp_data,
1177 struct iwl_rx_packet *pkt = tp_data->fw_pkt;
1178 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data;
1180 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd &&
1181 pkt->hdr.group_id == wanted_hdr->group_id)) {
1182 struct iwl_rx_packet *fw_pkt =
1184 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt),
1190 dump_data->fw_pkt = fw_pkt;
1199 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync,
1200 struct list_head *active_trig_list,
1201 union iwl_dbg_tlv_tp_data *tp_data,
1202 bool (*data_check)(struct iwl_fw_runtime *fwrt,
1203 struct iwl_fwrt_dump_data *dump_data,
1204 union iwl_dbg_tlv_tp_data *tp_data,
1207 struct iwl_dbg_tlv_node *node;
1209 list_for_each_entry(node, active_trig_list, list) {
1210 struct iwl_fwrt_dump_data dump_data = {
1211 .trig = (void *)node->tlv.data,
1213 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig,
1216 u32 tp = le32_to_cpu(dump_data.trig->time_point);
1220 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1225 for (i = 0; i < num_data; i++) {
1227 data_check(fwrt, &dump_data, tp_data,
1228 le32_to_cpu(dump_data.trig->data[i]))) {
1229 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1237 fwrt->trans->dbg.restart_required = FALSE;
1238 IWL_DEBUG_FW(fwrt, "WRT: tp %d, reset_fw %d\n",
1239 tp, dump_data.trig->reset_fw);
1241 "WRT: restart_required %d, last_tp_resetfw %d\n",
1242 fwrt->trans->dbg.restart_required,
1243 fwrt->trans->dbg.last_tp_resetfw);
1245 if (fwrt->trans->trans_cfg->device_family ==
1246 IWL_DEVICE_FAMILY_9000) {
1247 fwrt->trans->dbg.restart_required = TRUE;
1248 } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT &&
1249 fwrt->trans->dbg.last_tp_resetfw ==
1250 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) {
1251 fwrt->trans->dbg.restart_required = FALSE;
1252 fwrt->trans->dbg.last_tp_resetfw = 0xFF;
1253 IWL_DEBUG_FW(fwrt, "WRT: FW_ASSERT due to reset_fw_mode-no restart\n");
1254 } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1255 IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) {
1256 IWL_DEBUG_FW(fwrt, "WRT: stop and reload firmware\n");
1257 fwrt->trans->dbg.restart_required = TRUE;
1258 } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1259 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) {
1261 "WRT: stop only and no reload firmware\n");
1262 fwrt->trans->dbg.restart_required = FALSE;
1263 fwrt->trans->dbg.last_tp_resetfw =
1264 le32_to_cpu(dump_data.trig->reset_fw);
1265 } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1266 IWL_FW_INI_RESET_FW_MODE_NOTHING) {
1268 "WRT: nothing need to be done after debug collection\n");
1270 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n",
1271 le32_to_cpu(dump_data.trig->reset_fw));
1277 void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1279 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1281 u32 failed_alloc = 0;
1283 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) {
1285 "WRT: Generating active triggers list, domain 0x%x\n",
1286 fwrt->trans->dbg.domains_bitmap);
1288 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1289 struct iwl_dbg_tlv_time_point_data *tp =
1290 &fwrt->trans->dbg.time_point[i];
1292 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1294 } else if (*ini_dest != IWL_FW_INI_LOCATION_DRAM_PATH) {
1295 /* For DRAM, go through the loop below to clear all the buffers
1296 * properly on restart, otherwise garbage may be left there and
1297 * leak into new debug dumps.
1302 *ini_dest = IWL_FW_INI_LOCATION_INVALID;
1303 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
1304 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
1305 &fwrt->trans->dbg.fw_mon_cfg[i];
1306 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location);
1308 if (dest == IWL_FW_INI_LOCATION_INVALID) {
1309 failed_alloc |= BIT(i);
1313 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID)
1316 if (dest != *ini_dest)
1319 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1323 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n",
1325 failed_alloc |= BIT(i);
1332 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1333 struct iwl_fw_ini_region_tlv *reg;
1334 struct iwl_ucode_tlv **active_reg =
1335 &fwrt->trans->dbg.active_regions[i];
1339 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1343 reg = (void *)(*active_reg)->data;
1344 reg_type = reg->type;
1346 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER ||
1347 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc))
1351 "WRT: removing allocation id %d from region id %d\n",
1352 le32_to_cpu(reg->dram_alloc_id), i);
1354 failed_alloc &= ~BIT(le32_to_cpu(reg->dram_alloc_id));
1355 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1362 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1363 enum iwl_fw_ini_time_point tp_id,
1364 union iwl_dbg_tlv_tp_data *tp_data,
1367 struct list_head *hcmd_list, *trig_list, *conf_list;
1369 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1370 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
1371 tp_id >= IWL_FW_INI_TIME_POINT_NUM)
1374 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1375 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1376 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list;
1379 case IWL_FW_INI_TIME_POINT_EARLY:
1380 iwl_dbg_tlv_init_cfg(fwrt);
1381 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1382 iwl_dbg_tlv_update_drams(fwrt);
1383 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1385 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE:
1386 iwl_dbg_tlv_apply_buffers(fwrt);
1387 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1388 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1389 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1391 case IWL_FW_INI_TIME_POINT_PERIODIC:
1392 iwl_dbg_tlv_set_periodic_trigs(fwrt);
1393 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1395 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF:
1396 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS:
1397 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION:
1398 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1399 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1400 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data,
1401 iwl_dbg_tlv_check_fw_pkt);
1404 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1405 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1406 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1410 IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point);