drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <asm/unaligned.h>
  26
  27 #include <soc.h>
  28 #include <chipcommon.h>
  29 #include <brcmu_utils.h>
  30 #include <brcmu_wifi.h>
  31 #include <brcm_hw_ids.h>
  32
  33 #include "debug.h"
  34 #include "bus.h"
  35 #include "commonring.h"
  36 #include "msgbuf.h"
  37 #include "pcie.h"
  38 #include "firmware.h"
  39 #include "chip.h"
  40
  41
  42 enum brcmf_pcie_state {
  43         BRCMFMAC_PCIE_STATE_DOWN,
  44         BRCMFMAC_PCIE_STATE_UP
  45 };
  46
  47
  48 #define BRCMF_PCIE_43602_FW_NAME                "brcm/brcmfmac43602-pcie.bin"
  49 #define BRCMF_PCIE_43602_NVRAM_NAME             "brcm/brcmfmac43602-pcie.txt"
  50 #define BRCMF_PCIE_4350_FW_NAME                 "brcm/brcmfmac4350-pcie.bin"
  51 #define BRCMF_PCIE_4350_NVRAM_NAME              "brcm/brcmfmac4350-pcie.txt"
  52 #define BRCMF_PCIE_4356_FW_NAME                 "brcm/brcmfmac4356-pcie.bin"
  53 #define BRCMF_PCIE_4356_NVRAM_NAME              "brcm/brcmfmac4356-pcie.txt"
  54 #define BRCMF_PCIE_43570_FW_NAME                "brcm/brcmfmac43570-pcie.bin"
  55 #define BRCMF_PCIE_43570_NVRAM_NAME             "brcm/brcmfmac43570-pcie.txt"
  56 #define BRCMF_PCIE_4358_FW_NAME                 "brcm/brcmfmac4358-pcie.bin"
  57 #define BRCMF_PCIE_4358_NVRAM_NAME              "brcm/brcmfmac4358-pcie.txt"
  58 #define BRCMF_PCIE_4359_FW_NAME                 "brcm/brcmfmac4359-pcie.bin"
  59 #define BRCMF_PCIE_4359_NVRAM_NAME              "brcm/brcmfmac4359-pcie.txt"
  60 #define BRCMF_PCIE_4365_FW_NAME                 "brcm/brcmfmac4365b-pcie.bin"
  61 #define BRCMF_PCIE_4365_NVRAM_NAME              "brcm/brcmfmac4365b-pcie.txt"
  62 #define BRCMF_PCIE_4366_FW_NAME                 "brcm/brcmfmac4366b-pcie.bin"
  63 #define BRCMF_PCIE_4366_NVRAM_NAME              "brcm/brcmfmac4366b-pcie.txt"
  64 #define BRCMF_PCIE_4371_FW_NAME                 "brcm/brcmfmac4371-pcie.bin"
  65 #define BRCMF_PCIE_4371_NVRAM_NAME              "brcm/brcmfmac4371-pcie.txt"
  66
  67 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  68
  69 #define BRCMF_PCIE_TCM_MAP_SIZE                 (4096 * 1024)
  70 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  71
  72 /* backplane addres space accessed by BAR0 */
  73 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  74 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  75 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  76
  77 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  78 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  79
  80 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  81 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  82
  83 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  84 #define BRCMF_PCIE_REG_INTMASK                  0x94
  85 #define BRCMF_PCIE_REG_SBMBX                    0x98
  86
  87 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL         0xBC
  88
  89 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
  90 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
  91 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
  92 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
  93 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
  94 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
  95
  96 #define BRCMF_PCIE_GENREV1                      1
  97 #define BRCMF_PCIE_GENREV2                      2
  98
  99 #define BRCMF_PCIE2_INTA                        0x01
 100 #define BRCMF_PCIE2_INTB                        0x02
 101
 102 #define BRCMF_PCIE_INT_0                        0x01
 103 #define BRCMF_PCIE_INT_1                        0x02
 104 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
 105                                                  BRCMF_PCIE_INT_1)
 106
 107 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
 108 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
 109 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
 110 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
 111 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 112 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 113 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 114 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 115 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 116 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 117
 118 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 119                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 120                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 121                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 122                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 123                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 124                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 125                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 126
 127 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 128 #define BRCMF_PCIE_MAX_SHARED_VERSION           5
 129 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 130 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 131 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 132
 133 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 134 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 135
 136 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 137 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 138 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 139 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 140 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 141 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 142 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 143 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 144 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 145 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 146 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 147
 148 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 149 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 150 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 151 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 152
 153 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 154 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 155 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 156 #define BRCMF_RING_MEM_SZ                       16
 157 #define BRCMF_RING_STATE_SZ                     8
 158
 159 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET  4
 160 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET  8
 161 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET  12
 162 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET  16
 163 #define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET   20
 164 #define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET   28
 165 #define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET   36
 166 #define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET   44
 167 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET     0
 168 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES        52
 169
 170 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 171
 172 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 173 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 174 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 175
 176 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 177 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 178
 179 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 180 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 181 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 182
 183 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 184 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 185 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 186 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 187
 188 #define BRCMF_PCIE_MBDATA_TIMEOUT               2000
 189
 190 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 191 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 192 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 193 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 194 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 195 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 196 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 197 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 198 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 199 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 200 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 201 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 202 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 203
 204
 205 MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
 206 MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
 207 MODULE_FIRMWARE(BRCMF_PCIE_4350_FW_NAME);
 208 MODULE_FIRMWARE(BRCMF_PCIE_4350_NVRAM_NAME);
 209 MODULE_FIRMWARE(BRCMF_PCIE_4356_FW_NAME);
 210 MODULE_FIRMWARE(BRCMF_PCIE_4356_NVRAM_NAME);
 211 MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
 212 MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
 213 MODULE_FIRMWARE(BRCMF_PCIE_4358_FW_NAME);
 214 MODULE_FIRMWARE(BRCMF_PCIE_4358_NVRAM_NAME);
 215 MODULE_FIRMWARE(BRCMF_PCIE_4359_FW_NAME);
 216 MODULE_FIRMWARE(BRCMF_PCIE_4359_NVRAM_NAME);
 217 MODULE_FIRMWARE(BRCMF_PCIE_4365_FW_NAME);
 218 MODULE_FIRMWARE(BRCMF_PCIE_4365_NVRAM_NAME);
 219 MODULE_FIRMWARE(BRCMF_PCIE_4366_FW_NAME);
 220 MODULE_FIRMWARE(BRCMF_PCIE_4366_NVRAM_NAME);
 221 MODULE_FIRMWARE(BRCMF_PCIE_4371_FW_NAME);
 222 MODULE_FIRMWARE(BRCMF_PCIE_4371_NVRAM_NAME);
 223
 224
 225 struct brcmf_pcie_console {
 226         u32 base_addr;
 227         u32 buf_addr;
 228         u32 bufsize;
 229         u32 read_idx;
 230         u8 log_str[256];
 231         u8 log_idx;
 232 };
 233
 234 struct brcmf_pcie_shared_info {
 235         u32 tcm_base_address;
 236         u32 flags;
 237         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 238         struct brcmf_pcie_ringbuf *flowrings;
 239         u16 max_rxbufpost;
 240         u32 nrof_flowrings;
 241         u32 rx_dataoffset;
 242         u32 htod_mb_data_addr;
 243         u32 dtoh_mb_data_addr;
 244         u32 ring_info_addr;
 245         struct brcmf_pcie_console console;
 246         void *scratch;
 247         dma_addr_t scratch_dmahandle;
 248         void *ringupd;
 249         dma_addr_t ringupd_dmahandle;
 250 };
 251
 252 struct brcmf_pcie_core_info {
 253         u32 base;
 254         u32 wrapbase;
 255 };
 256
 257 struct brcmf_pciedev_info {
 258         enum brcmf_pcie_state state;
 259         bool in_irq;
 260         struct pci_dev *pdev;
 261         char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 262         char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 263         void __iomem *regs;
 264         void __iomem *tcm;
 265         u32 tcm_size;
 266         u32 ram_base;
 267         u32 ram_size;
 268         struct brcmf_chip *ci;
 269         u32 coreid;
 270         u32 generic_corerev;
 271         struct brcmf_pcie_shared_info shared;
 272         void (*ringbell)(struct brcmf_pciedev_info *devinfo);
 273         wait_queue_head_t mbdata_resp_wait;
 274         bool mbdata_completed;
 275         bool irq_allocated;
 276         bool wowl_enabled;
 277         u8 dma_idx_sz;
 278         void *idxbuf;
 279         u32 idxbuf_sz;
 280         dma_addr_t idxbuf_dmahandle;
 281         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 282         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 283                           u16 value);
 284 };
 285
 286 struct brcmf_pcie_ringbuf {
 287         struct brcmf_commonring commonring;
 288         dma_addr_t dma_handle;
 289         u32 w_idx_addr;
 290         u32 r_idx_addr;
 291         struct brcmf_pciedev_info *devinfo;
 292         u8 id;
 293 };
 294
 295
 296 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 297         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 298         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 299         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 300         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 301         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 302 };
 303
 304 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 305         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 306         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 307         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 308         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 309         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 310 };
 311
 312
 313 static u32
 314 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 315 {
 316         void __iomem *address = devinfo->regs + reg_offset;
 317
 318         return (ioread32(address));
 319 }
 320
 321
 322 static void
 323 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 324                        u32 value)
 325 {
 326         void __iomem *address = devinfo->regs + reg_offset;
 327
 328         iowrite32(value, address);
 329 }
 330
 331
 332 static u8
 333 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 334 {
 335         void __iomem *address = devinfo->tcm + mem_offset;
 336
 337         return (ioread8(address));
 338 }
 339
 340
 341 static u16
 342 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 343 {
 344         void __iomem *address = devinfo->tcm + mem_offset;
 345
 346         return (ioread16(address));
 347 }
 348
 349
 350 static void
 351 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 352                        u16 value)
 353 {
 354         void __iomem *address = devinfo->tcm + mem_offset;
 355
 356         iowrite16(value, address);
 357 }
 358
 359
 360 static u16
 361 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 362 {
 363         u16 *address = devinfo->idxbuf + mem_offset;
 364
 365         return (*(address));
 366 }
 367
 368
 369 static void
 370 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 371                      u16 value)
 372 {
 373         u16 *address = devinfo->idxbuf + mem_offset;
 374
 375         *(address) = value;
 376 }
 377
 378
 379 static u32
 380 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 381 {
 382         void __iomem *address = devinfo->tcm + mem_offset;
 383
 384         return (ioread32(address));
 385 }
 386
 387
 388 static void
 389 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 390                        u32 value)
 391 {
 392         void __iomem *address = devinfo->tcm + mem_offset;
 393
 394         iowrite32(value, address);
 395 }
 396
 397
 398 static u32
 399 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 400 {
 401         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 402
 403         return (ioread32(addr));
 404 }
 405
 406
 407 static void
 408 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 409                        u32 value)
 410 {
 411         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 412
 413         iowrite32(value, addr);
 414 }
 415
 416
 417 static void
 418 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 419                           void *srcaddr, u32 len)
 420 {
 421         void __iomem *address = devinfo->tcm + mem_offset;
 422         __le32 *src32;
 423         __le16 *src16;
 424         u8 *src8;
 425
 426         if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
 427                 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
 428                         src8 = (u8 *)srcaddr;
 429                         while (len) {
 430                                 iowrite8(*src8, address);
 431                                 address++;
 432                                 src8++;
 433                                 len--;
 434                         }
 435                 } else {
 436                         len = len / 2;
 437                         src16 = (__le16 *)srcaddr;
 438                         while (len) {
 439                                 iowrite16(le16_to_cpu(*src16), address);
 440                                 address += 2;
 441                                 src16++;
 442                                 len--;
 443                         }
 444                 }
 445         } else {
 446                 len = len / 4;
 447                 src32 = (__le32 *)srcaddr;
 448                 while (len) {
 449                         iowrite32(le32_to_cpu(*src32), address);
 450                         address += 4;
 451                         src32++;
 452                         len--;
 453                 }
 454         }
 455 }
 456
 457
 458 static void
 459 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 460                           void *dstaddr, u32 len)
 461 {
 462         void __iomem *address = devinfo->tcm + mem_offset;
 463         __le32 *dst32;
 464         __le16 *dst16;
 465         u8 *dst8;
 466
 467         if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
 468                 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
 469                         dst8 = (u8 *)dstaddr;
 470                         while (len) {
 471                                 *dst8 = ioread8(address);
 472                                 address++;
 473                                 dst8++;
 474                                 len--;
 475                         }
 476                 } else {
 477                         len = len / 2;
 478                         dst16 = (__le16 *)dstaddr;
 479                         while (len) {
 480                                 *dst16 = cpu_to_le16(ioread16(address));
 481                                 address += 2;
 482                                 dst16++;
 483                                 len--;
 484                         }
 485                 }
 486         } else {
 487                 len = len / 4;
 488                 dst32 = (__le32 *)dstaddr;
 489                 while (len) {
 490                         *dst32 = cpu_to_le32(ioread32(address));
 491                         address += 4;
 492                         dst32++;
 493                         len--;
 494                 }
 495         }
 496 }
 497
 498
 499 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 500                 CHIPCREGOFFS(reg), value)
 501
 502
 503 static void
 504 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 505 {
 506         const struct pci_dev *pdev = devinfo->pdev;
 507         struct brcmf_core *core;
 508         u32 bar0_win;
 509
 510         core = brcmf_chip_get_core(devinfo->ci, coreid);
 511         if (core) {
 512                 bar0_win = core->base;
 513                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 514                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 515                                           &bar0_win) == 0) {
 516                         if (bar0_win != core->base) {
 517                                 bar0_win = core->base;
 518                                 pci_write_config_dword(pdev,
 519                                                        BRCMF_PCIE_BAR0_WINDOW,
 520                                                        bar0_win);
 521                         }
 522                 }
 523         } else {
 524                 brcmf_err("Unsupported core selected %x\n", coreid);
 525         }
 526 }
 527
 528
 529 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 530 {
 531         struct brcmf_core *core;
 532         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 533                              BRCMF_PCIE_CFGREG_PM_CSR,
 534                              BRCMF_PCIE_CFGREG_MSI_CAP,
 535                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 536                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 537                              BRCMF_PCIE_CFGREG_MSI_DATA,
 538                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 539                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 540                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 541                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 542                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 543         u32 i;
 544         u32 val;
 545         u32 lsc;
 546
 547         if (!devinfo->ci)
 548                 return;
 549
 550         /* Disable ASPM */
 551         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 552         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 553                               &lsc);
 554         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 555         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 556                                val);
 557
 558         /* Watchdog reset */
 559         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 560         WRITECC32(devinfo, watchdog, 4);
 561         msleep(100);
 562
 563         /* Restore ASPM */
 564         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 565         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 566                                lsc);
 567
 568         core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 569         if (core->rev <= 13) {
 570                 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 571                         brcmf_pcie_write_reg32(devinfo,
 572                                                BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 573                                                cfg_offset[i]);
 574                         val = brcmf_pcie_read_reg32(devinfo,
 575                                 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 576                         brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 577                                   cfg_offset[i], val);
 578                         brcmf_pcie_write_reg32(devinfo,
 579                                                BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 580                                                val);
 581                 }
 582         }
 583 }
 584
 585
 586 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 587 {
 588         u32 config;
 589
 590         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 591         /* BAR1 window may not be sized properly */
 592         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 593         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 594         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 595         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 596
 597         device_wakeup_enable(&devinfo->pdev->dev);
 598 }
 599
 600
 601 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 602 {
 603         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 604                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 605                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 606                                        5);
 607                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 608                                        0);
 609                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 610                                        7);
 611                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 612                                        0);
 613         }
 614         return 0;
 615 }
 616
 617
 618 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 619                                           u32 resetintr)
 620 {
 621         struct brcmf_core *core;
 622
 623         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 624                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 625                 brcmf_chip_resetcore(core, 0, 0, 0);
 626         }
 627
 628         return !brcmf_chip_set_active(devinfo->ci, resetintr);
 629 }
 630
 631
 632 static int
 633 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 634 {
 635         struct brcmf_pcie_shared_info *shared;
 636         u32 addr;
 637         u32 cur_htod_mb_data;
 638         u32 i;
 639
 640         shared = &devinfo->shared;
 641         addr = shared->htod_mb_data_addr;
 642         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 643
 644         if (cur_htod_mb_data != 0)
 645                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 646                           cur_htod_mb_data);
 647
 648         i = 0;
 649         while (cur_htod_mb_data != 0) {
 650                 msleep(10);
 651                 i++;
 652                 if (i > 100)
 653                         return -EIO;
 654                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 655         }
 656
 657         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 658         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 659         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 660
 661         return 0;
 662 }
 663
 664
 665 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 666 {
 667         struct brcmf_pcie_shared_info *shared;
 668         u32 addr;
 669         u32 dtoh_mb_data;
 670
 671         shared = &devinfo->shared;
 672         addr = shared->dtoh_mb_data_addr;
 673         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 674
 675         if (!dtoh_mb_data)
 676                 return;
 677
 678         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 679
 680         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 681         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 682                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 683                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 684                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 685         }
 686         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 687                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 688         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 689                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 690                 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
 691                         devinfo->mbdata_completed = true;
 692                         wake_up(&devinfo->mbdata_resp_wait);
 693                 }
 694         }
 695 }
 696
 697
 698 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 699 {
 700         struct brcmf_pcie_shared_info *shared;
 701         struct brcmf_pcie_console *console;
 702         u32 addr;
 703
 704         shared = &devinfo->shared;
 705         console = &shared->console;
 706         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 707         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 708
 709         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 710         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 711         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 712         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 713
 714         brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 715                   console->base_addr, console->buf_addr, console->bufsize);
 716 }
 717
 718
 719 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 720 {
 721         struct brcmf_pcie_console *console;
 722         u32 addr;
 723         u8 ch;
 724         u32 newidx;
 725
 726         if (!BRCMF_FWCON_ON())
 727                 return;
 728
 729         console = &devinfo->shared.console;
 730         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 731         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 732         while (newidx != console->read_idx) {
 733                 addr = console->buf_addr + console->read_idx;
 734                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 735                 console->read_idx++;
 736                 if (console->read_idx == console->bufsize)
 737                         console->read_idx = 0;
 738                 if (ch == '\r')
 739                         continue;
 740                 console->log_str[console->log_idx] = ch;
 741                 console->log_idx++;
 742                 if ((ch != '\n') &&
 743                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 744                         ch = '\n';
 745                         console->log_str[console->log_idx] = ch;
 746                         console->log_idx++;
 747                 }
 748                 if (ch == '\n') {
 749                         console->log_str[console->log_idx] = 0;
 750                         pr_debug("CONSOLE: %s", console->log_str);
 751                         console->log_idx = 0;
 752                 }
 753         }
 754 }
 755
 756
 757 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
 758 {
 759         u32 reg_value;
 760
 761         brcmf_dbg(PCIE, "RING !\n");
 762         reg_value = brcmf_pcie_read_reg32(devinfo,
 763                                           BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 764         reg_value |= BRCMF_PCIE2_INTB;
 765         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 766                                reg_value);
 767 }
 768
 769
 770 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
 771 {
 772         brcmf_dbg(PCIE, "RING !\n");
 773         /* Any arbitrary value will do, lets use 1 */
 774         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 775 }
 776
 777
 778 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 779 {
 780         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 781                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 782                                        0);
 783         else
 784                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 785                                        0);
 786 }
 787
 788
 789 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 790 {
 791         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 792                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 793                                        BRCMF_PCIE_INT_DEF);
 794         else
 795                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 796                                        BRCMF_PCIE_MB_INT_D2H_DB |
 797                                        BRCMF_PCIE_MB_INT_FN0_0 |
 798                                        BRCMF_PCIE_MB_INT_FN0_1);
 799 }
 800
 801
 802 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
 803 {
 804         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 805         u32 status;
 806
 807         status = 0;
 808         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 809         if (status) {
 810                 brcmf_pcie_intr_disable(devinfo);
 811                 brcmf_dbg(PCIE, "Enter\n");
 812                 return IRQ_WAKE_THREAD;
 813         }
 814         return IRQ_NONE;
 815 }
 816
 817
 818 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
 819 {
 820         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 821
 822         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 823                 brcmf_pcie_intr_disable(devinfo);
 824                 brcmf_dbg(PCIE, "Enter\n");
 825                 return IRQ_WAKE_THREAD;
 826         }
 827         return IRQ_NONE;
 828 }
 829
 830
 831 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
 832 {
 833         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 834         const struct pci_dev *pdev = devinfo->pdev;
 835         u32 status;
 836
 837         devinfo->in_irq = true;
 838         status = 0;
 839         pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 840         brcmf_dbg(PCIE, "Enter %x\n", status);
 841         if (status) {
 842                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 843                 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 844                         brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
 845         }
 846         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 847                 brcmf_pcie_intr_enable(devinfo);
 848         devinfo->in_irq = false;
 849         return IRQ_HANDLED;
 850 }
 851
 852
 853 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
 854 {
 855         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 856         u32 status;
 857
 858         devinfo->in_irq = true;
 859         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 860         brcmf_dbg(PCIE, "Enter %x\n", status);
 861         if (status) {
 862                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 863                                        status);
 864                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 865                               BRCMF_PCIE_MB_INT_FN0_1))
 866                         brcmf_pcie_handle_mb_data(devinfo);
 867                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 868                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 869                                 brcmf_proto_msgbuf_rx_trigger(
 870                                                         &devinfo->pdev->dev);
 871                 }
 872         }
 873         brcmf_pcie_bus_console_read(devinfo);
 874         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 875                 brcmf_pcie_intr_enable(devinfo);
 876         devinfo->in_irq = false;
 877         return IRQ_HANDLED;
 878 }
 879
 880
 881 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 882 {
 883         struct pci_dev *pdev;
 884
 885         pdev = devinfo->pdev;
 886
 887         brcmf_pcie_intr_disable(devinfo);
 888
 889         brcmf_dbg(PCIE, "Enter\n");
 890         /* is it a v1 or v2 implementation */
 891         pci_enable_msi(pdev);
 892         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 893                 if (request_threaded_irq(pdev->irq,
 894                                          brcmf_pcie_quick_check_isr_v1,
 895                                          brcmf_pcie_isr_thread_v1,
 896                                          IRQF_SHARED, "brcmf_pcie_intr",
 897                                          devinfo)) {
 898                         pci_disable_msi(pdev);
 899                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 900                         return -EIO;
 901                 }
 902         } else {
 903                 if (request_threaded_irq(pdev->irq,
 904                                          brcmf_pcie_quick_check_isr_v2,
 905                                          brcmf_pcie_isr_thread_v2,
 906                                          IRQF_SHARED, "brcmf_pcie_intr",
 907                                          devinfo)) {
 908                         pci_disable_msi(pdev);
 909                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 910                         return -EIO;
 911                 }
 912         }
 913         devinfo->irq_allocated = true;
 914         return 0;
 915 }
 916
 917
 918 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 919 {
 920         struct pci_dev *pdev;
 921         u32 status;
 922         u32 count;
 923
 924         if (!devinfo->irq_allocated)
 925                 return;
 926
 927         pdev = devinfo->pdev;
 928
 929         brcmf_pcie_intr_disable(devinfo);
 930         free_irq(pdev->irq, devinfo);
 931         pci_disable_msi(pdev);
 932
 933         msleep(50);
 934         count = 0;
 935         while ((devinfo->in_irq) && (count < 20)) {
 936                 msleep(50);
 937                 count++;
 938         }
 939         if (devinfo->in_irq)
 940                 brcmf_err("Still in IRQ (processing) !!!\n");
 941
 942         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 943                 status = 0;
 944                 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 945                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 946         } else {
 947                 status = brcmf_pcie_read_reg32(devinfo,
 948                                                BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 949                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 950                                        status);
 951         }
 952         devinfo->irq_allocated = false;
 953 }
 954
 955
 956 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 957 {
 958         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 959         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 960         struct brcmf_commonring *commonring = &ring->commonring;
 961
 962         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 963                 return -EIO;
 964
 965         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 966                   commonring->w_ptr, ring->id);
 967
 968         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 969
 970         return 0;
 971 }
 972
 973
 974 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 975 {
 976         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 977         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 978         struct brcmf_commonring *commonring = &ring->commonring;
 979
 980         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 981                 return -EIO;
 982
 983         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 984                   commonring->r_ptr, ring->id);
 985
 986         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 987
 988         return 0;
 989 }
 990
 991
 992 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 993 {
 994         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 995         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 996
 997         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 998                 return -EIO;
 999
1000         devinfo->ringbell(devinfo);
1001
1002         return 0;
1003 }
1004
1005
1006 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
1007 {
1008         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1009         struct brcmf_pciedev_info *devinfo = ring->devinfo;
1010         struct brcmf_commonring *commonring = &ring->commonring;
1011
1012         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1013                 return -EIO;
1014
1015         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
1016
1017         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1018                   commonring->w_ptr, ring->id);
1019
1020         return 0;
1021 }
1022
1023
1024 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
1025 {
1026         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1027         struct brcmf_pciedev_info *devinfo = ring->devinfo;
1028         struct brcmf_commonring *commonring = &ring->commonring;
1029
1030         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1031                 return -EIO;
1032
1033         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
1034
1035         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1036                   commonring->r_ptr, ring->id);
1037
1038         return 0;
1039 }
1040
1041
1042 static void *
1043 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1044                                      u32 size, u32 tcm_dma_phys_addr,
1045                                      dma_addr_t *dma_handle)
1046 {
1047         void *ring;
1048         u64 address;
1049
1050         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1051                                   GFP_KERNEL);
1052         if (!ring)
1053                 return NULL;
1054
1055         address = (u64)*dma_handle;
1056         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1057                                address & 0xffffffff);
1058         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1059
1060         memset(ring, 0, size);
1061
1062         return (ring);
1063 }
1064
1065
1066 static struct brcmf_pcie_ringbuf *
1067 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1068                               u32 tcm_ring_phys_addr)
1069 {
1070         void *dma_buf;
1071         dma_addr_t dma_handle;
1072         struct brcmf_pcie_ringbuf *ring;
1073         u32 size;
1074         u32 addr;
1075
1076         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
1077         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1078                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1079                         &dma_handle);
1080         if (!dma_buf)
1081                 return NULL;
1082
1083         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1084         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1085         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1086         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
1087
1088         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1089         if (!ring) {
1090                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1091                                   dma_handle);
1092                 return NULL;
1093         }
1094         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1095                                 brcmf_ring_itemsize[ring_id], dma_buf);
1096         ring->dma_handle = dma_handle;
1097         ring->devinfo = devinfo;
1098         brcmf_commonring_register_cb(&ring->commonring,
1099                                      brcmf_pcie_ring_mb_ring_bell,
1100                                      brcmf_pcie_ring_mb_update_rptr,
1101                                      brcmf_pcie_ring_mb_update_wptr,
1102                                      brcmf_pcie_ring_mb_write_rptr,
1103                                      brcmf_pcie_ring_mb_write_wptr, ring);
1104
1105         return (ring);
1106 }
1107
1108
1109 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1110                                           struct brcmf_pcie_ringbuf *ring)
1111 {
1112         void *dma_buf;
1113         u32 size;
1114
1115         if (!ring)
1116                 return;
1117
1118         dma_buf = ring->commonring.buf_addr;
1119         if (dma_buf) {
1120                 size = ring->commonring.depth * ring->commonring.item_len;
1121                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1122         }
1123         kfree(ring);
1124 }
1125
1126
1127 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1128 {
1129         u32 i;
1130
1131         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1132                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1133                                               devinfo->shared.commonrings[i]);
1134                 devinfo->shared.commonrings[i] = NULL;
1135         }
1136         kfree(devinfo->shared.flowrings);
1137         devinfo->shared.flowrings = NULL;
1138         if (devinfo->idxbuf) {
1139                 dma_free_coherent(&devinfo->pdev->dev,
1140                                   devinfo->idxbuf_sz,
1141                                   devinfo->idxbuf,
1142                                   devinfo->idxbuf_dmahandle);
1143                 devinfo->idxbuf = NULL;
1144         }
1145 }
1146
1147
1148 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1149 {
1150         struct brcmf_pcie_ringbuf *ring;
1151         struct brcmf_pcie_ringbuf *rings;
1152         u32 ring_addr;
1153         u32 d2h_w_idx_ptr;
1154         u32 d2h_r_idx_ptr;
1155         u32 h2d_w_idx_ptr;
1156         u32 h2d_r_idx_ptr;
1157         u32 addr;
1158         u32 ring_mem_ptr;
1159         u32 i;
1160         u64 address;
1161         u32 bufsz;
1162         u16 max_sub_queues;
1163         u8 idx_offset;
1164
1165         ring_addr = devinfo->shared.ring_info_addr;
1166         brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1167         addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1168         max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1169
1170         if (devinfo->dma_idx_sz != 0) {
1171                 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
1172                         devinfo->dma_idx_sz * 2;
1173                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1174                                                      &devinfo->idxbuf_dmahandle,
1175                                                      GFP_KERNEL);
1176                 if (!devinfo->idxbuf)
1177                         devinfo->dma_idx_sz = 0;
1178         }
1179
1180         if (devinfo->dma_idx_sz == 0) {
1181                 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1182                 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1183                 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1184                 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1185                 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1186                 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1187                 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1188                 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1189                 idx_offset = sizeof(u32);
1190                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1191                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1192                 brcmf_dbg(PCIE, "Using TCM indices\n");
1193         } else {
1194                 memset(devinfo->idxbuf, 0, bufsz);
1195                 devinfo->idxbuf_sz = bufsz;
1196                 idx_offset = devinfo->dma_idx_sz;
1197                 devinfo->write_ptr = brcmf_pcie_write_idx;
1198                 devinfo->read_ptr = brcmf_pcie_read_idx;
1199
1200                 h2d_w_idx_ptr = 0;
1201                 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
1202                 address = (u64)devinfo->idxbuf_dmahandle;
1203                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1204                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1205
1206                 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
1207                 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
1208                 address += max_sub_queues * idx_offset;
1209                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1210                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1211
1212                 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
1213                 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
1214                 address += max_sub_queues * idx_offset;
1215                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1216                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1217
1218                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1219                                 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1220                 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
1221                 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1222                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1223                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1224                 brcmf_dbg(PCIE, "Using host memory indices\n");
1225         }
1226
1227         addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1228         ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1229
1230         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1231                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1232                 if (!ring)
1233                         goto fail;
1234                 ring->w_idx_addr = h2d_w_idx_ptr;
1235                 ring->r_idx_addr = h2d_r_idx_ptr;
1236                 ring->id = i;
1237                 devinfo->shared.commonrings[i] = ring;
1238
1239                 h2d_w_idx_ptr += idx_offset;
1240                 h2d_r_idx_ptr += idx_offset;
1241                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1242         }
1243
1244         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1245              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1246                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1247                 if (!ring)
1248                         goto fail;
1249                 ring->w_idx_addr = d2h_w_idx_ptr;
1250                 ring->r_idx_addr = d2h_r_idx_ptr;
1251                 ring->id = i;
1252                 devinfo->shared.commonrings[i] = ring;
1253
1254                 d2h_w_idx_ptr += idx_offset;
1255                 d2h_r_idx_ptr += idx_offset;
1256                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1257         }
1258
1259         devinfo->shared.nrof_flowrings =
1260                         max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1261         rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1262                         GFP_KERNEL);
1263         if (!rings)
1264                 goto fail;
1265
1266         brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1267                   devinfo->shared.nrof_flowrings);
1268
1269         for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1270                 ring = &rings[i];
1271                 ring->devinfo = devinfo;
1272                 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1273                 brcmf_commonring_register_cb(&ring->commonring,
1274                                              brcmf_pcie_ring_mb_ring_bell,
1275                                              brcmf_pcie_ring_mb_update_rptr,
1276                                              brcmf_pcie_ring_mb_update_wptr,
1277                                              brcmf_pcie_ring_mb_write_rptr,
1278                                              brcmf_pcie_ring_mb_write_wptr,
1279                                              ring);
1280                 ring->w_idx_addr = h2d_w_idx_ptr;
1281                 ring->r_idx_addr = h2d_r_idx_ptr;
1282                 h2d_w_idx_ptr += idx_offset;
1283                 h2d_r_idx_ptr += idx_offset;
1284         }
1285         devinfo->shared.flowrings = rings;
1286
1287         return 0;
1288
1289 fail:
1290         brcmf_err("Allocating ring buffers failed\n");
1291         brcmf_pcie_release_ringbuffers(devinfo);
1292         return -ENOMEM;
1293 }
1294
1295
1296 static void
1297 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1298 {
1299         if (devinfo->shared.scratch)
1300                 dma_free_coherent(&devinfo->pdev->dev,
1301                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1302                                   devinfo->shared.scratch,
1303                                   devinfo->shared.scratch_dmahandle);
1304         if (devinfo->shared.ringupd)
1305                 dma_free_coherent(&devinfo->pdev->dev,
1306                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1307                                   devinfo->shared.ringupd,
1308                                   devinfo->shared.ringupd_dmahandle);
1309 }
1310
1311 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1312 {
1313         u64 address;
1314         u32 addr;
1315
1316         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1317                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1318                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1319         if (!devinfo->shared.scratch)
1320                 goto fail;
1321
1322         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1323
1324         addr = devinfo->shared.tcm_base_address +
1325                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1326         address = (u64)devinfo->shared.scratch_dmahandle;
1327         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1328         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1329         addr = devinfo->shared.tcm_base_address +
1330                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1331         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1332
1333         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1334                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1335                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1336         if (!devinfo->shared.ringupd)
1337                 goto fail;
1338
1339         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1340
1341         addr = devinfo->shared.tcm_base_address +
1342                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1343         address = (u64)devinfo->shared.ringupd_dmahandle;
1344         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1345         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1346         addr = devinfo->shared.tcm_base_address +
1347                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1348         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1349         return 0;
1350
1351 fail:
1352         brcmf_err("Allocating scratch buffers failed\n");
1353         brcmf_pcie_release_scratchbuffers(devinfo);
1354         return -ENOMEM;
1355 }
1356
1357
1358 static void brcmf_pcie_down(struct device *dev)
1359 {
1360 }
1361
1362
1363 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1364 {
1365         return 0;
1366 }
1367
1368
1369 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1370                                 uint len)
1371 {
1372         return 0;
1373 }
1374
1375
1376 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1377                                 uint len)
1378 {
1379         return 0;
1380 }
1381
1382
1383 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1384 {
1385         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1386         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1387         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1388
1389         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1390         devinfo->wowl_enabled = enabled;
1391         if (enabled)
1392                 device_set_wakeup_enable(&devinfo->pdev->dev, true);
1393         else
1394                 device_set_wakeup_enable(&devinfo->pdev->dev, false);
1395 }
1396
1397
1398 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1399 {
1400         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1401         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1402         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1403
1404         return devinfo->ci->ramsize - devinfo->ci->srsize;
1405 }
1406
1407
1408 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1409 {
1410         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1411         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1412         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1413
1414         brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1415         brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1416         return 0;
1417 }
1418
1419
1420 static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1421         .txdata = brcmf_pcie_tx,
1422         .stop = brcmf_pcie_down,
1423         .txctl = brcmf_pcie_tx_ctlpkt,
1424         .rxctl = brcmf_pcie_rx_ctlpkt,
1425         .wowl_config = brcmf_pcie_wowl_config,
1426         .get_ramsize = brcmf_pcie_get_ramsize,
1427         .get_memdump = brcmf_pcie_get_memdump,
1428 };
1429
1430
1431 static int
1432 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1433                                u32 sharedram_addr)
1434 {
1435         struct brcmf_pcie_shared_info *shared;
1436         u32 addr;
1437         u32 version;
1438
1439         shared = &devinfo->shared;
1440         shared->tcm_base_address = sharedram_addr;
1441
1442         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1443         version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1444         brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1445         if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1446             (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1447                 brcmf_err("Unsupported PCIE version %d\n", version);
1448                 return -EINVAL;
1449         }
1450
1451         /* check firmware support dma indicies */
1452         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1453                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1454                         devinfo->dma_idx_sz = sizeof(u16);
1455                 else
1456                         devinfo->dma_idx_sz = sizeof(u32);
1457         }
1458
1459         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1460         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1461         if (shared->max_rxbufpost == 0)
1462                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1463
1464         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1465         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1466
1467         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1468         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1469
1470         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1471         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1472
1473         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1474         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1475
1476         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1477                   shared->max_rxbufpost, shared->rx_dataoffset);
1478
1479         brcmf_pcie_bus_console_init(devinfo);
1480
1481         return 0;
1482 }
1483
1484
1485 static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1486 {
1487         char *fw_name;
1488         char *nvram_name;
1489         uint fw_len, nv_len;
1490         char end;
1491
1492         brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1493                   devinfo->ci->chiprev);
1494
1495         switch (devinfo->ci->chip) {
1496         case BRCM_CC_43602_CHIP_ID:
1497                 fw_name = BRCMF_PCIE_43602_FW_NAME;
1498                 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1499                 break;
1500         case BRCM_CC_4350_CHIP_ID:
1501                 fw_name = BRCMF_PCIE_4350_FW_NAME;
1502                 nvram_name = BRCMF_PCIE_4350_NVRAM_NAME;
1503                 break;
1504         case BRCM_CC_4356_CHIP_ID:
1505                 fw_name = BRCMF_PCIE_4356_FW_NAME;
1506                 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1507                 break;
1508         case BRCM_CC_43567_CHIP_ID:
1509         case BRCM_CC_43569_CHIP_ID:
1510         case BRCM_CC_43570_CHIP_ID:
1511                 fw_name = BRCMF_PCIE_43570_FW_NAME;
1512                 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1513                 break;
1514         case BRCM_CC_4358_CHIP_ID:
1515                 fw_name = BRCMF_PCIE_4358_FW_NAME;
1516                 nvram_name = BRCMF_PCIE_4358_NVRAM_NAME;
1517                 break;
1518         case BRCM_CC_4359_CHIP_ID:
1519                 fw_name = BRCMF_PCIE_4359_FW_NAME;
1520                 nvram_name = BRCMF_PCIE_4359_NVRAM_NAME;
1521                 break;
1522         case BRCM_CC_4365_CHIP_ID:
1523                 fw_name = BRCMF_PCIE_4365_FW_NAME;
1524                 nvram_name = BRCMF_PCIE_4365_NVRAM_NAME;
1525                 break;
1526         case BRCM_CC_4366_CHIP_ID:
1527                 fw_name = BRCMF_PCIE_4366_FW_NAME;
1528                 nvram_name = BRCMF_PCIE_4366_NVRAM_NAME;
1529                 break;
1530         case BRCM_CC_4371_CHIP_ID:
1531                 fw_name = BRCMF_PCIE_4371_FW_NAME;
1532                 nvram_name = BRCMF_PCIE_4371_NVRAM_NAME;
1533                 break;
1534         default:
1535                 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1536                 return -ENODEV;
1537         }
1538
1539         fw_len = sizeof(devinfo->fw_name) - 1;
1540         nv_len = sizeof(devinfo->nvram_name) - 1;
1541         /* check if firmware path is provided by module parameter */
1542         if (brcmf_firmware_path[0] != '\0') {
1543                 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1544                 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1545                 fw_len -= strlen(devinfo->fw_name);
1546                 nv_len -= strlen(devinfo->nvram_name);
1547
1548                 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1549                 if (end != '/') {
1550                         strncat(devinfo->fw_name, "/", fw_len);
1551                         strncat(devinfo->nvram_name, "/", nv_len);
1552                         fw_len--;
1553                         nv_len--;
1554                 }
1555         }
1556         strncat(devinfo->fw_name, fw_name, fw_len);
1557         strncat(devinfo->nvram_name, nvram_name, nv_len);
1558
1559         return 0;
1560 }
1561
1562
1563 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1564                                         const struct firmware *fw, void *nvram,
1565                                         u32 nvram_len)
1566 {
1567         u32 sharedram_addr;
1568         u32 sharedram_addr_written;
1569         u32 loop_counter;
1570         int err;
1571         u32 address;
1572         u32 resetintr;
1573
1574         devinfo->ringbell = brcmf_pcie_ringbell_v2;
1575         devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1576
1577         brcmf_dbg(PCIE, "Halt ARM.\n");
1578         err = brcmf_pcie_enter_download_state(devinfo);
1579         if (err)
1580                 return err;
1581
1582         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1583         brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1584                                   (void *)fw->data, fw->size);
1585
1586         resetintr = get_unaligned_le32(fw->data);
1587         release_firmware(fw);
1588
1589         /* reset last 4 bytes of RAM address. to be used for shared
1590          * area. This identifies when FW is running
1591          */
1592         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1593
1594         if (nvram) {
1595                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1596                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1597                           nvram_len;
1598                 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1599                 brcmf_fw_nvram_free(nvram);
1600         } else {
1601                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1602                           devinfo->nvram_name);
1603         }
1604
1605         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1606                                                        devinfo->ci->ramsize -
1607                                                        4);
1608         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1609         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1610         if (err)
1611                 return err;
1612
1613         brcmf_dbg(PCIE, "Wait for FW init\n");
1614         sharedram_addr = sharedram_addr_written;
1615         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1616         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1617                 msleep(50);
1618                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1619                                                        devinfo->ci->ramsize -
1620                                                        4);
1621                 loop_counter--;
1622         }
1623         if (sharedram_addr == sharedram_addr_written) {
1624                 brcmf_err("FW failed to initialize\n");
1625                 return -ENODEV;
1626         }
1627         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1628
1629         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1630 }
1631
1632
1633 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1634 {
1635         struct pci_dev *pdev;
1636         int err;
1637         phys_addr_t  bar0_addr, bar1_addr;
1638         ulong bar1_size;
1639
1640         pdev = devinfo->pdev;
1641
1642         err = pci_enable_device(pdev);
1643         if (err) {
1644                 brcmf_err("pci_enable_device failed err=%d\n", err);
1645                 return err;
1646         }
1647
1648         pci_set_master(pdev);
1649
1650         /* Bar-0 mapped address */
1651         bar0_addr = pci_resource_start(pdev, 0);
1652         /* Bar-1 mapped address */
1653         bar1_addr = pci_resource_start(pdev, 2);
1654         /* read Bar-1 mapped memory range */
1655         bar1_size = pci_resource_len(pdev, 2);
1656         if ((bar1_size == 0) || (bar1_addr == 0)) {
1657                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1658                           bar1_size, (unsigned long long)bar1_addr);
1659                 return -EINVAL;
1660         }
1661
1662         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1663         devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1664         devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1665
1666         if (!devinfo->regs || !devinfo->tcm) {
1667                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1668                           devinfo->tcm);
1669                 return -EINVAL;
1670         }
1671         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1672                   devinfo->regs, (unsigned long long)bar0_addr);
1673         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1674                   devinfo->tcm, (unsigned long long)bar1_addr);
1675
1676         return 0;
1677 }
1678
1679
1680 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1681 {
1682         if (devinfo->tcm)
1683                 iounmap(devinfo->tcm);
1684         if (devinfo->regs)
1685                 iounmap(devinfo->regs);
1686
1687         pci_disable_device(devinfo->pdev);
1688 }
1689
1690
1691 static int brcmf_pcie_attach_bus(struct device *dev)
1692 {
1693         int ret;
1694
1695         /* Attach to the common driver interface */
1696         ret = brcmf_attach(dev);
1697         if (ret) {
1698                 brcmf_err("brcmf_attach failed\n");
1699         } else {
1700                 ret = brcmf_bus_start(dev);
1701                 if (ret)
1702                         brcmf_err("dongle is not responding\n");
1703         }
1704
1705         return ret;
1706 }
1707
1708
1709 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1710 {
1711         u32 ret_addr;
1712
1713         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1714         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1715         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1716
1717         return ret_addr;
1718 }
1719
1720
1721 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1722 {
1723         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1724
1725         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1726         return brcmf_pcie_read_reg32(devinfo, addr);
1727 }
1728
1729
1730 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1731 {
1732         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1733
1734         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1735         brcmf_pcie_write_reg32(devinfo, addr, value);
1736 }
1737
1738
1739 static int brcmf_pcie_buscoreprep(void *ctx)
1740 {
1741         return brcmf_pcie_get_resource(ctx);
1742 }
1743
1744
1745 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1746 {
1747         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1748         u32 val;
1749
1750         devinfo->ci = chip;
1751         brcmf_pcie_reset_device(devinfo);
1752
1753         val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1754         if (val != 0xffffffff)
1755                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1756                                        val);
1757
1758         return 0;
1759 }
1760
1761
1762 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1763                                         u32 rstvec)
1764 {
1765         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1766
1767         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1768 }
1769
1770
1771 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1772         .prepare = brcmf_pcie_buscoreprep,
1773         .reset = brcmf_pcie_buscore_reset,
1774         .activate = brcmf_pcie_buscore_activate,
1775         .read32 = brcmf_pcie_buscore_read32,
1776         .write32 = brcmf_pcie_buscore_write32,
1777 };
1778
1779 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1780                              void *nvram, u32 nvram_len)
1781 {
1782         struct brcmf_bus *bus = dev_get_drvdata(dev);
1783         struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1784         struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1785         struct brcmf_commonring **flowrings;
1786         int ret;
1787         u32 i;
1788
1789         brcmf_pcie_attach(devinfo);
1790
1791         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1792         if (ret)
1793                 goto fail;
1794
1795         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1796
1797         ret = brcmf_pcie_init_ringbuffers(devinfo);
1798         if (ret)
1799                 goto fail;
1800
1801         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1802         if (ret)
1803                 goto fail;
1804
1805         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1806         ret = brcmf_pcie_request_irq(devinfo);
1807         if (ret)
1808                 goto fail;
1809
1810         /* hook the commonrings in the bus structure. */
1811         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1812                 bus->msgbuf->commonrings[i] =
1813                                 &devinfo->shared.commonrings[i]->commonring;
1814
1815         flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
1816                             GFP_KERNEL);
1817         if (!flowrings)
1818                 goto fail;
1819
1820         for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1821                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1822         bus->msgbuf->flowrings = flowrings;
1823
1824         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1825         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1826         bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1827
1828         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1829
1830         brcmf_pcie_intr_enable(devinfo);
1831         if (brcmf_pcie_attach_bus(bus->dev) == 0)
1832                 return;
1833
1834         brcmf_pcie_bus_console_read(devinfo);
1835
1836 fail:
1837         device_release_driver(dev);
1838 }
1839
1840 static int
1841 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1842 {
1843         int ret;
1844         struct brcmf_pciedev_info *devinfo;
1845         struct brcmf_pciedev *pcie_bus_dev;
1846         struct brcmf_bus *bus;
1847         u16 domain_nr;
1848         u16 bus_nr;
1849
1850         domain_nr = pci_domain_nr(pdev->bus) + 1;
1851         bus_nr = pdev->bus->number;
1852         brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1853                   domain_nr, bus_nr);
1854
1855         ret = -ENOMEM;
1856         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1857         if (devinfo == NULL)
1858                 return ret;
1859
1860         devinfo->pdev = pdev;
1861         pcie_bus_dev = NULL;
1862         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1863         if (IS_ERR(devinfo->ci)) {
1864                 ret = PTR_ERR(devinfo->ci);
1865                 devinfo->ci = NULL;
1866                 goto fail;
1867         }
1868
1869         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1870         if (pcie_bus_dev == NULL) {
1871                 ret = -ENOMEM;
1872                 goto fail;
1873         }
1874
1875         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1876         if (!bus) {
1877                 ret = -ENOMEM;
1878                 goto fail;
1879         }
1880         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1881         if (!bus->msgbuf) {
1882                 ret = -ENOMEM;
1883                 kfree(bus);
1884                 goto fail;
1885         }
1886
1887         /* hook it all together. */
1888         pcie_bus_dev->devinfo = devinfo;
1889         pcie_bus_dev->bus = bus;
1890         bus->dev = &pdev->dev;
1891         bus->bus_priv.pcie = pcie_bus_dev;
1892         bus->ops = &brcmf_pcie_bus_ops;
1893         bus->proto_type = BRCMF_PROTO_MSGBUF;
1894         bus->chip = devinfo->coreid;
1895         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1896         dev_set_drvdata(&pdev->dev, bus);
1897
1898         ret = brcmf_pcie_get_fwnames(devinfo);
1899         if (ret)
1900                 goto fail_bus;
1901
1902         ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1903                                                     BRCMF_FW_REQ_NV_OPTIONAL,
1904                                           devinfo->fw_name, devinfo->nvram_name,
1905                                           brcmf_pcie_setup, domain_nr, bus_nr);
1906         if (ret == 0)
1907                 return 0;
1908 fail_bus:
1909         kfree(bus->msgbuf);
1910         kfree(bus);
1911 fail:
1912         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1913         brcmf_pcie_release_resource(devinfo);
1914         if (devinfo->ci)
1915                 brcmf_chip_detach(devinfo->ci);
1916         kfree(pcie_bus_dev);
1917         kfree(devinfo);
1918         return ret;
1919 }
1920
1921
1922 static void
1923 brcmf_pcie_remove(struct pci_dev *pdev)
1924 {
1925         struct brcmf_pciedev_info *devinfo;
1926         struct brcmf_bus *bus;
1927
1928         brcmf_dbg(PCIE, "Enter\n");
1929
1930         bus = dev_get_drvdata(&pdev->dev);
1931         if (bus == NULL)
1932                 return;
1933
1934         devinfo = bus->bus_priv.pcie->devinfo;
1935
1936         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1937         if (devinfo->ci)
1938                 brcmf_pcie_intr_disable(devinfo);
1939
1940         brcmf_detach(&pdev->dev);
1941
1942         kfree(bus->bus_priv.pcie);
1943         kfree(bus->msgbuf->flowrings);
1944         kfree(bus->msgbuf);
1945         kfree(bus);
1946
1947         brcmf_pcie_release_irq(devinfo);
1948         brcmf_pcie_release_scratchbuffers(devinfo);
1949         brcmf_pcie_release_ringbuffers(devinfo);
1950         brcmf_pcie_reset_device(devinfo);
1951         brcmf_pcie_release_resource(devinfo);
1952
1953         if (devinfo->ci)
1954                 brcmf_chip_detach(devinfo->ci);
1955
1956         kfree(devinfo);
1957         dev_set_drvdata(&pdev->dev, NULL);
1958 }
1959
1960
1961 #ifdef CONFIG_PM
1962
1963
1964 static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1965 {
1966         struct brcmf_pciedev_info *devinfo;
1967         struct brcmf_bus *bus;
1968         int err;
1969
1970         brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1971
1972         bus = dev_get_drvdata(&pdev->dev);
1973         devinfo = bus->bus_priv.pcie->devinfo;
1974
1975         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1976
1977         devinfo->mbdata_completed = false;
1978         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1979
1980         wait_event_timeout(devinfo->mbdata_resp_wait,
1981                            devinfo->mbdata_completed,
1982                            msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1983         if (!devinfo->mbdata_completed) {
1984                 brcmf_err("Timeout on response for entering D3 substate\n");
1985                 return -EIO;
1986         }
1987         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
1988
1989         err = pci_save_state(pdev);
1990         if (err)
1991                 brcmf_err("pci_save_state failed, err=%d\n", err);
1992         if ((err) || (!devinfo->wowl_enabled)) {
1993                 brcmf_chip_detach(devinfo->ci);
1994                 devinfo->ci = NULL;
1995                 brcmf_pcie_remove(pdev);
1996                 return 0;
1997         }
1998
1999         return pci_prepare_to_sleep(pdev);
2000 }
2001
2002 static int brcmf_pcie_resume(struct pci_dev *pdev)
2003 {
2004         struct brcmf_pciedev_info *devinfo;
2005         struct brcmf_bus *bus;
2006         int err;
2007
2008         bus = dev_get_drvdata(&pdev->dev);
2009         brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
2010
2011         err = pci_set_power_state(pdev, PCI_D0);
2012         if (err) {
2013                 brcmf_err("pci_set_power_state failed, err=%d\n", err);
2014                 goto cleanup;
2015         }
2016         pci_restore_state(pdev);
2017         pci_enable_wake(pdev, PCI_D3hot, false);
2018         pci_enable_wake(pdev, PCI_D3cold, false);
2019
2020         /* Check if device is still up and running, if so we are ready */
2021         if (bus) {
2022                 devinfo = bus->bus_priv.pcie->devinfo;
2023                 if (brcmf_pcie_read_reg32(devinfo,
2024                                           BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
2025                         if (brcmf_pcie_send_mb_data(devinfo,
2026                                                     BRCMF_H2D_HOST_D0_INFORM))
2027                                 goto cleanup;
2028                         brcmf_dbg(PCIE, "Hot resume, continue....\n");
2029                         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2030                         brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2031                         brcmf_pcie_intr_enable(devinfo);
2032                         return 0;
2033                 }
2034         }
2035
2036 cleanup:
2037         if (bus) {
2038                 devinfo = bus->bus_priv.pcie->devinfo;
2039                 brcmf_chip_detach(devinfo->ci);
2040                 devinfo->ci = NULL;
2041                 brcmf_pcie_remove(pdev);
2042         }
2043         err = brcmf_pcie_probe(pdev, NULL);
2044         if (err)
2045                 brcmf_err("probe after resume failed, err=%d\n", err);
2046
2047         return err;
2048 }
2049
2050
2051 #endif /* CONFIG_PM */
2052
2053
2054 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
2055         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
2056
2057 static struct pci_device_id brcmf_pcie_devid_table[] = {
2058         BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
2059         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
2060         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
2061         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
2062         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
2063         BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID),
2064         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
2065         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
2066         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
2067         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
2068         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
2069         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
2070         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
2071         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
2072         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
2073         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
2074         BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
2075         { /* end: all zeroes */ }
2076 };
2077
2078
2079 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2080
2081
2082 static struct pci_driver brcmf_pciedrvr = {
2083         .node = {},
2084         .name = KBUILD_MODNAME,
2085         .id_table = brcmf_pcie_devid_table,
2086         .probe = brcmf_pcie_probe,
2087         .remove = brcmf_pcie_remove,
2088 #ifdef CONFIG_PM
2089         .suspend = brcmf_pcie_suspend,
2090         .resume = brcmf_pcie_resume
2091 #endif /* CONFIG_PM */
2092 };
2093
2094
2095 void brcmf_pcie_register(void)
2096 {
2097         int err;
2098
2099         brcmf_dbg(PCIE, "Enter\n");
2100         err = pci_register_driver(&brcmf_pciedrvr);
2101         if (err)
2102                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
2103 }
2104
2105
2106 void brcmf_pcie_exit(void)
2107 {
2108         brcmf_dbg(PCIE, "Enter\n");
2109         pci_unregister_driver(&brcmf_pciedrvr);
2110 }