3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
60 #include <linux/mmc/sdio_func.h>
62 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63 MODULE_AUTHOR("Martin Langer");
64 MODULE_AUTHOR("Stefano Brivio");
65 MODULE_AUTHOR("Michael Buesch");
66 MODULE_AUTHOR("Gábor Stefanik");
67 MODULE_AUTHOR("Rafał Miłecki");
68 MODULE_LICENSE("GPL");
70 MODULE_FIRMWARE("b43/ucode11.fw");
71 MODULE_FIRMWARE("b43/ucode13.fw");
72 MODULE_FIRMWARE("b43/ucode14.fw");
73 MODULE_FIRMWARE("b43/ucode15.fw");
74 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
75 MODULE_FIRMWARE("b43/ucode5.fw");
76 MODULE_FIRMWARE("b43/ucode9.fw");
78 static int modparam_bad_frames_preempt;
79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt,
81 "enable(1) / disable(0) Bad Frames Preemption");
83 static char modparam_fwpostfix[16];
84 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
85 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87 static int modparam_hwpctl;
88 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
89 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91 static int modparam_nohwcrypt;
92 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
93 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95 static int modparam_hwtkip;
96 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
97 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99 static int modparam_qos = 1;
100 module_param_named(qos, modparam_qos, int, 0444);
101 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103 static int modparam_btcoex = 1;
104 module_param_named(btcoex, modparam_btcoex, int, 0444);
105 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
107 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
108 module_param_named(verbose, b43_modparam_verbose, int, 0644);
109 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111 static int b43_modparam_pio = 0;
112 module_param_named(pio, b43_modparam_pio, int, 0644);
113 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
115 static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC);
116 module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);
117 MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)");
119 #ifdef CONFIG_B43_BCMA
120 static const struct bcma_device_id b43_bcma_tbl[] = {
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x15, BCMA_ANY_CLASS),
123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS),
126 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
127 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS),
128 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS),
129 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS),
132 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
135 #ifdef CONFIG_B43_SSB
136 static const struct ssb_device_id b43_ssb_tbl[] = {
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
143 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
144 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
145 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
146 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
149 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
152 /* Channel and ratetables are shared for all devices.
153 * They can't be const, because ieee80211 puts some precalculated
154 * data in there. This data is the same for all devices, so we don't
155 * get concurrency issues */
156 #define RATETAB_ENT(_rateid, _flags) \
158 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
159 .hw_value = (_rateid), \
164 * NOTE: When changing this, sync with xmit.c's
165 * b43_plcp_get_bitrate_idx_* functions!
167 static struct ieee80211_rate __b43_ratetable[] = {
168 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
169 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
170 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
171 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
172 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
174 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
175 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
176 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
177 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
178 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
179 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
182 #define b43_a_ratetable (__b43_ratetable + 4)
183 #define b43_a_ratetable_size 8
184 #define b43_b_ratetable (__b43_ratetable + 0)
185 #define b43_b_ratetable_size 4
186 #define b43_g_ratetable (__b43_ratetable + 0)
187 #define b43_g_ratetable_size 12
189 #define CHAN2G(_channel, _freq, _flags) { \
190 .band = IEEE80211_BAND_2GHZ, \
191 .center_freq = (_freq), \
192 .hw_value = (_channel), \
194 .max_antenna_gain = 0, \
197 static struct ieee80211_channel b43_2ghz_chantable[] = {
214 /* No support for the last 3 channels (12, 13, 14) */
215 #define b43_2ghz_chantable_limited_size 11
218 #define CHAN4G(_channel, _flags) { \
219 .band = IEEE80211_BAND_5GHZ, \
220 .center_freq = 4000 + (5 * (_channel)), \
221 .hw_value = (_channel), \
223 .max_antenna_gain = 0, \
226 #define CHAN5G(_channel, _flags) { \
227 .band = IEEE80211_BAND_5GHZ, \
228 .center_freq = 5000 + (5 * (_channel)), \
229 .hw_value = (_channel), \
231 .max_antenna_gain = 0, \
234 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
235 CHAN4G(184, 0), CHAN4G(186, 0),
236 CHAN4G(188, 0), CHAN4G(190, 0),
237 CHAN4G(192, 0), CHAN4G(194, 0),
238 CHAN4G(196, 0), CHAN4G(198, 0),
239 CHAN4G(200, 0), CHAN4G(202, 0),
240 CHAN4G(204, 0), CHAN4G(206, 0),
241 CHAN4G(208, 0), CHAN4G(210, 0),
242 CHAN4G(212, 0), CHAN4G(214, 0),
243 CHAN4G(216, 0), CHAN4G(218, 0),
244 CHAN4G(220, 0), CHAN4G(222, 0),
245 CHAN4G(224, 0), CHAN4G(226, 0),
247 CHAN5G(32, 0), CHAN5G(34, 0),
248 CHAN5G(36, 0), CHAN5G(38, 0),
249 CHAN5G(40, 0), CHAN5G(42, 0),
250 CHAN5G(44, 0), CHAN5G(46, 0),
251 CHAN5G(48, 0), CHAN5G(50, 0),
252 CHAN5G(52, 0), CHAN5G(54, 0),
253 CHAN5G(56, 0), CHAN5G(58, 0),
254 CHAN5G(60, 0), CHAN5G(62, 0),
255 CHAN5G(64, 0), CHAN5G(66, 0),
256 CHAN5G(68, 0), CHAN5G(70, 0),
257 CHAN5G(72, 0), CHAN5G(74, 0),
258 CHAN5G(76, 0), CHAN5G(78, 0),
259 CHAN5G(80, 0), CHAN5G(82, 0),
260 CHAN5G(84, 0), CHAN5G(86, 0),
261 CHAN5G(88, 0), CHAN5G(90, 0),
262 CHAN5G(92, 0), CHAN5G(94, 0),
263 CHAN5G(96, 0), CHAN5G(98, 0),
264 CHAN5G(100, 0), CHAN5G(102, 0),
265 CHAN5G(104, 0), CHAN5G(106, 0),
266 CHAN5G(108, 0), CHAN5G(110, 0),
267 CHAN5G(112, 0), CHAN5G(114, 0),
268 CHAN5G(116, 0), CHAN5G(118, 0),
269 CHAN5G(120, 0), CHAN5G(122, 0),
270 CHAN5G(124, 0), CHAN5G(126, 0),
271 CHAN5G(128, 0), CHAN5G(130, 0),
272 CHAN5G(132, 0), CHAN5G(134, 0),
273 CHAN5G(136, 0), CHAN5G(138, 0),
274 CHAN5G(140, 0), CHAN5G(142, 0),
275 CHAN5G(144, 0), CHAN5G(145, 0),
276 CHAN5G(146, 0), CHAN5G(147, 0),
277 CHAN5G(148, 0), CHAN5G(149, 0),
278 CHAN5G(150, 0), CHAN5G(151, 0),
279 CHAN5G(152, 0), CHAN5G(153, 0),
280 CHAN5G(154, 0), CHAN5G(155, 0),
281 CHAN5G(156, 0), CHAN5G(157, 0),
282 CHAN5G(158, 0), CHAN5G(159, 0),
283 CHAN5G(160, 0), CHAN5G(161, 0),
284 CHAN5G(162, 0), CHAN5G(163, 0),
285 CHAN5G(164, 0), CHAN5G(165, 0),
286 CHAN5G(166, 0), CHAN5G(168, 0),
287 CHAN5G(170, 0), CHAN5G(172, 0),
288 CHAN5G(174, 0), CHAN5G(176, 0),
289 CHAN5G(178, 0), CHAN5G(180, 0),
293 static struct ieee80211_channel b43_5ghz_nphy_chantable_limited[] = {
294 CHAN5G(36, 0), CHAN5G(40, 0),
295 CHAN5G(44, 0), CHAN5G(48, 0),
296 CHAN5G(149, 0), CHAN5G(153, 0),
297 CHAN5G(157, 0), CHAN5G(161, 0),
301 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
302 CHAN5G(34, 0), CHAN5G(36, 0),
303 CHAN5G(38, 0), CHAN5G(40, 0),
304 CHAN5G(42, 0), CHAN5G(44, 0),
305 CHAN5G(46, 0), CHAN5G(48, 0),
306 CHAN5G(52, 0), CHAN5G(56, 0),
307 CHAN5G(60, 0), CHAN5G(64, 0),
308 CHAN5G(100, 0), CHAN5G(104, 0),
309 CHAN5G(108, 0), CHAN5G(112, 0),
310 CHAN5G(116, 0), CHAN5G(120, 0),
311 CHAN5G(124, 0), CHAN5G(128, 0),
312 CHAN5G(132, 0), CHAN5G(136, 0),
313 CHAN5G(140, 0), CHAN5G(149, 0),
314 CHAN5G(153, 0), CHAN5G(157, 0),
315 CHAN5G(161, 0), CHAN5G(165, 0),
316 CHAN5G(184, 0), CHAN5G(188, 0),
317 CHAN5G(192, 0), CHAN5G(196, 0),
318 CHAN5G(200, 0), CHAN5G(204, 0),
319 CHAN5G(208, 0), CHAN5G(212, 0),
325 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
326 .band = IEEE80211_BAND_5GHZ,
327 .channels = b43_5ghz_nphy_chantable,
328 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
329 .bitrates = b43_a_ratetable,
330 .n_bitrates = b43_a_ratetable_size,
333 static struct ieee80211_supported_band b43_band_5GHz_nphy_limited = {
334 .band = IEEE80211_BAND_5GHZ,
335 .channels = b43_5ghz_nphy_chantable_limited,
336 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable_limited),
337 .bitrates = b43_a_ratetable,
338 .n_bitrates = b43_a_ratetable_size,
341 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
342 .band = IEEE80211_BAND_5GHZ,
343 .channels = b43_5ghz_aphy_chantable,
344 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
345 .bitrates = b43_a_ratetable,
346 .n_bitrates = b43_a_ratetable_size,
349 static struct ieee80211_supported_band b43_band_2GHz = {
350 .band = IEEE80211_BAND_2GHZ,
351 .channels = b43_2ghz_chantable,
352 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
353 .bitrates = b43_g_ratetable,
354 .n_bitrates = b43_g_ratetable_size,
357 static struct ieee80211_supported_band b43_band_2ghz_limited = {
358 .band = IEEE80211_BAND_2GHZ,
359 .channels = b43_2ghz_chantable,
360 .n_channels = b43_2ghz_chantable_limited_size,
361 .bitrates = b43_g_ratetable,
362 .n_bitrates = b43_g_ratetable_size,
365 static void b43_wireless_core_exit(struct b43_wldev *dev);
366 static int b43_wireless_core_init(struct b43_wldev *dev);
367 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
368 static int b43_wireless_core_start(struct b43_wldev *dev);
369 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
370 struct ieee80211_vif *vif,
371 struct ieee80211_bss_conf *conf,
374 static int b43_ratelimit(struct b43_wl *wl)
376 if (!wl || !wl->current_dev)
378 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
380 /* We are up and running.
381 * Ratelimit the messages to avoid DoS over the net. */
382 return net_ratelimit();
385 void b43info(struct b43_wl *wl, const char *fmt, ...)
387 struct va_format vaf;
390 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
392 if (!b43_ratelimit(wl))
400 printk(KERN_INFO "b43-%s: %pV",
401 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
406 void b43err(struct b43_wl *wl, const char *fmt, ...)
408 struct va_format vaf;
411 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
413 if (!b43_ratelimit(wl))
421 printk(KERN_ERR "b43-%s ERROR: %pV",
422 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
427 void b43warn(struct b43_wl *wl, const char *fmt, ...)
429 struct va_format vaf;
432 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
434 if (!b43_ratelimit(wl))
442 printk(KERN_WARNING "b43-%s warning: %pV",
443 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
448 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
450 struct va_format vaf;
453 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
461 printk(KERN_DEBUG "b43-%s debug: %pV",
462 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
467 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
471 B43_WARN_ON(offset % 4 != 0);
473 macctl = b43_read32(dev, B43_MMIO_MACCTL);
474 if (macctl & B43_MACCTL_BE)
477 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
479 b43_write32(dev, B43_MMIO_RAM_DATA, val);
482 static inline void b43_shm_control_word(struct b43_wldev *dev,
483 u16 routing, u16 offset)
487 /* "offset" is the WORD offset. */
491 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
494 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
498 if (routing == B43_SHM_SHARED) {
499 B43_WARN_ON(offset & 0x0001);
500 if (offset & 0x0003) {
501 /* Unaligned access */
502 b43_shm_control_word(dev, routing, offset >> 2);
503 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
505 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
511 b43_shm_control_word(dev, routing, offset);
512 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
517 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
521 if (routing == B43_SHM_SHARED) {
522 B43_WARN_ON(offset & 0x0001);
523 if (offset & 0x0003) {
524 /* Unaligned access */
525 b43_shm_control_word(dev, routing, offset >> 2);
526 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
532 b43_shm_control_word(dev, routing, offset);
533 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
538 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
540 if (routing == B43_SHM_SHARED) {
541 B43_WARN_ON(offset & 0x0001);
542 if (offset & 0x0003) {
543 /* Unaligned access */
544 b43_shm_control_word(dev, routing, offset >> 2);
545 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
547 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
548 b43_write16(dev, B43_MMIO_SHM_DATA,
549 (value >> 16) & 0xFFFF);
554 b43_shm_control_word(dev, routing, offset);
555 b43_write32(dev, B43_MMIO_SHM_DATA, value);
558 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
560 if (routing == B43_SHM_SHARED) {
561 B43_WARN_ON(offset & 0x0001);
562 if (offset & 0x0003) {
563 /* Unaligned access */
564 b43_shm_control_word(dev, routing, offset >> 2);
565 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
570 b43_shm_control_word(dev, routing, offset);
571 b43_write16(dev, B43_MMIO_SHM_DATA, value);
575 u64 b43_hf_read(struct b43_wldev *dev)
579 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
581 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
583 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
588 /* Write HostFlags */
589 void b43_hf_write(struct b43_wldev *dev, u64 value)
593 lo = (value & 0x00000000FFFFULL);
594 mi = (value & 0x0000FFFF0000ULL) >> 16;
595 hi = (value & 0xFFFF00000000ULL) >> 32;
596 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
597 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
598 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
601 /* Read the firmware capabilities bitmask (Opensource firmware only) */
602 static u16 b43_fwcapa_read(struct b43_wldev *dev)
604 B43_WARN_ON(!dev->fw.opensource);
605 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
608 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
612 B43_WARN_ON(dev->dev->core_rev < 3);
614 /* The hardware guarantees us an atomic read, if we
615 * read the low register first. */
616 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
617 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
624 static void b43_time_lock(struct b43_wldev *dev)
626 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
627 /* Commit the write */
628 b43_read32(dev, B43_MMIO_MACCTL);
631 static void b43_time_unlock(struct b43_wldev *dev)
633 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
634 /* Commit the write */
635 b43_read32(dev, B43_MMIO_MACCTL);
638 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
642 B43_WARN_ON(dev->dev->core_rev < 3);
646 /* The hardware guarantees us an atomic write, if we
647 * write the low register first. */
648 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
650 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
654 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
657 b43_tsf_write_locked(dev, tsf);
658 b43_time_unlock(dev);
662 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
664 static const u8 zero_addr[ETH_ALEN] = { 0 };
671 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
675 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
678 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
681 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
684 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
688 u8 mac_bssid[ETH_ALEN * 2];
692 bssid = dev->wl->bssid;
693 mac = dev->wl->mac_addr;
695 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
697 memcpy(mac_bssid, mac, ETH_ALEN);
698 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
700 /* Write our MAC address and BSSID to template ram */
701 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
702 tmp = (u32) (mac_bssid[i + 0]);
703 tmp |= (u32) (mac_bssid[i + 1]) << 8;
704 tmp |= (u32) (mac_bssid[i + 2]) << 16;
705 tmp |= (u32) (mac_bssid[i + 3]) << 24;
706 b43_ram_write(dev, 0x20 + i, tmp);
710 static void b43_upload_card_macaddress(struct b43_wldev *dev)
712 b43_write_mac_bssid_templates(dev);
713 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
716 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
718 /* slot_time is in usec. */
719 /* This test used to exit for all but a G PHY. */
720 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
722 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
723 /* Shared memory location 0x0010 is the slot time and should be
724 * set to slot_time; however, this register is initially 0 and changing
725 * the value adversely affects the transmit rate for BCM4311
726 * devices. Until this behavior is unterstood, delete this step
728 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
732 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
734 b43_set_slot_time(dev, 9);
737 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
739 b43_set_slot_time(dev, 20);
742 /* DummyTransmission function, as documented on
743 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
745 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
747 struct b43_phy *phy = &dev->phy;
748 unsigned int i, max_loop;
760 buffer[0] = 0x000201CC;
763 buffer[0] = 0x000B846E;
766 for (i = 0; i < 5; i++)
767 b43_ram_write(dev, i * 4, buffer[i]);
769 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
771 if (dev->dev->core_rev < 11)
772 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
774 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
776 value = (ofdm ? 0x41 : 0x40);
777 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
778 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
779 phy->type == B43_PHYTYPE_LCN)
780 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
782 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
783 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
785 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
786 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
787 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
788 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
790 if (!pa_on && phy->type == B43_PHYTYPE_N)
791 ; /*b43_nphy_pa_override(dev, false) */
795 case B43_PHYTYPE_LCN:
796 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
799 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
802 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
804 b43_read16(dev, B43_MMIO_TXE0_AUX);
806 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
807 b43_radio_write16(dev, 0x0051, 0x0017);
808 for (i = 0x00; i < max_loop; i++) {
809 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
814 for (i = 0x00; i < 0x0A; i++) {
815 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
820 for (i = 0x00; i < 0x19; i++) {
821 value = b43_read16(dev, B43_MMIO_IFSSTAT);
822 if (!(value & 0x0100))
826 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
827 b43_radio_write16(dev, 0x0051, 0x0037);
830 static void key_write(struct b43_wldev *dev,
831 u8 index, u8 algorithm, const u8 *key)
838 /* Key index/algo block */
839 kidx = b43_kidx_to_fw(dev, index);
840 value = ((kidx << 4) | algorithm);
841 b43_shm_write16(dev, B43_SHM_SHARED,
842 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
844 /* Write the key to the Key Table Pointer offset */
845 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
846 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
848 value |= (u16) (key[i + 1]) << 8;
849 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
853 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
855 u32 addrtmp[2] = { 0, 0, };
856 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
858 if (b43_new_kidx_api(dev))
859 pairwise_keys_start = B43_NR_GROUP_KEYS;
861 B43_WARN_ON(index < pairwise_keys_start);
862 /* We have four default TX keys and possibly four default RX keys.
863 * Physical mac 0 is mapped to physical key 4 or 8, depending
864 * on the firmware version.
865 * So we must adjust the index here.
867 index -= pairwise_keys_start;
868 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
871 addrtmp[0] = addr[0];
872 addrtmp[0] |= ((u32) (addr[1]) << 8);
873 addrtmp[0] |= ((u32) (addr[2]) << 16);
874 addrtmp[0] |= ((u32) (addr[3]) << 24);
875 addrtmp[1] = addr[4];
876 addrtmp[1] |= ((u32) (addr[5]) << 8);
879 /* Receive match transmitter address (RCMTA) mechanism */
880 b43_shm_write32(dev, B43_SHM_RCMTA,
881 (index * 2) + 0, addrtmp[0]);
882 b43_shm_write16(dev, B43_SHM_RCMTA,
883 (index * 2) + 1, addrtmp[1]);
886 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
887 * When a packet is received, the iv32 is checked.
888 * - if it doesn't the packet is returned without modification (and software
889 * decryption can be done). That's what happen when iv16 wrap.
890 * - if it does, the rc4 key is computed, and decryption is tried.
891 * Either it will success and B43_RX_MAC_DEC is returned,
892 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
893 * and the packet is not usable (it got modified by the ucode).
894 * So in order to never have B43_RX_MAC_DECERR, we should provide
895 * a iv32 and phase1key that match. Because we drop packets in case of
896 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
897 * packets will be lost without higher layer knowing (ie no resync possible
900 * NOTE : this should support 50 key like RCMTA because
901 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
903 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
908 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
910 if (!modparam_hwtkip)
913 if (b43_new_kidx_api(dev))
914 pairwise_keys_start = B43_NR_GROUP_KEYS;
916 B43_WARN_ON(index < pairwise_keys_start);
917 /* We have four default TX keys and possibly four default RX keys.
918 * Physical mac 0 is mapped to physical key 4 or 8, depending
919 * on the firmware version.
920 * So we must adjust the index here.
922 index -= pairwise_keys_start;
923 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
925 if (b43_debug(dev, B43_DBG_KEYS)) {
926 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
929 /* Write the key to the RX tkip shared mem */
930 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
931 for (i = 0; i < 10; i += 2) {
932 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
933 phase1key ? phase1key[i / 2] : 0);
935 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
936 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
939 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
940 struct ieee80211_vif *vif,
941 struct ieee80211_key_conf *keyconf,
942 struct ieee80211_sta *sta,
943 u32 iv32, u16 *phase1key)
945 struct b43_wl *wl = hw_to_b43_wl(hw);
946 struct b43_wldev *dev;
947 int index = keyconf->hw_key_idx;
949 if (B43_WARN_ON(!modparam_hwtkip))
952 /* This is only called from the RX path through mac80211, where
953 * our mutex is already locked. */
954 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
955 dev = wl->current_dev;
956 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
958 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
960 rx_tkip_phase1_write(dev, index, iv32, phase1key);
961 /* only pairwise TKIP keys are supported right now */
964 keymac_write(dev, index, sta->addr);
967 static void do_key_write(struct b43_wldev *dev,
968 u8 index, u8 algorithm,
969 const u8 *key, size_t key_len, const u8 *mac_addr)
971 u8 buf[B43_SEC_KEYSIZE] = { 0, };
972 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
974 if (b43_new_kidx_api(dev))
975 pairwise_keys_start = B43_NR_GROUP_KEYS;
977 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
978 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
980 if (index >= pairwise_keys_start)
981 keymac_write(dev, index, NULL); /* First zero out mac. */
982 if (algorithm == B43_SEC_ALGO_TKIP) {
984 * We should provide an initial iv32, phase1key pair.
985 * We could start with iv32=0 and compute the corresponding
986 * phase1key, but this means calling ieee80211_get_tkip_key
987 * with a fake skb (or export other tkip function).
988 * Because we are lazy we hope iv32 won't start with
989 * 0xffffffff and let's b43_op_update_tkip_key provide a
992 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
993 } else if (index >= pairwise_keys_start) /* clear it */
994 rx_tkip_phase1_write(dev, index, 0, NULL);
996 memcpy(buf, key, key_len);
997 key_write(dev, index, algorithm, buf);
998 if (index >= pairwise_keys_start)
999 keymac_write(dev, index, mac_addr);
1001 dev->key[index].algorithm = algorithm;
1004 static int b43_key_write(struct b43_wldev *dev,
1005 int index, u8 algorithm,
1006 const u8 *key, size_t key_len,
1008 struct ieee80211_key_conf *keyconf)
1011 int pairwise_keys_start;
1013 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
1014 * - Temporal Encryption Key (128 bits)
1015 * - Temporal Authenticator Tx MIC Key (64 bits)
1016 * - Temporal Authenticator Rx MIC Key (64 bits)
1018 * Hardware only store TEK
1020 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
1022 if (key_len > B43_SEC_KEYSIZE)
1024 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
1025 /* Check that we don't already have this key. */
1026 B43_WARN_ON(dev->key[i].keyconf == keyconf);
1029 /* Pairwise key. Get an empty slot for the key. */
1030 if (b43_new_kidx_api(dev))
1031 pairwise_keys_start = B43_NR_GROUP_KEYS;
1033 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1034 for (i = pairwise_keys_start;
1035 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
1037 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
1038 if (!dev->key[i].keyconf) {
1045 b43warn(dev->wl, "Out of hardware key memory\n");
1049 B43_WARN_ON(index > 3);
1051 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1052 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1053 /* Default RX key */
1054 B43_WARN_ON(mac_addr);
1055 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1057 keyconf->hw_key_idx = index;
1058 dev->key[index].keyconf = keyconf;
1063 static int b43_key_clear(struct b43_wldev *dev, int index)
1065 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1067 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1068 NULL, B43_SEC_KEYSIZE, NULL);
1069 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1070 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1071 NULL, B43_SEC_KEYSIZE, NULL);
1073 dev->key[index].keyconf = NULL;
1078 static void b43_clear_keys(struct b43_wldev *dev)
1082 if (b43_new_kidx_api(dev))
1083 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1085 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1086 for (i = 0; i < count; i++)
1087 b43_key_clear(dev, i);
1090 static void b43_dump_keymemory(struct b43_wldev *dev)
1092 unsigned int i, index, count, offset, pairwise_keys_start;
1098 struct b43_key *key;
1100 if (!b43_debug(dev, B43_DBG_KEYS))
1103 hf = b43_hf_read(dev);
1104 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1105 !!(hf & B43_HF_USEDEFKEYS));
1106 if (b43_new_kidx_api(dev)) {
1107 pairwise_keys_start = B43_NR_GROUP_KEYS;
1108 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1110 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1111 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1113 for (index = 0; index < count; index++) {
1114 key = &(dev->key[index]);
1115 printk(KERN_DEBUG "Key slot %02u: %s",
1116 index, (key->keyconf == NULL) ? " " : "*");
1117 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1118 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1119 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1120 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1123 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1124 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1125 printk(" Algo: %04X/%02X", algo, key->algorithm);
1127 if (index >= pairwise_keys_start) {
1128 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1130 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1131 for (i = 0; i < 14; i += 2) {
1132 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1133 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1136 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1137 ((index - pairwise_keys_start) * 2) + 0);
1138 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1139 ((index - pairwise_keys_start) * 2) + 1);
1140 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1141 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1142 printk(" MAC: %pM", mac);
1144 printk(" DEFAULT KEY");
1149 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1157 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1158 (ps_flags & B43_PS_DISABLED));
1159 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1161 if (ps_flags & B43_PS_ENABLED) {
1163 } else if (ps_flags & B43_PS_DISABLED) {
1166 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1167 // and thus is not an AP and we are associated, set bit 25
1169 if (ps_flags & B43_PS_AWAKE) {
1171 } else if (ps_flags & B43_PS_ASLEEP) {
1174 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1175 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1176 // successful, set bit26
1179 /* FIXME: For now we force awake-on and hwps-off */
1183 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1185 macctl |= B43_MACCTL_HWPS;
1187 macctl &= ~B43_MACCTL_HWPS;
1189 macctl |= B43_MACCTL_AWAKE;
1191 macctl &= ~B43_MACCTL_AWAKE;
1192 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1194 b43_read32(dev, B43_MMIO_MACCTL);
1195 if (awake && dev->dev->core_rev >= 5) {
1196 /* Wait for the microcode to wake up. */
1197 for (i = 0; i < 100; i++) {
1198 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1199 B43_SHM_SH_UCODESTAT);
1200 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1207 /* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */
1208 void b43_wireless_core_phy_pll_reset(struct b43_wldev *dev)
1210 struct bcma_drv_cc *bcma_cc __maybe_unused;
1211 struct ssb_chipcommon *ssb_cc __maybe_unused;
1213 switch (dev->dev->bus_type) {
1214 #ifdef CONFIG_B43_BCMA
1216 bcma_cc = &dev->dev->bdev->bus->drv_cc;
1218 bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
1219 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
1220 bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
1221 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
1224 #ifdef CONFIG_B43_SSB
1226 ssb_cc = &dev->dev->sdev->bus->chipco;
1228 chipco_write32(ssb_cc, SSB_CHIPCO_CHIPCTL_ADDR, 0);
1229 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1230 chipco_set32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, 0x4);
1231 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4);
1237 #ifdef CONFIG_B43_BCMA
1238 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1242 /* Put PHY into reset */
1243 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1244 flags |= B43_BCMA_IOCTL_PHY_RESET;
1245 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1246 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1249 b43_phy_take_out_of_reset(dev);
1252 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1254 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1255 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1256 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1257 B43_BCMA_CLKCTLST_PHY_PLL_ST;
1260 flags = B43_BCMA_IOCTL_PHY_CLKEN;
1262 flags |= B43_BCMA_IOCTL_GMODE;
1263 b43_device_enable(dev, flags);
1265 if (dev->phy.type == B43_PHYTYPE_AC) {
1268 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1269 tmp &= ~B43_BCMA_IOCTL_DAC;
1271 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1273 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1274 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
1275 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1277 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1278 tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
1279 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
1282 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1283 b43_bcma_phy_reset(dev);
1284 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
1288 #ifdef CONFIG_B43_SSB
1289 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1294 flags |= B43_TMSLOW_GMODE;
1295 flags |= B43_TMSLOW_PHYCLKEN;
1296 flags |= B43_TMSLOW_PHYRESET;
1297 if (dev->phy.type == B43_PHYTYPE_N)
1298 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1299 b43_device_enable(dev, flags);
1300 msleep(2); /* Wait for the PLL to turn on. */
1302 b43_phy_take_out_of_reset(dev);
1306 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1310 switch (dev->dev->bus_type) {
1311 #ifdef CONFIG_B43_BCMA
1313 b43_bcma_wireless_core_reset(dev, gmode);
1316 #ifdef CONFIG_B43_SSB
1318 b43_ssb_wireless_core_reset(dev, gmode);
1323 /* Turn Analog ON, but only if we already know the PHY-type.
1324 * This protects against very early setup where we don't know the
1325 * PHY-type, yet. wireless_core_reset will be called once again later,
1326 * when we know the PHY-type. */
1328 dev->phy.ops->switch_analog(dev, 1);
1330 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1331 macctl &= ~B43_MACCTL_GMODE;
1333 macctl |= B43_MACCTL_GMODE;
1334 macctl |= B43_MACCTL_IHR_ENABLED;
1335 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1338 static void handle_irq_transmit_status(struct b43_wldev *dev)
1342 struct b43_txstatus stat;
1345 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1346 if (!(v0 & 0x00000001))
1348 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1350 stat.cookie = (v0 >> 16);
1351 stat.seq = (v1 & 0x0000FFFF);
1352 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1353 tmp = (v0 & 0x0000FFFF);
1354 stat.frame_count = ((tmp & 0xF000) >> 12);
1355 stat.rts_count = ((tmp & 0x0F00) >> 8);
1356 stat.supp_reason = ((tmp & 0x001C) >> 2);
1357 stat.pm_indicated = !!(tmp & 0x0080);
1358 stat.intermediate = !!(tmp & 0x0040);
1359 stat.for_ampdu = !!(tmp & 0x0020);
1360 stat.acked = !!(tmp & 0x0002);
1362 b43_handle_txstatus(dev, &stat);
1366 static void drain_txstatus_queue(struct b43_wldev *dev)
1370 if (dev->dev->core_rev < 5)
1372 /* Read all entries from the microcode TXstatus FIFO
1373 * and throw them away.
1376 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1377 if (!(dummy & 0x00000001))
1379 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1383 static u32 b43_jssi_read(struct b43_wldev *dev)
1387 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
1389 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
1394 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1396 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1397 (jssi & 0x0000FFFF));
1398 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1399 (jssi & 0xFFFF0000) >> 16);
1402 static void b43_generate_noise_sample(struct b43_wldev *dev)
1404 b43_jssi_write(dev, 0x7F7F7F7F);
1405 b43_write32(dev, B43_MMIO_MACCMD,
1406 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1409 static void b43_calculate_link_quality(struct b43_wldev *dev)
1411 /* Top half of Link Quality calculation. */
1413 if (dev->phy.type != B43_PHYTYPE_G)
1415 if (dev->noisecalc.calculation_running)
1417 dev->noisecalc.calculation_running = true;
1418 dev->noisecalc.nr_samples = 0;
1420 b43_generate_noise_sample(dev);
1423 static void handle_irq_noise(struct b43_wldev *dev)
1425 struct b43_phy_g *phy = dev->phy.g;
1431 /* Bottom half of Link Quality calculation. */
1433 if (dev->phy.type != B43_PHYTYPE_G)
1436 /* Possible race condition: It might be possible that the user
1437 * changed to a different channel in the meantime since we
1438 * started the calculation. We ignore that fact, since it's
1439 * not really that much of a problem. The background noise is
1440 * an estimation only anyway. Slightly wrong results will get damped
1441 * by the averaging of the 8 sample rounds. Additionally the
1442 * value is shortlived. So it will be replaced by the next noise
1443 * calculation round soon. */
1445 B43_WARN_ON(!dev->noisecalc.calculation_running);
1446 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1447 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1448 noise[2] == 0x7F || noise[3] == 0x7F)
1451 /* Get the noise samples. */
1452 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1453 i = dev->noisecalc.nr_samples;
1454 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1455 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1456 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1457 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1458 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1459 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1460 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1461 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1462 dev->noisecalc.nr_samples++;
1463 if (dev->noisecalc.nr_samples == 8) {
1464 /* Calculate the Link Quality by the noise samples. */
1466 for (i = 0; i < 8; i++) {
1467 for (j = 0; j < 4; j++)
1468 average += dev->noisecalc.samples[i][j];
1474 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1475 tmp = (tmp / 128) & 0x1F;
1485 dev->stats.link_noise = average;
1486 dev->noisecalc.calculation_running = false;
1490 b43_generate_noise_sample(dev);
1493 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1495 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1498 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1499 b43_power_saving_ctl_bits(dev, 0);
1501 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1502 dev->dfq_valid = true;
1505 static void handle_irq_atim_end(struct b43_wldev *dev)
1507 if (dev->dfq_valid) {
1508 b43_write32(dev, B43_MMIO_MACCMD,
1509 b43_read32(dev, B43_MMIO_MACCMD)
1510 | B43_MACCMD_DFQ_VALID);
1511 dev->dfq_valid = false;
1515 static void handle_irq_pmq(struct b43_wldev *dev)
1522 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1523 if (!(tmp & 0x00000008))
1526 /* 16bit write is odd, but correct. */
1527 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1530 static void b43_write_template_common(struct b43_wldev *dev,
1531 const u8 *data, u16 size,
1533 u16 shm_size_offset, u8 rate)
1536 struct b43_plcp_hdr4 plcp;
1539 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1540 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1541 ram_offset += sizeof(u32);
1542 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1543 * So leave the first two bytes of the next write blank.
1545 tmp = (u32) (data[0]) << 16;
1546 tmp |= (u32) (data[1]) << 24;
1547 b43_ram_write(dev, ram_offset, tmp);
1548 ram_offset += sizeof(u32);
1549 for (i = 2; i < size; i += sizeof(u32)) {
1550 tmp = (u32) (data[i + 0]);
1552 tmp |= (u32) (data[i + 1]) << 8;
1554 tmp |= (u32) (data[i + 2]) << 16;
1556 tmp |= (u32) (data[i + 3]) << 24;
1557 b43_ram_write(dev, ram_offset + i - 2, tmp);
1559 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1560 size + sizeof(struct b43_plcp_hdr6));
1563 /* Check if the use of the antenna that ieee80211 told us to
1564 * use is possible. This will fall back to DEFAULT.
1565 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1566 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1571 if (antenna_nr == 0) {
1572 /* Zero means "use default antenna". That's always OK. */
1576 /* Get the mask of available antennas. */
1578 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1580 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1582 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1583 /* This antenna is not available. Fall back to default. */
1590 /* Convert a b43 antenna number value to the PHY TX control value. */
1591 static u16 b43_antenna_to_phyctl(int antenna)
1595 return B43_TXH_PHY_ANT0;
1597 return B43_TXH_PHY_ANT1;
1599 return B43_TXH_PHY_ANT2;
1601 return B43_TXH_PHY_ANT3;
1602 case B43_ANTENNA_AUTO0:
1603 case B43_ANTENNA_AUTO1:
1604 return B43_TXH_PHY_ANT01AUTO;
1610 static void b43_write_beacon_template(struct b43_wldev *dev,
1612 u16 shm_size_offset)
1614 unsigned int i, len, variable_len;
1615 const struct ieee80211_mgmt *bcn;
1617 bool tim_found = false;
1621 struct ieee80211_tx_info *info;
1622 unsigned long flags;
1623 struct sk_buff *beacon_skb;
1625 spin_lock_irqsave(&dev->wl->beacon_lock, flags);
1626 info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1627 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1628 /* Clone the beacon, so it cannot go away, while we write it to hw. */
1629 beacon_skb = skb_clone(dev->wl->current_beacon, GFP_ATOMIC);
1630 spin_unlock_irqrestore(&dev->wl->beacon_lock, flags);
1633 b43dbg(dev->wl, "Could not upload beacon. "
1634 "Failed to clone beacon skb.");
1638 bcn = (const struct ieee80211_mgmt *)(beacon_skb->data);
1639 len = min_t(size_t, beacon_skb->len,
1640 0x200 - sizeof(struct b43_plcp_hdr6));
1642 b43_write_template_common(dev, (const u8 *)bcn,
1643 len, ram_offset, shm_size_offset, rate);
1645 /* Write the PHY TX control parameters. */
1646 antenna = B43_ANTENNA_DEFAULT;
1647 antenna = b43_antenna_to_phyctl(antenna);
1648 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1649 /* We can't send beacons with short preamble. Would get PHY errors. */
1650 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1651 ctl &= ~B43_TXH_PHY_ANT;
1652 ctl &= ~B43_TXH_PHY_ENC;
1654 if (b43_is_cck_rate(rate))
1655 ctl |= B43_TXH_PHY_ENC_CCK;
1657 ctl |= B43_TXH_PHY_ENC_OFDM;
1658 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1660 /* Find the position of the TIM and the DTIM_period value
1661 * and write them to SHM. */
1662 ie = bcn->u.beacon.variable;
1663 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1664 for (i = 0; i < variable_len - 2; ) {
1665 uint8_t ie_id, ie_len;
1672 /* This is the TIM Information Element */
1674 /* Check whether the ie_len is in the beacon data range. */
1675 if (variable_len < ie_len + 2 + i)
1677 /* A valid TIM is at least 4 bytes long. */
1682 tim_position = sizeof(struct b43_plcp_hdr6);
1683 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1686 dtim_period = ie[i + 3];
1688 b43_shm_write16(dev, B43_SHM_SHARED,
1689 B43_SHM_SH_TIMBPOS, tim_position);
1690 b43_shm_write16(dev, B43_SHM_SHARED,
1691 B43_SHM_SH_DTIMPER, dtim_period);
1698 * If ucode wants to modify TIM do it behind the beacon, this
1699 * will happen, for example, when doing mesh networking.
1701 b43_shm_write16(dev, B43_SHM_SHARED,
1703 len + sizeof(struct b43_plcp_hdr6));
1704 b43_shm_write16(dev, B43_SHM_SHARED,
1705 B43_SHM_SH_DTIMPER, 0);
1707 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1709 dev_kfree_skb_any(beacon_skb);
1712 static void b43_upload_beacon0(struct b43_wldev *dev)
1714 struct b43_wl *wl = dev->wl;
1716 if (wl->beacon0_uploaded)
1718 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
1719 wl->beacon0_uploaded = true;
1722 static void b43_upload_beacon1(struct b43_wldev *dev)
1724 struct b43_wl *wl = dev->wl;
1726 if (wl->beacon1_uploaded)
1728 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
1729 wl->beacon1_uploaded = true;
1732 static void handle_irq_beacon(struct b43_wldev *dev)
1734 struct b43_wl *wl = dev->wl;
1735 u32 cmd, beacon0_valid, beacon1_valid;
1737 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1738 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1739 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1742 /* This is the bottom half of the asynchronous beacon update. */
1744 /* Ignore interrupt in the future. */
1745 dev->irq_mask &= ~B43_IRQ_BEACON;
1747 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1748 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1749 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1751 /* Schedule interrupt manually, if busy. */
1752 if (beacon0_valid && beacon1_valid) {
1753 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1754 dev->irq_mask |= B43_IRQ_BEACON;
1758 if (unlikely(wl->beacon_templates_virgin)) {
1759 /* We never uploaded a beacon before.
1760 * Upload both templates now, but only mark one valid. */
1761 wl->beacon_templates_virgin = false;
1762 b43_upload_beacon0(dev);
1763 b43_upload_beacon1(dev);
1764 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1765 cmd |= B43_MACCMD_BEACON0_VALID;
1766 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1768 if (!beacon0_valid) {
1769 b43_upload_beacon0(dev);
1770 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1771 cmd |= B43_MACCMD_BEACON0_VALID;
1772 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1773 } else if (!beacon1_valid) {
1774 b43_upload_beacon1(dev);
1775 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1776 cmd |= B43_MACCMD_BEACON1_VALID;
1777 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1782 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1784 u32 old_irq_mask = dev->irq_mask;
1786 /* update beacon right away or defer to irq */
1787 handle_irq_beacon(dev);
1788 if (old_irq_mask != dev->irq_mask) {
1789 /* The handler updated the IRQ mask. */
1790 B43_WARN_ON(!dev->irq_mask);
1791 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1792 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1794 /* Device interrupts are currently disabled. That means
1795 * we just ran the hardirq handler and scheduled the
1796 * IRQ thread. The thread will write the IRQ mask when
1797 * it finished, so there's nothing to do here. Writing
1798 * the mask _here_ would incorrectly re-enable IRQs. */
1803 static void b43_beacon_update_trigger_work(struct work_struct *work)
1805 struct b43_wl *wl = container_of(work, struct b43_wl,
1806 beacon_update_trigger);
1807 struct b43_wldev *dev;
1809 mutex_lock(&wl->mutex);
1810 dev = wl->current_dev;
1811 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1812 if (b43_bus_host_is_sdio(dev->dev)) {
1813 /* wl->mutex is enough. */
1814 b43_do_beacon_update_trigger_work(dev);
1817 spin_lock_irq(&wl->hardirq_lock);
1818 b43_do_beacon_update_trigger_work(dev);
1820 spin_unlock_irq(&wl->hardirq_lock);
1823 mutex_unlock(&wl->mutex);
1826 /* Asynchronously update the packet templates in template RAM. */
1827 static void b43_update_templates(struct b43_wl *wl)
1829 struct sk_buff *beacon, *old_beacon;
1830 unsigned long flags;
1832 /* This is the top half of the asynchronous beacon update.
1833 * The bottom half is the beacon IRQ.
1834 * Beacon update must be asynchronous to avoid sending an
1835 * invalid beacon. This can happen for example, if the firmware
1836 * transmits a beacon while we are updating it. */
1838 /* We could modify the existing beacon and set the aid bit in
1839 * the TIM field, but that would probably require resizing and
1840 * moving of data within the beacon template.
1841 * Simply request a new beacon and let mac80211 do the hard work. */
1842 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1843 if (unlikely(!beacon))
1846 spin_lock_irqsave(&wl->beacon_lock, flags);
1847 old_beacon = wl->current_beacon;
1848 wl->current_beacon = beacon;
1849 wl->beacon0_uploaded = false;
1850 wl->beacon1_uploaded = false;
1851 spin_unlock_irqrestore(&wl->beacon_lock, flags);
1853 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1856 dev_kfree_skb_any(old_beacon);
1859 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1862 if (dev->dev->core_rev >= 3) {
1863 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1864 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1866 b43_write16(dev, 0x606, (beacon_int >> 6));
1867 b43_write16(dev, 0x610, beacon_int);
1869 b43_time_unlock(dev);
1870 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1873 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1877 /* Read the register that contains the reason code for the panic. */
1878 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1879 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1883 b43dbg(dev->wl, "The panic reason is unknown.\n");
1885 case B43_FWPANIC_DIE:
1886 /* Do not restart the controller or firmware.
1887 * The device is nonfunctional from now on.
1888 * Restarting would result in this panic to trigger again,
1889 * so we avoid that recursion. */
1891 case B43_FWPANIC_RESTART:
1892 b43_controller_restart(dev, "Microcode panic");
1897 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1899 unsigned int i, cnt;
1900 u16 reason, marker_id, marker_line;
1903 /* The proprietary firmware doesn't have this IRQ. */
1904 if (!dev->fw.opensource)
1907 /* Read the register that contains the reason code for this IRQ. */
1908 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1911 case B43_DEBUGIRQ_PANIC:
1912 b43_handle_firmware_panic(dev);
1914 case B43_DEBUGIRQ_DUMP_SHM:
1916 break; /* Only with driver debugging enabled. */
1917 buf = kmalloc(4096, GFP_ATOMIC);
1919 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1922 for (i = 0; i < 4096; i += 2) {
1923 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1924 buf[i / 2] = cpu_to_le16(tmp);
1926 b43info(dev->wl, "Shared memory dump:\n");
1927 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1928 16, 2, buf, 4096, 1);
1931 case B43_DEBUGIRQ_DUMP_REGS:
1933 break; /* Only with driver debugging enabled. */
1934 b43info(dev->wl, "Microcode register dump:\n");
1935 for (i = 0, cnt = 0; i < 64; i++) {
1936 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1939 printk("r%02u: 0x%04X ", i, tmp);
1948 case B43_DEBUGIRQ_MARKER:
1950 break; /* Only with driver debugging enabled. */
1951 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1953 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1954 B43_MARKER_LINE_REG);
1955 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1956 "at line number %u\n",
1957 marker_id, marker_line);
1960 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1964 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1965 b43_shm_write16(dev, B43_SHM_SCRATCH,
1966 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1969 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1972 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1973 u32 merged_dma_reason = 0;
1976 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1979 reason = dev->irq_reason;
1980 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1981 dma_reason[i] = dev->dma_reason[i];
1982 merged_dma_reason |= dma_reason[i];
1985 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1986 b43err(dev->wl, "MAC transmission error\n");
1988 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1989 b43err(dev->wl, "PHY transmission error\n");
1991 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1992 atomic_set(&dev->phy.txerr_cnt,
1993 B43_PHY_TX_BADNESS_LIMIT);
1994 b43err(dev->wl, "Too many PHY TX errors, "
1995 "restarting the controller\n");
1996 b43_controller_restart(dev, "PHY TX errors");
2000 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
2002 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
2003 dma_reason[0], dma_reason[1],
2004 dma_reason[2], dma_reason[3],
2005 dma_reason[4], dma_reason[5]);
2006 b43err(dev->wl, "This device does not support DMA "
2007 "on your system. It will now be switched to PIO.\n");
2008 /* Fall back to PIO transfers if we get fatal DMA errors! */
2009 dev->use_pio = true;
2010 b43_controller_restart(dev, "DMA error");
2014 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
2015 handle_irq_ucode_debug(dev);
2016 if (reason & B43_IRQ_TBTT_INDI)
2017 handle_irq_tbtt_indication(dev);
2018 if (reason & B43_IRQ_ATIM_END)
2019 handle_irq_atim_end(dev);
2020 if (reason & B43_IRQ_BEACON)
2021 handle_irq_beacon(dev);
2022 if (reason & B43_IRQ_PMQ)
2023 handle_irq_pmq(dev);
2024 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
2026 if (reason & B43_IRQ_NOISESAMPLE_OK)
2027 handle_irq_noise(dev);
2029 /* Check the DMA reason registers for received data. */
2030 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
2032 b43warn(dev->wl, "RX descriptor underrun\n");
2033 b43_dma_handle_rx_overflow(dev->dma.rx_ring);
2035 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
2036 if (b43_using_pio_transfers(dev))
2037 b43_pio_rx(dev->pio.rx_queue);
2039 b43_dma_rx(dev->dma.rx_ring);
2041 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
2042 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
2043 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
2044 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
2045 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
2047 if (reason & B43_IRQ_TX_OK)
2048 handle_irq_transmit_status(dev);
2050 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
2051 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2054 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2056 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2057 if (reason & (1 << i))
2058 dev->irq_bit_count[i]++;
2064 /* Interrupt thread handler. Handles device interrupts in thread context. */
2065 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
2067 struct b43_wldev *dev = dev_id;
2069 mutex_lock(&dev->wl->mutex);
2070 b43_do_interrupt_thread(dev);
2072 mutex_unlock(&dev->wl->mutex);
2077 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
2081 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
2082 * On SDIO, this runs under wl->mutex. */
2084 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2085 if (reason == 0xffffffff) /* shared IRQ */
2087 reason &= dev->irq_mask;
2091 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
2093 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2095 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2097 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2099 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2102 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2106 /* ACK the interrupt. */
2107 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2108 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2109 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2110 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2111 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2112 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2114 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2117 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2118 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2119 /* Save the reason bitmasks for the IRQ thread handler. */
2120 dev->irq_reason = reason;
2122 return IRQ_WAKE_THREAD;
2125 /* Interrupt handler top-half. This runs with interrupts disabled. */
2126 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2128 struct b43_wldev *dev = dev_id;
2131 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2134 spin_lock(&dev->wl->hardirq_lock);
2135 ret = b43_do_interrupt(dev);
2137 spin_unlock(&dev->wl->hardirq_lock);
2142 /* SDIO interrupt handler. This runs in process context. */
2143 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2145 struct b43_wl *wl = dev->wl;
2148 mutex_lock(&wl->mutex);
2150 ret = b43_do_interrupt(dev);
2151 if (ret == IRQ_WAKE_THREAD)
2152 b43_do_interrupt_thread(dev);
2154 mutex_unlock(&wl->mutex);
2157 void b43_do_release_fw(struct b43_firmware_file *fw)
2159 release_firmware(fw->data);
2161 fw->filename = NULL;
2164 static void b43_release_firmware(struct b43_wldev *dev)
2166 complete(&dev->fw_load_complete);
2167 b43_do_release_fw(&dev->fw.ucode);
2168 b43_do_release_fw(&dev->fw.pcm);
2169 b43_do_release_fw(&dev->fw.initvals);
2170 b43_do_release_fw(&dev->fw.initvals_band);
2173 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2177 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2178 "and download the correct firmware for this driver version. " \
2179 "Please carefully read all instructions on this website.\n";
2187 static void b43_fw_cb(const struct firmware *firmware, void *context)
2189 struct b43_request_fw_context *ctx = context;
2191 ctx->blob = firmware;
2192 complete(&ctx->dev->fw_load_complete);
2195 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2197 struct b43_firmware_file *fw, bool async)
2199 struct b43_fw_header *hdr;
2204 /* Don't fetch anything. Free possibly cached firmware. */
2205 /* FIXME: We should probably keep it anyway, to save some headache
2206 * on suspend/resume with multiband devices. */
2207 b43_do_release_fw(fw);
2211 if ((fw->type == ctx->req_type) &&
2212 (strcmp(fw->filename, name) == 0))
2213 return 0; /* Already have this fw. */
2214 /* Free the cached firmware first. */
2215 /* FIXME: We should probably do this later after we successfully
2216 * got the new fw. This could reduce headache with multiband devices.
2217 * We could also redesign this to cache the firmware for all possible
2218 * bands all the time. */
2219 b43_do_release_fw(fw);
2222 switch (ctx->req_type) {
2223 case B43_FWTYPE_PROPRIETARY:
2224 snprintf(ctx->fwname, sizeof(ctx->fwname),
2226 modparam_fwpostfix, name);
2228 case B43_FWTYPE_OPENSOURCE:
2229 snprintf(ctx->fwname, sizeof(ctx->fwname),
2231 modparam_fwpostfix, name);
2238 /* do this part asynchronously */
2239 init_completion(&ctx->dev->fw_load_complete);
2240 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2241 ctx->dev->dev->dev, GFP_KERNEL,
2244 pr_err("Unable to load firmware\n");
2247 wait_for_completion(&ctx->dev->fw_load_complete);
2250 /* On some ARM systems, the async request will fail, but the next sync
2251 * request works. For this reason, we fall through here
2254 err = request_firmware(&ctx->blob, ctx->fwname,
2255 ctx->dev->dev->dev);
2256 if (err == -ENOENT) {
2257 snprintf(ctx->errors[ctx->req_type],
2258 sizeof(ctx->errors[ctx->req_type]),
2259 "Firmware file \"%s\" not found\n",
2263 snprintf(ctx->errors[ctx->req_type],
2264 sizeof(ctx->errors[ctx->req_type]),
2265 "Firmware file \"%s\" request failed (err=%d)\n",
2270 if (ctx->blob->size < sizeof(struct b43_fw_header))
2272 hdr = (struct b43_fw_header *)(ctx->blob->data);
2273 switch (hdr->type) {
2274 case B43_FW_TYPE_UCODE:
2275 case B43_FW_TYPE_PCM:
2276 size = be32_to_cpu(hdr->size);
2277 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
2280 case B43_FW_TYPE_IV:
2288 fw->data = ctx->blob;
2289 fw->filename = name;
2290 fw->type = ctx->req_type;
2295 snprintf(ctx->errors[ctx->req_type],
2296 sizeof(ctx->errors[ctx->req_type]),
2297 "Firmware file \"%s\" format error.\n", ctx->fwname);
2298 release_firmware(ctx->blob);
2303 /* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */
2304 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2306 struct b43_wldev *dev = ctx->dev;
2307 struct b43_firmware *fw = &ctx->dev->fw;
2308 struct b43_phy *phy = &dev->phy;
2309 const u8 rev = ctx->dev->dev->core_rev;
2310 const char *filename;
2317 if (phy->type == B43_PHYTYPE_AC)
2318 filename = "ucode42";
2321 if (phy->type == B43_PHYTYPE_AC)
2322 filename = "ucode40";
2325 if (phy->type == B43_PHYTYPE_LCN40)
2326 filename = "ucode33_lcn40";
2329 if (phy->type == B43_PHYTYPE_N)
2330 filename = "ucode30_mimo";
2333 if (phy->type == B43_PHYTYPE_HT)
2334 filename = "ucode29_mimo";
2337 if (phy->type == B43_PHYTYPE_HT)
2338 filename = "ucode26_mimo";
2342 if (phy->type == B43_PHYTYPE_N)
2343 filename = "ucode25_mimo";
2344 else if (phy->type == B43_PHYTYPE_LCN)
2345 filename = "ucode25_lcn";
2348 if (phy->type == B43_PHYTYPE_LCN)
2349 filename = "ucode24_lcn";
2352 if (phy->type == B43_PHYTYPE_N)
2353 filename = "ucode16_mimo";
2356 if (phy->type == B43_PHYTYPE_N)
2357 filename = "ucode16_mimo";
2358 else if (phy->type == B43_PHYTYPE_LP)
2359 filename = "ucode16_lp";
2362 filename = "ucode15";
2365 filename = "ucode14";
2368 filename = "ucode13";
2371 filename = "ucode11";
2374 filename = "ucode5";
2379 err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
2384 if ((rev >= 5) && (rev <= 10))
2390 fw->pcm_request_failed = false;
2391 err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
2392 if (err == -ENOENT) {
2393 /* We did not find a PCM file? Not fatal, but
2394 * core rev <= 10 must do without hwcrypto then. */
2395 fw->pcm_request_failed = true;
2401 switch (dev->phy.type) {
2404 filename = "b0g0initvals13";
2405 else if (rev >= 5 && rev <= 10)
2406 filename = "b0g0initvals5";
2410 filename = "n16initvals30";
2411 else if (rev == 28 || rev == 25)
2412 filename = "n0initvals25";
2414 filename = "n0initvals24";
2416 filename = "n0initvals16"; /* What about n0initvals22? */
2417 else if (rev >= 16 && rev <= 18)
2418 filename = "n0initvals16";
2419 else if (rev >= 11 && rev <= 12)
2420 filename = "n0initvals11";
2422 case B43_PHYTYPE_LP:
2423 if (rev >= 16 && rev <= 18)
2424 filename = "lp0initvals16";
2426 filename = "lp0initvals15";
2428 filename = "lp0initvals14";
2430 filename = "lp0initvals13";
2432 case B43_PHYTYPE_HT:
2434 filename = "ht0initvals29";
2436 filename = "ht0initvals26";
2438 case B43_PHYTYPE_LCN:
2440 filename = "lcn0initvals24";
2442 case B43_PHYTYPE_LCN40:
2444 filename = "lcn400initvals33";
2446 case B43_PHYTYPE_AC:
2448 filename = "ac1initvals42";
2450 filename = "ac0initvals40";
2454 goto err_no_initvals;
2455 err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
2459 /* Get bandswitch initvals */
2461 switch (dev->phy.type) {
2464 filename = "b0g0bsinitvals13";
2465 else if (rev >= 5 && rev <= 10)
2466 filename = "b0g0bsinitvals5";
2470 filename = "n16bsinitvals30";
2471 else if (rev == 28 || rev == 25)
2472 filename = "n0bsinitvals25";
2474 filename = "n0bsinitvals24";
2476 filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */
2477 else if (rev >= 16 && rev <= 18)
2478 filename = "n0bsinitvals16";
2479 else if (rev >= 11 && rev <= 12)
2480 filename = "n0bsinitvals11";
2482 case B43_PHYTYPE_LP:
2483 if (rev >= 16 && rev <= 18)
2484 filename = "lp0bsinitvals16";
2486 filename = "lp0bsinitvals15";
2488 filename = "lp0bsinitvals14";
2490 filename = "lp0bsinitvals13";
2492 case B43_PHYTYPE_HT:
2494 filename = "ht0bsinitvals29";
2496 filename = "ht0bsinitvals26";
2498 case B43_PHYTYPE_LCN:
2500 filename = "lcn0bsinitvals24";
2502 case B43_PHYTYPE_LCN40:
2504 filename = "lcn400bsinitvals33";
2506 case B43_PHYTYPE_AC:
2508 filename = "ac1bsinitvals42";
2510 filename = "ac0bsinitvals40";
2514 goto err_no_initvals;
2515 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
2519 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
2524 err = ctx->fatal_failure = -EOPNOTSUPP;
2525 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2526 "is required for your device (wl-core rev %u)\n", rev);
2530 err = ctx->fatal_failure = -EOPNOTSUPP;
2531 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2532 "is required for your device (wl-core rev %u)\n", rev);
2536 err = ctx->fatal_failure = -EOPNOTSUPP;
2537 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2538 "is required for your device (wl-core rev %u)\n", rev);
2542 /* We failed to load this firmware image. The error message
2543 * already is in ctx->errors. Return and let our caller decide
2548 b43_release_firmware(dev);
2552 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2553 static void b43_one_core_detach(struct b43_bus_dev *dev);
2554 static int b43_rng_init(struct b43_wl *wl);
2556 static void b43_request_firmware(struct work_struct *work)
2558 struct b43_wl *wl = container_of(work,
2559 struct b43_wl, firmware_load);
2560 struct b43_wldev *dev = wl->current_dev;
2561 struct b43_request_fw_context *ctx;
2566 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2571 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2572 err = b43_try_request_fw(ctx);
2574 goto start_ieee80211; /* Successfully loaded it. */
2575 /* Was fw version known? */
2576 if (ctx->fatal_failure)
2579 /* proprietary fw not found, try open source */
2580 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2581 err = b43_try_request_fw(ctx);
2583 goto start_ieee80211; /* Successfully loaded it. */
2584 if(ctx->fatal_failure)
2587 /* Could not find a usable firmware. Print the errors. */
2588 for (i = 0; i < B43_NR_FWTYPES; i++) {
2589 errmsg = ctx->errors[i];
2591 b43err(dev->wl, "%s", errmsg);
2593 b43_print_fw_helptext(dev->wl, 1);
2597 wl->hw->queues = B43_QOS_QUEUE_NUM;
2598 if (!modparam_qos || dev->fw.opensource)
2601 err = ieee80211_register_hw(wl->hw);
2603 goto err_one_core_detach;
2604 wl->hw_registred = true;
2605 b43_leds_register(wl->current_dev);
2607 /* Register HW RNG driver */
2612 err_one_core_detach:
2613 b43_one_core_detach(dev->dev);
2619 static int b43_upload_microcode(struct b43_wldev *dev)
2621 struct wiphy *wiphy = dev->wl->hw->wiphy;
2622 const size_t hdr_len = sizeof(struct b43_fw_header);
2624 unsigned int i, len;
2625 u16 fwrev, fwpatch, fwdate, fwtime;
2629 /* Jump the microcode PSM to offset 0 */
2630 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2631 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2632 macctl |= B43_MACCTL_PSM_JMP0;
2633 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2634 /* Zero out all microcode PSM registers and shared memory. */
2635 for (i = 0; i < 64; i++)
2636 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2637 for (i = 0; i < 4096; i += 2)
2638 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2640 /* Upload Microcode. */
2641 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2642 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2643 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2644 for (i = 0; i < len; i++) {
2645 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2649 if (dev->fw.pcm.data) {
2650 /* Upload PCM data. */
2651 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2652 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2653 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2654 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2655 /* No need for autoinc bit in SHM_HW */
2656 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2657 for (i = 0; i < len; i++) {
2658 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2663 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2665 /* Start the microcode PSM */
2666 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2667 B43_MACCTL_PSM_RUN);
2669 /* Wait for the microcode to load and respond */
2672 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2673 if (tmp == B43_IRQ_MAC_SUSPENDED)
2677 b43err(dev->wl, "Microcode not responding\n");
2678 b43_print_fw_helptext(dev->wl, 1);
2684 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2686 /* Get and check the revisions. */
2687 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2688 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2689 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2690 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2692 if (fwrev <= 0x128) {
2693 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2694 "binary drivers older than version 4.x is unsupported. "
2695 "You must upgrade your firmware files.\n");
2696 b43_print_fw_helptext(dev->wl, 1);
2700 dev->fw.rev = fwrev;
2701 dev->fw.patch = fwpatch;
2702 if (dev->fw.rev >= 598)
2703 dev->fw.hdr_format = B43_FW_HDR_598;
2704 else if (dev->fw.rev >= 410)
2705 dev->fw.hdr_format = B43_FW_HDR_410;
2707 dev->fw.hdr_format = B43_FW_HDR_351;
2708 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
2710 dev->qos_enabled = dev->wl->hw->queues > 1;
2711 /* Default to firmware/hardware crypto acceleration. */
2712 dev->hwcrypto_enabled = true;
2714 if (dev->fw.opensource) {
2717 /* Patchlevel info is encoded in the "time" field. */
2718 dev->fw.patch = fwtime;
2719 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2720 dev->fw.rev, dev->fw.patch);
2722 fwcapa = b43_fwcapa_read(dev);
2723 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2724 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2725 /* Disable hardware crypto and fall back to software crypto. */
2726 dev->hwcrypto_enabled = false;
2728 /* adding QoS support should use an offline discovery mechanism */
2729 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
2731 b43info(dev->wl, "Loading firmware version %u.%u "
2732 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2734 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2735 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2736 if (dev->fw.pcm_request_failed) {
2737 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2738 "Hardware accelerated cryptography is disabled.\n");
2739 b43_print_fw_helptext(dev->wl, 0);
2743 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2744 dev->fw.rev, dev->fw.patch);
2745 wiphy->hw_version = dev->dev->core_id;
2747 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2748 /* We're over the deadline, but we keep support for old fw
2749 * until it turns out to be in major conflict with something new. */
2750 b43warn(dev->wl, "You are using an old firmware image. "
2751 "Support for old firmware will be removed soon "
2752 "(official deadline was July 2008).\n");
2753 b43_print_fw_helptext(dev->wl, 0);
2759 /* Stop the microcode PSM. */
2760 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2761 B43_MACCTL_PSM_JMP0);
2766 static int b43_write_initvals(struct b43_wldev *dev,
2767 const struct b43_iv *ivals,
2771 const struct b43_iv *iv;
2776 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2778 for (i = 0; i < count; i++) {
2779 if (array_size < sizeof(iv->offset_size))
2781 array_size -= sizeof(iv->offset_size);
2782 offset = be16_to_cpu(iv->offset_size);
2783 bit32 = !!(offset & B43_IV_32BIT);
2784 offset &= B43_IV_OFFSET_MASK;
2785 if (offset >= 0x1000)
2790 if (array_size < sizeof(iv->data.d32))
2792 array_size -= sizeof(iv->data.d32);
2794 value = get_unaligned_be32(&iv->data.d32);
2795 b43_write32(dev, offset, value);
2797 iv = (const struct b43_iv *)((const uint8_t *)iv +
2803 if (array_size < sizeof(iv->data.d16))
2805 array_size -= sizeof(iv->data.d16);
2807 value = be16_to_cpu(iv->data.d16);
2808 b43_write16(dev, offset, value);
2810 iv = (const struct b43_iv *)((const uint8_t *)iv +
2821 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2822 b43_print_fw_helptext(dev->wl, 1);
2827 static int b43_upload_initvals(struct b43_wldev *dev)
2829 const size_t hdr_len = sizeof(struct b43_fw_header);
2830 const struct b43_fw_header *hdr;
2831 struct b43_firmware *fw = &dev->fw;
2832 const struct b43_iv *ivals;
2835 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2836 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2837 count = be32_to_cpu(hdr->size);
2838 return b43_write_initvals(dev, ivals, count,
2839 fw->initvals.data->size - hdr_len);
2842 static int b43_upload_initvals_band(struct b43_wldev *dev)
2844 const size_t hdr_len = sizeof(struct b43_fw_header);
2845 const struct b43_fw_header *hdr;
2846 struct b43_firmware *fw = &dev->fw;
2847 const struct b43_iv *ivals;
2850 if (!fw->initvals_band.data)
2853 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2854 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2855 count = be32_to_cpu(hdr->size);
2856 return b43_write_initvals(dev, ivals, count,
2857 fw->initvals_band.data->size - hdr_len);
2860 /* Initialize the GPIOs
2861 * http://bcm-specs.sipsolutions.net/GPIO
2864 #ifdef CONFIG_B43_SSB
2865 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2867 struct ssb_bus *bus = dev->dev->sdev->bus;
2869 #ifdef CONFIG_SSB_DRIVER_PCICORE
2870 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2872 return bus->chipco.dev;
2877 static int b43_gpio_init(struct b43_wldev *dev)
2879 #ifdef CONFIG_B43_SSB
2880 struct ssb_device *gpiodev;
2884 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2885 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2889 if (dev->dev->chip_id == 0x4301) {
2892 } else if (dev->dev->chip_id == 0x5354) {
2893 /* Don't allow overtaking buttons GPIOs */
2894 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
2897 if (0 /* FIXME: conditional unknown */ ) {
2898 b43_write16(dev, B43_MMIO_GPIO_MASK,
2899 b43_read16(dev, B43_MMIO_GPIO_MASK)
2901 /* BT Coexistance Input */
2904 /* BT Coexistance Out */
2908 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2909 /* PA is controlled by gpio 9, let ucode handle it */
2910 b43_write16(dev, B43_MMIO_GPIO_MASK,
2911 b43_read16(dev, B43_MMIO_GPIO_MASK)
2917 switch (dev->dev->bus_type) {
2918 #ifdef CONFIG_B43_BCMA
2920 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
2923 #ifdef CONFIG_B43_SSB
2925 gpiodev = b43_ssb_gpio_dev(dev);
2927 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2928 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2937 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2938 static void b43_gpio_cleanup(struct b43_wldev *dev)
2940 #ifdef CONFIG_B43_SSB
2941 struct ssb_device *gpiodev;
2944 switch (dev->dev->bus_type) {
2945 #ifdef CONFIG_B43_BCMA
2947 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
2950 #ifdef CONFIG_B43_SSB
2952 gpiodev = b43_ssb_gpio_dev(dev);
2954 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2960 /* http://bcm-specs.sipsolutions.net/EnableMac */
2961 void b43_mac_enable(struct b43_wldev *dev)
2963 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2966 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2967 B43_SHM_SH_UCODESTAT);
2968 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2969 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2970 b43err(dev->wl, "b43_mac_enable(): The firmware "
2971 "should be suspended, but current state is %u\n",
2976 dev->mac_suspended--;
2977 B43_WARN_ON(dev->mac_suspended < 0);
2978 if (dev->mac_suspended == 0) {
2979 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2980 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2981 B43_IRQ_MAC_SUSPENDED);
2983 b43_read32(dev, B43_MMIO_MACCTL);
2984 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2985 b43_power_saving_ctl_bits(dev, 0);
2989 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2990 void b43_mac_suspend(struct b43_wldev *dev)
2996 B43_WARN_ON(dev->mac_suspended < 0);
2998 if (dev->mac_suspended == 0) {
2999 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
3000 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
3001 /* force pci to flush the write */
3002 b43_read32(dev, B43_MMIO_MACCTL);
3003 for (i = 35; i; i--) {
3004 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
3005 if (tmp & B43_IRQ_MAC_SUSPENDED)
3009 /* Hm, it seems this will take some time. Use msleep(). */
3010 for (i = 40; i; i--) {
3011 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
3012 if (tmp & B43_IRQ_MAC_SUSPENDED)
3016 b43err(dev->wl, "MAC suspend failed\n");
3019 dev->mac_suspended++;
3022 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3023 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3027 switch (dev->dev->bus_type) {
3028 #ifdef CONFIG_B43_BCMA
3030 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3032 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
3034 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
3035 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3038 #ifdef CONFIG_B43_SSB
3040 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3042 tmp |= B43_TMSLOW_MACPHYCLKEN;
3044 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
3045 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3051 /* brcms_b_switch_macfreq */
3052 void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode)
3054 u16 chip_id = dev->dev->chip_id;
3056 if (chip_id == BCMA_CHIP_ID_BCM4331) {
3058 case 2: /* 168 Mhz: 2^26/168 = 0x61862 */
3059 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x1862);
3060 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3062 case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */
3063 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x3e70);
3064 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3066 default: /* 160 Mhz: 2^26/160 = 0x66666 */
3067 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x6666);
3068 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6);
3071 } else if (chip_id == BCMA_CHIP_ID_BCM43131 ||
3072 chip_id == BCMA_CHIP_ID_BCM43217 ||
3073 chip_id == BCMA_CHIP_ID_BCM43222 ||
3074 chip_id == BCMA_CHIP_ID_BCM43224 ||
3075 chip_id == BCMA_CHIP_ID_BCM43225 ||
3076 chip_id == BCMA_CHIP_ID_BCM43227 ||
3077 chip_id == BCMA_CHIP_ID_BCM43228) {
3079 case 2: /* 126 Mhz */
3080 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082);
3081 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3083 case 1: /* 123 Mhz */
3084 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341);
3085 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3087 default: /* 120 Mhz */
3088 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889);
3089 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
3092 } else if (dev->phy.type == B43_PHYTYPE_LCN) {
3094 case 1: /* 82 Mhz */
3095 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0);
3096 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3098 default: /* 80 Mhz */
3099 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD);
3100 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
3106 static void b43_adjust_opmode(struct b43_wldev *dev)
3108 struct b43_wl *wl = dev->wl;
3112 ctl = b43_read32(dev, B43_MMIO_MACCTL);
3113 /* Reset status to STA infrastructure mode. */
3114 ctl &= ~B43_MACCTL_AP;
3115 ctl &= ~B43_MACCTL_KEEP_CTL;
3116 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
3117 ctl &= ~B43_MACCTL_KEEP_BAD;
3118 ctl &= ~B43_MACCTL_PROMISC;
3119 ctl &= ~B43_MACCTL_BEACPROMISC;
3120 ctl |= B43_MACCTL_INFRA;
3122 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3123 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
3124 ctl |= B43_MACCTL_AP;
3125 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
3126 ctl &= ~B43_MACCTL_INFRA;
3128 if (wl->filter_flags & FIF_CONTROL)
3129 ctl |= B43_MACCTL_KEEP_CTL;
3130 if (wl->filter_flags & FIF_FCSFAIL)
3131 ctl |= B43_MACCTL_KEEP_BAD;
3132 if (wl->filter_flags & FIF_PLCPFAIL)
3133 ctl |= B43_MACCTL_KEEP_BADPLCP;
3134 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
3135 ctl |= B43_MACCTL_BEACPROMISC;
3137 /* Workaround: On old hardware the HW-MAC-address-filter
3138 * doesn't work properly, so always run promisc in filter
3139 * it in software. */
3140 if (dev->dev->core_rev <= 4)
3141 ctl |= B43_MACCTL_PROMISC;
3143 b43_write32(dev, B43_MMIO_MACCTL, ctl);
3146 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
3147 if (dev->dev->chip_id == 0x4306 &&
3148 dev->dev->chip_rev == 3)
3153 b43_write16(dev, 0x612, cfp_pretbtt);
3155 /* FIXME: We don't currently implement the PMQ mechanism,
3156 * so always disable it. If we want to implement PMQ,
3157 * we need to enable it here (clear DISCPMQ) in AP mode.
3159 if (0 /* ctl & B43_MACCTL_AP */)
3160 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
3162 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
3165 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
3171 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
3174 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
3176 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
3177 b43_shm_read16(dev, B43_SHM_SHARED, offset));
3180 static void b43_rate_memory_init(struct b43_wldev *dev)
3182 switch (dev->phy.type) {
3186 case B43_PHYTYPE_LP:
3187 case B43_PHYTYPE_HT:
3188 case B43_PHYTYPE_LCN:
3189 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
3190 b43_rate_memory_write(dev, B43_OFDM_RATE_9MB, 1);
3191 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
3192 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
3193 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
3194 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
3195 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
3196 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
3197 if (dev->phy.type == B43_PHYTYPE_A)
3201 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3202 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3203 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3204 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3211 /* Set the default values for the PHY TX Control Words. */
3212 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3216 ctl |= B43_TXH_PHY_ENC_CCK;
3217 ctl |= B43_TXH_PHY_ANT01AUTO;
3218 ctl |= B43_TXH_PHY_TXPWR;
3220 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3221 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3222 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3225 /* Set the TX-Antenna for management frames sent by firmware. */
3226 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3231 ant = b43_antenna_to_phyctl(antenna);
3234 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3235 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3236 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3237 /* For Probe Resposes */
3238 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3239 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3240 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3243 /* This is the opposite of b43_chip_init() */
3244 static void b43_chip_exit(struct b43_wldev *dev)
3247 b43_gpio_cleanup(dev);
3248 /* firmware is released later */
3251 /* Initialize the chip
3252 * http://bcm-specs.sipsolutions.net/ChipInit
3254 static int b43_chip_init(struct b43_wldev *dev)
3256 struct b43_phy *phy = &dev->phy;
3261 /* Initialize the MAC control */
3262 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3264 macctl |= B43_MACCTL_GMODE;
3265 macctl |= B43_MACCTL_INFRA;
3266 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3268 err = b43_upload_microcode(dev);
3270 goto out; /* firmware is released later */
3272 err = b43_gpio_init(dev);
3274 goto out; /* firmware is released later */
3276 err = b43_upload_initvals(dev);
3278 goto err_gpio_clean;
3280 err = b43_upload_initvals_band(dev);
3282 goto err_gpio_clean;
3284 /* Turn the Analog on and initialize the PHY. */
3285 phy->ops->switch_analog(dev, 1);
3286 err = b43_phy_init(dev);
3288 goto err_gpio_clean;
3290 /* Disable Interference Mitigation. */
3291 if (phy->ops->interf_mitigation)
3292 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3294 /* Select the antennae */
3295 if (phy->ops->set_rx_antenna)
3296 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3297 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3299 if (phy->type == B43_PHYTYPE_B) {
3300 value16 = b43_read16(dev, 0x005E);
3302 b43_write16(dev, 0x005E, value16);
3304 b43_write32(dev, 0x0100, 0x01000000);
3305 if (dev->dev->core_rev < 5)
3306 b43_write32(dev, 0x010C, 0x01000000);
3308 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3309 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3311 /* Probe Response Timeout value */
3312 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3313 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
3315 /* Initially set the wireless operation mode. */
3316 b43_adjust_opmode(dev);
3318 if (dev->dev->core_rev < 3) {
3319 b43_write16(dev, 0x060E, 0x0000);
3320 b43_write16(dev, 0x0610, 0x8000);
3321 b43_write16(dev, 0x0604, 0x0000);
3322 b43_write16(dev, 0x0606, 0x0200);
3324 b43_write32(dev, 0x0188, 0x80000000);
3325 b43_write32(dev, 0x018C, 0x02000000);
3327 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3328 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
3329 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3330 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3331 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3332 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3333 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3335 b43_mac_phy_clock_set(dev, true);
3337 switch (dev->dev->bus_type) {
3338 #ifdef CONFIG_B43_BCMA
3340 /* FIXME: 0xE74 is quite common, but should be read from CC */
3341 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3344 #ifdef CONFIG_B43_SSB
3346 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3347 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3353 b43dbg(dev->wl, "Chip initialized\n");
3358 b43_gpio_cleanup(dev);
3362 static void b43_periodic_every60sec(struct b43_wldev *dev)
3364 const struct b43_phy_operations *ops = dev->phy.ops;
3366 if (ops->pwork_60sec)
3367 ops->pwork_60sec(dev);
3369 /* Force check the TX power emission now. */
3370 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3373 static void b43_periodic_every30sec(struct b43_wldev *dev)
3375 /* Update device statistics. */
3376 b43_calculate_link_quality(dev);
3379 static void b43_periodic_every15sec(struct b43_wldev *dev)
3381 struct b43_phy *phy = &dev->phy;
3384 if (dev->fw.opensource) {
3385 /* Check if the firmware is still alive.
3386 * It will reset the watchdog counter to 0 in its idle loop. */
3387 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3388 if (unlikely(wdr)) {
3389 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3390 b43_controller_restart(dev, "Firmware watchdog");
3393 b43_shm_write16(dev, B43_SHM_SCRATCH,
3394 B43_WATCHDOG_REG, 1);
3398 if (phy->ops->pwork_15sec)
3399 phy->ops->pwork_15sec(dev);
3401 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3405 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3408 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3409 dev->irq_count / 15,
3411 dev->rx_count / 15);
3415 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3416 if (dev->irq_bit_count[i]) {
3417 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3418 dev->irq_bit_count[i] / 15, i, (1 << i));
3419 dev->irq_bit_count[i] = 0;
3426 static void do_periodic_work(struct b43_wldev *dev)
3430 state = dev->periodic_state;
3432 b43_periodic_every60sec(dev);
3434 b43_periodic_every30sec(dev);
3435 b43_periodic_every15sec(dev);
3438 /* Periodic work locking policy:
3439 * The whole periodic work handler is protected by
3440 * wl->mutex. If another lock is needed somewhere in the
3441 * pwork callchain, it's acquired in-place, where it's needed.
3443 static void b43_periodic_work_handler(struct work_struct *work)
3445 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3446 periodic_work.work);
3447 struct b43_wl *wl = dev->wl;
3448 unsigned long delay;
3450 mutex_lock(&wl->mutex);
3452 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3454 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3457 do_periodic_work(dev);
3459 dev->periodic_state++;
3461 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3462 delay = msecs_to_jiffies(50);
3464 delay = round_jiffies_relative(HZ * 15);
3465 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3467 mutex_unlock(&wl->mutex);
3470 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3472 struct delayed_work *work = &dev->periodic_work;
3474 dev->periodic_state = 0;
3475 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3476 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3479 /* Check if communication with the device works correctly. */
3480 static int b43_validate_chipaccess(struct b43_wldev *dev)
3482 u32 v, backup0, backup4;
3484 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3485 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3487 /* Check for read/write and endianness problems. */
3488 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3489 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3491 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3492 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3495 /* Check if unaligned 32bit SHM_SHARED access works properly.
3496 * However, don't bail out on failure, because it's noncritical. */
3497 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3498 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3499 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3500 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3501 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3502 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3503 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3504 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3505 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3506 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3507 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3508 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3510 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3511 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3513 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3514 /* The 32bit register shadows the two 16bit registers
3515 * with update sideeffects. Validate this. */
3516 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3517 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3518 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3520 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3523 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3525 v = b43_read32(dev, B43_MMIO_MACCTL);
3526 v |= B43_MACCTL_GMODE;
3527 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3532 b43err(dev->wl, "Failed to validate the chipaccess\n");
3536 static void b43_security_init(struct b43_wldev *dev)
3538 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3539 /* KTP is a word address, but we address SHM bytewise.
3540 * So multiply by two.
3543 /* Number of RCMTA address slots */
3544 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3545 /* Clear the key memory. */
3546 b43_clear_keys(dev);
3549 #ifdef CONFIG_B43_HWRNG
3550 static int b43_rng_read(struct hwrng *rng, u32 *data)
3552 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3553 struct b43_wldev *dev;
3554 int count = -ENODEV;
3556 mutex_lock(&wl->mutex);
3557 dev = wl->current_dev;
3558 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3559 *data = b43_read16(dev, B43_MMIO_RNG);
3560 count = sizeof(u16);
3562 mutex_unlock(&wl->mutex);
3566 #endif /* CONFIG_B43_HWRNG */
3568 static void b43_rng_exit(struct b43_wl *wl)
3570 #ifdef CONFIG_B43_HWRNG
3571 if (wl->rng_initialized)
3572 hwrng_unregister(&wl->rng);
3573 #endif /* CONFIG_B43_HWRNG */
3576 static int b43_rng_init(struct b43_wl *wl)
3580 #ifdef CONFIG_B43_HWRNG
3581 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3582 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3583 wl->rng.name = wl->rng_name;
3584 wl->rng.data_read = b43_rng_read;
3585 wl->rng.priv = (unsigned long)wl;
3586 wl->rng_initialized = true;
3587 err = hwrng_register(&wl->rng);
3589 wl->rng_initialized = false;
3590 b43err(wl, "Failed to register the random "
3591 "number generator (%d)\n", err);
3593 #endif /* CONFIG_B43_HWRNG */
3598 static void b43_tx_work(struct work_struct *work)
3600 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3601 struct b43_wldev *dev;
3602 struct sk_buff *skb;
3606 mutex_lock(&wl->mutex);
3607 dev = wl->current_dev;
3608 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3609 mutex_unlock(&wl->mutex);
3613 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3614 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3615 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3616 if (b43_using_pio_transfers(dev))
3617 err = b43_pio_tx(dev, skb);
3619 err = b43_dma_tx(dev, skb);
3620 if (err == -ENOSPC) {
3621 wl->tx_queue_stopped[queue_num] = 1;
3622 ieee80211_stop_queue(wl->hw, queue_num);
3623 skb_queue_head(&wl->tx_queue[queue_num], skb);
3627 ieee80211_free_txskb(wl->hw, skb);
3632 wl->tx_queue_stopped[queue_num] = 0;
3638 mutex_unlock(&wl->mutex);
3641 static void b43_op_tx(struct ieee80211_hw *hw,
3642 struct ieee80211_tx_control *control,
3643 struct sk_buff *skb)
3645 struct b43_wl *wl = hw_to_b43_wl(hw);
3647 if (unlikely(skb->len < 2 + 2 + 6)) {
3648 /* Too short, this can't be a valid frame. */
3649 ieee80211_free_txskb(hw, skb);
3652 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3654 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3655 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3656 ieee80211_queue_work(wl->hw, &wl->tx_work);
3658 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3662 static void b43_qos_params_upload(struct b43_wldev *dev,
3663 const struct ieee80211_tx_queue_params *p,
3666 u16 params[B43_NR_QOSPARAMS];
3670 if (!dev->qos_enabled)
3673 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3675 memset(¶ms, 0, sizeof(params));
3677 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3678 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3679 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3680 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3681 params[B43_QOSPARAM_AIFS] = p->aifs;
3682 params[B43_QOSPARAM_BSLOTS] = bslots;
3683 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3685 for (i = 0; i < ARRAY_SIZE(params); i++) {
3686 if (i == B43_QOSPARAM_STATUS) {
3687 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3688 shm_offset + (i * 2));
3689 /* Mark the parameters as updated. */
3691 b43_shm_write16(dev, B43_SHM_SHARED,
3692 shm_offset + (i * 2),
3695 b43_shm_write16(dev, B43_SHM_SHARED,
3696 shm_offset + (i * 2),
3702 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3703 static const u16 b43_qos_shm_offsets[] = {
3704 /* [mac80211-queue-nr] = SHM_OFFSET, */
3705 [0] = B43_QOS_VOICE,
3706 [1] = B43_QOS_VIDEO,
3707 [2] = B43_QOS_BESTEFFORT,
3708 [3] = B43_QOS_BACKGROUND,
3711 /* Update all QOS parameters in hardware. */
3712 static void b43_qos_upload_all(struct b43_wldev *dev)
3714 struct b43_wl *wl = dev->wl;
3715 struct b43_qos_params *params;
3718 if (!dev->qos_enabled)
3721 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3722 ARRAY_SIZE(wl->qos_params));
3724 b43_mac_suspend(dev);
3725 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3726 params = &(wl->qos_params[i]);
3727 b43_qos_params_upload(dev, &(params->p),
3728 b43_qos_shm_offsets[i]);
3730 b43_mac_enable(dev);
3733 static void b43_qos_clear(struct b43_wl *wl)
3735 struct b43_qos_params *params;
3738 /* Initialize QoS parameters to sane defaults. */
3740 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3741 ARRAY_SIZE(wl->qos_params));
3743 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3744 params = &(wl->qos_params[i]);
3746 switch (b43_qos_shm_offsets[i]) {
3750 params->p.cw_min = 0x0001;
3751 params->p.cw_max = 0x0001;
3756 params->p.cw_min = 0x0001;
3757 params->p.cw_max = 0x0001;
3759 case B43_QOS_BESTEFFORT:
3762 params->p.cw_min = 0x0001;
3763 params->p.cw_max = 0x03FF;
3765 case B43_QOS_BACKGROUND:
3768 params->p.cw_min = 0x0001;
3769 params->p.cw_max = 0x03FF;
3777 /* Initialize the core's QOS capabilities */
3778 static void b43_qos_init(struct b43_wldev *dev)
3780 if (!dev->qos_enabled) {
3781 /* Disable QOS support. */
3782 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3783 b43_write16(dev, B43_MMIO_IFSCTL,
3784 b43_read16(dev, B43_MMIO_IFSCTL)
3785 & ~B43_MMIO_IFSCTL_USE_EDCF);
3786 b43dbg(dev->wl, "QoS disabled\n");
3790 /* Upload the current QOS parameters. */
3791 b43_qos_upload_all(dev);
3793 /* Enable QOS support. */
3794 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3795 b43_write16(dev, B43_MMIO_IFSCTL,
3796 b43_read16(dev, B43_MMIO_IFSCTL)
3797 | B43_MMIO_IFSCTL_USE_EDCF);
3798 b43dbg(dev->wl, "QoS enabled\n");
3801 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3802 struct ieee80211_vif *vif, u16 _queue,
3803 const struct ieee80211_tx_queue_params *params)
3805 struct b43_wl *wl = hw_to_b43_wl(hw);
3806 struct b43_wldev *dev;
3807 unsigned int queue = (unsigned int)_queue;
3810 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3811 /* Queue not available or don't support setting
3812 * params on this queue. Return success to not
3813 * confuse mac80211. */
3816 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3817 ARRAY_SIZE(wl->qos_params));
3819 mutex_lock(&wl->mutex);
3820 dev = wl->current_dev;
3821 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3824 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3825 b43_mac_suspend(dev);
3826 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3827 b43_qos_shm_offsets[queue]);
3828 b43_mac_enable(dev);
3832 mutex_unlock(&wl->mutex);
3837 static int b43_op_get_stats(struct ieee80211_hw *hw,
3838 struct ieee80211_low_level_stats *stats)
3840 struct b43_wl *wl = hw_to_b43_wl(hw);
3842 mutex_lock(&wl->mutex);
3843 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3844 mutex_unlock(&wl->mutex);
3849 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3851 struct b43_wl *wl = hw_to_b43_wl(hw);
3852 struct b43_wldev *dev;
3855 mutex_lock(&wl->mutex);
3856 dev = wl->current_dev;
3858 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3859 b43_tsf_read(dev, &tsf);
3863 mutex_unlock(&wl->mutex);
3868 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3869 struct ieee80211_vif *vif, u64 tsf)
3871 struct b43_wl *wl = hw_to_b43_wl(hw);
3872 struct b43_wldev *dev;
3874 mutex_lock(&wl->mutex);
3875 dev = wl->current_dev;
3877 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3878 b43_tsf_write(dev, tsf);
3880 mutex_unlock(&wl->mutex);
3883 static const char *band_to_string(enum ieee80211_band band)
3886 case IEEE80211_BAND_5GHZ:
3888 case IEEE80211_BAND_2GHZ:
3897 /* Expects wl->mutex locked */
3898 static int b43_switch_band(struct b43_wldev *dev,
3899 struct ieee80211_channel *chan)
3901 struct b43_phy *phy = &dev->phy;
3905 switch (chan->band) {
3906 case IEEE80211_BAND_5GHZ:
3909 case IEEE80211_BAND_2GHZ:
3917 if (!((gmode && phy->supports_2ghz) ||
3918 (!gmode && phy->supports_5ghz))) {
3919 b43err(dev->wl, "This device doesn't support %s-GHz band\n",
3920 band_to_string(chan->band));
3924 if (!!phy->gmode == !!gmode) {
3925 /* This device is already running. */
3929 b43dbg(dev->wl, "Switching to %s GHz band\n",
3930 band_to_string(chan->band));
3932 /* Some new devices don't need disabling radio for band switching */
3933 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3))
3934 b43_software_rfkill(dev, true);
3937 b43_phy_put_into_reset(dev);
3938 switch (dev->dev->bus_type) {
3939 #ifdef CONFIG_B43_BCMA
3941 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
3943 tmp |= B43_BCMA_IOCTL_GMODE;
3945 tmp &= ~B43_BCMA_IOCTL_GMODE;
3946 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
3949 #ifdef CONFIG_B43_SSB
3951 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3953 tmp |= B43_TMSLOW_GMODE;
3955 tmp &= ~B43_TMSLOW_GMODE;
3956 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3960 b43_phy_take_out_of_reset(dev);
3962 b43_upload_initvals_band(dev);
3969 static void b43_set_beacon_listen_interval(struct b43_wldev *dev, u16 interval)
3971 interval = min_t(u16, interval, (u16)0xFF);
3972 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BCN_LI, interval);
3975 /* Write the short and long frame retry limit values. */
3976 static void b43_set_retry_limits(struct b43_wldev *dev,
3977 unsigned int short_retry,
3978 unsigned int long_retry)
3980 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3981 * the chip-internal counter. */
3982 short_retry = min(short_retry, (unsigned int)0xF);
3983 long_retry = min(long_retry, (unsigned int)0xF);
3985 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3987 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3991 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3993 struct b43_wl *wl = hw_to_b43_wl(hw);
3994 struct b43_wldev *dev = wl->current_dev;
3995 struct b43_phy *phy = &dev->phy;
3996 struct ieee80211_conf *conf = &hw->conf;
4000 mutex_lock(&wl->mutex);
4001 b43_mac_suspend(dev);
4003 if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL)
4004 b43_set_beacon_listen_interval(dev, conf->listen_interval);
4006 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
4007 phy->chandef = &conf->chandef;
4008 phy->channel = conf->chandef.chan->hw_value;
4010 /* Switch the band (if necessary). */
4011 err = b43_switch_band(dev, conf->chandef.chan);
4013 goto out_mac_enable;
4015 /* Switch to the requested channel.
4016 * The firmware takes care of races with the TX handler.
4018 b43_switch_channel(dev, phy->channel);
4021 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4022 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
4023 conf->long_frame_max_tx_count);
4024 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
4026 goto out_mac_enable;
4028 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
4030 /* Adjust the desired TX power level. */
4031 if (conf->power_level != 0) {
4032 if (conf->power_level != phy->desired_txpower) {
4033 phy->desired_txpower = conf->power_level;
4034 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
4035 B43_TXPWR_IGNORE_TSSI);
4039 /* Antennas for RX and management frame TX. */
4040 antenna = B43_ANTENNA_DEFAULT;
4041 b43_mgmtframe_txantenna(dev, antenna);
4042 antenna = B43_ANTENNA_DEFAULT;
4043 if (phy->ops->set_rx_antenna)
4044 phy->ops->set_rx_antenna(dev, antenna);
4046 if (wl->radio_enabled != phy->radio_on) {
4047 if (wl->radio_enabled) {
4048 b43_software_rfkill(dev, false);
4049 b43info(dev->wl, "Radio turned on by software\n");
4050 if (!dev->radio_hw_enable) {
4051 b43info(dev->wl, "The hardware RF-kill button "
4052 "still turns the radio physically off. "
4053 "Press the button to turn it on.\n");
4056 b43_software_rfkill(dev, true);
4057 b43info(dev->wl, "Radio turned off by software\n");
4062 b43_mac_enable(dev);
4063 mutex_unlock(&wl->mutex);
4068 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
4070 struct ieee80211_supported_band *sband =
4071 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
4072 struct ieee80211_rate *rate;
4074 u16 basic, direct, offset, basic_offset, rateptr;
4076 for (i = 0; i < sband->n_bitrates; i++) {
4077 rate = &sband->bitrates[i];
4079 if (b43_is_cck_rate(rate->hw_value)) {
4080 direct = B43_SHM_SH_CCKDIRECT;
4081 basic = B43_SHM_SH_CCKBASIC;
4082 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4085 direct = B43_SHM_SH_OFDMDIRECT;
4086 basic = B43_SHM_SH_OFDMBASIC;
4087 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4091 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
4093 if (b43_is_cck_rate(rate->hw_value)) {
4094 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
4095 basic_offset &= 0xF;
4097 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
4098 basic_offset &= 0xF;
4102 * Get the pointer that we need to point to
4103 * from the direct map
4105 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
4106 direct + 2 * basic_offset);
4107 /* and write it to the basic map */
4108 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
4113 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
4114 struct ieee80211_vif *vif,
4115 struct ieee80211_bss_conf *conf,
4118 struct b43_wl *wl = hw_to_b43_wl(hw);
4119 struct b43_wldev *dev;
4121 mutex_lock(&wl->mutex);
4123 dev = wl->current_dev;
4124 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4125 goto out_unlock_mutex;
4127 B43_WARN_ON(wl->vif != vif);
4129 if (changed & BSS_CHANGED_BSSID) {
4131 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
4133 eth_zero_addr(wl->bssid);
4136 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
4137 if (changed & BSS_CHANGED_BEACON &&
4138 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4139 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4140 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
4141 b43_update_templates(wl);
4143 if (changed & BSS_CHANGED_BSSID)
4144 b43_write_mac_bssid_templates(dev);
4147 b43_mac_suspend(dev);
4149 /* Update templates for AP/mesh mode. */
4150 if (changed & BSS_CHANGED_BEACON_INT &&
4151 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4152 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4153 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4155 b43_set_beacon_int(dev, conf->beacon_int);
4157 if (changed & BSS_CHANGED_BASIC_RATES)
4158 b43_update_basic_rates(dev, conf->basic_rates);
4160 if (changed & BSS_CHANGED_ERP_SLOT) {
4161 if (conf->use_short_slot)
4162 b43_short_slot_timing_enable(dev);
4164 b43_short_slot_timing_disable(dev);
4167 b43_mac_enable(dev);
4169 mutex_unlock(&wl->mutex);
4172 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4173 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4174 struct ieee80211_key_conf *key)
4176 struct b43_wl *wl = hw_to_b43_wl(hw);
4177 struct b43_wldev *dev;
4181 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4183 if (modparam_nohwcrypt)
4184 return -ENOSPC; /* User disabled HW-crypto */
4186 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4187 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4188 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4189 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4190 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4192 * For now, disable hw crypto for the RSN IBSS group keys. This
4193 * could be optimized in the future, but until that gets
4194 * implemented, use of software crypto for group addressed
4195 * frames is a acceptable to allow RSN IBSS to be used.
4200 mutex_lock(&wl->mutex);
4202 dev = wl->current_dev;
4204 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4207 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4208 /* We don't have firmware for the crypto engine.
4209 * Must use software-crypto. */
4215 switch (key->cipher) {
4216 case WLAN_CIPHER_SUITE_WEP40:
4217 algorithm = B43_SEC_ALGO_WEP40;
4219 case WLAN_CIPHER_SUITE_WEP104:
4220 algorithm = B43_SEC_ALGO_WEP104;
4222 case WLAN_CIPHER_SUITE_TKIP:
4223 algorithm = B43_SEC_ALGO_TKIP;
4225 case WLAN_CIPHER_SUITE_CCMP:
4226 algorithm = B43_SEC_ALGO_AES;
4232 index = (u8) (key->keyidx);
4238 if (algorithm == B43_SEC_ALGO_TKIP &&
4239 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4240 !modparam_hwtkip)) {
4241 /* We support only pairwise key */
4246 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4247 if (WARN_ON(!sta)) {
4251 /* Pairwise key with an assigned MAC address. */
4252 err = b43_key_write(dev, -1, algorithm,
4253 key->key, key->keylen,
4257 err = b43_key_write(dev, index, algorithm,
4258 key->key, key->keylen, NULL, key);
4263 if (algorithm == B43_SEC_ALGO_WEP40 ||
4264 algorithm == B43_SEC_ALGO_WEP104) {
4265 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4268 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4270 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4271 if (algorithm == B43_SEC_ALGO_TKIP)
4272 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4275 err = b43_key_clear(dev, key->hw_key_idx);
4286 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4288 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4289 sta ? sta->addr : bcast_addr);
4290 b43_dump_keymemory(dev);
4292 mutex_unlock(&wl->mutex);
4297 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4298 unsigned int changed, unsigned int *fflags,
4301 struct b43_wl *wl = hw_to_b43_wl(hw);
4302 struct b43_wldev *dev;
4304 mutex_lock(&wl->mutex);
4305 dev = wl->current_dev;
4311 *fflags &= FIF_ALLMULTI |
4316 FIF_BCN_PRBRESP_PROMISC;
4318 changed &= FIF_ALLMULTI |
4323 FIF_BCN_PRBRESP_PROMISC;
4325 wl->filter_flags = *fflags;
4327 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4328 b43_adjust_opmode(dev);
4331 mutex_unlock(&wl->mutex);
4334 /* Locking: wl->mutex
4335 * Returns the current dev. This might be different from the passed in dev,
4336 * because the core might be gone away while we unlocked the mutex. */
4337 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4340 struct b43_wldev *orig_dev;
4348 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4351 /* Cancel work. Unlock to avoid deadlocks. */
4352 mutex_unlock(&wl->mutex);
4353 cancel_delayed_work_sync(&dev->periodic_work);
4354 cancel_work_sync(&wl->tx_work);
4356 mutex_lock(&wl->mutex);
4357 dev = wl->current_dev;
4358 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4359 /* Whoops, aliens ate up the device while we were unlocked. */
4363 /* Disable interrupts on the device. */
4364 b43_set_status(dev, B43_STAT_INITIALIZED);
4365 if (b43_bus_host_is_sdio(dev->dev)) {
4366 /* wl->mutex is locked. That is enough. */
4367 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4368 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4370 spin_lock_irq(&wl->hardirq_lock);
4371 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4372 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4373 spin_unlock_irq(&wl->hardirq_lock);
4375 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4377 mutex_unlock(&wl->mutex);
4378 if (b43_bus_host_is_sdio(dev->dev))
4379 b43_sdio_free_irq(dev);
4381 free_irq(dev->dev->irq, dev);
4382 mutex_lock(&wl->mutex);
4383 dev = wl->current_dev;
4386 if (dev != orig_dev) {
4387 if (b43_status(dev) >= B43_STAT_STARTED)
4391 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4392 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4394 /* Drain all TX queues. */
4395 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4396 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4397 struct sk_buff *skb;
4399 skb = skb_dequeue(&wl->tx_queue[queue_num]);
4400 ieee80211_free_txskb(wl->hw, skb);
4404 b43_mac_suspend(dev);
4406 b43dbg(wl, "Wireless interface stopped\n");
4411 /* Locking: wl->mutex */
4412 static int b43_wireless_core_start(struct b43_wldev *dev)
4416 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4418 drain_txstatus_queue(dev);
4419 if (b43_bus_host_is_sdio(dev->dev)) {
4420 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4422 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4426 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4427 b43_interrupt_thread_handler,
4428 IRQF_SHARED, KBUILD_MODNAME, dev);
4430 b43err(dev->wl, "Cannot request IRQ-%d\n",
4436 /* We are ready to run. */
4437 ieee80211_wake_queues(dev->wl->hw);
4438 b43_set_status(dev, B43_STAT_STARTED);
4440 /* Start data flow (TX/RX). */
4441 b43_mac_enable(dev);
4442 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4444 /* Start maintenance work */
4445 b43_periodic_tasks_setup(dev);
4449 b43dbg(dev->wl, "Wireless interface started\n");
4454 static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
4465 case B43_PHYTYPE_LP:
4467 case B43_PHYTYPE_SSLPN:
4469 case B43_PHYTYPE_HT:
4471 case B43_PHYTYPE_LCN:
4473 case B43_PHYTYPE_LCNXN:
4475 case B43_PHYTYPE_LCN40:
4477 case B43_PHYTYPE_AC:
4483 /* Get PHY and RADIO versioning numbers */
4484 static int b43_phy_versioning(struct b43_wldev *dev)
4486 struct b43_phy *phy = &dev->phy;
4487 const u8 core_rev = dev->dev->core_rev;
4496 int unsupported = 0;
4498 /* Get PHY versioning */
4499 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4500 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4501 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4502 phy_rev = (tmp & B43_PHYVER_VERSION);
4504 /* LCNXN is continuation of N which run out of revisions */
4505 if (phy_type == B43_PHYTYPE_LCNXN) {
4506 phy_type = B43_PHYTYPE_N;
4511 #ifdef CONFIG_B43_PHY_G
4517 #ifdef CONFIG_B43_PHY_N
4523 #ifdef CONFIG_B43_PHY_LP
4524 case B43_PHYTYPE_LP:
4529 #ifdef CONFIG_B43_PHY_HT
4530 case B43_PHYTYPE_HT:
4535 #ifdef CONFIG_B43_PHY_LCN
4536 case B43_PHYTYPE_LCN:
4541 #ifdef CONFIG_B43_PHY_AC
4542 case B43_PHYTYPE_AC:
4551 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
4552 analog_type, phy_type, b43_phy_name(dev, phy_type),
4556 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
4557 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
4559 /* Get RADIO versioning */
4560 if (core_rev == 40 || core_rev == 42) {
4561 radio_manuf = 0x17F;
4563 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0);
4564 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4566 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1);
4567 radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4569 radio_ver = 0; /* Is there version somewhere? */
4570 } else if (core_rev >= 24) {
4573 for (tmp = 0; tmp < 3; tmp++) {
4574 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4575 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4578 radio_manuf = 0x17F;
4579 radio_id = (radio24[2] << 8) | radio24[1];
4580 radio_rev = (radio24[0] & 0xF);
4581 radio_ver = (radio24[0] & 0xF0) >> 4;
4583 if (dev->dev->chip_id == 0x4317) {
4584 if (dev->dev->chip_rev == 0)
4586 else if (dev->dev->chip_rev == 1)
4591 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4593 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4594 b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
4596 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4598 radio_manuf = (tmp & 0x00000FFF);
4599 radio_id = (tmp & 0x0FFFF000) >> 12;
4600 radio_rev = (tmp & 0xF0000000) >> 28;
4601 radio_ver = 0; /* Probably not available on old hw */
4604 if (radio_manuf != 0x17F /* Broadcom */)
4608 if (radio_id != 0x2060)
4612 if (radio_manuf != 0x17F)
4616 if ((radio_id & 0xFFF0) != 0x2050)
4620 if (radio_id != 0x2050)
4624 if (radio_id != 0x2055 && radio_id != 0x2056 &&
4627 if (radio_id == 0x2057 &&
4628 !(radio_rev == 9 || radio_rev == 14))
4631 case B43_PHYTYPE_LP:
4632 if (radio_id != 0x2062 && radio_id != 0x2063)
4635 case B43_PHYTYPE_HT:
4636 if (radio_id != 0x2059)
4639 case B43_PHYTYPE_LCN:
4640 if (radio_id != 0x2064)
4643 case B43_PHYTYPE_AC:
4644 if (radio_id != 0x2069)
4652 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n",
4653 radio_manuf, radio_id, radio_rev, radio_ver);
4657 "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n",
4658 radio_manuf, radio_id, radio_rev, radio_ver);
4660 /* FIXME: b43 treats "id" as "ver" and ignores the real "ver" */
4661 phy->radio_manuf = radio_manuf;
4662 phy->radio_ver = radio_id;
4663 phy->radio_rev = radio_rev;
4665 phy->analog = analog_type;
4666 phy->type = phy_type;
4672 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4673 struct b43_phy *phy)
4675 phy->hardware_power_control = !!modparam_hwpctl;
4676 phy->next_txpwr_check_time = jiffies;
4677 /* PHY TX errors counter. */
4678 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4681 phy->phy_locked = false;
4682 phy->radio_locked = false;
4686 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4688 dev->dfq_valid = false;
4690 /* Assume the radio is enabled. If it's not enabled, the state will
4691 * immediately get fixed on the first periodic work run. */
4692 dev->radio_hw_enable = true;
4695 memset(&dev->stats, 0, sizeof(dev->stats));
4697 setup_struct_phy_for_init(dev, &dev->phy);
4699 /* IRQ related flags */
4700 dev->irq_reason = 0;
4701 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4702 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4703 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4704 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4706 dev->mac_suspended = 1;
4708 /* Noise calculation context */
4709 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4712 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4714 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4717 if (!modparam_btcoex)
4719 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4721 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4724 hf = b43_hf_read(dev);
4725 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4726 hf |= B43_HF_BTCOEXALT;
4728 hf |= B43_HF_BTCOEX;
4729 b43_hf_write(dev, hf);
4732 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4734 if (!modparam_btcoex)
4739 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4741 struct ssb_bus *bus;
4744 #ifdef CONFIG_B43_SSB
4745 if (dev->dev->bus_type != B43_BUS_SSB)
4751 bus = dev->dev->sdev->bus;
4753 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4754 (bus->chip_id == 0x4312)) {
4755 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4756 tmp &= ~SSB_IMCFGLO_REQTO;
4757 tmp &= ~SSB_IMCFGLO_SERTO;
4759 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4760 ssb_commit_settings(bus);
4764 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4768 /* The time value is in microseconds. */
4769 if (dev->phy.type == B43_PHYTYPE_A)
4773 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4775 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4776 pu_delay = max(pu_delay, (u16)2400);
4778 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4781 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4782 static void b43_set_pretbtt(struct b43_wldev *dev)
4786 /* The time value is in microseconds. */
4787 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4790 if (dev->phy.type == B43_PHYTYPE_A)
4795 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4796 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4799 /* Shutdown a wireless core */
4800 /* Locking: wl->mutex */
4801 static void b43_wireless_core_exit(struct b43_wldev *dev)
4803 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4804 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4807 b43_set_status(dev, B43_STAT_UNINIT);
4809 /* Stop the microcode PSM. */
4810 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4811 B43_MACCTL_PSM_JMP0);
4813 switch (dev->dev->bus_type) {
4814 #ifdef CONFIG_B43_BCMA
4816 bcma_host_pci_down(dev->dev->bdev->bus);
4819 #ifdef CONFIG_B43_SSB
4829 dev->phy.ops->switch_analog(dev, 0);
4830 if (dev->wl->current_beacon) {
4831 dev_kfree_skb_any(dev->wl->current_beacon);
4832 dev->wl->current_beacon = NULL;
4835 b43_device_disable(dev, 0);
4836 b43_bus_may_powerdown(dev);
4839 /* Initialize a wireless core */
4840 static int b43_wireless_core_init(struct b43_wldev *dev)
4842 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4843 struct b43_phy *phy = &dev->phy;
4847 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4849 err = b43_bus_powerup(dev, 0);
4852 if (!b43_device_is_enabled(dev))
4853 b43_wireless_core_reset(dev, phy->gmode);
4855 /* Reset all data structures. */
4856 setup_struct_wldev_for_init(dev);
4857 phy->ops->prepare_structs(dev);
4859 /* Enable IRQ routing to this device. */
4860 switch (dev->dev->bus_type) {
4861 #ifdef CONFIG_B43_BCMA
4863 bcma_host_pci_irq_ctl(dev->dev->bdev->bus,
4864 dev->dev->bdev, true);
4865 bcma_host_pci_up(dev->dev->bdev->bus);
4868 #ifdef CONFIG_B43_SSB
4870 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4876 b43_imcfglo_timeouts_workaround(dev);
4877 b43_bluetooth_coext_disable(dev);
4878 if (phy->ops->prepare_hardware) {
4879 err = phy->ops->prepare_hardware(dev);
4883 err = b43_chip_init(dev);
4886 b43_shm_write16(dev, B43_SHM_SHARED,
4887 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4888 hf = b43_hf_read(dev);
4889 if (phy->type == B43_PHYTYPE_G) {
4893 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4894 hf |= B43_HF_OFDMPABOOST;
4896 if (phy->radio_ver == 0x2050) {
4897 if (phy->radio_rev == 6)
4898 hf |= B43_HF_4318TSSI;
4899 if (phy->radio_rev < 6)
4900 hf |= B43_HF_VCORECALC;
4902 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4903 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4904 #if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)
4905 if (dev->dev->bus_type == B43_BUS_SSB &&
4906 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4907 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4908 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4910 hf &= ~B43_HF_SKCFPUP;
4911 b43_hf_write(dev, hf);
4913 /* tell the ucode MAC capabilities */
4914 if (dev->dev->core_rev >= 13) {
4915 u32 mac_hw_cap = b43_read32(dev, B43_MMIO_MAC_HW_CAP);
4917 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_L,
4918 mac_hw_cap & 0xffff);
4919 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_H,
4920 (mac_hw_cap >> 16) & 0xffff);
4923 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4924 B43_DEFAULT_LONG_RETRY_LIMIT);
4925 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4926 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4928 /* Disable sending probe responses from firmware.
4929 * Setting the MaxTime to one usec will always trigger
4930 * a timeout, so we never send any probe resp.
4931 * A timeout of zero is infinite. */
4932 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4934 b43_rate_memory_init(dev);
4935 b43_set_phytxctl_defaults(dev);
4937 /* Minimum Contention Window */
4938 if (phy->type == B43_PHYTYPE_B)
4939 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4941 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4942 /* Maximum Contention Window */
4943 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4945 /* write phytype and phyvers */
4946 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYTYPE, phy->type);
4947 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYVER, phy->rev);
4949 if (b43_bus_host_is_pcmcia(dev->dev) ||
4950 b43_bus_host_is_sdio(dev->dev)) {
4951 dev->__using_pio_transfers = true;
4952 err = b43_pio_init(dev);
4953 } else if (dev->use_pio) {
4954 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4955 "This should not be needed and will result in lower "
4957 dev->__using_pio_transfers = true;
4958 err = b43_pio_init(dev);
4960 dev->__using_pio_transfers = false;
4961 err = b43_dma_init(dev);
4966 b43_set_synth_pu_delay(dev, 1);
4967 b43_bluetooth_coext_enable(dev);
4969 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4970 b43_upload_card_macaddress(dev);
4971 b43_security_init(dev);
4973 ieee80211_wake_queues(dev->wl->hw);
4975 b43_set_status(dev, B43_STAT_INITIALIZED);
4983 b43_bus_may_powerdown(dev);
4984 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4988 static int b43_op_add_interface(struct ieee80211_hw *hw,
4989 struct ieee80211_vif *vif)
4991 struct b43_wl *wl = hw_to_b43_wl(hw);
4992 struct b43_wldev *dev;
4993 int err = -EOPNOTSUPP;
4995 /* TODO: allow WDS/AP devices to coexist */
4997 if (vif->type != NL80211_IFTYPE_AP &&
4998 vif->type != NL80211_IFTYPE_MESH_POINT &&
4999 vif->type != NL80211_IFTYPE_STATION &&
5000 vif->type != NL80211_IFTYPE_WDS &&
5001 vif->type != NL80211_IFTYPE_ADHOC)
5004 mutex_lock(&wl->mutex);
5006 goto out_mutex_unlock;
5008 b43dbg(wl, "Adding Interface type %d\n", vif->type);
5010 dev = wl->current_dev;
5011 wl->operating = true;
5013 wl->if_type = vif->type;
5014 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
5016 b43_adjust_opmode(dev);
5017 b43_set_pretbtt(dev);
5018 b43_set_synth_pu_delay(dev, 0);
5019 b43_upload_card_macaddress(dev);
5023 mutex_unlock(&wl->mutex);
5026 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
5031 static void b43_op_remove_interface(struct ieee80211_hw *hw,
5032 struct ieee80211_vif *vif)
5034 struct b43_wl *wl = hw_to_b43_wl(hw);
5035 struct b43_wldev *dev = wl->current_dev;
5037 b43dbg(wl, "Removing Interface type %d\n", vif->type);
5039 mutex_lock(&wl->mutex);
5041 B43_WARN_ON(!wl->operating);
5042 B43_WARN_ON(wl->vif != vif);
5045 wl->operating = false;
5047 b43_adjust_opmode(dev);
5048 eth_zero_addr(wl->mac_addr);
5049 b43_upload_card_macaddress(dev);
5051 mutex_unlock(&wl->mutex);
5054 static int b43_op_start(struct ieee80211_hw *hw)
5056 struct b43_wl *wl = hw_to_b43_wl(hw);
5057 struct b43_wldev *dev = wl->current_dev;
5061 /* Kill all old instance specific information to make sure
5062 * the card won't use it in the short timeframe between start
5063 * and mac80211 reconfiguring it. */
5064 eth_zero_addr(wl->bssid);
5065 eth_zero_addr(wl->mac_addr);
5066 wl->filter_flags = 0;
5067 wl->radiotap_enabled = false;
5069 wl->beacon0_uploaded = false;
5070 wl->beacon1_uploaded = false;
5071 wl->beacon_templates_virgin = true;
5072 wl->radio_enabled = true;
5074 mutex_lock(&wl->mutex);
5076 if (b43_status(dev) < B43_STAT_INITIALIZED) {
5077 err = b43_wireless_core_init(dev);
5079 goto out_mutex_unlock;
5083 if (b43_status(dev) < B43_STAT_STARTED) {
5084 err = b43_wireless_core_start(dev);
5087 b43_wireless_core_exit(dev);
5088 goto out_mutex_unlock;
5092 /* XXX: only do if device doesn't support rfkill irq */
5093 wiphy_rfkill_start_polling(hw->wiphy);
5096 mutex_unlock(&wl->mutex);
5099 * Configuration may have been overwritten during initialization.
5100 * Reload the configuration, but only if initialization was
5101 * successful. Reloading the configuration after a failed init
5102 * may hang the system.
5105 b43_op_config(hw, ~0);
5110 static void b43_op_stop(struct ieee80211_hw *hw)
5112 struct b43_wl *wl = hw_to_b43_wl(hw);
5113 struct b43_wldev *dev = wl->current_dev;
5115 cancel_work_sync(&(wl->beacon_update_trigger));
5120 mutex_lock(&wl->mutex);
5121 if (b43_status(dev) >= B43_STAT_STARTED) {
5122 dev = b43_wireless_core_stop(dev);
5126 b43_wireless_core_exit(dev);
5127 wl->radio_enabled = false;
5130 mutex_unlock(&wl->mutex);
5132 cancel_work_sync(&(wl->txpower_adjust_work));
5135 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
5136 struct ieee80211_sta *sta, bool set)
5138 struct b43_wl *wl = hw_to_b43_wl(hw);
5140 b43_update_templates(wl);
5145 static void b43_op_sta_notify(struct ieee80211_hw *hw,
5146 struct ieee80211_vif *vif,
5147 enum sta_notify_cmd notify_cmd,
5148 struct ieee80211_sta *sta)
5150 struct b43_wl *wl = hw_to_b43_wl(hw);
5152 B43_WARN_ON(!vif || wl->vif != vif);
5155 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw,
5156 struct ieee80211_vif *vif,
5159 struct b43_wl *wl = hw_to_b43_wl(hw);
5160 struct b43_wldev *dev;
5162 mutex_lock(&wl->mutex);
5163 dev = wl->current_dev;
5164 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5165 /* Disable CFP update during scan on other channels. */
5166 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
5168 mutex_unlock(&wl->mutex);
5171 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw,
5172 struct ieee80211_vif *vif)
5174 struct b43_wl *wl = hw_to_b43_wl(hw);
5175 struct b43_wldev *dev;
5177 mutex_lock(&wl->mutex);
5178 dev = wl->current_dev;
5179 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
5180 /* Re-enable CFP update. */
5181 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
5183 mutex_unlock(&wl->mutex);
5186 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
5187 struct survey_info *survey)
5189 struct b43_wl *wl = hw_to_b43_wl(hw);
5190 struct b43_wldev *dev = wl->current_dev;
5191 struct ieee80211_conf *conf = &hw->conf;
5196 survey->channel = conf->chandef.chan;
5197 survey->filled = SURVEY_INFO_NOISE_DBM;
5198 survey->noise = dev->stats.link_noise;
5203 static const struct ieee80211_ops b43_hw_ops = {
5205 .conf_tx = b43_op_conf_tx,
5206 .add_interface = b43_op_add_interface,
5207 .remove_interface = b43_op_remove_interface,
5208 .config = b43_op_config,
5209 .bss_info_changed = b43_op_bss_info_changed,
5210 .configure_filter = b43_op_configure_filter,
5211 .set_key = b43_op_set_key,
5212 .update_tkip_key = b43_op_update_tkip_key,
5213 .get_stats = b43_op_get_stats,
5214 .get_tsf = b43_op_get_tsf,
5215 .set_tsf = b43_op_set_tsf,
5216 .start = b43_op_start,
5217 .stop = b43_op_stop,
5218 .set_tim = b43_op_beacon_set_tim,
5219 .sta_notify = b43_op_sta_notify,
5220 .sw_scan_start = b43_op_sw_scan_start_notifier,
5221 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
5222 .get_survey = b43_op_get_survey,
5223 .rfkill_poll = b43_rfkill_poll,
5226 /* Hard-reset the chip. Do not call this directly.
5227 * Use b43_controller_restart()
5229 static void b43_chip_reset(struct work_struct *work)
5231 struct b43_wldev *dev =
5232 container_of(work, struct b43_wldev, restart_work);
5233 struct b43_wl *wl = dev->wl;
5237 mutex_lock(&wl->mutex);
5239 prev_status = b43_status(dev);
5240 /* Bring the device down... */
5241 if (prev_status >= B43_STAT_STARTED) {
5242 dev = b43_wireless_core_stop(dev);
5248 if (prev_status >= B43_STAT_INITIALIZED)
5249 b43_wireless_core_exit(dev);
5251 /* ...and up again. */
5252 if (prev_status >= B43_STAT_INITIALIZED) {
5253 err = b43_wireless_core_init(dev);
5257 if (prev_status >= B43_STAT_STARTED) {
5258 err = b43_wireless_core_start(dev);
5260 b43_wireless_core_exit(dev);
5266 wl->current_dev = NULL; /* Failed to init the dev. */
5267 mutex_unlock(&wl->mutex);
5270 b43err(wl, "Controller restart FAILED\n");
5274 /* reload configuration */
5275 b43_op_config(wl->hw, ~0);
5277 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5279 b43info(wl, "Controller restarted\n");
5282 static int b43_setup_bands(struct b43_wldev *dev,
5283 bool have_2ghz_phy, bool have_5ghz_phy)
5285 struct ieee80211_hw *hw = dev->wl->hw;
5286 struct b43_phy *phy = &dev->phy;
5290 /* We don't support all 2 GHz channels on some devices */
5291 limited_2g = phy->radio_ver == 0x2057 &&
5292 (phy->radio_rev == 9 || phy->radio_rev == 14);
5293 limited_5g = phy->radio_ver == 0x2057 &&
5294 phy->radio_rev == 9;
5297 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = limited_2g ?
5298 &b43_band_2ghz_limited : &b43_band_2GHz;
5299 if (dev->phy.type == B43_PHYTYPE_N) {
5301 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = limited_5g ?
5302 &b43_band_5GHz_nphy_limited :
5303 &b43_band_5GHz_nphy;
5306 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5309 dev->phy.supports_2ghz = have_2ghz_phy;
5310 dev->phy.supports_5ghz = have_5ghz_phy;
5315 static void b43_wireless_core_detach(struct b43_wldev *dev)
5317 /* We release firmware that late to not be required to re-request
5318 * is all the time when we reinit the core. */
5319 b43_release_firmware(dev);
5323 static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy,
5324 bool *have_5ghz_phy)
5328 #ifdef CONFIG_B43_BCMA
5329 if (dev->dev->bus_type == B43_BUS_BCMA &&
5330 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI)
5331 dev_id = dev->dev->bdev->bus->host_pci->device;
5333 #ifdef CONFIG_B43_SSB
5334 if (dev->dev->bus_type == B43_BUS_SSB &&
5335 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5336 dev_id = dev->dev->sdev->bus->host_pci->device;
5338 /* Override with SPROM value if available */
5339 if (dev->dev->bus_sprom->dev_id)
5340 dev_id = dev->dev->bus_sprom->dev_id;
5342 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */
5344 case 0x4324: /* BCM4306 */
5345 case 0x4312: /* BCM4311 */
5346 case 0x4319: /* BCM4318 */
5347 case 0x4328: /* BCM4321 */
5348 case 0x432b: /* BCM4322 */
5349 case 0x4350: /* BCM43222 */
5350 case 0x4353: /* BCM43224 */
5351 case 0x0576: /* BCM43224 */
5352 case 0x435f: /* BCM6362 */
5353 case 0x4331: /* BCM4331 */
5354 case 0x4359: /* BCM43228 */
5355 case 0x43a0: /* BCM4360 */
5356 case 0x43b1: /* BCM4352 */
5357 /* Dual band devices */
5358 *have_2ghz_phy = true;
5359 *have_5ghz_phy = true;
5361 case 0x4321: /* BCM4306 */
5362 /* There are 14e4:4321 PCI devs with 2.4 GHz BCM4321 (N-PHY) */
5363 if (dev->phy.type != B43_PHYTYPE_G)
5366 case 0x4313: /* BCM4311 */
5367 case 0x431a: /* BCM4318 */
5368 case 0x432a: /* BCM4321 */
5369 case 0x432d: /* BCM4322 */
5370 case 0x4352: /* BCM43222 */
5371 case 0x435a: /* BCM43228 */
5372 case 0x4333: /* BCM4331 */
5373 case 0x43a2: /* BCM4360 */
5374 case 0x43b3: /* BCM4352 */
5375 /* 5 GHz only devices */
5376 *have_2ghz_phy = false;
5377 *have_5ghz_phy = true;
5381 /* As a fallback, try to guess using PHY type */
5382 switch (dev->phy.type) {
5384 *have_2ghz_phy = false;
5385 *have_5ghz_phy = true;
5389 case B43_PHYTYPE_LP:
5390 case B43_PHYTYPE_HT:
5391 case B43_PHYTYPE_LCN:
5392 *have_2ghz_phy = true;
5393 *have_5ghz_phy = false;
5400 static int b43_wireless_core_attach(struct b43_wldev *dev)
5402 struct b43_wl *wl = dev->wl;
5403 struct b43_phy *phy = &dev->phy;
5406 bool have_2ghz_phy = false, have_5ghz_phy = false;
5408 /* Do NOT do any device initialization here.
5409 * Do it in wireless_core_init() instead.
5410 * This function is for gathering basic information about the HW, only.
5411 * Also some structs may be set up here. But most likely you want to have
5412 * that in core_init(), too.
5415 err = b43_bus_powerup(dev, 0);
5417 b43err(wl, "Bus powerup failed\n");
5421 phy->do_full_init = true;
5423 /* Try to guess supported bands for the first init needs */
5424 switch (dev->dev->bus_type) {
5425 #ifdef CONFIG_B43_BCMA
5427 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5428 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5429 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5432 #ifdef CONFIG_B43_SSB
5434 if (dev->dev->core_rev >= 5) {
5435 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5436 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5437 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5444 dev->phy.gmode = have_2ghz_phy;
5445 b43_wireless_core_reset(dev, dev->phy.gmode);
5447 /* Get the PHY type. */
5448 err = b43_phy_versioning(dev);
5452 /* Get real info about supported bands */
5453 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy);
5455 /* We don't support 5 GHz on some PHYs yet */
5456 if (have_5ghz_phy) {
5457 switch (dev->phy.type) {
5460 case B43_PHYTYPE_LP:
5461 case B43_PHYTYPE_HT:
5462 b43warn(wl, "5 GHz band is unsupported on this PHY\n");
5463 have_5ghz_phy = false;
5467 if (!have_2ghz_phy && !have_5ghz_phy) {
5468 b43err(wl, "b43 can't support any band on this device\n");
5473 err = b43_phy_allocate(dev);
5477 dev->phy.gmode = have_2ghz_phy;
5478 b43_wireless_core_reset(dev, dev->phy.gmode);
5480 err = b43_validate_chipaccess(dev);
5483 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5487 /* Now set some default "current_dev" */
5488 if (!wl->current_dev)
5489 wl->current_dev = dev;
5490 INIT_WORK(&dev->restart_work, b43_chip_reset);
5492 dev->phy.ops->switch_analog(dev, 0);
5493 b43_device_disable(dev, 0);
5494 b43_bus_may_powerdown(dev);
5502 b43_bus_may_powerdown(dev);
5506 static void b43_one_core_detach(struct b43_bus_dev *dev)
5508 struct b43_wldev *wldev;
5511 /* Do not cancel ieee80211-workqueue based work here.
5512 * See comment in b43_remove(). */
5514 wldev = b43_bus_get_wldev(dev);
5516 b43_debugfs_remove_device(wldev);
5517 b43_wireless_core_detach(wldev);
5518 list_del(&wldev->list);
5519 b43_bus_set_wldev(dev, NULL);
5523 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5525 struct b43_wldev *wldev;
5528 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5532 wldev->use_pio = b43_modparam_pio;
5535 b43_set_status(wldev, B43_STAT_UNINIT);
5536 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5537 INIT_LIST_HEAD(&wldev->list);
5539 err = b43_wireless_core_attach(wldev);
5541 goto err_kfree_wldev;
5543 b43_bus_set_wldev(dev, wldev);
5544 b43_debugfs_add_device(wldev);
5554 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5555 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5556 (pdev->device == _device) && \
5557 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5558 (pdev->subsystem_device == _subdevice) )
5560 #ifdef CONFIG_B43_SSB
5561 static void b43_sprom_fixup(struct ssb_bus *bus)
5563 struct pci_dev *pdev;
5565 /* boardflags workarounds */
5566 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5567 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
5568 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5569 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5570 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
5571 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5572 if (bus->bustype == SSB_BUSTYPE_PCI) {
5573 pdev = bus->host_pci;
5574 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5575 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5576 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5577 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5578 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5579 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5580 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5581 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5585 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5587 struct ieee80211_hw *hw = wl->hw;
5589 ssb_set_devtypedata(dev->sdev, NULL);
5590 ieee80211_free_hw(hw);
5594 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5596 struct ssb_sprom *sprom = dev->bus_sprom;
5597 struct ieee80211_hw *hw;
5602 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5604 b43err(NULL, "Could not allocate ieee80211 device\n");
5605 return ERR_PTR(-ENOMEM);
5607 wl = hw_to_b43_wl(hw);
5610 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
5611 ieee80211_hw_set(hw, SIGNAL_DBM);
5613 hw->wiphy->interface_modes =
5614 BIT(NL80211_IFTYPE_AP) |
5615 BIT(NL80211_IFTYPE_MESH_POINT) |
5616 BIT(NL80211_IFTYPE_STATION) |
5617 BIT(NL80211_IFTYPE_WDS) |
5618 BIT(NL80211_IFTYPE_ADHOC);
5620 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5622 wl->hw_registred = false;
5624 SET_IEEE80211_DEV(hw, dev->dev);
5625 if (is_valid_ether_addr(sprom->et1mac))
5626 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5628 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5630 /* Initialize struct b43_wl */
5632 mutex_init(&wl->mutex);
5633 spin_lock_init(&wl->hardirq_lock);
5634 spin_lock_init(&wl->beacon_lock);
5635 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5636 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5637 INIT_WORK(&wl->tx_work, b43_tx_work);
5639 /* Initialize queues and flags. */
5640 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5641 skb_queue_head_init(&wl->tx_queue[queue_num]);
5642 wl->tx_queue_stopped[queue_num] = 0;
5645 snprintf(chip_name, ARRAY_SIZE(chip_name),
5646 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5647 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5652 #ifdef CONFIG_B43_BCMA
5653 static int b43_bcma_probe(struct bcma_device *core)
5655 struct b43_bus_dev *dev;
5659 if (!modparam_allhwsupport &&
5660 (core->id.rev == 0x17 || core->id.rev == 0x18)) {
5661 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n");
5665 dev = b43_bus_dev_bcma_init(core);
5669 wl = b43_wireless_init(dev);
5675 err = b43_one_core_attach(dev, wl);
5677 goto bcma_err_wireless_exit;
5679 /* setup and start work to load firmware */
5680 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5681 schedule_work(&wl->firmware_load);
5686 bcma_err_wireless_exit:
5687 ieee80211_free_hw(wl->hw);
5691 static void b43_bcma_remove(struct bcma_device *core)
5693 struct b43_wldev *wldev = bcma_get_drvdata(core);
5694 struct b43_wl *wl = wldev->wl;
5696 /* We must cancel any work here before unregistering from ieee80211,
5697 * as the ieee80211 unreg will destroy the workqueue. */
5698 cancel_work_sync(&wldev->restart_work);
5699 cancel_work_sync(&wl->firmware_load);
5702 if (!wldev->fw.ucode.data)
5703 return; /* NULL if firmware never loaded */
5704 if (wl->current_dev == wldev && wl->hw_registred) {
5705 b43_leds_stop(wldev);
5706 ieee80211_unregister_hw(wl->hw);
5709 b43_one_core_detach(wldev->dev);
5711 /* Unregister HW RNG driver */
5714 b43_leds_unregister(wl);
5716 ieee80211_free_hw(wl->hw);
5719 static struct bcma_driver b43_bcma_driver = {
5720 .name = KBUILD_MODNAME,
5721 .id_table = b43_bcma_tbl,
5722 .probe = b43_bcma_probe,
5723 .remove = b43_bcma_remove,
5727 #ifdef CONFIG_B43_SSB
5729 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5731 struct b43_bus_dev *dev;
5735 dev = b43_bus_dev_ssb_init(sdev);
5739 wl = ssb_get_devtypedata(sdev);
5741 b43err(NULL, "Dual-core devices are not supported\n");
5743 goto err_ssb_kfree_dev;
5746 b43_sprom_fixup(sdev->bus);
5748 wl = b43_wireless_init(dev);
5751 goto err_ssb_kfree_dev;
5753 ssb_set_devtypedata(sdev, wl);
5754 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5756 err = b43_one_core_attach(dev, wl);
5758 goto err_ssb_wireless_exit;
5760 /* setup and start work to load firmware */
5761 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5762 schedule_work(&wl->firmware_load);
5766 err_ssb_wireless_exit:
5767 b43_wireless_exit(dev, wl);
5773 static void b43_ssb_remove(struct ssb_device *sdev)
5775 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5776 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5777 struct b43_bus_dev *dev = wldev->dev;
5779 /* We must cancel any work here before unregistering from ieee80211,
5780 * as the ieee80211 unreg will destroy the workqueue. */
5781 cancel_work_sync(&wldev->restart_work);
5782 cancel_work_sync(&wl->firmware_load);
5785 if (!wldev->fw.ucode.data)
5786 return; /* NULL if firmware never loaded */
5787 if (wl->current_dev == wldev && wl->hw_registred) {
5788 b43_leds_stop(wldev);
5789 ieee80211_unregister_hw(wl->hw);
5792 b43_one_core_detach(dev);
5794 /* Unregister HW RNG driver */
5797 b43_leds_unregister(wl);
5798 b43_wireless_exit(dev, wl);
5801 static struct ssb_driver b43_ssb_driver = {
5802 .name = KBUILD_MODNAME,
5803 .id_table = b43_ssb_tbl,
5804 .probe = b43_ssb_probe,
5805 .remove = b43_ssb_remove,
5807 #endif /* CONFIG_B43_SSB */
5809 /* Perform a hardware reset. This can be called from any context. */
5810 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5812 /* Must avoid requeueing, if we are in shutdown. */
5813 if (b43_status(dev) < B43_STAT_INITIALIZED)
5815 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5816 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5819 static void b43_print_driverinfo(void)
5821 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5822 *feat_leds = "", *feat_sdio = "";
5824 #ifdef CONFIG_B43_PCI_AUTOSELECT
5827 #ifdef CONFIG_B43_PCMCIA
5830 #ifdef CONFIG_B43_PHY_N
5833 #ifdef CONFIG_B43_LEDS
5836 #ifdef CONFIG_B43_SDIO
5839 printk(KERN_INFO "Broadcom 43xx driver loaded "
5840 "[ Features: %s%s%s%s%s ]\n",
5841 feat_pci, feat_pcmcia, feat_nphy,
5842 feat_leds, feat_sdio);
5845 static int __init b43_init(void)
5850 err = b43_sdio_init();
5853 #ifdef CONFIG_B43_BCMA
5854 err = bcma_driver_register(&b43_bcma_driver);
5858 #ifdef CONFIG_B43_SSB
5859 err = ssb_driver_register(&b43_ssb_driver);
5861 goto err_bcma_driver_exit;
5863 b43_print_driverinfo();
5867 #ifdef CONFIG_B43_SSB
5868 err_bcma_driver_exit:
5870 #ifdef CONFIG_B43_BCMA
5871 bcma_driver_unregister(&b43_bcma_driver);
5880 static void __exit b43_exit(void)
5882 #ifdef CONFIG_B43_SSB
5883 ssb_driver_unregister(&b43_ssb_driver);
5885 #ifdef CONFIG_B43_BCMA
5886 bcma_driver_unregister(&b43_bcma_driver);
5892 module_init(b43_init)
5893 module_exit(b43_exit)