2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_ids.h>
27 #include <linux/mmc/sdio_func.h>
28 #include <linux/mmc/card.h>
29 #include <linux/semaphore.h>
30 #include <linux/firmware.h>
31 #include <linux/module.h>
32 #include <linux/bcma/bcma.h>
33 #include <linux/debugfs.h>
34 #include <linux/vmalloc.h>
35 #include <linux/platform_data/brcmfmac-sdio.h>
36 #include <linux/moduleparam.h>
37 #include <asm/unaligned.h>
39 #include <brcmu_wifi.h>
40 #include <brcmu_utils.h>
41 #include <brcm_hw_ids.h>
43 #include "sdio_host.h"
47 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
51 #define BRCMF_TRAP_INFO_SIZE 80
53 #define CBUF_LEN (128)
55 /* Device console log buffer state */
56 #define CONSOLE_BUFFER_MAX 2024
59 __le32 buf; /* Can't be pointer on (64-bit) hosts */
62 char *_buf_compat; /* Redundant pointer for backward compat. */
67 * When there is no UART (e.g. Quickturn),
68 * the host should write a complete
69 * input line directly into cbuf and then write
70 * the length into vcons_in.
71 * This may also be used when there is a real UART
72 * (at risk of conflicting with
73 * the real UART). vcons_out is currently unused.
78 /* Output (logging) buffer
79 * Console output is written to a ring buffer log_buf at index log_idx.
80 * The host may read the output when it sees log_idx advance.
81 * Output will be lost if the output wraps around faster than the host
84 struct rte_log_le log_le;
86 /* Console input line buffer
87 * Characters are read one at a time into cbuf
88 * until <CR> is received, then
89 * the buffer is processed as a command line.
90 * Also used for virtual UART.
97 #include <chipcommon.h>
101 #include "tracepoint.h"
103 #define TXQLEN 2048 /* bulk tx queue length */
104 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
105 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
108 #define TXRETRIES 2 /* # of retries for tx frames */
110 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
113 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
116 #define BRCMF_DEFAULT_TXGLOM_SIZE 32 /* max tx frames in glom chain */
118 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
120 #define MEMBLOCK 2048 /* Block size used for downloading
122 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
123 biggest possible glom */
125 #define BRCMF_FIRSTREAD (1 << 6)
128 /* SBSDIO_DEVICE_CTL */
130 /* 1: device will assert busy signal when receiving CMD53 */
131 #define SBSDIO_DEVCTL_SETBUSY 0x01
132 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
133 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
134 /* 1: mask all interrupts to host except the chipActive (rev 8) */
135 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
136 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
137 * sdio bus power cycle to clear (rev 9) */
138 #define SBSDIO_DEVCTL_PADS_ISO 0x08
139 /* Force SD->SB reset mapping (rev 11) */
140 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
141 /* Determined by CoreControl bit */
142 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
143 /* Force backplane reset */
144 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
145 /* Force no backplane reset */
146 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
148 /* direct(mapped) cis space */
150 /* MAPPED common CIS address */
151 #define SBSDIO_CIS_BASE_COMMON 0x1000
152 /* maximum bytes in one CIS */
153 #define SBSDIO_CIS_SIZE_LIMIT 0x200
154 /* cis offset addr is < 17 bits */
155 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
157 /* manfid tuple length, include tuple, link bytes */
158 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
160 #define CORE_BUS_REG(base, field) \
161 (base + offsetof(struct sdpcmd_regs, field))
163 /* SDIO function 1 register CHIPCLKCSR */
164 /* Force ALP request to backplane */
165 #define SBSDIO_FORCE_ALP 0x01
166 /* Force HT request to backplane */
167 #define SBSDIO_FORCE_HT 0x02
168 /* Force ILP request to backplane */
169 #define SBSDIO_FORCE_ILP 0x04
170 /* Make ALP ready (power up xtal) */
171 #define SBSDIO_ALP_AVAIL_REQ 0x08
172 /* Make HT ready (power up PLL) */
173 #define SBSDIO_HT_AVAIL_REQ 0x10
174 /* Squelch clock requests from HW */
175 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
176 /* Status: ALP is ready */
177 #define SBSDIO_ALP_AVAIL 0x40
178 /* Status: HT is ready */
179 #define SBSDIO_HT_AVAIL 0x80
180 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
181 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
182 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
183 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
184 #define SBSDIO_CLKAV(regval, alponly) \
185 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
188 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
189 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
190 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
191 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
192 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
193 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
194 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
195 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
196 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
197 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
198 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
199 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
200 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
201 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
202 #define I_PC (1 << 10) /* descriptor error */
203 #define I_PD (1 << 11) /* data error */
204 #define I_DE (1 << 12) /* Descriptor protocol Error */
205 #define I_RU (1 << 13) /* Receive descriptor Underflow */
206 #define I_RO (1 << 14) /* Receive fifo Overflow */
207 #define I_XU (1 << 15) /* Transmit fifo Underflow */
208 #define I_RI (1 << 16) /* Receive Interrupt */
209 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
210 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
211 #define I_XI (1 << 24) /* Transmit Interrupt */
212 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
213 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
214 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
215 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
216 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
217 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
218 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
219 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
220 #define I_DMA (I_RI | I_XI | I_ERRORS)
223 #define CC_CISRDY (1 << 0) /* CIS Ready */
224 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
225 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
226 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
227 #define CC_XMTDATAAVAIL_MODE (1 << 4)
228 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
231 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
232 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
233 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
234 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
237 * Software allocation of To SB Mailbox resources
240 /* tosbmailbox bits corresponding to intstatus bits */
241 #define SMB_NAK (1 << 0) /* Frame NAK */
242 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
243 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
244 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
246 /* tosbmailboxdata */
247 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
250 * Software allocation of To Host Mailbox resources
254 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
255 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
256 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
257 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
259 /* tohostmailboxdata */
260 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
261 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
262 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
263 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
265 #define HMB_DATA_FCDATA_MASK 0xff000000
266 #define HMB_DATA_FCDATA_SHIFT 24
268 #define HMB_DATA_VERSION_MASK 0x00ff0000
269 #define HMB_DATA_VERSION_SHIFT 16
272 * Software-defined protocol header
275 /* Current protocol version */
276 #define SDPCM_PROT_VERSION 4
279 * Shared structure between dongle and the host.
280 * The structure contains pointers to trap or assert information.
282 #define SDPCM_SHARED_VERSION 0x0003
283 #define SDPCM_SHARED_VERSION_MASK 0x00FF
284 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
285 #define SDPCM_SHARED_ASSERT 0x0200
286 #define SDPCM_SHARED_TRAP 0x0400
288 /* Space for header read, limit for data packets */
289 #define MAX_HDR_READ (1 << 6)
290 #define MAX_RX_DATASZ 2048
292 /* Bump up limit on waiting for HT to account for first startup;
293 * if the image is doing a CRC calculation before programming the PMU
294 * for HT availability, it could take a couple hundred ms more, so
295 * max out at a 1 second (1000000us).
297 #undef PMU_MAX_TRANSITION_DLY
298 #define PMU_MAX_TRANSITION_DLY 1000000
300 /* Value for ChipClockCSR during initial setup */
301 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
302 SBSDIO_ALP_AVAIL_REQ)
304 /* Flags for SDH calls */
305 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
307 #define BRCMF_IDLE_IMMEDIATE (-1) /* Enter idle immediately */
308 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
311 #define BRCMF_IDLE_INTERVAL 1
313 #define KSO_WAIT_US 50
314 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
317 * Conversion of 802.1D priority to precedence level
319 static uint prio2prec(u32 prio)
321 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
326 /* Device console log buffer state */
327 struct brcmf_console {
328 uint count; /* Poll interval msec counter */
329 uint log_addr; /* Log struct address (fixed) */
330 struct rte_log_le log_le; /* Log struct (host copy) */
331 uint bufsize; /* Size of log buffer */
332 u8 *buf; /* Log buffer (host copy) */
333 uint last; /* Last buffer read index */
336 struct brcmf_trap_info {
350 __le32 r9; /* sb/v6 */
351 __le32 r10; /* sl/v7 */
352 __le32 r11; /* fp/v8 */
360 struct sdpcm_shared {
364 u32 assert_file_addr;
366 u32 console_addr; /* Address of struct rte_console */
372 struct sdpcm_shared_le {
375 __le32 assert_exp_addr;
376 __le32 assert_file_addr;
378 __le32 console_addr; /* Address of struct rte_console */
379 __le32 msgtrace_addr;
384 /* dongle SDIO bus specific header info */
385 struct brcmf_sdio_hdrinfo {
396 /* misc chip info needed by some of the routines */
397 /* Private data for SDIO bus interaction */
399 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
400 struct brcmf_chip *ci; /* Chip info struct */
402 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
404 u32 hostintmask; /* Copy of Host Interrupt Mask */
405 atomic_t intstatus; /* Intstatus bits (events) pending */
406 atomic_t fcstate; /* State of dongle flow-control */
408 uint blocksize; /* Block size of SDIO transfers */
409 uint roundup; /* Max roundup limit */
411 struct pktq txq; /* Queue length used for flow-control */
412 u8 flowcontrol; /* per prio flow control bitmask */
413 u8 tx_seq; /* Transmit sequence number (next) */
414 u8 tx_max; /* Maximum transmit sequence allowed */
416 u8 *hdrbuf; /* buffer for handling rx frame */
417 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
418 u8 rx_seq; /* Receive sequence number (expected) */
419 struct brcmf_sdio_hdrinfo cur_read;
420 /* info of current read frame */
421 bool rxskip; /* Skip receive (awaiting NAK ACK) */
422 bool rxpending; /* Data frame pending in dongle */
424 uint rxbound; /* Rx frames to read before resched */
425 uint txbound; /* Tx frames to send before resched */
428 struct sk_buff *glomd; /* Packet containing glomming descriptor */
429 struct sk_buff_head glom; /* Packet list for glommed superframe */
430 uint glomerr; /* Glom packet read errors */
432 u8 *rxbuf; /* Buffer for receiving control packets */
433 uint rxblen; /* Allocated length of rxbuf */
434 u8 *rxctl; /* Aligned pointer into rxbuf */
435 u8 *rxctl_orig; /* pointer for freeing rxctl */
436 uint rxlen; /* Length of valid data in buffer */
437 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
439 u8 sdpcm_ver; /* Bus protocol reported by dongle */
441 bool intr; /* Use interrupts */
442 bool poll; /* Use polling */
443 atomic_t ipend; /* Device interrupt is pending */
444 uint spurious; /* Count of spurious interrupts */
445 uint pollrate; /* Ticks between device polls */
446 uint polltick; /* Tick counter */
449 uint console_interval;
450 struct brcmf_console console; /* Console output polling support */
451 uint console_addr; /* Console address from shared struct */
454 uint clkstate; /* State of sd and backplane clock(s) */
455 bool activity; /* Activity flag for clock down */
456 s32 idletime; /* Control for activity timeout */
457 s32 idlecount; /* Activity timeout counter */
458 s32 idleclock; /* How to set bus driver when idle */
459 bool rxflow_mode; /* Rx flow control mode */
460 bool rxflow; /* Is rx flow control on */
461 bool alp_only; /* Don't use HT clock (ALP only) */
465 bool ctrl_frame_stat;
468 wait_queue_head_t ctrl_wait;
469 wait_queue_head_t dcmd_resp_wait;
471 struct timer_list timer;
472 struct completion watchdog_wait;
473 struct task_struct *watchdog_tsk;
477 struct workqueue_struct *brcmf_wq;
478 struct work_struct datawork;
481 bool txoff; /* Transmit flow-controlled */
482 struct brcmf_sdio_count sdcnt;
483 bool sr_enabled; /* SaveRestore enabled */
484 bool sleeping; /* SDIO bus sleeping */
486 u8 tx_hdrlen; /* sdio bus header length for tx packet */
487 bool txglom; /* host tx glomming enable flag */
488 struct sk_buff *txglom_sgpad; /* scatter-gather padding buffer */
489 u16 head_align; /* buffer pointer alignment */
490 u16 sgentry_align; /* scatter-gather buffer alignment */
496 #define CLK_PENDING 2
500 static int qcount[NUMPRIO];
503 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
505 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
507 /* Retry count for register access failures */
508 static const uint retry_limit = 2;
510 /* Limit on rounding up frames */
511 static const uint max_roundup = 512;
515 static int brcmf_sdio_txglomsz = BRCMF_DEFAULT_TXGLOM_SIZE;
516 module_param_named(txglomsz, brcmf_sdio_txglomsz, int, 0);
517 MODULE_PARM_DESC(txglomsz, "maximum tx packet chain size [SDIO]");
519 enum brcmf_sdio_frmtype {
520 BRCMF_SDIO_FT_NORMAL,
525 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
527 /* SDIO Pad drive strength to select value mappings */
528 struct sdiod_drive_str {
529 u8 strength; /* Pad Drive Strength in mA */
530 u8 sel; /* Chip-specific select value */
533 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
534 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
545 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
546 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
556 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
557 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
563 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
564 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
571 #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin"
572 #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt"
573 #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin"
574 #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt"
575 #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin"
576 #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt"
577 #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin"
578 #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt"
579 #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin"
580 #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
581 #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
582 #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
583 #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
584 #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
585 #define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin"
586 #define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt"
587 #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
588 #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
590 MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME);
591 MODULE_FIRMWARE(BCM43143_NVRAM_NAME);
592 MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME);
593 MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME);
594 MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME);
595 MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME);
596 MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME);
597 MODULE_FIRMWARE(BCM4329_NVRAM_NAME);
598 MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
599 MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
600 MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
601 MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
602 MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
603 MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
604 MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME);
605 MODULE_FIRMWARE(BCM43362_NVRAM_NAME);
606 MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
607 MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
609 struct brcmf_firmware_names {
616 enum brcmf_firmware_type {
621 #define BRCMF_FIRMWARE_NVRAM(name) \
622 name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
624 static const struct brcmf_firmware_names brcmf_fwname_data[] = {
625 { BCM43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
626 { BCM43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
627 { BCM43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
628 { BCM4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
629 { BCM4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
630 { BCM4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
631 { BCM4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
632 { BCM43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
633 { BCM4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) }
637 static const struct firmware *brcmf_sdio_get_fw(struct brcmf_sdio *bus,
638 enum brcmf_firmware_type type)
640 const struct firmware *fw;
644 for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
645 if (brcmf_fwname_data[i].chipid == bus->ci->chip &&
646 brcmf_fwname_data[i].revmsk & BIT(bus->ci->chiprev)) {
648 case BRCMF_FIRMWARE_BIN:
649 name = brcmf_fwname_data[i].bin;
651 case BRCMF_FIRMWARE_NVRAM:
652 name = brcmf_fwname_data[i].nv;
655 brcmf_err("invalid firmware type (%d)\n", type);
661 brcmf_err("Unknown chipid %d [%d]\n",
662 bus->ci->chip, bus->ci->chiprev);
666 err = request_firmware(&fw, name, &bus->sdiodev->func[2]->dev);
667 if ((err) || (!fw)) {
668 brcmf_err("fail to request firmware %s (%d)\n", name, err);
675 static void pkt_align(struct sk_buff *p, int len, int align)
678 datalign = (unsigned long)(p->data);
679 datalign = roundup(datalign, (align)) - datalign;
681 skb_pull(p, datalign);
685 /* To check if there's window offered */
686 static bool data_ok(struct brcmf_sdio *bus)
688 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
689 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
693 * Reads a register in the SDIO hardware block. This block occupies a series of
694 * adresses on the 32 bit backplane bus.
696 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
698 struct brcmf_core *core;
701 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
702 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
707 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
709 struct brcmf_core *core;
712 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
713 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
719 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
721 u8 wr_val = 0, rd_val, cmp_val, bmask;
725 brcmf_dbg(TRACE, "Enter\n");
727 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
728 /* 1st KSO write goes to AOS wake up core if device is asleep */
729 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
732 brcmf_err("SDIO_AOS KSO write error: %d\n", err);
737 /* device WAKEUP through KSO:
738 * write bit 0 & read back until
739 * both bits 0 (kso bit) & 1 (dev on status) are set
741 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
742 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
744 usleep_range(2000, 3000);
746 /* Put device to sleep, turn off KSO */
748 /* only check for bit0, bit1(dev on status) may not
749 * get cleared right away
751 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
755 /* reliable KSO bit set/clr:
756 * the sdiod sleep write access is synced to PMU 32khz clk
757 * just one write attempt may fail,
758 * read it back until it matches written value
760 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
762 if (((rd_val & bmask) == cmp_val) && !err)
764 brcmf_dbg(SDIO, "KSO wr/rd retry:%d (max: %d) ERR:%x\n",
765 try_cnt, MAX_KSO_ATTEMPTS, err);
767 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
769 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
774 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
776 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
778 /* Turn backplane clock on or off */
779 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
782 u8 clkctl, clkreq, devctl;
783 unsigned long timeout;
785 brcmf_dbg(SDIO, "Enter\n");
789 if (bus->sr_enabled) {
790 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
795 /* Request HT Avail */
797 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
799 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
802 brcmf_err("HT Avail request error: %d\n", err);
806 /* Check current status */
807 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
808 SBSDIO_FUNC1_CHIPCLKCSR, &err);
810 brcmf_err("HT Avail read error: %d\n", err);
814 /* Go to pending and await interrupt if appropriate */
815 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
816 /* Allow only clock-available interrupt */
817 devctl = brcmf_sdiod_regrb(bus->sdiodev,
818 SBSDIO_DEVICE_CTL, &err);
820 brcmf_err("Devctl error setting CA: %d\n",
825 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
826 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
828 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
829 bus->clkstate = CLK_PENDING;
832 } else if (bus->clkstate == CLK_PENDING) {
833 /* Cancel CA-only interrupt filter */
834 devctl = brcmf_sdiod_regrb(bus->sdiodev,
835 SBSDIO_DEVICE_CTL, &err);
836 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
837 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
841 /* Otherwise, wait here (polling) for HT Avail */
843 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
844 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
845 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
846 SBSDIO_FUNC1_CHIPCLKCSR,
848 if (time_after(jiffies, timeout))
851 usleep_range(5000, 10000);
854 brcmf_err("HT Avail request error: %d\n", err);
857 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
858 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
859 PMU_MAX_TRANSITION_DLY, clkctl);
863 /* Mark clock available */
864 bus->clkstate = CLK_AVAIL;
865 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
868 if (!bus->alp_only) {
869 if (SBSDIO_ALPONLY(clkctl))
870 brcmf_err("HT Clock should be on\n");
872 #endif /* defined (DEBUG) */
874 bus->activity = true;
878 if (bus->clkstate == CLK_PENDING) {
879 /* Cancel CA-only interrupt filter */
880 devctl = brcmf_sdiod_regrb(bus->sdiodev,
881 SBSDIO_DEVICE_CTL, &err);
882 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
883 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
887 bus->clkstate = CLK_SDONLY;
888 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
890 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
892 brcmf_err("Failed access turning clock off: %d\n",
900 /* Change idle/active SD state */
901 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
903 brcmf_dbg(SDIO, "Enter\n");
906 bus->clkstate = CLK_SDONLY;
908 bus->clkstate = CLK_NONE;
913 /* Transition SD and backplane clock readiness */
914 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
917 uint oldstate = bus->clkstate;
920 brcmf_dbg(SDIO, "Enter\n");
922 /* Early exit if we're already there */
923 if (bus->clkstate == target) {
924 if (target == CLK_AVAIL) {
925 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
926 bus->activity = true;
933 /* Make sure SD clock is available */
934 if (bus->clkstate == CLK_NONE)
935 brcmf_sdio_sdclk(bus, true);
936 /* Now request HT Avail on the backplane */
937 brcmf_sdio_htclk(bus, true, pendok);
938 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
939 bus->activity = true;
943 /* Remove HT request, or bring up SD clock */
944 if (bus->clkstate == CLK_NONE)
945 brcmf_sdio_sdclk(bus, true);
946 else if (bus->clkstate == CLK_AVAIL)
947 brcmf_sdio_htclk(bus, false, false);
949 brcmf_err("request for %d -> %d\n",
950 bus->clkstate, target);
951 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
955 /* Make sure to remove HT request */
956 if (bus->clkstate == CLK_AVAIL)
957 brcmf_sdio_htclk(bus, false, false);
958 /* Now remove the SD clock */
959 brcmf_sdio_sdclk(bus, false);
960 brcmf_sdio_wd_timer(bus, 0);
964 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
971 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
975 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
976 (sleep ? "SLEEP" : "WAKE"),
977 (bus->sleeping ? "SLEEP" : "WAKE"));
979 /* If SR is enabled control bus state with KSO */
980 if (bus->sr_enabled) {
981 /* Done if we're already in the requested state */
982 if (sleep == bus->sleeping)
987 /* Don't sleep if something is pending */
988 if (atomic_read(&bus->intstatus) ||
989 atomic_read(&bus->ipend) > 0 ||
990 (!atomic_read(&bus->fcstate) &&
991 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
994 err = brcmf_sdio_kso_control(bus, false);
995 /* disable watchdog */
997 brcmf_sdio_wd_timer(bus, 0);
1000 err = brcmf_sdio_kso_control(bus, true);
1004 bus->sleeping = sleep;
1005 brcmf_dbg(SDIO, "new state %s\n",
1006 (sleep ? "SLEEP" : "WAKE"));
1008 brcmf_err("error while changing bus sleep state %d\n",
1015 /* control clocks */
1017 if (!bus->sr_enabled)
1018 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
1020 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
1028 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
1030 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
1033 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
1034 struct sdpcm_shared *sh)
1039 struct sdpcm_shared_le sh_le;
1042 shaddr = bus->ci->rambase + bus->ramsize - 4;
1045 * Read last word in socram to determine
1046 * address of sdpcm_shared structure
1048 sdio_claim_host(bus->sdiodev->func[1]);
1049 brcmf_sdio_bus_sleep(bus, false, false);
1050 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4);
1051 sdio_release_host(bus->sdiodev->func[1]);
1055 addr = le32_to_cpu(addr_le);
1057 brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr);
1060 * Check if addr is valid.
1061 * NVRAM length at the end of memory should have been overwritten.
1063 if (!brcmf_sdio_valid_shared_address(addr)) {
1064 brcmf_err("invalid sdpcm_shared address 0x%08X\n",
1069 /* Read hndrte_shared structure */
1070 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1071 sizeof(struct sdpcm_shared_le));
1076 sh->flags = le32_to_cpu(sh_le.flags);
1077 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1078 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1079 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1080 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1081 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1082 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1084 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1085 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1086 SDPCM_SHARED_VERSION,
1087 sh->flags & SDPCM_SHARED_VERSION_MASK);
1094 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1096 struct sdpcm_shared sh;
1098 if (brcmf_sdio_readshared(bus, &sh) == 0)
1099 bus->console_addr = sh.console_addr;
1102 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1107 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1114 brcmf_dbg(SDIO, "Enter\n");
1116 /* Read mailbox data and ack that we did so */
1117 ret = r_sdreg32(bus, &hmb_data,
1118 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1121 w_sdreg32(bus, SMB_INT_ACK,
1122 offsetof(struct sdpcmd_regs, tosbmailbox));
1123 bus->sdcnt.f1regdata += 2;
1125 /* Dongle recomposed rx frames, accept them again */
1126 if (hmb_data & HMB_DATA_NAKHANDLED) {
1127 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1130 brcmf_err("unexpected NAKHANDLED!\n");
1132 bus->rxskip = false;
1133 intstatus |= I_HMB_FRAME_IND;
1137 * DEVREADY does not occur with gSPI.
1139 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1141 (hmb_data & HMB_DATA_VERSION_MASK) >>
1142 HMB_DATA_VERSION_SHIFT;
1143 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1144 brcmf_err("Version mismatch, dongle reports %d, "
1146 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1148 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1152 * Retrieve console state address now that firmware should have
1155 brcmf_sdio_get_console_addr(bus);
1159 * Flow Control has been moved into the RX headers and this out of band
1160 * method isn't used any more.
1161 * remaining backward compatible with older dongles.
1163 if (hmb_data & HMB_DATA_FC) {
1164 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1165 HMB_DATA_FCDATA_SHIFT;
1167 if (fcbits & ~bus->flowcontrol)
1168 bus->sdcnt.fc_xoff++;
1170 if (bus->flowcontrol & ~fcbits)
1171 bus->sdcnt.fc_xon++;
1173 bus->sdcnt.fc_rcvd++;
1174 bus->flowcontrol = fcbits;
1177 /* Shouldn't be any others */
1178 if (hmb_data & ~(HMB_DATA_DEVREADY |
1179 HMB_DATA_NAKHANDLED |
1182 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1183 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1189 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1196 brcmf_err("%sterminate frame%s\n",
1197 abort ? "abort command, " : "",
1198 rtx ? ", send NAK" : "");
1201 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1203 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1205 bus->sdcnt.f1regdata++;
1207 /* Wait until the packet has been flushed (device/FIFO stable) */
1208 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1209 hi = brcmf_sdiod_regrb(bus->sdiodev,
1210 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1211 lo = brcmf_sdiod_regrb(bus->sdiodev,
1212 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1213 bus->sdcnt.f1regdata += 2;
1215 if ((hi == 0) && (lo == 0))
1218 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1219 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1220 lastrbc, (hi << 8) + lo);
1222 lastrbc = (hi << 8) + lo;
1226 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1228 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1232 err = w_sdreg32(bus, SMB_NAK,
1233 offsetof(struct sdpcmd_regs, tosbmailbox));
1235 bus->sdcnt.f1regdata++;
1240 /* Clear partial in any case */
1241 bus->cur_read.len = 0;
1244 /* return total length of buffer chain */
1245 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1251 skb_queue_walk(&bus->glom, p)
1256 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1258 struct sk_buff *cur, *next;
1260 skb_queue_walk_safe(&bus->glom, cur, next) {
1261 skb_unlink(cur, &bus->glom);
1262 brcmu_pkt_buf_free_skb(cur);
1267 * brcmfmac sdio bus specific header
1268 * This is the lowest layer header wrapped on the packets transmitted between
1269 * host and WiFi dongle which contains information needed for SDIO core and
1272 * It consists of 3 parts: hardware header, hardware extension header and
1274 * hardware header (frame tag) - 4 bytes
1275 * Byte 0~1: Frame length
1276 * Byte 2~3: Checksum, bit-wise inverse of frame length
1277 * hardware extension header - 8 bytes
1278 * Tx glom mode only, N/A for Rx or normal Tx
1279 * Byte 0~1: Packet length excluding hw frame tag
1281 * Byte 3: Frame flags, bit 0: last frame indication
1282 * Byte 4~5: Reserved
1283 * Byte 6~7: Tail padding length
1284 * software header - 8 bytes
1285 * Byte 0: Rx/Tx sequence number
1286 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1287 * Byte 2: Length of next data frame, reserved for Tx
1288 * Byte 3: Data offset
1289 * Byte 4: Flow control bits, reserved for Tx
1290 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1291 * Byte 6~7: Reserved
1293 #define SDPCM_HWHDR_LEN 4
1294 #define SDPCM_HWEXT_LEN 8
1295 #define SDPCM_SWHDR_LEN 8
1296 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1297 /* software header */
1298 #define SDPCM_SEQ_MASK 0x000000ff
1299 #define SDPCM_SEQ_WRAP 256
1300 #define SDPCM_CHANNEL_MASK 0x00000f00
1301 #define SDPCM_CHANNEL_SHIFT 8
1302 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1303 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1304 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1305 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1306 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1307 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1308 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1309 #define SDPCM_NEXTLEN_SHIFT 16
1310 #define SDPCM_DOFFSET_MASK 0xff000000
1311 #define SDPCM_DOFFSET_SHIFT 24
1312 #define SDPCM_FCMASK_MASK 0x000000ff
1313 #define SDPCM_WINDOW_MASK 0x0000ff00
1314 #define SDPCM_WINDOW_SHIFT 8
1316 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1319 hdrvalue = *(u32 *)swheader;
1320 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1323 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1324 struct brcmf_sdio_hdrinfo *rd,
1325 enum brcmf_sdio_frmtype type)
1328 u8 rx_seq, fc, tx_seq_max;
1331 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1334 len = get_unaligned_le16(header);
1335 checksum = get_unaligned_le16(header + sizeof(u16));
1336 /* All zero means no more to read */
1337 if (!(len | checksum)) {
1338 bus->rxpending = false;
1341 if ((u16)(~(len ^ checksum))) {
1342 brcmf_err("HW header checksum error\n");
1343 bus->sdcnt.rx_badhdr++;
1344 brcmf_sdio_rxfail(bus, false, false);
1347 if (len < SDPCM_HDRLEN) {
1348 brcmf_err("HW header length error\n");
1351 if (type == BRCMF_SDIO_FT_SUPER &&
1352 (roundup(len, bus->blocksize) != rd->len)) {
1353 brcmf_err("HW superframe header length error\n");
1356 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1357 brcmf_err("HW subframe header length error\n");
1362 /* software header */
1363 header += SDPCM_HWHDR_LEN;
1364 swheader = le32_to_cpu(*(__le32 *)header);
1365 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1366 brcmf_err("Glom descriptor found in superframe head\n");
1370 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1371 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1372 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1373 type != BRCMF_SDIO_FT_SUPER) {
1374 brcmf_err("HW header length too long\n");
1375 bus->sdcnt.rx_toolong++;
1376 brcmf_sdio_rxfail(bus, false, false);
1380 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1381 brcmf_err("Wrong channel for superframe\n");
1385 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1386 rd->channel != SDPCM_EVENT_CHANNEL) {
1387 brcmf_err("Wrong channel for subframe\n");
1391 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1392 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1393 brcmf_err("seq %d: bad data offset\n", rx_seq);
1394 bus->sdcnt.rx_badhdr++;
1395 brcmf_sdio_rxfail(bus, false, false);
1399 if (rd->seq_num != rx_seq) {
1400 brcmf_err("seq %d: sequence number error, expect %d\n",
1401 rx_seq, rd->seq_num);
1402 bus->sdcnt.rx_badseq++;
1403 rd->seq_num = rx_seq;
1405 /* no need to check the reset for subframe */
1406 if (type == BRCMF_SDIO_FT_SUB)
1408 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1409 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1410 /* only warm for NON glom packet */
1411 if (rd->channel != SDPCM_GLOM_CHANNEL)
1412 brcmf_err("seq %d: next length error\n", rx_seq);
1415 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1416 fc = swheader & SDPCM_FCMASK_MASK;
1417 if (bus->flowcontrol != fc) {
1418 if (~bus->flowcontrol & fc)
1419 bus->sdcnt.fc_xoff++;
1420 if (bus->flowcontrol & ~fc)
1421 bus->sdcnt.fc_xon++;
1422 bus->sdcnt.fc_rcvd++;
1423 bus->flowcontrol = fc;
1425 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1426 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1427 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1428 tx_seq_max = bus->tx_seq + 2;
1430 bus->tx_max = tx_seq_max;
1435 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1437 *(__le16 *)header = cpu_to_le16(frm_length);
1438 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1441 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1442 struct brcmf_sdio_hdrinfo *hd_info)
1447 brcmf_sdio_update_hwhdr(header, hd_info->len);
1448 hdr_offset = SDPCM_HWHDR_LEN;
1451 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1452 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1453 hdrval = (u16)hd_info->tail_pad << 16;
1454 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1455 hdr_offset += SDPCM_HWEXT_LEN;
1458 hdrval = hd_info->seq_num;
1459 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1461 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1463 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1464 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1465 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1468 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1473 struct sk_buff *pfirst, *pnext;
1478 struct brcmf_sdio_hdrinfo rd_new;
1480 /* If packets, issue read(s) and send up packet chain */
1481 /* Return sequence numbers consumed? */
1483 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1484 bus->glomd, skb_peek(&bus->glom));
1486 /* If there's a descriptor, generate the packet chain */
1488 pfirst = pnext = NULL;
1489 dlen = (u16) (bus->glomd->len);
1490 dptr = bus->glomd->data;
1491 if (!dlen || (dlen & 1)) {
1492 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1497 for (totlen = num = 0; dlen; num++) {
1498 /* Get (and move past) next length */
1499 sublen = get_unaligned_le16(dptr);
1500 dlen -= sizeof(u16);
1501 dptr += sizeof(u16);
1502 if ((sublen < SDPCM_HDRLEN) ||
1503 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1504 brcmf_err("descriptor len %d bad: %d\n",
1509 if (sublen % bus->sgentry_align) {
1510 brcmf_err("sublen %d not multiple of %d\n",
1511 sublen, bus->sgentry_align);
1515 /* For last frame, adjust read len so total
1516 is a block multiple */
1519 (roundup(totlen, bus->blocksize) - totlen);
1520 totlen = roundup(totlen, bus->blocksize);
1523 /* Allocate/chain packet for next subframe */
1524 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1525 if (pnext == NULL) {
1526 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1530 skb_queue_tail(&bus->glom, pnext);
1532 /* Adhere to start alignment requirements */
1533 pkt_align(pnext, sublen, bus->sgentry_align);
1536 /* If all allocations succeeded, save packet chain
1539 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1541 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1542 totlen != bus->cur_read.len) {
1543 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1544 bus->cur_read.len, totlen, rxseq);
1546 pfirst = pnext = NULL;
1548 brcmf_sdio_free_glom(bus);
1552 /* Done with descriptor packet */
1553 brcmu_pkt_buf_free_skb(bus->glomd);
1555 bus->cur_read.len = 0;
1558 /* Ok -- either we just generated a packet chain,
1559 or had one from before */
1560 if (!skb_queue_empty(&bus->glom)) {
1561 if (BRCMF_GLOM_ON()) {
1562 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1563 skb_queue_walk(&bus->glom, pnext) {
1564 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1565 pnext, (u8 *) (pnext->data),
1566 pnext->len, pnext->len);
1570 pfirst = skb_peek(&bus->glom);
1571 dlen = (u16) brcmf_sdio_glom_len(bus);
1573 /* Do an SDIO read for the superframe. Configurable iovar to
1574 * read directly into the chained packet, or allocate a large
1575 * packet and and copy into the chain.
1577 sdio_claim_host(bus->sdiodev->func[1]);
1578 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1580 sdio_release_host(bus->sdiodev->func[1]);
1581 bus->sdcnt.f2rxdata++;
1583 /* On failure, kill the superframe, allow a couple retries */
1585 brcmf_err("glom read of %d bytes failed: %d\n",
1588 sdio_claim_host(bus->sdiodev->func[1]);
1589 if (bus->glomerr++ < 3) {
1590 brcmf_sdio_rxfail(bus, true, true);
1593 brcmf_sdio_rxfail(bus, true, false);
1594 bus->sdcnt.rxglomfail++;
1595 brcmf_sdio_free_glom(bus);
1597 sdio_release_host(bus->sdiodev->func[1]);
1601 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1602 pfirst->data, min_t(int, pfirst->len, 48),
1605 rd_new.seq_num = rxseq;
1607 sdio_claim_host(bus->sdiodev->func[1]);
1608 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1609 BRCMF_SDIO_FT_SUPER);
1610 sdio_release_host(bus->sdiodev->func[1]);
1611 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1613 /* Remove superframe header, remember offset */
1614 skb_pull(pfirst, rd_new.dat_offset);
1615 sfdoff = rd_new.dat_offset;
1618 /* Validate all the subframe headers */
1619 skb_queue_walk(&bus->glom, pnext) {
1620 /* leave when invalid subframe is found */
1624 rd_new.len = pnext->len;
1625 rd_new.seq_num = rxseq++;
1626 sdio_claim_host(bus->sdiodev->func[1]);
1627 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1629 sdio_release_host(bus->sdiodev->func[1]);
1630 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1631 pnext->data, 32, "subframe:\n");
1637 /* Terminate frame on error, request
1639 sdio_claim_host(bus->sdiodev->func[1]);
1640 if (bus->glomerr++ < 3) {
1641 /* Restore superframe header space */
1642 skb_push(pfirst, sfdoff);
1643 brcmf_sdio_rxfail(bus, true, true);
1646 brcmf_sdio_rxfail(bus, true, false);
1647 bus->sdcnt.rxglomfail++;
1648 brcmf_sdio_free_glom(bus);
1650 sdio_release_host(bus->sdiodev->func[1]);
1651 bus->cur_read.len = 0;
1655 /* Basic SD framing looks ok - process each packet (header) */
1657 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1658 dptr = (u8 *) (pfirst->data);
1659 sublen = get_unaligned_le16(dptr);
1660 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1662 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1664 "Rx Subframe Data:\n");
1666 __skb_trim(pfirst, sublen);
1667 skb_pull(pfirst, doff);
1669 if (pfirst->len == 0) {
1670 skb_unlink(pfirst, &bus->glom);
1671 brcmu_pkt_buf_free_skb(pfirst);
1675 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1677 min_t(int, pfirst->len, 32),
1678 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1679 bus->glom.qlen, pfirst, pfirst->data,
1680 pfirst->len, pfirst->next,
1682 skb_unlink(pfirst, &bus->glom);
1683 brcmf_rx_frame(bus->sdiodev->dev, pfirst);
1684 bus->sdcnt.rxglompkts++;
1687 bus->sdcnt.rxglomframes++;
1692 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1695 DECLARE_WAITQUEUE(wait, current);
1696 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1698 /* Wait until control frame is available */
1699 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1700 set_current_state(TASK_INTERRUPTIBLE);
1702 while (!(*condition) && (!signal_pending(current) && timeout))
1703 timeout = schedule_timeout(timeout);
1705 if (signal_pending(current))
1708 set_current_state(TASK_RUNNING);
1709 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1714 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1716 if (waitqueue_active(&bus->dcmd_resp_wait))
1717 wake_up_interruptible(&bus->dcmd_resp_wait);
1722 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1725 u8 *buf = NULL, *rbuf;
1728 brcmf_dbg(TRACE, "Enter\n");
1731 buf = vzalloc(bus->rxblen);
1736 pad = ((unsigned long)rbuf % bus->head_align);
1738 rbuf += (bus->head_align - pad);
1740 /* Copy the already-read portion over */
1741 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1742 if (len <= BRCMF_FIRSTREAD)
1745 /* Raise rdlen to next SDIO block to avoid tail command */
1746 rdlen = len - BRCMF_FIRSTREAD;
1747 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1748 pad = bus->blocksize - (rdlen % bus->blocksize);
1749 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1750 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1752 } else if (rdlen % bus->head_align) {
1753 rdlen += bus->head_align - (rdlen % bus->head_align);
1756 /* Drop if the read is too big or it exceeds our maximum */
1757 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1758 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1759 rdlen, bus->sdiodev->bus_if->maxctl);
1760 brcmf_sdio_rxfail(bus, false, false);
1764 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1765 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1766 len, len - doff, bus->sdiodev->bus_if->maxctl);
1767 bus->sdcnt.rx_toolong++;
1768 brcmf_sdio_rxfail(bus, false, false);
1772 /* Read remain of frame body */
1773 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1774 bus->sdcnt.f2rxdata++;
1776 /* Control frame failures need retransmission */
1778 brcmf_err("read %d control bytes failed: %d\n",
1780 bus->sdcnt.rxc_errors++;
1781 brcmf_sdio_rxfail(bus, true, true);
1784 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1788 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1789 buf, len, "RxCtrl:\n");
1791 /* Point to valid data and indicate its length */
1792 spin_lock_bh(&bus->rxctl_lock);
1794 brcmf_err("last control frame is being processed.\n");
1795 spin_unlock_bh(&bus->rxctl_lock);
1799 bus->rxctl = buf + doff;
1800 bus->rxctl_orig = buf;
1801 bus->rxlen = len - doff;
1802 spin_unlock_bh(&bus->rxctl_lock);
1805 /* Awake any waiters */
1806 brcmf_sdio_dcmd_resp_wake(bus);
1809 /* Pad read to blocksize for efficiency */
1810 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1812 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1813 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1814 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1815 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1817 } else if (*rdlen % bus->head_align) {
1818 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1822 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1824 struct sk_buff *pkt; /* Packet for event or data frames */
1825 u16 pad; /* Number of pad bytes to read */
1826 uint rxleft = 0; /* Remaining number of frames allowed */
1827 int ret; /* Return code from calls */
1828 uint rxcount = 0; /* Total frames read */
1829 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1832 brcmf_dbg(TRACE, "Enter\n");
1834 /* Not finished unless we encounter no more frames indication */
1835 bus->rxpending = true;
1837 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1838 !bus->rxskip && rxleft && brcmf_bus_ready(bus->sdiodev->bus_if);
1839 rd->seq_num++, rxleft--) {
1841 /* Handle glomming separately */
1842 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1844 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1845 bus->glomd, skb_peek(&bus->glom));
1846 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1847 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1848 rd->seq_num += cnt - 1;
1849 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1853 rd->len_left = rd->len;
1854 /* read header first for unknow frame length */
1855 sdio_claim_host(bus->sdiodev->func[1]);
1857 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1858 bus->rxhdr, BRCMF_FIRSTREAD);
1859 bus->sdcnt.f2rxhdrs++;
1861 brcmf_err("RXHEADER FAILED: %d\n",
1863 bus->sdcnt.rx_hdrfail++;
1864 brcmf_sdio_rxfail(bus, true, true);
1865 sdio_release_host(bus->sdiodev->func[1]);
1869 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1870 bus->rxhdr, SDPCM_HDRLEN,
1873 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1874 BRCMF_SDIO_FT_NORMAL)) {
1875 sdio_release_host(bus->sdiodev->func[1]);
1876 if (!bus->rxpending)
1882 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1883 brcmf_sdio_read_control(bus, bus->rxhdr,
1886 /* prepare the descriptor for the next read */
1887 rd->len = rd->len_nxtfrm << 4;
1889 /* treat all packet as event if we don't know */
1890 rd->channel = SDPCM_EVENT_CHANNEL;
1891 sdio_release_host(bus->sdiodev->func[1]);
1894 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1895 rd->len - BRCMF_FIRSTREAD : 0;
1896 head_read = BRCMF_FIRSTREAD;
1899 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1901 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1904 /* Give up on data, request rtx of events */
1905 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1906 brcmf_sdio_rxfail(bus, false,
1907 RETRYCHAN(rd->channel));
1908 sdio_release_host(bus->sdiodev->func[1]);
1911 skb_pull(pkt, head_read);
1912 pkt_align(pkt, rd->len_left, bus->head_align);
1914 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1915 bus->sdcnt.f2rxdata++;
1916 sdio_release_host(bus->sdiodev->func[1]);
1919 brcmf_err("read %d bytes from channel %d failed: %d\n",
1920 rd->len, rd->channel, ret);
1921 brcmu_pkt_buf_free_skb(pkt);
1922 sdio_claim_host(bus->sdiodev->func[1]);
1923 brcmf_sdio_rxfail(bus, true,
1924 RETRYCHAN(rd->channel));
1925 sdio_release_host(bus->sdiodev->func[1]);
1930 skb_push(pkt, head_read);
1931 memcpy(pkt->data, bus->rxhdr, head_read);
1934 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1935 rd_new.seq_num = rd->seq_num;
1936 sdio_claim_host(bus->sdiodev->func[1]);
1937 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1938 BRCMF_SDIO_FT_NORMAL)) {
1940 brcmu_pkt_buf_free_skb(pkt);
1942 bus->sdcnt.rx_readahead_cnt++;
1943 if (rd->len != roundup(rd_new.len, 16)) {
1944 brcmf_err("frame length mismatch:read %d, should be %d\n",
1946 roundup(rd_new.len, 16) >> 4);
1948 brcmf_sdio_rxfail(bus, true, true);
1949 sdio_release_host(bus->sdiodev->func[1]);
1950 brcmu_pkt_buf_free_skb(pkt);
1953 sdio_release_host(bus->sdiodev->func[1]);
1954 rd->len_nxtfrm = rd_new.len_nxtfrm;
1955 rd->channel = rd_new.channel;
1956 rd->dat_offset = rd_new.dat_offset;
1958 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1961 bus->rxhdr, SDPCM_HDRLEN,
1964 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1965 brcmf_err("readahead on control packet %d?\n",
1967 /* Force retry w/normal header read */
1969 sdio_claim_host(bus->sdiodev->func[1]);
1970 brcmf_sdio_rxfail(bus, false, true);
1971 sdio_release_host(bus->sdiodev->func[1]);
1972 brcmu_pkt_buf_free_skb(pkt);
1977 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1978 pkt->data, rd->len, "Rx Data:\n");
1980 /* Save superframe descriptor and allocate packet frame */
1981 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1982 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1983 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1985 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1988 __skb_trim(pkt, rd->len);
1989 skb_pull(pkt, SDPCM_HDRLEN);
1992 brcmf_err("%s: glom superframe w/o "
1993 "descriptor!\n", __func__);
1994 sdio_claim_host(bus->sdiodev->func[1]);
1995 brcmf_sdio_rxfail(bus, false, false);
1996 sdio_release_host(bus->sdiodev->func[1]);
1998 /* prepare the descriptor for the next read */
1999 rd->len = rd->len_nxtfrm << 4;
2001 /* treat all packet as event if we don't know */
2002 rd->channel = SDPCM_EVENT_CHANNEL;
2006 /* Fill in packet len and prio, deliver upward */
2007 __skb_trim(pkt, rd->len);
2008 skb_pull(pkt, rd->dat_offset);
2010 /* prepare the descriptor for the next read */
2011 rd->len = rd->len_nxtfrm << 4;
2013 /* treat all packet as event if we don't know */
2014 rd->channel = SDPCM_EVENT_CHANNEL;
2016 if (pkt->len == 0) {
2017 brcmu_pkt_buf_free_skb(pkt);
2021 brcmf_rx_frame(bus->sdiodev->dev, pkt);
2024 rxcount = maxframes - rxleft;
2025 /* Message if we hit the limit */
2027 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2029 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2030 /* Back off rxseq if awaiting rtx, update rx_seq */
2033 bus->rx_seq = rd->seq_num;
2039 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2041 if (waitqueue_active(&bus->ctrl_wait))
2042 wake_up_interruptible(&bus->ctrl_wait);
2046 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2051 dat_buf = (u8 *)(pkt->data);
2053 /* Check head padding */
2054 head_pad = ((unsigned long)dat_buf % bus->head_align);
2056 if (skb_headroom(pkt) < head_pad) {
2057 bus->sdiodev->bus_if->tx_realloc++;
2059 if (skb_cow(pkt, head_pad))
2062 skb_push(pkt, head_pad);
2063 dat_buf = (u8 *)(pkt->data);
2064 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2070 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2073 /* flag marking a dummy skb added for DMA alignment requirement */
2074 #define ALIGN_SKB_FLAG 0x8000
2075 /* bit mask of data length chopped from the previous packet */
2076 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2078 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2079 struct sk_buff_head *pktq,
2080 struct sk_buff *pkt, u16 total_len)
2082 struct brcmf_sdio_dev *sdiodev;
2083 struct sk_buff *pkt_pad;
2084 u16 tail_pad, tail_chop, chain_pad;
2085 unsigned int blksize;
2089 sdiodev = bus->sdiodev;
2090 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2091 /* sg entry alignment should be a divisor of block size */
2092 WARN_ON(blksize % bus->sgentry_align);
2094 /* Check tail padding */
2095 lastfrm = skb_queue_is_last(pktq, pkt);
2097 tail_chop = pkt->len % bus->sgentry_align;
2099 tail_pad = bus->sgentry_align - tail_chop;
2100 chain_pad = (total_len + tail_pad) % blksize;
2101 if (lastfrm && chain_pad)
2102 tail_pad += blksize - chain_pad;
2103 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2104 pkt_pad = bus->txglom_sgpad;
2105 if (pkt_pad == NULL)
2106 brcmu_pkt_buf_get_skb(tail_pad + tail_chop);
2107 if (pkt_pad == NULL)
2109 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2110 if (unlikely(ret < 0))
2112 memcpy(pkt_pad->data,
2113 pkt->data + pkt->len - tail_chop,
2115 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2116 skb_trim(pkt, pkt->len - tail_chop);
2117 __skb_queue_after(pktq, pkt, pkt_pad);
2119 ntail = pkt->data_len + tail_pad -
2120 (pkt->end - pkt->tail);
2121 if (skb_cloned(pkt) || ntail > 0)
2122 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2124 if (skb_linearize(pkt))
2126 __skb_put(pkt, tail_pad);
2133 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2134 * @bus: brcmf_sdio structure pointer
2135 * @pktq: packet list pointer
2136 * @chan: virtual channel to transmit the packet
2138 * Processes to be applied to the packet
2139 * - Align data buffer pointer
2140 * - Align data buffer length
2142 * Return: negative value if there is error
2145 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2148 u16 head_pad, total_len;
2149 struct sk_buff *pkt_next;
2152 struct brcmf_sdio_hdrinfo hd_info = {0};
2154 txseq = bus->tx_seq;
2156 skb_queue_walk(pktq, pkt_next) {
2157 /* alignment packet inserted in previous
2158 * loop cycle can be skipped as it is
2159 * already properly aligned and does not
2160 * need an sdpcm header.
2162 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2165 /* align packet data pointer */
2166 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2169 head_pad = (u16)ret;
2171 memset(pkt_next->data, 0, head_pad + bus->tx_hdrlen);
2173 total_len += pkt_next->len;
2175 hd_info.len = pkt_next->len;
2176 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2177 if (bus->txglom && pktq->qlen > 1) {
2178 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2179 pkt_next, total_len);
2182 hd_info.tail_pad = (u16)ret;
2183 total_len += (u16)ret;
2186 hd_info.channel = chan;
2187 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2188 hd_info.seq_num = txseq++;
2190 /* Now fill the header */
2191 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2193 if (BRCMF_BYTES_ON() &&
2194 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2195 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2196 brcmf_dbg_hex_dump(true, pkt_next, hd_info.len,
2198 else if (BRCMF_HDRS_ON())
2199 brcmf_dbg_hex_dump(true, pkt_next,
2200 head_pad + bus->tx_hdrlen,
2203 /* Hardware length tag of the first packet should be total
2204 * length of the chain (including padding)
2207 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2212 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2213 * @bus: brcmf_sdio structure pointer
2214 * @pktq: packet list pointer
2216 * Processes to be applied to the packet
2217 * - Remove head padding
2218 * - Remove tail padding
2221 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2226 u16 dummy_flags, chop_len;
2227 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2229 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2230 dummy_flags = *(u16 *)(pkt_next->cb);
2231 if (dummy_flags & ALIGN_SKB_FLAG) {
2232 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2234 pkt_prev = pkt_next->prev;
2235 skb_put(pkt_prev, chop_len);
2237 __skb_unlink(pkt_next, pktq);
2238 brcmu_pkt_buf_free_skb(pkt_next);
2240 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2241 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2242 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2243 SDPCM_DOFFSET_SHIFT;
2244 skb_pull(pkt_next, dat_offset);
2246 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2247 skb_trim(pkt_next, pkt_next->len - tail_pad);
2253 /* Writes a HW/SW header into the packet and sends it. */
2254 /* Assumes: (a) header space already there, (b) caller holds lock */
2255 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2260 struct sk_buff *pkt_next, *tmp;
2262 brcmf_dbg(TRACE, "Enter\n");
2264 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2268 sdio_claim_host(bus->sdiodev->func[1]);
2269 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2270 bus->sdcnt.f2txdata++;
2273 /* On failure, abort the command and terminate the frame */
2274 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2276 bus->sdcnt.tx_sderrs++;
2278 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
2279 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
2281 bus->sdcnt.f1regdata++;
2283 for (i = 0; i < 3; i++) {
2285 hi = brcmf_sdiod_regrb(bus->sdiodev,
2286 SBSDIO_FUNC1_WFRAMEBCHI, NULL);
2287 lo = brcmf_sdiod_regrb(bus->sdiodev,
2288 SBSDIO_FUNC1_WFRAMEBCLO, NULL);
2289 bus->sdcnt.f1regdata += 2;
2290 if ((hi == 0) && (lo == 0))
2294 sdio_release_host(bus->sdiodev->func[1]);
2297 brcmf_sdio_txpkt_postp(bus, pktq);
2299 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2300 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2301 __skb_unlink(pkt_next, pktq);
2302 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2307 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2309 struct sk_buff *pkt;
2310 struct sk_buff_head pktq;
2312 int ret = 0, prec_out, i;
2314 u8 tx_prec_map, pkt_num;
2316 brcmf_dbg(TRACE, "Enter\n");
2318 tx_prec_map = ~bus->flowcontrol;
2320 /* Send frames until the limit or some other event */
2321 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2323 __skb_queue_head_init(&pktq);
2325 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2326 brcmf_sdio_txglomsz);
2327 pkt_num = min_t(u32, pkt_num,
2328 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2329 spin_lock_bh(&bus->txqlock);
2330 for (i = 0; i < pkt_num; i++) {
2331 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2335 __skb_queue_tail(&pktq, pkt);
2337 spin_unlock_bh(&bus->txqlock);
2341 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2344 /* In poll mode, need to check for other events */
2345 if (!bus->intr && cnt) {
2346 /* Check device status, signal pending interrupt */
2347 sdio_claim_host(bus->sdiodev->func[1]);
2348 ret = r_sdreg32(bus, &intstatus,
2349 offsetof(struct sdpcmd_regs,
2351 sdio_release_host(bus->sdiodev->func[1]);
2352 bus->sdcnt.f2txdata++;
2355 if (intstatus & bus->hostintmask)
2356 atomic_set(&bus->ipend, 1);
2360 /* Deflow-control stack if needed */
2361 if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) &&
2362 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2364 brcmf_txflowblock(bus->sdiodev->dev, false);
2370 static void brcmf_sdio_bus_stop(struct device *dev)
2372 u32 local_hostintmask;
2375 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2376 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2377 struct brcmf_sdio *bus = sdiodev->bus;
2379 brcmf_dbg(TRACE, "Enter\n");
2381 if (bus->watchdog_tsk) {
2382 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2383 kthread_stop(bus->watchdog_tsk);
2384 bus->watchdog_tsk = NULL;
2387 if (bus_if->state == BRCMF_BUS_DOWN) {
2388 sdio_claim_host(sdiodev->func[1]);
2390 /* Enable clock for device interrupts */
2391 brcmf_sdio_bus_sleep(bus, false, false);
2393 /* Disable and clear interrupts at the chip level also */
2394 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2395 local_hostintmask = bus->hostintmask;
2396 bus->hostintmask = 0;
2398 /* Force backplane clocks to assure F2 interrupt propagates */
2399 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2402 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2403 (saveclk | SBSDIO_FORCE_HT), &err);
2405 brcmf_err("Failed to force clock for F2: err %d\n",
2408 /* Turn off the bus (F2), free any pending packets */
2409 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2410 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2412 /* Clear any pending interrupts now that F2 is disabled */
2413 w_sdreg32(bus, local_hostintmask,
2414 offsetof(struct sdpcmd_regs, intstatus));
2416 sdio_release_host(sdiodev->func[1]);
2418 /* Clear the data packet queues */
2419 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2421 /* Clear any held glomming stuff */
2423 brcmu_pkt_buf_free_skb(bus->glomd);
2424 brcmf_sdio_free_glom(bus);
2426 /* Clear rx control and wake any waiters */
2427 spin_lock_bh(&bus->rxctl_lock);
2429 spin_unlock_bh(&bus->rxctl_lock);
2430 brcmf_sdio_dcmd_resp_wake(bus);
2432 /* Reset some F2 state stuff */
2433 bus->rxskip = false;
2434 bus->tx_seq = bus->rx_seq = 0;
2437 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2439 unsigned long flags;
2441 if (bus->sdiodev->oob_irq_requested) {
2442 spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
2443 if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2444 enable_irq(bus->sdiodev->pdata->oob_irq_nr);
2445 bus->sdiodev->irq_en = true;
2447 spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
2451 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2453 struct brcmf_core *buscore;
2458 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2459 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2461 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2462 bus->sdcnt.f1regdata++;
2466 val &= bus->hostintmask;
2467 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2469 /* Clear interrupts */
2471 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2472 bus->sdcnt.f1regdata++;
2476 atomic_set(&bus->intstatus, 0);
2478 for_each_set_bit(n, &val, 32)
2479 set_bit(n, (unsigned long *)&bus->intstatus.counter);
2485 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2488 unsigned long intstatus;
2489 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2490 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2491 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2494 brcmf_dbg(TRACE, "Enter\n");
2496 sdio_claim_host(bus->sdiodev->func[1]);
2498 /* If waiting for HTAVAIL, check status */
2499 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2500 u8 clkctl, devctl = 0;
2503 /* Check for inconsistent device control */
2504 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2505 SBSDIO_DEVICE_CTL, &err);
2508 /* Read CSR, if clock on switch to AVAIL, else ignore */
2509 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2510 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2512 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2515 if (SBSDIO_HTAV(clkctl)) {
2516 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2517 SBSDIO_DEVICE_CTL, &err);
2518 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2519 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2521 bus->clkstate = CLK_AVAIL;
2525 /* Make sure backplane clock is on */
2526 brcmf_sdio_bus_sleep(bus, false, true);
2528 /* Pending interrupt indicates new device status */
2529 if (atomic_read(&bus->ipend) > 0) {
2530 atomic_set(&bus->ipend, 0);
2531 err = brcmf_sdio_intr_rstatus(bus);
2534 /* Start with leftover status bits */
2535 intstatus = atomic_xchg(&bus->intstatus, 0);
2537 /* Handle flow-control change: read new state in case our ack
2538 * crossed another change interrupt. If change still set, assume
2539 * FC ON for safety, let next loop through do the debounce.
2541 if (intstatus & I_HMB_FC_CHANGE) {
2542 intstatus &= ~I_HMB_FC_CHANGE;
2543 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2544 offsetof(struct sdpcmd_regs, intstatus));
2546 err = r_sdreg32(bus, &newstatus,
2547 offsetof(struct sdpcmd_regs, intstatus));
2548 bus->sdcnt.f1regdata += 2;
2549 atomic_set(&bus->fcstate,
2550 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2551 intstatus |= (newstatus & bus->hostintmask);
2554 /* Handle host mailbox indication */
2555 if (intstatus & I_HMB_HOST_INT) {
2556 intstatus &= ~I_HMB_HOST_INT;
2557 intstatus |= brcmf_sdio_hostmail(bus);
2560 sdio_release_host(bus->sdiodev->func[1]);
2562 /* Generally don't ask for these, can get CRC errors... */
2563 if (intstatus & I_WR_OOSYNC) {
2564 brcmf_err("Dongle reports WR_OOSYNC\n");
2565 intstatus &= ~I_WR_OOSYNC;
2568 if (intstatus & I_RD_OOSYNC) {
2569 brcmf_err("Dongle reports RD_OOSYNC\n");
2570 intstatus &= ~I_RD_OOSYNC;
2573 if (intstatus & I_SBINT) {
2574 brcmf_err("Dongle reports SBINT\n");
2575 intstatus &= ~I_SBINT;
2578 /* Would be active due to wake-wlan in gSPI */
2579 if (intstatus & I_CHIPACTIVE) {
2580 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2581 intstatus &= ~I_CHIPACTIVE;
2584 /* Ignore frame indications if rxskip is set */
2586 intstatus &= ~I_HMB_FRAME_IND;
2588 /* On frame indication, read available frames */
2589 if (PKT_AVAILABLE() && bus->clkstate == CLK_AVAIL) {
2590 framecnt = brcmf_sdio_readframes(bus, rxlimit);
2591 if (!bus->rxpending)
2592 intstatus &= ~I_HMB_FRAME_IND;
2593 rxlimit -= min(framecnt, rxlimit);
2596 /* Keep still-pending events for next scheduling */
2598 for_each_set_bit(n, &intstatus, 32)
2599 set_bit(n, (unsigned long *)&bus->intstatus.counter);
2602 brcmf_sdio_clrintr(bus);
2604 if (data_ok(bus) && bus->ctrl_frame_stat &&
2605 (bus->clkstate == CLK_AVAIL)) {
2608 sdio_claim_host(bus->sdiodev->func[1]);
2609 err = brcmf_sdiod_send_buf(bus->sdiodev, bus->ctrl_frame_buf,
2610 (u32)bus->ctrl_frame_len);
2613 /* On failure, abort the command and
2614 terminate the frame */
2615 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2617 bus->sdcnt.tx_sderrs++;
2619 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
2621 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
2623 bus->sdcnt.f1regdata++;
2625 for (i = 0; i < 3; i++) {
2627 hi = brcmf_sdiod_regrb(bus->sdiodev,
2628 SBSDIO_FUNC1_WFRAMEBCHI,
2630 lo = brcmf_sdiod_regrb(bus->sdiodev,
2631 SBSDIO_FUNC1_WFRAMEBCLO,
2633 bus->sdcnt.f1regdata += 2;
2634 if ((hi == 0) && (lo == 0))
2639 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2641 sdio_release_host(bus->sdiodev->func[1]);
2642 bus->ctrl_frame_stat = false;
2643 brcmf_sdio_wait_event_wakeup(bus);
2645 /* Send queued frames (limit 1 if rx may still be pending) */
2646 else if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2647 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2649 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2651 framecnt = brcmf_sdio_sendfromq(bus, framecnt);
2652 txlimit -= framecnt;
2655 if (!brcmf_bus_ready(bus->sdiodev->bus_if) || (err != 0)) {
2656 brcmf_err("failed backplane access over SDIO, halting operation\n");
2657 atomic_set(&bus->intstatus, 0);
2658 } else if (atomic_read(&bus->intstatus) ||
2659 atomic_read(&bus->ipend) > 0 ||
2660 (!atomic_read(&bus->fcstate) &&
2661 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2662 data_ok(bus)) || PKT_AVAILABLE()) {
2663 atomic_inc(&bus->dpc_tskcnt);
2666 /* If we're done for now, turn off clock request. */
2667 if ((bus->clkstate != CLK_PENDING)
2668 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2669 bus->activity = false;
2670 brcmf_dbg(SDIO, "idle state\n");
2671 sdio_claim_host(bus->sdiodev->func[1]);
2672 brcmf_sdio_bus_sleep(bus, true, false);
2673 sdio_release_host(bus->sdiodev->func[1]);
2677 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2679 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2680 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2681 struct brcmf_sdio *bus = sdiodev->bus;
2686 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2690 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2691 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2692 struct brcmf_sdio *bus = sdiodev->bus;
2695 brcmf_dbg(TRACE, "Enter\n");
2699 /* Add space for the header */
2700 skb_push(pkt, bus->tx_hdrlen);
2701 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2703 prec = prio2prec((pkt->priority & PRIOMASK));
2705 /* Check for existing queue, current flow-control,
2706 pending event, or pending clock */
2707 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2708 bus->sdcnt.fcqueued++;
2710 /* Priority based enq */
2711 spin_lock_irqsave(&bus->txqlock, flags);
2712 /* reset bus_flags in packet cb */
2713 *(u16 *)(pkt->cb) = 0;
2714 if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) {
2715 skb_pull(pkt, bus->tx_hdrlen);
2716 brcmf_err("out of bus->txq !!!\n");
2722 if (pktq_len(&bus->txq) >= TXHI) {
2724 brcmf_txflowblock(bus->sdiodev->dev, true);
2726 spin_unlock_irqrestore(&bus->txqlock, flags);
2729 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2730 qcount[prec] = pktq_plen(&bus->txq, prec);
2733 if (atomic_read(&bus->dpc_tskcnt) == 0) {
2734 atomic_inc(&bus->dpc_tskcnt);
2735 queue_work(bus->brcmf_wq, &bus->datawork);
2742 #define CONSOLE_LINE_MAX 192
2744 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2746 struct brcmf_console *c = &bus->console;
2747 u8 line[CONSOLE_LINE_MAX], ch;
2751 /* Don't do anything until FWREADY updates console address */
2752 if (bus->console_addr == 0)
2755 /* Read console log struct */
2756 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2757 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2762 /* Allocate console buffer (one time only) */
2763 if (c->buf == NULL) {
2764 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2765 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2770 idx = le32_to_cpu(c->log_le.idx);
2772 /* Protect against corrupt value */
2773 if (idx > c->bufsize)
2776 /* Skip reading the console buffer if the index pointer
2781 /* Read the console buffer */
2782 addr = le32_to_cpu(c->log_le.buf);
2783 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2787 while (c->last != idx) {
2788 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2789 if (c->last == idx) {
2790 /* This would output a partial line.
2792 * the buffer pointer and output this
2793 * line next time around.
2798 c->last = c->bufsize - n;
2801 ch = c->buf[c->last];
2802 c->last = (c->last + 1) % c->bufsize;
2809 if (line[n - 1] == '\r')
2812 pr_debug("CONSOLE: %s\n", line);
2821 static int brcmf_sdio_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
2826 bus->ctrl_frame_stat = false;
2827 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2830 /* On failure, abort the command and terminate the frame */
2831 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2833 bus->sdcnt.tx_sderrs++;
2835 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
2837 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
2839 bus->sdcnt.f1regdata++;
2841 for (i = 0; i < 3; i++) {
2843 hi = brcmf_sdiod_regrb(bus->sdiodev,
2844 SBSDIO_FUNC1_WFRAMEBCHI, NULL);
2845 lo = brcmf_sdiod_regrb(bus->sdiodev,
2846 SBSDIO_FUNC1_WFRAMEBCLO, NULL);
2847 bus->sdcnt.f1regdata += 2;
2848 if (hi == 0 && lo == 0)
2854 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2860 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2867 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2868 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2869 struct brcmf_sdio *bus = sdiodev->bus;
2870 struct brcmf_sdio_hdrinfo hd_info = {0};
2872 brcmf_dbg(TRACE, "Enter\n");
2874 /* Back the pointer to make a room for bus header */
2875 frame = msg - bus->tx_hdrlen;
2876 len = (msglen += bus->tx_hdrlen);
2878 /* Add alignment padding (optional for ctl frames) */
2879 doff = ((unsigned long)frame % bus->head_align);
2884 memset(frame, 0, doff + bus->tx_hdrlen);
2886 /* precondition: doff < bus->head_align */
2887 doff += bus->tx_hdrlen;
2889 /* Round send length to next SDIO block */
2891 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2892 pad = bus->blocksize - (len % bus->blocksize);
2893 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2895 } else if (len % bus->head_align) {
2896 pad = bus->head_align - (len % bus->head_align);
2900 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2902 /* Make sure backplane clock is on */
2903 sdio_claim_host(bus->sdiodev->func[1]);
2904 brcmf_sdio_bus_sleep(bus, false, false);
2905 sdio_release_host(bus->sdiodev->func[1]);
2907 hd_info.len = (u16)msglen;
2908 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2909 hd_info.dat_offset = doff;
2910 hd_info.seq_num = bus->tx_seq;
2911 hd_info.lastfrm = true;
2912 hd_info.tail_pad = pad;
2913 brcmf_sdio_hdpack(bus, frame, &hd_info);
2916 brcmf_sdio_update_hwhdr(frame, len);
2918 if (!data_ok(bus)) {
2919 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
2920 bus->tx_max, bus->tx_seq);
2921 bus->ctrl_frame_stat = true;
2923 bus->ctrl_frame_buf = frame;
2924 bus->ctrl_frame_len = len;
2926 wait_event_interruptible_timeout(bus->ctrl_wait,
2927 !bus->ctrl_frame_stat,
2928 msecs_to_jiffies(2000));
2930 if (!bus->ctrl_frame_stat) {
2931 brcmf_dbg(SDIO, "ctrl_frame_stat == false\n");
2934 brcmf_dbg(SDIO, "ctrl_frame_stat == true\n");
2940 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2941 frame, len, "Tx Frame:\n");
2942 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2944 frame, min_t(u16, len, 16), "TxHdr:\n");
2947 sdio_claim_host(bus->sdiodev->func[1]);
2948 ret = brcmf_sdio_tx_frame(bus, frame, len);
2949 sdio_release_host(bus->sdiodev->func[1]);
2950 } while (ret < 0 && retries++ < TXRETRIES);
2953 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) &&
2954 atomic_read(&bus->dpc_tskcnt) == 0) {
2955 bus->activity = false;
2956 sdio_claim_host(bus->sdiodev->func[1]);
2957 brcmf_dbg(INFO, "idle\n");
2958 brcmf_sdio_clkctl(bus, CLK_NONE, true);
2959 sdio_release_host(bus->sdiodev->func[1]);
2963 bus->sdcnt.tx_ctlerrs++;
2965 bus->sdcnt.tx_ctlpkts++;
2967 return ret ? -EIO : 0;
2971 static int brcmf_sdio_dump_console(struct brcmf_sdio *bus,
2972 struct sdpcm_shared *sh, char __user *data,
2975 u32 addr, console_ptr, console_size, console_index;
2976 char *conbuf = NULL;
2982 /* obtain console information from device memory */
2983 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2984 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2985 (u8 *)&sh_val, sizeof(u32));
2988 console_ptr = le32_to_cpu(sh_val);
2990 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2991 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2992 (u8 *)&sh_val, sizeof(u32));
2995 console_size = le32_to_cpu(sh_val);
2997 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2998 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2999 (u8 *)&sh_val, sizeof(u32));
3002 console_index = le32_to_cpu(sh_val);
3004 /* allocate buffer for console data */
3005 if (console_size <= CONSOLE_BUFFER_MAX)
3006 conbuf = vzalloc(console_size+1);
3011 /* obtain the console data from device */
3012 conbuf[console_size] = '\0';
3013 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
3018 rv = simple_read_from_buffer(data, count, &pos,
3019 conbuf + console_index,
3020 console_size - console_index);
3025 if (console_index > 0) {
3027 rv = simple_read_from_buffer(data+nbytes, count, &pos,
3028 conbuf, console_index - 1);
3038 static int brcmf_sdio_trap_info(struct brcmf_sdio *bus, struct sdpcm_shared *sh,
3039 char __user *data, size_t count)
3043 struct brcmf_trap_info tr;
3046 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
3047 brcmf_dbg(INFO, "no trap in firmware\n");
3051 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3052 sizeof(struct brcmf_trap_info));
3056 res = scnprintf(buf, sizeof(buf),
3057 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3058 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3059 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3060 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3061 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3062 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3063 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3064 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3065 le32_to_cpu(tr.pc), sh->trap_addr,
3066 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3067 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3068 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3069 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3071 return simple_read_from_buffer(data, count, &pos, buf, res);
3074 static int brcmf_sdio_assert_info(struct brcmf_sdio *bus,
3075 struct sdpcm_shared *sh, char __user *data,
3080 char file[80] = "?";
3081 char expr[80] = "<???>";
3085 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3086 brcmf_dbg(INFO, "firmware not built with -assert\n");
3088 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3089 brcmf_dbg(INFO, "no assert in dongle\n");
3093 sdio_claim_host(bus->sdiodev->func[1]);
3094 if (sh->assert_file_addr != 0) {
3095 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3096 sh->assert_file_addr, (u8 *)file, 80);
3100 if (sh->assert_exp_addr != 0) {
3101 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3102 sh->assert_exp_addr, (u8 *)expr, 80);
3106 sdio_release_host(bus->sdiodev->func[1]);
3108 res = scnprintf(buf, sizeof(buf),
3109 "dongle assert: %s:%d: assert(%s)\n",
3110 file, sh->assert_line, expr);
3111 return simple_read_from_buffer(data, count, &pos, buf, res);
3114 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3117 struct sdpcm_shared sh;
3119 error = brcmf_sdio_readshared(bus, &sh);
3124 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3125 brcmf_dbg(INFO, "firmware not built with -assert\n");
3126 else if (sh.flags & SDPCM_SHARED_ASSERT)
3127 brcmf_err("assertion in dongle\n");
3129 if (sh.flags & SDPCM_SHARED_TRAP)
3130 brcmf_err("firmware trap in dongle\n");
3135 static int brcmf_sdio_died_dump(struct brcmf_sdio *bus, char __user *data,
3136 size_t count, loff_t *ppos)
3139 struct sdpcm_shared sh;
3146 error = brcmf_sdio_readshared(bus, &sh);
3150 error = brcmf_sdio_assert_info(bus, &sh, data, count);
3155 error = brcmf_sdio_trap_info(bus, &sh, data+nbytes, count);
3160 error = brcmf_sdio_dump_console(bus, &sh, data+nbytes, count);
3171 static ssize_t brcmf_sdio_forensic_read(struct file *f, char __user *data,
3172 size_t count, loff_t *ppos)
3174 struct brcmf_sdio *bus = f->private_data;
3177 res = brcmf_sdio_died_dump(bus, data, count, ppos);
3180 return (ssize_t)res;
3183 static const struct file_operations brcmf_sdio_forensic_ops = {
3184 .owner = THIS_MODULE,
3185 .open = simple_open,
3186 .read = brcmf_sdio_forensic_read
3189 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3191 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3192 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3194 if (IS_ERR_OR_NULL(dentry))
3197 debugfs_create_file("forensics", S_IRUGO, dentry, bus,
3198 &brcmf_sdio_forensic_ops);
3199 brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt);
3200 debugfs_create_u32("console_interval", 0644, dentry,
3201 &bus->console_interval);
3204 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3209 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3215 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3221 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3222 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3223 struct brcmf_sdio *bus = sdiodev->bus;
3225 brcmf_dbg(TRACE, "Enter\n");
3227 /* Wait until control frame is available */
3228 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3230 spin_lock_bh(&bus->rxctl_lock);
3232 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3234 buf = bus->rxctl_orig;
3235 bus->rxctl_orig = NULL;
3237 spin_unlock_bh(&bus->rxctl_lock);
3241 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3243 } else if (timeleft == 0) {
3244 brcmf_err("resumed on timeout\n");
3245 brcmf_sdio_checkdied(bus);
3246 } else if (pending) {
3247 brcmf_dbg(CTL, "cancelled\n");
3248 return -ERESTARTSYS;
3250 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3251 brcmf_sdio_checkdied(bus);
3255 bus->sdcnt.rx_ctlpkts++;
3257 bus->sdcnt.rx_ctlerrs++;
3259 return rxlen ? (int)rxlen : -ETIMEDOUT;
3264 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3265 u8 *ram_data, uint ram_sz)
3274 /* read back and verify */
3275 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3277 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3278 /* do not proceed while no memory but */
3284 while (offset < ram_sz) {
3285 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3287 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3289 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3293 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3294 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3309 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3310 u8 *ram_data, uint ram_sz)
3316 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3317 const struct firmware *fw)
3321 brcmf_dbg(TRACE, "Enter\n");
3323 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3324 (u8 *)fw->data, fw->size);
3326 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3327 err, (int)fw->size, bus->ci->rambase);
3328 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3329 (u8 *)fw->data, fw->size))
3335 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3336 const struct firmware *nv)
3343 brcmf_dbg(TRACE, "Enter\n");
3345 vars = brcmf_nvram_strip(nv, &varsz);
3350 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3351 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3353 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3354 err, varsz, address);
3355 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3358 brcmf_nvram_free(vars);
3363 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus)
3365 int bcmerror = -EFAULT;
3366 const struct firmware *fw;
3369 sdio_claim_host(bus->sdiodev->func[1]);
3370 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3372 /* Keep arm in reset */
3373 brcmf_chip_enter_download(bus->ci);
3375 fw = brcmf_sdio_get_fw(bus, BRCMF_FIRMWARE_BIN);
3381 rstvec = get_unaligned_le32(fw->data);
3382 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3384 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3385 release_firmware(fw);
3387 brcmf_err("dongle image file download failed\n");
3391 fw = brcmf_sdio_get_fw(bus, BRCMF_FIRMWARE_NVRAM);
3397 bcmerror = brcmf_sdio_download_nvram(bus, fw);
3398 release_firmware(fw);
3400 brcmf_err("dongle nvram file download failed\n");
3404 /* Take arm out of reset */
3405 if (!brcmf_chip_exit_download(bus->ci, rstvec)) {
3406 brcmf_err("error getting out of ARM core reset\n");
3410 /* Allow HT Clock now that the ARM is running. */
3411 brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_LOAD);
3415 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3416 sdio_release_host(bus->sdiodev->func[1]);
3420 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3425 brcmf_dbg(TRACE, "Enter\n");
3427 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3429 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3433 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3434 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3436 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3440 /* Add CMD14 Support */
3441 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3442 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3443 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3446 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3450 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3451 SBSDIO_FORCE_HT, &err);
3453 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3458 bus->sr_enabled = true;
3459 brcmf_dbg(INFO, "SR enabled\n");
3462 /* enable KSO bit */
3463 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3468 brcmf_dbg(TRACE, "Enter\n");
3470 /* KSO bit added in SDIO core rev 12 */
3471 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3474 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3476 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3480 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3481 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3482 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3483 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3486 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3495 static int brcmf_sdio_bus_preinit(struct device *dev)
3497 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3498 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3499 struct brcmf_sdio *bus = sdiodev->bus;
3504 /* the commands below use the terms tx and rx from
3505 * a device perspective, ie. bus:txglom affects the
3506 * bus transfers from device to host.
3508 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3509 /* for sdio core rev < 12, disable txgloming */
3511 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3514 /* otherwise, set txglomalign */
3517 value = sdiodev->pdata->sd_sgentry_align;
3518 /* SDIO ADMA requires at least 32 bit alignment */
3519 value = max_t(u32, value, 4);
3520 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3527 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3528 if (sdiodev->sg_support) {
3529 bus->txglom = false;
3531 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3532 bus->txglom_sgpad = brcmu_pkt_buf_get_skb(pad_size);
3533 if (!bus->txglom_sgpad)
3534 brcmf_err("allocating txglom padding skb failed, reduced performance\n");
3536 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3537 &value, sizeof(u32));
3539 /* bus:rxglom is allowed to fail */
3543 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3546 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3552 static int brcmf_sdio_bus_init(struct device *dev)
3554 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3555 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3556 struct brcmf_sdio *bus = sdiodev->bus;
3560 brcmf_dbg(TRACE, "Enter\n");
3562 /* try to download image and nvram to the dongle */
3563 if (bus_if->state == BRCMF_BUS_DOWN) {
3564 bus->alp_only = true;
3565 err = brcmf_sdio_download_firmware(bus);
3568 bus->alp_only = false;
3571 if (!bus->sdiodev->bus_if->drvr)
3574 /* Start the watchdog timer */
3575 bus->sdcnt.tickcnt = 0;
3576 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
3578 sdio_claim_host(bus->sdiodev->func[1]);
3580 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3581 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3582 if (bus->clkstate != CLK_AVAIL)
3585 /* Force clocks on backplane to be sure F2 interrupt propagates */
3586 saveclk = brcmf_sdiod_regrb(bus->sdiodev,
3587 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3589 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3590 (saveclk | SBSDIO_FORCE_HT), &err);
3593 brcmf_err("Failed to force clock for F2: err %d\n", err);
3597 /* Enable function 2 (frame transfers) */
3598 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3599 offsetof(struct sdpcmd_regs, tosbmailboxdata));
3600 err = sdio_enable_func(bus->sdiodev->func[SDIO_FUNC_2]);
3603 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
3605 /* If F2 successfully enabled, set core and enable interrupts */
3607 /* Set up the interrupt mask and enable interrupts */
3608 bus->hostintmask = HOSTINTMASK;
3609 w_sdreg32(bus, bus->hostintmask,
3610 offsetof(struct sdpcmd_regs, hostintmask));
3612 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_WATERMARK, 8, &err);
3614 /* Disable F2 again */
3615 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
3619 if (brcmf_chip_sr_capable(bus->ci)) {
3620 brcmf_sdio_sr_init(bus);
3622 /* Restore previous clock setting */
3623 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3628 ret = brcmf_sdiod_intr_register(bus->sdiodev);
3630 brcmf_err("intr register failed:%d\n", ret);
3633 /* If we didn't come up, turn off backplane clock */
3635 brcmf_sdio_clkctl(bus, CLK_NONE, false);
3638 sdio_release_host(bus->sdiodev->func[1]);
3643 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3645 brcmf_dbg(TRACE, "Enter\n");
3648 brcmf_err("bus is null pointer, exiting\n");
3652 if (!brcmf_bus_ready(bus->sdiodev->bus_if)) {
3653 brcmf_err("bus is down. we have nothing to do\n");
3656 /* Count the interrupt call */
3657 bus->sdcnt.intrcount++;
3659 atomic_set(&bus->ipend, 1);
3661 if (brcmf_sdio_intr_rstatus(bus)) {
3662 brcmf_err("failed backplane access\n");
3665 /* Disable additional interrupts (is this needed now)? */
3667 brcmf_err("isr w/o interrupt configured!\n");
3669 atomic_inc(&bus->dpc_tskcnt);
3670 queue_work(bus->brcmf_wq, &bus->datawork);
3673 static bool brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3676 struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
3679 brcmf_dbg(TIMER, "Enter\n");
3681 /* Poll period: check device if appropriate. */
3682 if (!bus->sr_enabled &&
3683 bus->poll && (++bus->polltick >= bus->pollrate)) {
3686 /* Reset poll tick */
3689 /* Check device if no interrupts */
3691 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3693 if (atomic_read(&bus->dpc_tskcnt) == 0) {
3696 sdio_claim_host(bus->sdiodev->func[1]);
3697 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3700 sdio_release_host(bus->sdiodev->func[1]);
3702 devpend & (INTR_STATUS_FUNC1 |
3706 /* If there is something, make like the ISR and
3709 bus->sdcnt.pollcnt++;
3710 atomic_set(&bus->ipend, 1);
3712 atomic_inc(&bus->dpc_tskcnt);
3713 queue_work(bus->brcmf_wq, &bus->datawork);
3717 /* Update interrupt tracking */
3718 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3721 /* Poll for console output periodically */
3722 if (bus_if && bus_if->state == BRCMF_BUS_DATA &&
3723 bus->console_interval != 0) {
3724 bus->console.count += BRCMF_WD_POLL_MS;
3725 if (bus->console.count >= bus->console_interval) {
3726 bus->console.count -= bus->console_interval;
3727 sdio_claim_host(bus->sdiodev->func[1]);
3728 /* Make sure backplane clock is on */
3729 brcmf_sdio_bus_sleep(bus, false, false);
3730 if (brcmf_sdio_readconsole(bus) < 0)
3732 bus->console_interval = 0;
3733 sdio_release_host(bus->sdiodev->func[1]);
3738 /* On idle timeout clear activity flag and/or turn off clock */
3739 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3740 if (++bus->idlecount >= bus->idletime) {
3742 if (bus->activity) {
3743 bus->activity = false;
3744 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
3746 brcmf_dbg(SDIO, "idle\n");
3747 sdio_claim_host(bus->sdiodev->func[1]);
3748 brcmf_sdio_bus_sleep(bus, true, false);
3749 sdio_release_host(bus->sdiodev->func[1]);
3754 return (atomic_read(&bus->ipend) > 0);
3757 static void brcmf_sdio_dataworker(struct work_struct *work)
3759 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3762 while (atomic_read(&bus->dpc_tskcnt)) {
3763 brcmf_sdio_dpc(bus);
3764 atomic_dec(&bus->dpc_tskcnt);
3769 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3770 struct brcmf_chip *ci, u32 drivestrength)
3772 const struct sdiod_drive_str *str_tab = NULL;
3777 u32 drivestrength_sel = 0;
3781 if (!(ci->cc_caps & CC_CAP_PMU))
3784 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3785 case SDIOD_DRVSTR_KEY(BCM4330_CHIP_ID, 12):
3786 str_tab = sdiod_drvstr_tab1_1v8;
3787 str_mask = 0x00003800;
3790 case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17):
3791 str_tab = sdiod_drvstr_tab6_1v8;
3792 str_mask = 0x00001800;
3795 case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17):
3796 /* note: 43143 does not support tristate */
3797 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3798 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3799 str_tab = sdiod_drvstr_tab2_3v3;
3800 str_mask = 0x00000007;
3803 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3804 ci->name, drivestrength);
3806 case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13):
3807 str_tab = sdiod_drive_strength_tab5_1v8;
3808 str_mask = 0x00003800;
3812 brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
3813 ci->name, ci->chiprev, ci->pmurev);
3817 if (str_tab != NULL) {
3818 for (i = 0; str_tab[i].strength != 0; i++) {
3819 if (drivestrength >= str_tab[i].strength) {
3820 drivestrength_sel = str_tab[i].sel;
3824 base = brcmf_chip_get_chipcommon(ci)->base;
3825 addr = CORE_CC_REG(base, chipcontrol_addr);
3826 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3827 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3828 cc_data_temp &= ~str_mask;
3829 drivestrength_sel <<= str_shift;
3830 cc_data_temp |= drivestrength_sel;
3831 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3833 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3834 str_tab[i].strength, drivestrength, cc_data_temp);
3838 static int brcmf_sdio_buscoreprep(void *ctx)
3840 struct brcmf_sdio_dev *sdiodev = ctx;
3844 /* Try forcing SDIO core to do ALPAvail request only */
3845 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3846 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3848 brcmf_err("error writing for HT off\n");
3852 /* If register supported, wait for ALPAvail and then force ALP */
3853 /* This may take up to 15 milliseconds */
3854 clkval = brcmf_sdiod_regrb(sdiodev,
3855 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3857 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3858 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3863 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3864 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3865 !SBSDIO_ALPAV(clkval)),
3866 PMU_MAX_TRANSITION_DLY);
3867 if (!SBSDIO_ALPAV(clkval)) {
3868 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3873 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3874 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3877 /* Also, disable the extra SDIO pull-ups */
3878 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3883 static void brcmf_sdio_buscore_exitdl(void *ctx, struct brcmf_chip *chip,
3886 struct brcmf_sdio_dev *sdiodev = ctx;
3887 struct brcmf_core *core;
3890 /* clear all interrupts */
3891 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3892 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3893 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3896 /* Write reset vector to address 0 */
3897 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3901 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3903 struct brcmf_sdio_dev *sdiodev = ctx;
3906 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3907 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
3908 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3909 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3911 val &= ~CID_ID_MASK;
3912 val |= BCM4339_CHIP_ID;
3918 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3920 struct brcmf_sdio_dev *sdiodev = ctx;
3922 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3925 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3926 .prepare = brcmf_sdio_buscoreprep,
3927 .exit_dl = brcmf_sdio_buscore_exitdl,
3928 .read32 = brcmf_sdio_buscore_read32,
3929 .write32 = brcmf_sdio_buscore_write32,
3933 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3941 sdio_claim_host(bus->sdiodev->func[1]);
3943 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3944 brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
3947 * Force PLL off until brcmf_chip_attach()
3948 * programs PLL control regs
3951 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3952 BRCMF_INIT_CLKCTL1, &err);
3954 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
3955 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3957 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3958 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3959 err, BRCMF_INIT_CLKCTL1, clkctl);
3963 /* SDIO register access works so moving
3964 * state from UNKNOWN to DOWN.
3966 brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_DOWN);
3968 bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops);
3969 if (IS_ERR(bus->ci)) {
3970 brcmf_err("brcmf_chip_attach failed!\n");
3975 if (brcmf_sdio_kso_init(bus)) {
3976 brcmf_err("error enabling KSO\n");
3980 if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength))
3981 drivestrength = bus->sdiodev->pdata->drive_strength;
3983 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3984 brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength);
3986 /* Get info on the SOCRAM cores... */
3987 bus->ramsize = bus->ci->ramsize;
3988 if (!(bus->ramsize)) {
3989 brcmf_err("failed to find SOCRAM memory!\n");
3993 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3994 reg_val = brcmf_sdiod_regrb(bus->sdiodev,
3995 SDIO_CCCR_BRCM_CARDCTRL, &err);
3999 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
4001 brcmf_sdiod_regwb(bus->sdiodev,
4002 SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
4006 /* set PMUControl so a backplane reset does PMU state reload */
4007 reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base,
4009 reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err);
4013 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
4015 brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err);
4019 sdio_release_host(bus->sdiodev->func[1]);
4021 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4023 /* allocate header buffer */
4024 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
4027 /* Locate an appropriately-aligned portion of hdrbuf */
4028 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4031 /* Set the poll and/or interrupt flags */
4040 sdio_release_host(bus->sdiodev->func[1]);
4045 brcmf_sdio_watchdog_thread(void *data)
4047 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
4049 allow_signal(SIGTERM);
4050 /* Run until signal received */
4052 if (kthread_should_stop())
4054 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
4055 brcmf_sdio_bus_watchdog(bus);
4056 /* Count the tick for reference */
4057 bus->sdcnt.tickcnt++;
4065 brcmf_sdio_watchdog(unsigned long data)
4067 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
4069 if (bus->watchdog_tsk) {
4070 complete(&bus->watchdog_wait);
4071 /* Reschedule the watchdog */
4072 if (bus->wd_timer_valid)
4073 mod_timer(&bus->timer,
4074 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4078 static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
4079 .stop = brcmf_sdio_bus_stop,
4080 .preinit = brcmf_sdio_bus_preinit,
4081 .init = brcmf_sdio_bus_init,
4082 .txdata = brcmf_sdio_bus_txdata,
4083 .txctl = brcmf_sdio_bus_txctl,
4084 .rxctl = brcmf_sdio_bus_rxctl,
4085 .gettxq = brcmf_sdio_bus_gettxq,
4088 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4091 struct brcmf_sdio *bus;
4093 brcmf_dbg(TRACE, "Enter\n");
4095 /* Allocate private bus interface state */
4096 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4100 bus->sdiodev = sdiodev;
4102 skb_queue_head_init(&bus->glom);
4103 bus->txbound = BRCMF_TXBOUND;
4104 bus->rxbound = BRCMF_RXBOUND;
4105 bus->txminmax = BRCMF_TXMINMAX;
4106 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4108 /* platform specific configuration:
4109 * alignments must be at least 4 bytes for ADMA
4111 bus->head_align = ALIGNMENT;
4112 bus->sgentry_align = ALIGNMENT;
4113 if (sdiodev->pdata) {
4114 if (sdiodev->pdata->sd_head_align > ALIGNMENT)
4115 bus->head_align = sdiodev->pdata->sd_head_align;
4116 if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT)
4117 bus->sgentry_align = sdiodev->pdata->sd_sgentry_align;
4120 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4121 bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq");
4122 if (bus->brcmf_wq == NULL) {
4123 brcmf_err("insufficient memory to create txworkqueue\n");
4127 /* attempt to attach to the dongle */
4128 if (!(brcmf_sdio_probe_attach(bus))) {
4129 brcmf_err("brcmf_sdio_probe_attach failed\n");
4133 spin_lock_init(&bus->rxctl_lock);
4134 spin_lock_init(&bus->txqlock);
4135 init_waitqueue_head(&bus->ctrl_wait);
4136 init_waitqueue_head(&bus->dcmd_resp_wait);
4138 /* Set up the watchdog timer */
4139 init_timer(&bus->timer);
4140 bus->timer.data = (unsigned long)bus;
4141 bus->timer.function = brcmf_sdio_watchdog;
4143 /* Initialize watchdog thread */
4144 init_completion(&bus->watchdog_wait);
4145 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4146 bus, "brcmf_watchdog");
4147 if (IS_ERR(bus->watchdog_tsk)) {
4148 pr_warn("brcmf_watchdog thread failed to start\n");
4149 bus->watchdog_tsk = NULL;
4151 /* Initialize DPC thread */
4152 atomic_set(&bus->dpc_tskcnt, 0);
4154 /* Assign bus interface call back */
4155 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4156 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4157 bus->sdiodev->bus_if->chip = bus->ci->chip;
4158 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4160 /* default sdio bus header length for tx packet */
4161 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4163 /* Attach to the common layer, reserve hdr space */
4164 ret = brcmf_attach(bus->sdiodev->dev);
4166 brcmf_err("brcmf_attach failed\n");
4170 /* Allocate buffers */
4171 if (bus->sdiodev->bus_if->maxctl) {
4173 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4174 ALIGNMENT) + bus->head_align;
4175 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4176 if (!(bus->rxbuf)) {
4177 brcmf_err("rxbuf allocation failed\n");
4182 sdio_claim_host(bus->sdiodev->func[1]);
4184 /* Disable F2 to clear any intermediate frame state on the dongle */
4185 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4187 bus->rxflow = false;
4189 /* Done with backplane-dependent accesses, can drop clock... */
4190 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4192 sdio_release_host(bus->sdiodev->func[1]);
4194 /* ...and initialize clock/power states */
4195 bus->clkstate = CLK_SDONLY;
4196 bus->idletime = BRCMF_IDLE_INTERVAL;
4197 bus->idleclock = BRCMF_IDLE_ACTIVE;
4199 /* Query the F2 block size, set roundup accordingly */
4200 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4201 bus->roundup = min(max_roundup, bus->blocksize);
4204 bus->sleeping = false;
4205 bus->sr_enabled = false;
4207 brcmf_sdio_debugfs_create(bus);
4208 brcmf_dbg(INFO, "completed!!\n");
4210 /* if firmware path present try to download and bring up bus */
4211 ret = brcmf_bus_start(bus->sdiodev->dev);
4213 brcmf_err("dongle is not responding\n");
4220 brcmf_sdio_remove(bus);
4224 /* Detach and free everything */
4225 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4227 brcmf_dbg(TRACE, "Enter\n");
4230 /* De-register interrupt handler */
4231 brcmf_sdiod_intr_unregister(bus->sdiodev);
4233 if (bus->sdiodev->bus_if->drvr) {
4234 brcmf_detach(bus->sdiodev->dev);
4237 cancel_work_sync(&bus->datawork);
4239 destroy_workqueue(bus->brcmf_wq);
4242 if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) {
4243 sdio_claim_host(bus->sdiodev->func[1]);
4244 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4245 /* Leave the device in state where it is
4246 * 'quiet'. This is done by putting it in
4247 * download_state which essentially resets
4248 * all necessary cores.
4251 brcmf_chip_enter_download(bus->ci);
4252 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4253 sdio_release_host(bus->sdiodev->func[1]);
4255 brcmf_chip_detach(bus->ci);
4258 brcmu_pkt_buf_free_skb(bus->txglom_sgpad);
4264 brcmf_dbg(TRACE, "Disconnected\n");
4267 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
4269 /* Totally stop the timer */
4270 if (!wdtick && bus->wd_timer_valid) {
4271 del_timer_sync(&bus->timer);
4272 bus->wd_timer_valid = false;
4273 bus->save_ms = wdtick;
4277 /* don't start the wd until fw is loaded */
4278 if (bus->sdiodev->bus_if->state != BRCMF_BUS_DATA)
4282 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4283 if (bus->wd_timer_valid)
4284 /* Stop timer and restart at new value */
4285 del_timer_sync(&bus->timer);
4287 /* Create timer again when watchdog period is
4288 dynamically changed or in the first instance
4290 bus->timer.expires =
4291 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4292 add_timer(&bus->timer);
4295 /* Re arm the timer, at last watchdog period */
4296 mod_timer(&bus->timer,
4297 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4300 bus->wd_timer_valid = true;
4301 bus->save_ms = wdtick;