4 #include <linux/hw_random.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/interrupt.h>
8 #include <linux/stringify.h>
9 #include <linux/netdevice.h>
10 #include <linux/pci.h>
11 #include <asm/atomic.h>
14 #include <linux/ssb/ssb.h>
15 #include <linux/ssb/ssb_driver_chipcommon.h>
17 #include <linux/wireless.h>
18 #include <net/mac80211.h>
26 /* The unique identifier of the firmware that's officially supported by this
28 #define B43legacy_SUPPORTED_FIRMWARE_ID "FW10"
30 #define B43legacy_IRQWAIT_MAX_RETRIES 20
32 #define B43legacy_RX_MAX_SSI 60 /* best guess at max ssi */
35 #define B43legacy_MMIO_DMA0_REASON 0x20
36 #define B43legacy_MMIO_DMA0_IRQ_MASK 0x24
37 #define B43legacy_MMIO_DMA1_REASON 0x28
38 #define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C
39 #define B43legacy_MMIO_DMA2_REASON 0x30
40 #define B43legacy_MMIO_DMA2_IRQ_MASK 0x34
41 #define B43legacy_MMIO_DMA3_REASON 0x38
42 #define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C
43 #define B43legacy_MMIO_DMA4_REASON 0x40
44 #define B43legacy_MMIO_DMA4_IRQ_MASK 0x44
45 #define B43legacy_MMIO_DMA5_REASON 0x48
46 #define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C
47 #define B43legacy_MMIO_MACCTL 0x120 /* MAC control */
48 #define B43legacy_MMIO_MACCMD 0x124 /* MAC command */
49 #define B43legacy_MMIO_GEN_IRQ_REASON 0x128
50 #define B43legacy_MMIO_GEN_IRQ_MASK 0x12C
51 #define B43legacy_MMIO_RAM_CONTROL 0x130
52 #define B43legacy_MMIO_RAM_DATA 0x134
53 #define B43legacy_MMIO_PS_STATUS 0x140
54 #define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158
55 #define B43legacy_MMIO_SHM_CONTROL 0x160
56 #define B43legacy_MMIO_SHM_DATA 0x164
57 #define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166
58 #define B43legacy_MMIO_XMITSTAT_0 0x170
59 #define B43legacy_MMIO_XMITSTAT_1 0x174
60 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
61 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
64 #define B43legacy_MMIO_DMA32_BASE0 0x200
65 #define B43legacy_MMIO_DMA32_BASE1 0x220
66 #define B43legacy_MMIO_DMA32_BASE2 0x240
67 #define B43legacy_MMIO_DMA32_BASE3 0x260
68 #define B43legacy_MMIO_DMA32_BASE4 0x280
69 #define B43legacy_MMIO_DMA32_BASE5 0x2A0
71 #define B43legacy_MMIO_DMA64_BASE0 0x200
72 #define B43legacy_MMIO_DMA64_BASE1 0x240
73 #define B43legacy_MMIO_DMA64_BASE2 0x280
74 #define B43legacy_MMIO_DMA64_BASE3 0x2C0
75 #define B43legacy_MMIO_DMA64_BASE4 0x300
76 #define B43legacy_MMIO_DMA64_BASE5 0x340
78 #define B43legacy_MMIO_PIO1_BASE 0x300
79 #define B43legacy_MMIO_PIO2_BASE 0x310
80 #define B43legacy_MMIO_PIO3_BASE 0x320
81 #define B43legacy_MMIO_PIO4_BASE 0x330
83 #define B43legacy_MMIO_PHY_VER 0x3E0
84 #define B43legacy_MMIO_PHY_RADIO 0x3E2
85 #define B43legacy_MMIO_PHY0 0x3E6
86 #define B43legacy_MMIO_ANTENNA 0x3E8
87 #define B43legacy_MMIO_CHANNEL 0x3F0
88 #define B43legacy_MMIO_CHANNEL_EXT 0x3F4
89 #define B43legacy_MMIO_RADIO_CONTROL 0x3F6
90 #define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8
91 #define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA
92 #define B43legacy_MMIO_PHY_CONTROL 0x3FC
93 #define B43legacy_MMIO_PHY_DATA 0x3FE
94 #define B43legacy_MMIO_MACFILTER_CONTROL 0x420
95 #define B43legacy_MMIO_MACFILTER_DATA 0x422
96 #define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */
97 #define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A
98 #define B43legacy_MMIO_GPIO_CONTROL 0x49C
99 #define B43legacy_MMIO_GPIO_MASK 0x49E
100 #define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */
101 #define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */
102 #define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */
103 #define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */
104 #define B43legacy_MMIO_RNG 0x65A
105 #define B43legacy_MMIO_POWERUP_DELAY 0x6A8
107 /* SPROM boardflags_lo values */
108 #define B43legacy_BFL_PACTRL 0x0002
109 #define B43legacy_BFL_RSSI 0x0008
110 #define B43legacy_BFL_EXTLNA 0x1000
112 /* GPIO register offset, in both ChipCommon and PCI core. */
113 #define B43legacy_GPIO_CONTROL 0x6c
116 #define B43legacy_SHM_SHARED 0x0001
117 #define B43legacy_SHM_WIRELESS 0x0002
118 #define B43legacy_SHM_HW 0x0004
119 #define B43legacy_SHM_UCODE 0x0300
121 /* SHM Routing modifiers */
122 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
123 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
124 #define B43legacy_SHM_AUTOINC_RW (B43legacy_SHM_AUTOINC_R | \
125 B43legacy_SHM_AUTOINC_W)
127 /* Misc SHM_SHARED offsets */
128 #define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
129 #define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */
130 #define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */
131 /* SHM_SHARED crypto engine */
132 #define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */
133 /* SHM_SHARED beacon variables */
134 #define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */
135 /* SHM_SHARED ACK/CTS control */
136 #define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */
137 /* SHM_SHARED probe response variables */
138 #define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */
139 #define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
140 /* SHM_SHARED rate tables */
141 /* SHM_SHARED microcode soft registers */
142 #define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
143 #define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
144 #define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
145 #define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */
147 #define B43legacy_UCODEFLAGS_OFFSET 0x005E
149 /* Hardware Radio Enable masks */
150 #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
151 #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
153 /* HostFlags. See b43legacy_hf_read/write() */
154 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
155 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
156 #define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */
157 #define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */
159 /* MacFilter offsets. */
160 #define B43legacy_MACFILTER_SELF 0x0000
161 #define B43legacy_MACFILTER_BSSID 0x0003
162 #define B43legacy_MACFILTER_MAC 0x0010
165 #define B43legacy_PHYTYPE_B 0x01
166 #define B43legacy_PHYTYPE_G 0x02
169 #define B43legacy_PHY_G_LO_CONTROL 0x0810
170 #define B43legacy_PHY_ILT_G_CTRL 0x0472
171 #define B43legacy_PHY_ILT_G_DATA1 0x0473
172 #define B43legacy_PHY_ILT_G_DATA2 0x0474
173 #define B43legacy_PHY_G_PCTL 0x0029
174 #define B43legacy_PHY_RADIO_BITFIELD 0x0401
175 #define B43legacy_PHY_G_CRS 0x0429
176 #define B43legacy_PHY_NRSSILT_CTRL 0x0803
177 #define B43legacy_PHY_NRSSILT_DATA 0x0804
180 #define B43legacy_RADIOCTL_ID 0x01
182 /* MAC Control bitfield */
183 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
184 #define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
185 #define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
186 #define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
187 #define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
188 #define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */
189 #define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
190 #define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */
191 #define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
192 #define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
193 #define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */
194 #define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
195 #define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
196 #define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
197 #define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
198 #define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */
199 #define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
200 #define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */
202 /* 802.11 core specific TM State Low flags */
203 #define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
204 #define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */
205 #define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */
206 #define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
207 #define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
209 /* 802.11 core specific TM State High flags */
210 #define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */
211 #define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */
213 #define B43legacy_UCODEFLAG_AUTODIV 0x0001
215 /* Generic-Interrupt reasons. */
216 #define B43legacy_IRQ_MAC_SUSPENDED 0x00000001
217 #define B43legacy_IRQ_BEACON 0x00000002
218 #define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */
219 #define B43legacy_IRQ_BEACON_TX_OK 0x00000008
220 #define B43legacy_IRQ_BEACON_CANCEL 0x00000010
221 #define B43legacy_IRQ_ATIM_END 0x00000020
222 #define B43legacy_IRQ_PMQ 0x00000040
223 #define B43legacy_IRQ_PIO_WORKAROUND 0x00000100
224 #define B43legacy_IRQ_MAC_TXERR 0x00000200
225 #define B43legacy_IRQ_PHY_TXERR 0x00000800
226 #define B43legacy_IRQ_PMEVENT 0x00001000
227 #define B43legacy_IRQ_TIMER0 0x00002000
228 #define B43legacy_IRQ_TIMER1 0x00004000
229 #define B43legacy_IRQ_DMA 0x00008000
230 #define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000
231 #define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000
232 #define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000
233 #define B43legacy_IRQ_UCODE_DEBUG 0x08000000
234 #define B43legacy_IRQ_RFKILL 0x10000000
235 #define B43legacy_IRQ_TX_OK 0x20000000
236 #define B43legacy_IRQ_PHY_G_CHANGED 0x40000000
237 #define B43legacy_IRQ_TIMEOUT 0x80000000
239 #define B43legacy_IRQ_ALL 0xFFFFFFFF
240 #define B43legacy_IRQ_MASKTEMPLATE (B43legacy_IRQ_MAC_SUSPENDED | \
241 B43legacy_IRQ_BEACON | \
242 B43legacy_IRQ_TBTT_INDI | \
243 B43legacy_IRQ_ATIM_END | \
244 B43legacy_IRQ_PMQ | \
245 B43legacy_IRQ_MAC_TXERR | \
246 B43legacy_IRQ_PHY_TXERR | \
247 B43legacy_IRQ_DMA | \
248 B43legacy_IRQ_TXFIFO_FLUSH_OK | \
249 B43legacy_IRQ_NOISESAMPLE_OK | \
250 B43legacy_IRQ_UCODE_DEBUG | \
251 B43legacy_IRQ_RFKILL | \
254 /* Device specific rate values.
255 * The actual values defined here are (rate_in_mbps * 2).
256 * Some code depends on this. Don't change it. */
257 #define B43legacy_CCK_RATE_1MB 2
258 #define B43legacy_CCK_RATE_2MB 4
259 #define B43legacy_CCK_RATE_5MB 11
260 #define B43legacy_CCK_RATE_11MB 22
261 #define B43legacy_OFDM_RATE_6MB 12
262 #define B43legacy_OFDM_RATE_9MB 18
263 #define B43legacy_OFDM_RATE_12MB 24
264 #define B43legacy_OFDM_RATE_18MB 36
265 #define B43legacy_OFDM_RATE_24MB 48
266 #define B43legacy_OFDM_RATE_36MB 72
267 #define B43legacy_OFDM_RATE_48MB 96
268 #define B43legacy_OFDM_RATE_54MB 108
269 /* Convert a b43legacy rate value to a rate in 100kbps */
270 #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
273 #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT 7
274 #define B43legacy_DEFAULT_LONG_RETRY_LIMIT 4
276 #define B43legacy_PHY_TX_BADNESS_LIMIT 1000
278 /* Max size of a security key */
279 #define B43legacy_SEC_KEYSIZE 16
280 /* Security algorithms. */
282 B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
283 B43legacy_SEC_ALGO_WEP40,
284 B43legacy_SEC_ALGO_TKIP,
285 B43legacy_SEC_ALGO_AES,
286 B43legacy_SEC_ALGO_WEP104,
287 B43legacy_SEC_ALGO_AES_LEGACY,
290 /* Core Information Registers */
291 #define B43legacy_CIR_BASE 0xf00
292 #define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18)
293 #define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90)
294 #define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94)
295 #define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98)
296 #define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c)
297 #define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8)
298 #define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc)
300 /* sbtmstatehigh state flags */
301 #define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001
302 #define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004
303 #define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020
304 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000
305 #define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
306 #define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000
307 #define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000
308 #define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000
309 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
311 /* sbimstate flags */
312 #define B43legacy_SBIMSTATE_IB_ERROR 0x20000
313 #define B43legacy_SBIMSTATE_TIMEOUT 0x40000
315 #define PFX KBUILD_MODNAME ": "
319 #ifdef CONFIG_B43LEGACY_DEBUG
320 # define B43legacy_WARN_ON(expr) \
322 if (unlikely((expr))) { \
323 printk(KERN_INFO PFX "Test (%s) failed at:" \
326 __LINE__, __FUNCTION__); \
329 # define B43legacy_BUG_ON(expr) \
331 if (unlikely((expr))) { \
332 printk(KERN_INFO PFX "Test (%s) failed\n", \
337 # define B43legacy_DEBUG 1
339 # define B43legacy_WARN_ON(x) do { /* nothing */ } while (0)
340 # define B43legacy_BUG_ON(x) do { /* nothing */ } while (0)
341 # define B43legacy_DEBUG 0
347 struct b43legacy_dmaring;
348 struct b43legacy_pioqueue;
350 /* The firmware file header */
351 #define B43legacy_FW_TYPE_UCODE 'u'
352 #define B43legacy_FW_TYPE_PCM 'p'
353 #define B43legacy_FW_TYPE_IV 'i'
354 struct b43legacy_fw_header {
357 /* File format version */
360 /* Size of the data. For ucode and PCM this is in bytes.
361 * For IV this is number-of-ivs. */
363 } __attribute__((__packed__));
365 /* Initial Value file format */
366 #define B43legacy_IV_OFFSET_MASK 0x7FFF
367 #define B43legacy_IV_32BIT 0x8000
368 struct b43legacy_iv {
373 } data __attribute__((__packed__));
374 } __attribute__((__packed__));
376 #define B43legacy_PHYMODE(phytype) (1 << (phytype))
377 #define B43legacy_PHYMODE_B B43legacy_PHYMODE \
378 ((B43legacy_PHYTYPE_B))
379 #define B43legacy_PHYMODE_G B43legacy_PHYMODE \
380 ((B43legacy_PHYTYPE_G))
382 /* Value pair to measure the LocalOscillator. */
383 struct b43legacy_lopair {
388 #define B43legacy_LO_COUNT (14*4)
390 struct b43legacy_phy {
391 /* Possible PHYMODEs on this PHY */
392 u8 possible_phymodes;
393 /* GMODE bit enabled in MACCTL? */
398 /* B43legacy_PHYTYPE_ */
400 /* PHY revision number. */
403 u16 antenna_diversity;
405 /* Radio versioning */
406 u16 radio_manuf; /* Radio manufacturer */
407 u16 radio_ver; /* Radio version */
409 u8 radio_rev; /* Radio revision */
411 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
413 /* ACI (adjacent channel interference) flags. */
415 bool aci_wlan_automatic;
418 /* Radio switched on/off */
421 /* Values saved when turning the radio off.
422 * They are needed when turning it on again. */
431 /* LO Measurement Data.
432 * Use b43legacy_get_lopair() to get a value.
434 struct b43legacy_lopair *_lo_pairs;
435 /* TSSI to dBm table in use */
437 /* idle TSSI value */
439 /* Target idle TSSI */
441 /* Current idle TSSI */
444 /* LocalOscillator control values. */
445 struct b43legacy_txpower_lo_control *lo_control;
446 /* Values from b43legacy_calc_loopback_gain() */
447 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
448 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
449 s16 lna_lod_gain; /* LNA lod */
450 s16 lna_gain; /* LNA */
451 s16 pga_gain; /* PGA */
453 /* Desired TX power level (in dBm). This is set by the user and
454 * adjusted in b43legacy_phy_xmitpower(). */
457 /* Values from b43legacy_calc_loopback_gain() */
458 u16 loopback_gain[2];
460 /* TX Power control values. */
463 /* Current Radio Attenuation for TXpower recalculation. */
465 /* Current Baseband Attenuation for TXpower recalculation. */
467 /* Current TXpower control value for TXpower recalculation. */
476 /* Current Interference Mitigation mode */
478 /* Stack of saved values from the Interference Mitigation code.
479 * Each value in the stack is layed out as follows:
481 * bit 12-15: register ID
483 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
485 #define B43legacy_INTERFSTACK_SIZE 26
486 u32 interfstack[B43legacy_INTERFSTACK_SIZE];
488 /* Saved values from the NRSSI Slope calculation */
491 /* In memory nrssi lookup table. */
494 /* current channel */
501 /* PHY TX errors counter. */
505 /* Manual TX-power control enabled? */
506 bool manual_txpower_control;
507 /* PHY registers locked by b43legacy_phy_lock()? */
509 #endif /* B43legacy_DEBUG */
512 /* Data structures for DMA transmission, per 80211 core. */
513 struct b43legacy_dma {
514 struct b43legacy_dmaring *tx_ring0;
515 struct b43legacy_dmaring *tx_ring1;
516 struct b43legacy_dmaring *tx_ring2;
517 struct b43legacy_dmaring *tx_ring3;
518 struct b43legacy_dmaring *tx_ring4;
519 struct b43legacy_dmaring *tx_ring5;
521 struct b43legacy_dmaring *rx_ring0;
522 struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
525 /* Data structures for PIO transmission, per 80211 core. */
526 struct b43legacy_pio {
527 struct b43legacy_pioqueue *queue0;
528 struct b43legacy_pioqueue *queue1;
529 struct b43legacy_pioqueue *queue2;
530 struct b43legacy_pioqueue *queue3;
533 /* Context information for a noise calculation (Link Quality). */
534 struct b43legacy_noise_calculation {
536 bool calculation_running;
541 struct b43legacy_stats {
543 /* Store the last TX/RX times here for updating the leds. */
544 unsigned long last_tx;
545 unsigned long last_rx;
548 struct b43legacy_key {
554 struct b43legacy_wldev;
556 /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
557 struct b43legacy_wl {
558 /* Pointer to the active wireless device on this chip */
559 struct b43legacy_wldev *current_dev;
560 /* Pointer to the ieee80211 hardware data structure */
561 struct ieee80211_hw *hw;
563 spinlock_t irq_lock; /* locks IRQ */
564 struct mutex mutex; /* locks wireless core state */
565 spinlock_t leds_lock; /* lock for leds */
567 /* We can only have one operating interface (802.11 core)
568 * at a time. General information about this interface follows.
571 struct ieee80211_vif *vif;
572 /* MAC address (can be NULL). */
573 u8 mac_addr[ETH_ALEN];
574 /* Current BSSID (can be NULL). */
576 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
578 /* Is the card operating in AP, STA or IBSS mode? */
581 unsigned int filter_flags;
582 /* Stats about the wireless interface */
583 struct ieee80211_low_level_stats ieee_stats;
587 char rng_name[30 + 1];
589 /* The RF-kill button */
590 struct b43legacy_rfkill rfkill;
592 /* List of all wireless devices on this chip */
593 struct list_head devlist;
596 bool radiotap_enabled;
599 /* Pointers to the firmware data and meta information about it. */
600 struct b43legacy_firmware {
602 const struct firmware *ucode;
604 const struct firmware *pcm;
605 /* Initial MMIO values for the firmware */
606 const struct firmware *initvals;
607 /* Initial MMIO values for the firmware, band-specific */
608 const struct firmware *initvals_band;
609 /* Firmware revision */
611 /* Firmware patchlevel */
615 /* Device (802.11 core) initialization status. */
617 B43legacy_STAT_UNINIT = 0, /* Uninitialized. */
618 B43legacy_STAT_INITIALIZED = 1, /* Initialized, not yet started. */
619 B43legacy_STAT_STARTED = 2, /* Up and running. */
621 #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
622 #define b43legacy_set_status(wldev, stat) do { \
623 atomic_set(&(wldev)->__init_status, (stat)); \
627 /* *** --- HOW LOCKING WORKS IN B43legacy --- ***
629 * You should always acquire both, wl->mutex and wl->irq_lock unless:
630 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
631 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
632 * and packet TX path (and _ONLY_ there.)
635 /* Data structure for one wireless device (802.11 core) */
636 struct b43legacy_wldev {
637 struct ssb_device *dev;
638 struct b43legacy_wl *wl;
640 /* The device initialization status.
641 * Use b43legacy_status() to query. */
642 atomic_t __init_status;
643 /* Saved init status for handling suspend. */
644 int suspend_init_status;
646 bool __using_pio; /* Using pio rather than dma. */
647 bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
648 bool reg124_set_0x4; /* Variable to keep track of IRQ. */
649 bool short_preamble; /* TRUE if using short preamble. */
650 bool short_slot; /* TRUE if using short slot timing. */
651 bool radio_hw_enable; /* State of radio hardware enable bit. */
653 /* PHY/Radio device. */
654 struct b43legacy_phy phy;
657 struct b43legacy_dma dma;
659 struct b43legacy_pio pio;
662 /* Various statistics about the physical device. */
663 struct b43legacy_stats stats;
665 /* The device LEDs. */
666 struct b43legacy_led led_tx;
667 struct b43legacy_led led_rx;
668 struct b43legacy_led led_assoc;
669 struct b43legacy_led led_radio;
671 /* Reason code of the last interrupt. */
674 /* saved irq enable/disable state bitfield. */
676 /* Link Quality calculation context. */
677 struct b43legacy_noise_calculation noisecalc;
678 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
681 /* Interrupt Service Routine tasklet (bottom-half) */
682 struct tasklet_struct isr_tasklet;
685 struct delayed_work periodic_work;
686 unsigned int periodic_state;
688 struct work_struct restart_work;
690 /* encryption/decryption */
691 u16 ktp; /* Key table pointer */
693 struct b43legacy_key key[58];
695 /* Cached beacon template while uploading the template. */
696 struct sk_buff *cached_beacon;
699 struct b43legacy_firmware fw;
701 /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
702 struct list_head list;
704 /* Debugging stuff follows. */
705 #ifdef CONFIG_B43LEGACY_DEBUG
706 struct b43legacy_dfsentry *dfsentry;
712 struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
717 /* Helper function, which returns a boolean.
718 * TRUE, if PIO is used; FALSE, if DMA is used.
720 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
722 int b43legacy_using_pio(struct b43legacy_wldev *dev)
724 return dev->__using_pio;
726 #elif defined(CONFIG_B43LEGACY_DMA)
728 int b43legacy_using_pio(struct b43legacy_wldev *dev)
732 #elif defined(CONFIG_B43LEGACY_PIO)
734 int b43legacy_using_pio(struct b43legacy_wldev *dev)
739 # error "Using neither DMA nor PIO? Confused..."
744 struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
746 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
747 return ssb_get_drvdata(ssb_dev);
750 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
752 int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
754 return (wl->operating &&
755 wl->if_type == type);
759 bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
761 return (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
765 u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
767 return ssb_read16(dev->dev, offset);
771 void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
773 ssb_write16(dev->dev, offset, value);
777 u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
779 return ssb_read32(dev->dev, offset);
783 void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
785 ssb_write32(dev->dev, offset, value);
789 struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
790 u16 radio_attenuation,
791 u16 baseband_attenuation)
793 return phy->_lo_pairs + (radio_attenuation
794 + 14 * (baseband_attenuation / 2));
799 /* Message printing */
800 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
801 __attribute__((format(printf, 2, 3)));
802 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
803 __attribute__((format(printf, 2, 3)));
804 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
805 __attribute__((format(printf, 2, 3)));
807 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
808 __attribute__((format(printf, 2, 3)));
810 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
814 /** Limit a value between two limits */
818 #define limit_value(value, min, max) \
820 typeof(value) __value = (value); \
821 typeof(value) __min = (min); \
822 typeof(value) __max = (max); \
823 if (__value < __min) \
825 else if (__value > __max) \
830 /* Macros for printing a value in Q5.2 format */
831 #define Q52_FMT "%u.%u"
832 #define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4)
834 #endif /* B43legacy_H_ */