3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
32 #include "tables_nphy.h"
33 #include "radio_2055.h"
34 #include "radio_2056.h"
35 #include "radio_2057.h"
45 struct nphy_iqcal_params {
63 enum b43_nphy_rf_sequence {
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
72 enum n_intc_override {
73 N_INTC_OVERRIDE_OFF = 0,
74 N_INTC_OVERRIDE_TRSW = 1,
75 N_INTC_OVERRIDE_PA = 2,
76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
95 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
97 enum ieee80211_band band = b43_current_band(dev->wl);
98 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
99 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
102 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
103 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
105 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
106 B43_NPHY_RFSEQCA_RXEN_SHIFT;
109 /**************************************************
110 * RF (just without b43_nphy_rf_ctl_intc_override)
111 **************************************************/
113 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
114 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
115 enum b43_nphy_rf_sequence seq)
117 static const u16 trigger[] = {
118 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
119 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
120 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
121 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
122 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
123 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
126 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
128 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
130 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
131 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
132 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
133 for (i = 0; i < 200; i++) {
134 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
138 b43err(dev->wl, "RF sequence status timeout\n");
140 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
143 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
144 static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
145 u16 value, u8 core, bool off,
148 const struct nphy_rf_control_override_rev7 *e;
149 u16 en_addrs[3][2] = {
150 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
157 /* Remember: we can get NULL! */
158 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
160 for (i = 0; i < 2; i++) {
161 if (override >= ARRAY_SIZE(en_addrs)) {
162 b43err(dev->wl, "Invalid override value %d\n", override);
165 en_addr = en_addrs[override][i];
168 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
171 b43_phy_mask(dev, en_addr, ~en_mask);
172 if (e) /* Do it safer, better than wl */
173 b43_phy_mask(dev, val_addr, ~e->val_mask);
175 if (!core || (core & (1 << i))) {
176 b43_phy_set(dev, en_addr, en_mask);
178 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
184 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
185 static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
186 u16 value, u8 core, bool off)
189 u8 index = fls(field);
190 u8 addr, en_addr, val_addr;
191 /* we expect only one bit set */
192 B43_WARN_ON(field & (~(1 << (index - 1))));
194 if (dev->phy.rev >= 3) {
195 const struct nphy_rf_control_override_rev3 *rf_ctrl;
196 for (i = 0; i < 2; i++) {
197 if (index == 0 || index == 16) {
199 "Unsupported RF Ctrl Override call\n");
203 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
204 en_addr = B43_PHY_N((i == 0) ?
205 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
206 val_addr = B43_PHY_N((i == 0) ?
207 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
210 b43_phy_mask(dev, en_addr, ~(field));
211 b43_phy_mask(dev, val_addr,
212 ~(rf_ctrl->val_mask));
214 if (core == 0 || ((1 << i) & core)) {
215 b43_phy_set(dev, en_addr, field);
216 b43_phy_maskset(dev, val_addr,
217 ~(rf_ctrl->val_mask),
218 (value << rf_ctrl->val_shift));
223 const struct nphy_rf_control_override_rev2 *rf_ctrl;
225 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
228 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
231 for (i = 0; i < 2; i++) {
232 if (index <= 1 || index == 16) {
234 "Unsupported RF Ctrl Override call\n");
238 if (index == 2 || index == 10 ||
239 (index >= 13 && index <= 15)) {
243 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
244 addr = B43_PHY_N((i == 0) ?
245 rf_ctrl->addr0 : rf_ctrl->addr1);
248 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
249 (value << rf_ctrl->shift));
251 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
252 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
253 B43_NPHY_RFCTL_CMD_START);
255 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
260 static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
261 enum n_intc_override intc_override,
262 u16 value, u8 core_sel)
264 u16 reg, tmp, tmp2, val;
267 for (core = 0; core < 2; core++) {
268 if ((core_sel == 1 && core != 0) ||
269 (core_sel == 2 && core != 1))
272 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
274 switch (intc_override) {
275 case N_INTC_OVERRIDE_OFF:
276 b43_phy_write(dev, reg, 0);
277 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
279 case N_INTC_OVERRIDE_TRSW:
280 b43_phy_maskset(dev, reg, ~0xC0, value << 6);
281 b43_phy_set(dev, reg, 0x400);
283 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
284 b43_phy_set(dev, 0x2ff, 0x2000);
285 b43_phy_set(dev, 0x2ff, 0x0001);
287 case N_INTC_OVERRIDE_PA:
289 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
293 b43_phy_maskset(dev, reg, ~tmp, val);
294 b43_phy_set(dev, reg, 0x1000);
296 case N_INTC_OVERRIDE_EXT_LNA_PU:
297 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
306 b43_phy_maskset(dev, reg, ~tmp, val);
307 b43_phy_mask(dev, reg, ~tmp2);
309 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
310 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
319 b43_phy_maskset(dev, reg, ~tmp, val);
320 b43_phy_mask(dev, reg, ~tmp2);
326 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
327 static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
328 enum n_intc_override intc_override,
334 if (dev->phy.rev >= 7) {
335 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
340 B43_WARN_ON(dev->phy.rev < 3);
342 for (i = 0; i < 2; i++) {
343 if ((core == 1 && i == 1) || (core == 2 && !i))
347 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
348 b43_phy_set(dev, reg, 0x400);
350 switch (intc_override) {
351 case N_INTC_OVERRIDE_OFF:
352 b43_phy_write(dev, reg, 0);
353 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
355 case N_INTC_OVERRIDE_TRSW:
357 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
358 0xFC3F, (value << 6));
359 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
361 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
362 B43_NPHY_RFCTL_CMD_START);
363 for (j = 0; j < 100; j++) {
364 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
372 "intc override timeout\n");
373 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
376 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
377 0xFC3F, (value << 6));
378 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
380 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
381 B43_NPHY_RFCTL_CMD_RXTX);
382 for (j = 0; j < 100; j++) {
383 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
391 "intc override timeout\n");
392 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
396 case N_INTC_OVERRIDE_PA:
397 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
404 b43_phy_maskset(dev, reg, ~tmp, val);
406 case N_INTC_OVERRIDE_EXT_LNA_PU:
407 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
414 b43_phy_maskset(dev, reg, ~tmp, val);
416 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
417 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
424 b43_phy_maskset(dev, reg, ~tmp, val);
430 /**************************************************
432 **************************************************/
434 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
435 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
438 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
439 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
442 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
443 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
445 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
446 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
449 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
450 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
454 if (dev->dev->core_rev == 16)
455 b43_mac_suspend(dev);
457 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
458 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
459 B43_NPHY_CLASSCTL_WAITEDEN);
462 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
464 if (dev->dev->core_rev == 16)
470 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
471 static void b43_nphy_reset_cca(struct b43_wldev *dev)
475 b43_phy_force_clock(dev, 1);
476 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
477 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
479 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
480 b43_phy_force_clock(dev, 0);
481 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
484 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
485 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
487 struct b43_phy *phy = &dev->phy;
488 struct b43_phy_n *nphy = phy->n;
491 static const u16 clip[] = { 0xFFFF, 0xFFFF };
492 if (nphy->deaf_count++ == 0) {
493 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
494 b43_nphy_classifier(dev, 0x7,
495 B43_NPHY_CLASSCTL_WAITEDEN);
496 b43_nphy_read_clip_detection(dev, nphy->clip_state);
497 b43_nphy_write_clip_detection(dev, clip);
499 b43_nphy_reset_cca(dev);
501 if (--nphy->deaf_count == 0) {
502 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
503 b43_nphy_write_clip_detection(dev, nphy->clip_state);
508 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
509 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
511 struct b43_phy_n *nphy = dev->phy.n;
518 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
520 if (nphy->hang_avoid)
521 b43_nphy_stay_in_carrier_search(dev, 1);
523 if (nphy->gain_boost) {
524 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
528 tmp = 40370 - 315 * dev->phy.channel;
529 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
530 tmp = 23242 - 224 * dev->phy.channel;
531 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
538 for (i = 0; i < 2; i++) {
539 if (nphy->elna_gain_config) {
540 data[0] = 19 + gain[i];
541 data[1] = 25 + gain[i];
542 data[2] = 25 + gain[i];
543 data[3] = 25 + gain[i];
545 data[0] = lna_gain[0] + gain[i];
546 data[1] = lna_gain[1] + gain[i];
547 data[2] = lna_gain[2] + gain[i];
548 data[3] = lna_gain[3] + gain[i];
550 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
552 minmax[i] = 23 + gain[i];
555 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
556 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
557 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
558 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
560 if (nphy->hang_avoid)
561 b43_nphy_stay_in_carrier_search(dev, 0);
564 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
565 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
566 u8 *events, u8 *delays, u8 length)
568 struct b43_phy_n *nphy = dev->phy.n;
570 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
571 u16 offset1 = cmd << 4;
572 u16 offset2 = offset1 + 0x80;
574 if (nphy->hang_avoid)
575 b43_nphy_stay_in_carrier_search(dev, true);
577 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
578 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
580 for (i = length; i < 16; i++) {
581 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
582 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
585 if (nphy->hang_avoid)
586 b43_nphy_stay_in_carrier_search(dev, false);
589 /**************************************************
591 **************************************************/
593 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
594 static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
596 struct b43_phy *phy = &dev->phy;
599 if (phy->radio_rev == 5) {
600 b43_phy_mask(dev, 0x342, ~0x2);
602 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
603 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
606 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
608 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
609 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
610 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
613 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
614 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
615 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
617 if (phy->radio_rev == 5) {
618 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
619 b43_radio_mask(dev, 0x1ca, ~0x2);
621 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
622 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
623 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
630 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
631 static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
633 struct b43_phy *phy = &dev->phy;
634 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
635 phy->radio_rev == 6);
639 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
640 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
642 b43_radio_write(dev, 0x1AE, 0x61);
643 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
645 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
646 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
647 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
649 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
650 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
652 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
653 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
655 b43_radio_write(dev, 0x1AE, 0x69);
656 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
658 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
659 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
660 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
662 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
663 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
665 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
666 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
667 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
669 b43_radio_write(dev, 0x1AE, 0x73);
670 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
671 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
673 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
674 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
676 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
679 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
680 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
684 static void b43_radio_2057_init_pre(struct b43_wldev *dev)
686 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
687 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
688 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
689 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
690 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
693 static void b43_radio_2057_init_post(struct b43_wldev *dev)
695 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
697 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
698 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
700 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
701 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
703 if (dev->phy.do_full_init) {
704 b43_radio_2057_rcal(dev);
705 b43_radio_2057_rccal(dev);
707 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
710 /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
711 static void b43_radio_2057_init(struct b43_wldev *dev)
713 b43_radio_2057_init_pre(dev);
714 r2057_upload_inittabs(dev);
715 b43_radio_2057_init_post(dev);
718 /**************************************************
720 **************************************************/
722 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
723 const struct b43_nphy_channeltab_entry_rev3 *e)
725 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
726 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
727 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
728 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
729 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
730 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
731 e->radio_syn_pll_loopfilter1);
732 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
733 e->radio_syn_pll_loopfilter2);
734 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
735 e->radio_syn_pll_loopfilter3);
736 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
737 e->radio_syn_pll_loopfilter4);
738 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
739 e->radio_syn_pll_loopfilter5);
740 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
741 e->radio_syn_reserved_addr27);
742 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
743 e->radio_syn_reserved_addr28);
744 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
745 e->radio_syn_reserved_addr29);
746 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
747 e->radio_syn_logen_vcobuf1);
748 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
749 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
750 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
752 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
753 e->radio_rx0_lnaa_tune);
754 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
755 e->radio_rx0_lnag_tune);
757 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
758 e->radio_tx0_intpaa_boost_tune);
759 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
760 e->radio_tx0_intpag_boost_tune);
761 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
762 e->radio_tx0_pada_boost_tune);
763 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
764 e->radio_tx0_padg_boost_tune);
765 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
766 e->radio_tx0_pgaa_boost_tune);
767 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
768 e->radio_tx0_pgag_boost_tune);
769 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
770 e->radio_tx0_mixa_boost_tune);
771 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
772 e->radio_tx0_mixg_boost_tune);
774 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
775 e->radio_rx1_lnaa_tune);
776 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
777 e->radio_rx1_lnag_tune);
779 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
780 e->radio_tx1_intpaa_boost_tune);
781 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
782 e->radio_tx1_intpag_boost_tune);
783 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
784 e->radio_tx1_pada_boost_tune);
785 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
786 e->radio_tx1_padg_boost_tune);
787 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
788 e->radio_tx1_pgaa_boost_tune);
789 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
790 e->radio_tx1_pgag_boost_tune);
791 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
792 e->radio_tx1_mixa_boost_tune);
793 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
794 e->radio_tx1_mixg_boost_tune);
797 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
798 static void b43_radio_2056_setup(struct b43_wldev *dev,
799 const struct b43_nphy_channeltab_entry_rev3 *e)
801 struct ssb_sprom *sprom = dev->dev->bus_sprom;
802 enum ieee80211_band band = b43_current_band(dev->wl);
806 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
807 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
808 bool is_pkg_fab_smic;
810 B43_WARN_ON(dev->phy.rev < 3);
813 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
814 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
815 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
816 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
818 b43_chantab_radio_2056_upload(dev, e);
819 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
821 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
822 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
823 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
824 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
825 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
826 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
827 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
828 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
830 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
831 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
834 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
835 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
836 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
837 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
838 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
839 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
841 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
842 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
843 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
844 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
845 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
846 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
849 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
850 for (i = 0; i < 2; i++) {
851 offset = i ? B2056_TX1 : B2056_TX0;
852 if (dev->phy.rev >= 5) {
854 offset | B2056_TX_PADG_IDAC, 0xcc);
856 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
857 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
866 if (is_pkg_fab_smic) {
877 offset | B2056_TX_INTPAG_IMAIN_STAT,
880 offset | B2056_TX_INTPAG_IAUX_STAT,
883 offset | B2056_TX_INTPAG_CASCBIAS,
886 offset | B2056_TX_INTPAG_BOOST_TUNE,
889 offset | B2056_TX_PGAG_BOOST_TUNE,
892 offset | B2056_TX_PADG_BOOST_TUNE,
895 offset | B2056_TX_MIXG_BOOST_TUNE,
898 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
900 offset | B2056_TX_INTPAG_IMAIN_STAT,
903 offset | B2056_TX_INTPAG_IAUX_STAT,
906 offset | B2056_TX_INTPAG_CASCBIAS,
909 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
911 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
912 u16 freq = dev->phy.channel_freq;
918 } else if (freq < 5340) {
923 } else if (freq < 5650) {
932 pgaa_boost = -(freq - 18) / 36 + 168;
938 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
940 for (i = 0; i < 2; i++) {
941 offset = i ? B2056_TX1 : B2056_TX0;
944 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
946 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
948 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
950 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
952 offset | B2056_TX_TXSPARE1, 0x30);
954 offset | B2056_TX_PA_SPARE2, 0xee);
956 offset | B2056_TX_PADA_CASCBIAS, 0x03);
958 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
960 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
962 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
967 /* VCO calibration */
968 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
969 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
970 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
971 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
972 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
976 static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
978 struct b43_phy *phy = &dev->phy;
984 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
985 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
988 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
990 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
992 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
994 b43err(dev->wl, "Radio recalibration timeout\n");
998 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
999 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1000 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1002 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1007 static void b43_radio_init2056_pre(struct b43_wldev *dev)
1009 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1010 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1011 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1012 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1013 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1014 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1015 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1016 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1017 B43_NPHY_RFCTL_CMD_CHIP0PU);
1020 static void b43_radio_init2056_post(struct b43_wldev *dev)
1022 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1023 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1024 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1026 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1027 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1028 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
1029 if (dev->phy.do_full_init)
1030 b43_radio_2056_rcal(dev);
1034 * Initialize a Broadcom 2056 N-radio
1035 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1037 static void b43_radio_init2056(struct b43_wldev *dev)
1039 b43_radio_init2056_pre(dev);
1040 b2056_upload_inittabs(dev, 0, 0);
1041 b43_radio_init2056_post(dev);
1044 /**************************************************
1046 **************************************************/
1048 static void b43_chantab_radio_upload(struct b43_wldev *dev,
1049 const struct b43_nphy_channeltab_entry_rev2 *e)
1051 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1052 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1053 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1054 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1055 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1057 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1058 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1059 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1060 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1061 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1063 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1064 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1065 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1066 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1067 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1069 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1070 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1071 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1072 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1073 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1075 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1076 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1077 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1078 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1079 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1081 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1082 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
1085 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1086 static void b43_radio_2055_setup(struct b43_wldev *dev,
1087 const struct b43_nphy_channeltab_entry_rev2 *e)
1089 B43_WARN_ON(dev->phy.rev >= 3);
1091 b43_chantab_radio_upload(dev, e);
1093 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1094 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1095 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1096 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1100 static void b43_radio_init2055_pre(struct b43_wldev *dev)
1102 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1103 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1104 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1105 B43_NPHY_RFCTL_CMD_CHIP0PU |
1106 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1107 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1108 B43_NPHY_RFCTL_CMD_PORFORCE);
1111 static void b43_radio_init2055_post(struct b43_wldev *dev)
1113 struct b43_phy_n *nphy = dev->phy.n;
1114 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1115 bool workaround = false;
1117 if (sprom->revision < 4)
1118 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1119 && dev->dev->board_type == SSB_BOARD_CB2_4321
1120 && dev->dev->board_rev >= 0x41);
1123 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1125 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1127 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1128 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1130 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1131 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1132 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1133 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1134 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1136 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1137 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1138 b43err(dev->wl, "radio post init timeout\n");
1139 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1140 b43_switch_channel(dev, dev->phy.channel);
1141 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1142 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1143 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1144 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1145 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1146 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1147 if (!nphy->gain_boost) {
1148 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1149 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1151 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1152 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1158 * Initialize a Broadcom 2055 N-radio
1159 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1161 static void b43_radio_init2055(struct b43_wldev *dev)
1163 b43_radio_init2055_pre(dev);
1164 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1165 /* Follow wl, not specs. Do not force uploading all regs */
1166 b2055_upload_inittab(dev, 0, 0);
1168 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1169 b2055_upload_inittab(dev, ghz5, 0);
1171 b43_radio_init2055_post(dev);
1174 /**************************************************
1176 **************************************************/
1178 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1179 static int b43_nphy_load_samples(struct b43_wldev *dev,
1180 struct b43_c32 *samples, u16 len) {
1181 struct b43_phy_n *nphy = dev->phy.n;
1185 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1187 b43err(dev->wl, "allocation for samples loading failed\n");
1190 if (nphy->hang_avoid)
1191 b43_nphy_stay_in_carrier_search(dev, 1);
1193 for (i = 0; i < len; i++) {
1194 data[i] = (samples[i].i & 0x3FF << 10);
1195 data[i] |= samples[i].q & 0x3FF;
1197 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1200 if (nphy->hang_avoid)
1201 b43_nphy_stay_in_carrier_search(dev, 0);
1205 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1206 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1210 u16 bw, len, rot, angle;
1211 struct b43_c32 *samples;
1214 bw = (dev->phy.is_40mhz) ? 40 : 20;
1218 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1223 if (dev->phy.is_40mhz)
1229 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1231 b43err(dev->wl, "allocation for samples generation failed\n");
1234 rot = (((freq * 36) / bw) << 16) / 100;
1237 for (i = 0; i < len; i++) {
1238 samples[i] = b43_cordic(angle);
1240 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1241 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1244 i = b43_nphy_load_samples(dev, samples, len);
1246 return (i < 0) ? 0 : len;
1249 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1250 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1251 u16 wait, bool iqmode, bool dac_test)
1253 struct b43_phy_n *nphy = dev->phy.n;
1258 b43_nphy_stay_in_carrier_search(dev, true);
1260 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1261 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1262 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1265 /* TODO: add modify_bbmult argument */
1266 if (!dev->phy.is_40mhz)
1270 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1272 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1274 if (loops != 0xFFFF)
1275 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1277 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1279 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1281 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1283 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1285 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1286 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1289 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1291 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1293 for (i = 0; i < 100; i++) {
1294 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1301 b43err(dev->wl, "run samples timeout\n");
1303 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1305 b43_nphy_stay_in_carrier_search(dev, false);
1308 /**************************************************
1310 **************************************************/
1312 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1313 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1315 enum n_rail_type rail,
1316 enum n_rssi_type rssi_type)
1319 bool core1or5 = (core == 1) || (core == 5);
1320 bool core2or5 = (core == 2) || (core == 5);
1322 offset = clamp_val(offset, -32, 31);
1323 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1325 switch (rssi_type) {
1327 if (core1or5 && rail == N_RAIL_I)
1328 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1329 if (core1or5 && rail == N_RAIL_Q)
1330 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1331 if (core2or5 && rail == N_RAIL_I)
1332 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1333 if (core2or5 && rail == N_RAIL_Q)
1334 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1337 if (core1or5 && rail == N_RAIL_I)
1338 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1339 if (core1or5 && rail == N_RAIL_Q)
1340 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1341 if (core2or5 && rail == N_RAIL_I)
1342 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1343 if (core2or5 && rail == N_RAIL_Q)
1344 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1347 if (core1or5 && rail == N_RAIL_I)
1348 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1349 if (core1or5 && rail == N_RAIL_Q)
1350 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1351 if (core2or5 && rail == N_RAIL_I)
1352 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1353 if (core2or5 && rail == N_RAIL_Q)
1354 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1357 if (core1or5 && rail == N_RAIL_I)
1358 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1359 if (core1or5 && rail == N_RAIL_Q)
1360 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1361 if (core2or5 && rail == N_RAIL_I)
1362 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1363 if (core2or5 && rail == N_RAIL_Q)
1364 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1367 if (core1or5 && rail == N_RAIL_I)
1368 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1369 if (core1or5 && rail == N_RAIL_Q)
1370 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1371 if (core2or5 && rail == N_RAIL_I)
1372 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1373 if (core2or5 && rail == N_RAIL_Q)
1374 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1376 case N_RSSI_TSSI_2G:
1378 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1380 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1382 case N_RSSI_TSSI_5G:
1384 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1386 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1391 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1392 enum n_rssi_type rssi_type)
1398 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1399 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1400 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1401 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1402 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1403 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1404 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1405 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1407 for (i = 0; i < 2; i++) {
1408 if ((code == 1 && i == 1) || (code == 2 && !i))
1412 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1413 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1415 if (rssi_type == N_RSSI_W1 ||
1416 rssi_type == N_RSSI_W2 ||
1417 rssi_type == N_RSSI_NB) {
1419 B43_NPHY_AFECTL_C1 :
1421 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1424 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1425 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1426 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1428 if (rssi_type == N_RSSI_W1)
1429 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1430 else if (rssi_type == N_RSSI_W2)
1434 b43_phy_set(dev, reg, val);
1437 B43_NPHY_TXF_40CO_B1S0 :
1438 B43_NPHY_TXF_40CO_B32S1;
1439 b43_phy_set(dev, reg, 0x0020);
1441 if (rssi_type == N_RSSI_TBD)
1443 else if (rssi_type == N_RSSI_IQ)
1449 B43_NPHY_AFECTL_C1 :
1452 b43_phy_maskset(dev, reg, 0xFCFF, val);
1453 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1455 if (rssi_type != N_RSSI_IQ &&
1456 rssi_type != N_RSSI_TBD) {
1457 enum ieee80211_band band =
1458 b43_current_band(dev->wl);
1460 if (b43_nphy_ipa(dev))
1461 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1464 reg = (i == 0) ? 0x2000 : 0x3000;
1465 reg |= B2055_PADDRV;
1466 b43_radio_write(dev, reg, val);
1469 B43_NPHY_AFECTL_OVER1 :
1470 B43_NPHY_AFECTL_OVER;
1471 b43_phy_set(dev, reg, 0x0200);
1478 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1479 enum n_rssi_type rssi_type)
1482 bool rssi_w1_w2_nb = false;
1484 switch (rssi_type) {
1489 rssi_w1_w2_nb = true;
1501 val = (val << 12) | (val << 14);
1502 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1503 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1505 if (rssi_w1_w2_nb) {
1506 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1507 (rssi_type + 1) << 4);
1508 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1509 (rssi_type + 1) << 4);
1513 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1514 if (rssi_w1_w2_nb) {
1515 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1516 ~(B43_NPHY_RFCTL_CMD_RXEN |
1517 B43_NPHY_RFCTL_CMD_CORESEL));
1518 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1523 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1524 ~B43_NPHY_RFCTL_CMD_START);
1526 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1529 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1530 if (rssi_w1_w2_nb) {
1531 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1532 ~(B43_NPHY_RFCTL_CMD_RXEN |
1533 B43_NPHY_RFCTL_CMD_CORESEL),
1534 (B43_NPHY_RFCTL_CMD_RXEN |
1535 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1536 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1541 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1542 B43_NPHY_RFCTL_CMD_START);
1544 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1549 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1550 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1551 enum n_rssi_type type)
1553 if (dev->phy.rev >= 3)
1554 b43_nphy_rev3_rssi_select(dev, code, type);
1556 b43_nphy_rev2_rssi_select(dev, code, type);
1559 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1560 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1561 enum n_rssi_type rssi_type, u8 *buf)
1564 for (i = 0; i < 2; i++) {
1565 if (rssi_type == N_RSSI_NB) {
1567 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1569 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1572 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1574 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1575 0xFC, buf[2 * i + 1]);
1579 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1582 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1583 0xF3, buf[2 * i + 1] << 2);
1588 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1589 static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1594 u16 save_regs_phy[9];
1597 if (dev->phy.rev >= 3) {
1598 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1599 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1600 save_regs_phy[2] = b43_phy_read(dev,
1601 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1602 save_regs_phy[3] = b43_phy_read(dev,
1603 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1604 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1605 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1606 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1607 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1608 save_regs_phy[8] = 0;
1610 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1611 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1612 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1613 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1614 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1615 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1616 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1617 save_regs_phy[7] = 0;
1618 save_regs_phy[8] = 0;
1621 b43_nphy_rssi_select(dev, 5, rssi_type);
1623 if (dev->phy.rev < 2) {
1624 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1625 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1628 for (i = 0; i < 4; i++)
1631 for (i = 0; i < nsamp; i++) {
1632 if (dev->phy.rev < 2) {
1633 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1634 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1636 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1637 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1640 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1641 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1642 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1643 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1645 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1646 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1648 if (dev->phy.rev < 2)
1649 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1651 if (dev->phy.rev >= 3) {
1652 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1653 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1654 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1656 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1658 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1659 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1660 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1661 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1663 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1664 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1665 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1666 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1667 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1668 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1669 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1675 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1676 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1678 struct b43_phy_n *nphy = dev->phy.n;
1680 u16 saved_regs_phy_rfctl[2];
1681 u16 saved_regs_phy[22];
1682 u16 regs_to_store_rev3[] = {
1683 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1684 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1685 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1686 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1688 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1689 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1691 u16 regs_to_store_rev7[] = {
1692 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1693 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1694 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1695 0x342, 0x343, 0x346, 0x347,
1697 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1699 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1700 0x340, 0x341, 0x344, 0x345,
1701 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1709 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1713 s32 results[8][4] = { };
1714 s32 results_min[4] = { };
1715 s32 poll_results[4] = { };
1717 u16 *rssical_radio_regs = NULL;
1718 u16 *rssical_phy_regs = NULL;
1720 u16 r; /* routing */
1722 int core, i, j, vcm;
1724 if (dev->phy.rev >= 7) {
1725 regs_to_store = regs_to_store_rev7;
1726 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
1728 regs_to_store = regs_to_store_rev3;
1729 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
1731 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
1733 class = b43_nphy_classifier(dev, 0, 0);
1734 b43_nphy_classifier(dev, 7, 4);
1735 b43_nphy_read_clip_detection(dev, clip_state);
1736 b43_nphy_write_clip_detection(dev, clip_off);
1738 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1739 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1740 for (i = 0; i < regs_amount; i++)
1741 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1743 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1744 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
1746 if (dev->phy.rev >= 7) {
1748 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1752 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1753 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1754 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1755 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1756 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1757 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1758 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1760 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1761 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1765 rx_core_state = b43_nphy_get_rx_core_state(dev);
1766 for (core = 0; core < 2; core++) {
1767 if (!(rx_core_state & (1 << core)))
1769 r = core ? B2056_RX1 : B2056_RX0;
1770 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1772 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1775 /* Grab RSSI results for every possible VCM */
1776 for (vcm = 0; vcm < 8; vcm++) {
1777 if (dev->phy.rev >= 7)
1780 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1782 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
1785 /* Find out which VCM got the best results */
1786 for (i = 0; i < 4; i += 2) {
1788 s32 mind = 0x100000;
1793 for (vcm = 0; vcm < 8; vcm++) {
1794 currd = results[vcm][i] * results[vcm][i] +
1795 results[vcm][i + 1] * results[vcm][i];
1800 if (results[vcm][i] < minpoll)
1801 minpoll = results[vcm][i];
1804 results_min[i] = minpoll;
1807 /* Select the best VCM */
1808 if (dev->phy.rev >= 7)
1811 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1812 0xE3, vcm_final << 2);
1814 for (i = 0; i < 4; i++) {
1817 offset[i] = -results[vcm_final][i];
1819 offset[i] = -((abs(offset[i]) + 4) / 8);
1821 offset[i] = (offset[i] + 4) / 8;
1822 if (results_min[i] == 248)
1824 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1825 (i / 2 == 0) ? 1 : 2,
1826 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
1831 for (core = 0; core < 2; core++) {
1832 if (!(rx_core_state & (1 << core)))
1834 for (i = 0; i < 2; i++) {
1835 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1837 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1839 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1840 for (j = 0; j < 4; j++) {
1841 if (j / 2 == core) {
1842 offset[j] = 232 - poll_results[j];
1844 offset[j] = -(abs(offset[j] + 4) / 8);
1846 offset[j] = (offset[j] + 4) / 8;
1847 b43_nphy_scale_offset_rssi(dev, 0,
1848 offset[2 * core], core + 1, j % 2, i);
1854 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1855 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1857 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1859 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1860 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1861 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1863 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1864 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1865 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1867 for (i = 0; i < regs_amount; i++)
1868 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1870 /* Store for future configuration */
1871 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1872 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1873 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1875 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1876 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1878 if (dev->phy.rev >= 7) {
1880 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1881 B2056_RX_RSSI_MISC);
1882 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1883 B2056_RX_RSSI_MISC);
1885 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1886 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1887 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1888 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1889 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1890 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1891 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1892 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1893 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1894 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1895 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1896 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1898 /* Remember for which channel we store configuration */
1899 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1900 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1902 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1904 /* End of calibration, restore configuration */
1905 b43_nphy_classifier(dev, 7, class);
1906 b43_nphy_write_clip_detection(dev, clip_state);
1909 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1910 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
1915 u16 class, override;
1916 u8 regs_save_radio[2];
1917 u16 regs_save_phy[2];
1924 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1925 s32 results_min[4] = { };
1926 u8 vcm_final[4] = { };
1927 s32 results[4][4] = { };
1928 s32 miniq[4][2] = { };
1930 if (type == N_RSSI_NB) {
1933 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
1941 class = b43_nphy_classifier(dev, 0, 0);
1942 b43_nphy_classifier(dev, 7, 4);
1943 b43_nphy_read_clip_detection(dev, clip_state);
1944 b43_nphy_write_clip_detection(dev, clip_off);
1946 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1951 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1952 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
1953 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1954 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
1956 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1957 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
1958 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1959 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
1961 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1962 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1963 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1964 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1965 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1966 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
1968 b43_nphy_rssi_select(dev, 5, type);
1969 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1970 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
1972 for (vcm = 0; vcm < 4; vcm++) {
1974 for (j = 0; j < 4; j++)
1976 if (type != N_RSSI_W2)
1977 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1978 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
1979 if (type == N_RSSI_W1 || type == N_RSSI_W2)
1980 for (j = 0; j < 2; j++)
1981 miniq[vcm][j] = min(results[vcm][2 * j],
1982 results[vcm][2 * j + 1]);
1985 for (i = 0; i < 4; i++) {
1986 s32 mind = 0x100000;
1990 for (vcm = 0; vcm < 4; vcm++) {
1991 if (type == N_RSSI_NB)
1992 currd = abs(results[vcm][i] - code * 8);
1994 currd = abs(miniq[vcm][i / 2] - code * 8);
2001 if (results[vcm][i] < minpoll)
2002 minpoll = results[vcm][i];
2004 results_min[i] = minpoll;
2005 vcm_final[i] = minvcm;
2008 if (type != N_RSSI_W2)
2009 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2011 for (i = 0; i < 4; i++) {
2012 offset[i] = (code * 8) - results[vcm_final[i]][i];
2015 offset[i] = -((abs(offset[i]) + 4) / 8);
2017 offset[i] = (offset[i] + 4) / 8;
2019 if (results_min[i] == 248)
2020 offset[i] = code - 32;
2022 core = (i / 2) ? 2 : 1;
2023 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
2025 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2029 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2030 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2034 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
2037 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
2040 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2043 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2049 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
2052 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
2055 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
2059 b43_nphy_rssi_select(dev, 0, type);
2061 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2062 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2063 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2064 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2066 b43_nphy_classifier(dev, 7, class);
2067 b43_nphy_write_clip_detection(dev, clip_state);
2068 /* Specs don't say about reset here, but it makes wl and b43 dumps
2069 identical, it really seems wl performs this */
2070 b43_nphy_reset_cca(dev);
2075 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2077 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2079 if (dev->phy.rev >= 3) {
2080 b43_nphy_rev3_rssi_cal(dev);
2082 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2083 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2084 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
2088 /**************************************************
2090 **************************************************/
2092 static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
2094 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2099 struct nphy_gain_ctl_workaround_entry *e;
2100 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2101 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2103 /* Prepare values */
2104 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2105 & B43_NPHY_BANDCTL_5GHZ;
2106 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2107 sprom->boardflags_lo & B43_BFL_EXTLNA;
2108 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2109 if (ghz5 && dev->phy.rev >= 5)
2114 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2116 /* Set Clip 2 detect */
2117 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2118 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2120 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2122 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2124 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2125 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2126 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2127 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2128 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2130 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2132 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2134 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2136 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2137 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2139 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2140 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2141 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2142 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2143 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2144 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2145 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2146 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2147 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2148 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2149 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2150 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2152 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2153 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2155 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2158 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2159 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2160 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2161 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2162 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2163 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2165 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2166 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2167 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
2168 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2169 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2170 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2171 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2172 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2173 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2174 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2177 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2179 struct b43_phy_n *nphy = dev->phy.n;
2184 u8 rfseq_events[3] = { 6, 8, 7 };
2185 u8 rfseq_delays[3] = { 10, 30, 1 };
2187 /* Set Clip 2 detect */
2188 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2189 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2191 /* Set narrowband clip threshold */
2192 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2193 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2195 if (!dev->phy.is_40mhz) {
2196 /* Set dwell lengths */
2197 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2198 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2199 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2200 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2203 /* Set wideband clip 2 threshold */
2204 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2205 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2206 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2207 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2209 if (!dev->phy.is_40mhz) {
2210 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2211 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2212 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2213 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2214 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2215 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2216 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2217 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2220 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2222 if (nphy->gain_boost) {
2223 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2229 code = dev->phy.is_40mhz ? 6 : 7;
2232 /* Set HPVGA2 index */
2233 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2234 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2235 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2236 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2238 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2239 /* specs say about 2 loops, but wl does 4 */
2240 for (i = 0; i < 4; i++)
2241 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2243 b43_nphy_adjust_lna_gain_table(dev);
2245 if (nphy->elna_gain_config) {
2246 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2247 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2248 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2249 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2250 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2252 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2253 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2254 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2255 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2256 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2258 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2259 /* specs say about 2 loops, but wl does 4 */
2260 for (i = 0; i < 4; i++)
2261 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2262 (code << 8 | 0x74));
2265 if (dev->phy.rev == 2) {
2266 for (i = 0; i < 4; i++) {
2267 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2268 (0x0400 * i) + 0x0020);
2269 for (j = 0; j < 21; j++) {
2270 tmp = j * (i < 2 ? 3 : 1);
2272 B43_NPHY_TABLE_DATALO, tmp);
2277 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2278 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2279 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2280 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2282 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2283 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2286 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2287 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2289 if (dev->phy.rev >= 7)
2291 else if (dev->phy.rev >= 3)
2292 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2294 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2297 /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2298 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2301 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2302 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2305 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2307 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2308 struct b43_phy *phy = &dev->phy;
2310 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2312 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2314 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2315 u8 ntab7_138_146[] = { 0x11, 0x11 };
2316 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2318 u16 lpf_20, lpf_40, lpf_11b;
2319 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2320 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2321 bool rccal_ovrd = false;
2323 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2324 u16 bias, conv, filt;
2329 if (phy->rev == 7) {
2330 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2331 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2332 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2333 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2334 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2335 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2336 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2337 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2338 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2339 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2340 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2341 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2342 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2343 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2344 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2345 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2346 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2348 if (phy->rev <= 8) {
2349 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2350 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2353 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2355 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2356 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2357 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2359 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2360 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2361 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2363 if (b43_nphy_ipa(dev))
2364 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2365 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2367 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2368 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2370 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2371 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2372 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2373 if (b43_nphy_ipa(dev)) {
2374 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2375 phy->radio_rev == 7 || phy->radio_rev == 8) {
2376 bcap_val = b43_radio_read(dev, 0x16b);
2377 scap_val = b43_radio_read(dev, 0x16a);
2378 scap_val_11b = scap_val;
2379 bcap_val_11b = bcap_val;
2380 if (phy->radio_rev == 5 && phy->is_40mhz) {
2381 scap_val_11n_20 = scap_val;
2382 bcap_val_11n_20 = bcap_val;
2383 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2385 } else { /* Rev 7/8 */
2388 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2389 scap_val_11n_20 = 0xc;
2390 bcap_val_11n_20 = 0xc;
2391 scap_val_11n_40 = 0xa;
2392 bcap_val_11n_40 = 0xa;
2394 scap_val_11n_20 = 0x14;
2395 bcap_val_11n_20 = 0x14;
2396 scap_val_11n_40 = 0xf;
2397 bcap_val_11n_40 = 0xf;
2403 if (phy->radio_rev == 5) {
2406 bcap_val = b43_radio_read(dev, 0x16b);
2407 scap_val = b43_radio_read(dev, 0x16a);
2408 scap_val_11b = scap_val;
2409 bcap_val_11b = bcap_val;
2410 scap_val_11n_20 = 0x11;
2411 scap_val_11n_40 = 0x11;
2412 bcap_val_11n_20 = 0x13;
2413 bcap_val_11n_40 = 0x13;
2418 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2419 (scap_val_11b << 3) |
2421 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2422 (scap_val_11n_20 << 3) |
2424 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2425 (scap_val_11n_40 << 3) |
2427 for (core = 0; core < 2; core++) {
2428 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2430 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2432 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2434 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2436 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2438 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2440 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2442 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2445 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
2447 b43_phy_write(dev, 0x32F, 0x3);
2448 if (phy->radio_rev == 4 || phy->radio_rev == 6)
2449 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
2451 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2452 if (sprom->revision &&
2453 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2454 b43_radio_write(dev, 0x5, 0x05);
2455 b43_radio_write(dev, 0x6, 0x30);
2456 b43_radio_write(dev, 0x7, 0x00);
2457 b43_radio_set(dev, 0x4f, 0x1);
2458 b43_radio_set(dev, 0xd4, 0x1);
2467 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2468 for (core = 0; core < 2; core++) {
2470 b43_radio_write(dev, 0x5F, bias);
2471 b43_radio_write(dev, 0x64, conv);
2472 b43_radio_write(dev, 0x66, filt);
2474 b43_radio_write(dev, 0xE8, bias);
2475 b43_radio_write(dev, 0xE9, conv);
2476 b43_radio_write(dev, 0xEB, filt);
2482 if (b43_nphy_ipa(dev)) {
2483 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2484 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2485 phy->radio_rev == 6) {
2486 for (core = 0; core < 2; core++) {
2488 b43_radio_write(dev, 0x51,
2491 b43_radio_write(dev, 0xd6,
2495 if (phy->radio_rev == 3) {
2496 for (core = 0; core < 2; core++) {
2498 b43_radio_write(dev, 0x64,
2500 b43_radio_write(dev, 0x5F,
2502 b43_radio_write(dev, 0x66,
2504 b43_radio_write(dev, 0x59,
2506 b43_radio_write(dev, 0x80,
2509 b43_radio_write(dev, 0x69,
2511 b43_radio_write(dev, 0xE8,
2513 b43_radio_write(dev, 0xEB,
2515 b43_radio_write(dev, 0xDE,
2517 b43_radio_write(dev, 0x105,
2521 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2522 if (!phy->is_40mhz) {
2523 b43_radio_write(dev, 0x5F, 0x14);
2524 b43_radio_write(dev, 0xE8, 0x12);
2526 b43_radio_write(dev, 0x5F, 0x16);
2527 b43_radio_write(dev, 0xE8, 0x16);
2531 u16 freq = phy->channel_freq;
2532 if ((freq >= 5180 && freq <= 5230) ||
2533 (freq >= 5745 && freq <= 5805)) {
2534 b43_radio_write(dev, 0x7D, 0xFF);
2535 b43_radio_write(dev, 0xFE, 0xFF);
2539 if (phy->radio_rev != 5) {
2540 for (core = 0; core < 2; core++) {
2542 b43_radio_write(dev, 0x5c, 0x61);
2543 b43_radio_write(dev, 0x51, 0x70);
2545 b43_radio_write(dev, 0xe1, 0x61);
2546 b43_radio_write(dev, 0xd6, 0x70);
2552 if (phy->radio_rev == 4) {
2553 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2554 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2555 for (core = 0; core < 2; core++) {
2557 b43_radio_write(dev, 0x1a1, 0x00);
2558 b43_radio_write(dev, 0x1a2, 0x3f);
2559 b43_radio_write(dev, 0x1a6, 0x3f);
2561 b43_radio_write(dev, 0x1a7, 0x00);
2562 b43_radio_write(dev, 0x1ab, 0x3f);
2563 b43_radio_write(dev, 0x1ac, 0x3f);
2567 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2568 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2569 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2570 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2572 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2573 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2574 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2575 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2576 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2577 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2579 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2580 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2581 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2582 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2585 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2587 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2588 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2589 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2590 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2591 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2592 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2593 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2595 if (!phy->is_40mhz) {
2596 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2597 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2599 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2600 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2603 b43_nphy_gain_ctl_workarounds(dev);
2606 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2607 aux_adc_vmid_rev7_core0);
2608 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2609 aux_adc_vmid_rev7_core1);
2610 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2612 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2617 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2619 struct b43_phy_n *nphy = dev->phy.n;
2620 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2623 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
2624 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
2626 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2628 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2629 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2630 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2633 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
2634 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
2635 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
2636 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
2637 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
2640 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
2641 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
2642 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
2643 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
2644 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
2652 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2653 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
2655 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2657 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2659 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2660 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2661 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2662 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2663 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2664 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2666 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2667 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
2670 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2671 ARRAY_SIZE(tx2rx_events));
2674 if (b43_nphy_ipa(dev))
2675 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2676 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2677 if (nphy->hw_phyrxchain != 3 &&
2678 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2679 if (b43_nphy_ipa(dev)) {
2680 rx2tx_delays[5] = 59;
2681 rx2tx_delays[6] = 1;
2682 rx2tx_events[7] = 0x1F;
2684 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
2685 ARRAY_SIZE(rx2tx_events));
2688 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2690 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2692 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
2694 if (!dev->phy.is_40mhz) {
2695 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2696 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2698 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2699 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2702 b43_nphy_gain_ctl_workarounds(dev);
2704 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2705 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
2707 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2708 pdet_range = sprom->fem.ghz2.pdet_range;
2710 pdet_range = sprom->fem.ghz5.pdet_range;
2711 vmid = vmids[min_t(u16, pdet_range, 4)];
2712 gain = gains[min_t(u16, pdet_range, 4)];
2713 switch (pdet_range) {
2715 if (!(dev->phy.rev >= 4 &&
2716 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2721 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2722 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2723 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2724 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2727 if (dev->phy.rev >= 6) {
2728 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2733 } else if (dev->phy.rev == 5) {
2737 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2738 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2739 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2740 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2744 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
2745 if (pdet_range == 4) {
2755 if (pdet_range == 4) {
2765 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2766 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2768 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2769 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2773 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2774 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2775 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2776 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2777 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2778 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2779 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2780 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2781 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2782 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2783 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2784 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2786 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2788 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2789 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2790 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2791 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2795 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2796 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2797 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2799 if (dev->phy.rev == 4 &&
2800 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2801 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2803 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2807 /* Dropped probably-always-true condition */
2808 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2809 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
2810 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
2811 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2812 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2813 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2814 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2815 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2816 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2817 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2818 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2819 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
2821 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2822 ; /* TODO: 0x0080000000000000 HF */
2825 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2827 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2828 struct b43_phy *phy = &dev->phy;
2829 struct b43_phy_n *nphy = phy->n;
2831 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2832 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
2834 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2835 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2837 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2838 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
2843 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2844 nphy->band5g_pwrgain) {
2845 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2846 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2848 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2849 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2852 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2853 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2854 if (dev->phy.rev < 3) {
2855 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2856 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2859 if (dev->phy.rev < 2) {
2860 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2861 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2862 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2863 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2864 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2865 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2868 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2869 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2870 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2871 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2873 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2874 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2876 b43_nphy_gain_ctl_workarounds(dev);
2878 if (dev->phy.rev < 2) {
2879 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2880 b43_hf_write(dev, b43_hf_read(dev) |
2882 } else if (dev->phy.rev == 2) {
2883 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2884 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2887 if (dev->phy.rev < 2)
2888 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2889 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2891 /* Set phase track alpha and beta */
2892 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2893 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2894 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2895 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2896 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2897 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2899 if (dev->phy.rev < 3) {
2900 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2901 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2902 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2903 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2904 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2907 if (dev->phy.rev == 2)
2908 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2909 B43_NPHY_FINERX2_CGC_DECGC);
2912 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2913 static void b43_nphy_workarounds(struct b43_wldev *dev)
2915 struct b43_phy *phy = &dev->phy;
2916 struct b43_phy_n *nphy = phy->n;
2918 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2919 b43_nphy_classifier(dev, 1, 0);
2921 b43_nphy_classifier(dev, 1, 1);
2923 if (nphy->hang_avoid)
2924 b43_nphy_stay_in_carrier_search(dev, 1);
2926 b43_phy_set(dev, B43_NPHY_IQFLIP,
2927 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2929 if (dev->phy.rev >= 7)
2930 b43_nphy_workarounds_rev7plus(dev);
2931 else if (dev->phy.rev >= 3)
2932 b43_nphy_workarounds_rev3plus(dev);
2934 b43_nphy_workarounds_rev1_2(dev);
2936 if (nphy->hang_avoid)
2937 b43_nphy_stay_in_carrier_search(dev, 0);
2940 /**************************************************
2942 **************************************************/
2945 * Transmits a known value for LO calibration
2946 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2948 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2949 bool iqmode, bool dac_test)
2951 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2954 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2958 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2959 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2961 struct b43_phy_n *nphy = dev->phy.n;
2963 bool override = false;
2966 if (nphy->txrx_chain == 0) {
2969 } else if (nphy->txrx_chain == 1) {
2974 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2975 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2979 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2980 B43_NPHY_RFSEQMODE_CAOVER);
2982 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2983 ~B43_NPHY_RFSEQMODE_CAOVER);
2986 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2987 static void b43_nphy_stop_playback(struct b43_wldev *dev)
2989 struct b43_phy_n *nphy = dev->phy.n;
2992 if (nphy->hang_avoid)
2993 b43_nphy_stay_in_carrier_search(dev, 1);
2995 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2997 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2999 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3001 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3003 if (nphy->bb_mult_save & 0x80000000) {
3004 tmp = nphy->bb_mult_save & 0xFFFF;
3005 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3006 nphy->bb_mult_save = 0;
3009 if (nphy->hang_avoid)
3010 b43_nphy_stay_in_carrier_search(dev, 0);
3013 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3014 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3015 struct nphy_txgains target,
3016 struct nphy_iqcal_params *params)
3021 if (dev->phy.rev >= 3) {
3022 params->txgm = target.txgm[core];
3023 params->pga = target.pga[core];
3024 params->pad = target.pad[core];
3025 params->ipa = target.ipa[core];
3026 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
3027 (params->pad << 4) | (params->ipa);
3028 for (j = 0; j < 5; j++)
3029 params->ncorr[j] = 0x79;
3031 gain = (target.pad[core]) | (target.pga[core] << 4) |
3032 (target.txgm[core] << 8);
3034 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3036 for (i = 0; i < 9; i++)
3037 if (tbl_iqcal_gainparams[indx][i][0] == gain)
3041 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3042 params->pga = tbl_iqcal_gainparams[indx][i][2];
3043 params->pad = tbl_iqcal_gainparams[indx][i][3];
3044 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3046 for (j = 0; j < 4; j++)
3047 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3051 /**************************************************
3053 **************************************************/
3055 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3059 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3062 return B43_TXPWR_RES_DONE;
3065 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3066 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3068 struct b43_phy_n *nphy = dev->phy.n;
3070 u16 bmask, val, tmp;
3071 enum ieee80211_band band = b43_current_band(dev->wl);
3073 if (nphy->hang_avoid)
3074 b43_nphy_stay_in_carrier_search(dev, 1);
3076 nphy->txpwrctrl = enable;
3078 if (dev->phy.rev >= 3 &&
3079 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3080 (B43_NPHY_TXPCTL_CMD_COEFF |
3081 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3082 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3083 /* We disable enabled TX pwr ctl, save it's state */
3084 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3085 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3086 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3087 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3090 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3091 for (i = 0; i < 84; i++)
3092 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
3094 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3095 for (i = 0; i < 84; i++)
3096 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
3098 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3099 if (dev->phy.rev >= 3)
3100 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3101 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
3103 if (dev->phy.rev >= 3) {
3104 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3105 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3107 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3110 if (dev->phy.rev == 2)
3111 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3112 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3113 else if (dev->phy.rev < 2)
3114 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3115 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
3117 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
3118 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
3120 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3122 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3125 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3126 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3127 /* wl does useless check for "enable" param here */
3128 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3129 if (dev->phy.rev >= 3) {
3130 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3132 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3134 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
3136 if (band == IEEE80211_BAND_5GHZ) {
3137 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3138 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
3139 if (dev->phy.rev > 1)
3140 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3141 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3145 if (dev->phy.rev >= 3) {
3146 if (nphy->tx_pwr_idx[0] != 128 &&
3147 nphy->tx_pwr_idx[1] != 128) {
3148 /* Recover TX pwr ctl state */
3149 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3150 ~B43_NPHY_TXPCTL_CMD_INIT,
3151 nphy->tx_pwr_idx[0]);
3152 if (dev->phy.rev > 1)
3153 b43_phy_maskset(dev,
3154 B43_NPHY_TXPCTL_INIT,
3155 ~0xff, nphy->tx_pwr_idx[1]);
3159 if (dev->phy.rev >= 3) {
3160 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3161 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3163 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3166 if (dev->phy.rev == 2)
3167 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3168 else if (dev->phy.rev < 2)
3169 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
3171 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
3172 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
3174 if (b43_nphy_ipa(dev)) {
3175 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3176 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
3180 if (nphy->hang_avoid)
3181 b43_nphy_stay_in_carrier_search(dev, 0);
3184 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
3185 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
3187 struct b43_phy_n *nphy = dev->phy.n;
3188 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3190 u8 txpi[2], bbmult, i;
3191 u16 tmp, radio_gain, dac_gain;
3192 u16 freq = dev->phy.channel_freq;
3194 /* u32 gaintbl; rev3+ */
3196 if (nphy->hang_avoid)
3197 b43_nphy_stay_in_carrier_search(dev, 1);
3199 if (dev->phy.rev >= 7) {
3200 txpi[0] = txpi[1] = 30;
3201 } else if (dev->phy.rev >= 3) {
3204 } else if (sprom->revision < 4) {
3208 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3209 txpi[0] = sprom->txpid2g[0];
3210 txpi[1] = sprom->txpid2g[1];
3211 } else if (freq >= 4900 && freq < 5100) {
3212 txpi[0] = sprom->txpid5gl[0];
3213 txpi[1] = sprom->txpid5gl[1];
3214 } else if (freq >= 5100 && freq < 5500) {
3215 txpi[0] = sprom->txpid5g[0];
3216 txpi[1] = sprom->txpid5g[1];
3217 } else if (freq >= 5500) {
3218 txpi[0] = sprom->txpid5gh[0];
3219 txpi[1] = sprom->txpid5gh[1];
3225 if (dev->phy.rev < 7 &&
3226 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
3227 txpi[0] = txpi[1] = 91;
3230 for (i = 0; i < 2; i++) {
3231 nphy->txpwrindex[i].index_internal = txpi[i];
3232 nphy->txpwrindex[i].index_internal_save = txpi[i];
3236 for (i = 0; i < 2; i++) {
3237 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3239 if (dev->phy.rev >= 3)
3240 radio_gain = (txgain >> 16) & 0x1FFFF;
3242 radio_gain = (txgain >> 16) & 0x1FFF;
3244 if (dev->phy.rev >= 7)
3245 dac_gain = (txgain >> 8) & 0x7;
3247 dac_gain = (txgain >> 8) & 0x3F;
3248 bbmult = txgain & 0xFF;
3250 if (dev->phy.rev >= 3) {
3252 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3254 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3256 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3260 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3262 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3264 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3266 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3268 tmp = (tmp & 0x00FF) | (bbmult << 8);
3270 tmp = (tmp & 0xFF00) | bbmult;
3271 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3273 if (b43_nphy_ipa(dev)) {
3275 u16 reg = (i == 0) ?
3276 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3277 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3279 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3280 b43_phy_set(dev, reg, 0x4);
3284 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3286 if (nphy->hang_avoid)
3287 b43_nphy_stay_in_carrier_search(dev, 0);
3290 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3292 struct b43_phy *phy = &dev->phy;
3295 u16 r; /* routing */
3297 if (phy->rev >= 7) {
3298 for (core = 0; core < 2; core++) {
3299 r = core ? 0x190 : 0x170;
3300 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3301 b43_radio_write(dev, r + 0x5, 0x5);
3302 b43_radio_write(dev, r + 0x9, 0xE);
3304 b43_radio_write(dev, r + 0xA, 0);
3306 b43_radio_write(dev, r + 0xB, 1);
3308 b43_radio_write(dev, r + 0xB, 0x31);
3310 b43_radio_write(dev, r + 0x5, 0x9);
3311 b43_radio_write(dev, r + 0x9, 0xC);
3312 b43_radio_write(dev, r + 0xB, 0x0);
3314 b43_radio_write(dev, r + 0xA, 1);
3316 b43_radio_write(dev, r + 0xA, 0x31);
3318 b43_radio_write(dev, r + 0x6, 0);
3319 b43_radio_write(dev, r + 0x7, 0);
3320 b43_radio_write(dev, r + 0x8, 3);
3321 b43_radio_write(dev, r + 0xC, 0);
3324 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3325 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3327 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3328 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3329 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3331 for (core = 0; core < 2; core++) {
3332 r = core ? B2056_TX1 : B2056_TX0;
3334 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3335 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3336 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3337 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3338 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3339 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3340 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3341 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3342 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3345 b43_radio_write(dev, r | B2056_TX_TSSIA,
3348 b43_radio_write(dev, r | B2056_TX_TSSIG,
3351 b43_radio_write(dev, r | B2056_TX_TSSIG,
3353 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3356 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3358 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3359 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3360 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3368 * Stop radio and transmit known signal. Then check received signal strength to
3369 * get TSSI (Transmit Signal Strength Indicator).
3370 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3372 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3374 struct b43_phy *phy = &dev->phy;
3375 struct b43_phy_n *nphy = dev->phy.n;
3380 /* TODO: check if we can transmit */
3382 if (b43_nphy_ipa(dev))
3383 b43_nphy_ipa_internal_tssi_setup(dev);
3386 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3387 else if (phy->rev >= 3)
3388 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3390 b43_nphy_stop_playback(dev);
3391 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3393 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3394 b43_nphy_stop_playback(dev);
3395 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3398 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3399 else if (phy->rev >= 3)
3400 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3402 if (phy->rev >= 3) {
3403 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3404 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3406 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3407 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3409 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3410 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3413 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3414 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3416 struct b43_phy_n *nphy = dev->phy.n;
3421 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
3422 * 21 groups, each containing 4 entries.
3424 * First group has entries for CCK modulation.
3425 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
3427 * Group 0 is for CCK
3428 * Groups 1..4 use BPSK (group per coding rate)
3429 * Groups 5..8 use QPSK (group per coding rate)
3430 * Groups 9..12 use 16-QAM (group per coding rate)
3431 * Groups 13..16 use 64-QAM (group per coding rate)
3432 * Groups 17..20 are unknown
3435 for (i = 0; i < 4; i++)
3436 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3438 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3442 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3446 idx = dev->phy.is_40mhz ? 52 : 4;
3450 idx = dev->phy.is_40mhz ? 76 : 28;
3453 idx = dev->phy.is_40mhz ? 84 : 36;
3456 idx = dev->phy.is_40mhz ? 92 : 44;
3460 for (i = 0; i < 20; i++) {
3461 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3462 nphy->tx_power_offset[idx];
3467 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3474 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3475 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3477 struct b43_phy_n *nphy = dev->phy.n;
3478 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3480 s16 a1[2], b0[2], b1[2];
3486 u16 freq = dev->phy.channel_freq;
3488 u16 r; /* routing */
3491 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3492 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3493 b43_read32(dev, B43_MMIO_MACCTL);
3497 if (nphy->hang_avoid)
3498 b43_nphy_stay_in_carrier_search(dev, true);
3500 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3501 if (dev->phy.rev >= 3)
3502 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3503 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3505 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3506 B43_NPHY_TXPCTL_CMD_PCTLEN);
3508 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3509 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3511 if (sprom->revision < 4) {
3512 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3513 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3514 target[0] = target[1] = 52;
3515 a1[0] = a1[1] = -424;
3516 b0[0] = b0[1] = 5612;
3517 b1[0] = b1[1] = -1393;
3519 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3520 for (c = 0; c < 2; c++) {
3521 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3522 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3523 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3524 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3525 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3527 } else if (freq >= 4900 && freq < 5100) {
3528 for (c = 0; c < 2; c++) {
3529 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3530 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3531 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3532 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3533 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3535 } else if (freq >= 5100 && freq < 5500) {
3536 for (c = 0; c < 2; c++) {
3537 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3538 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3539 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3540 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3541 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3543 } else if (freq >= 5500) {
3544 for (c = 0; c < 2; c++) {
3545 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3546 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3547 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3548 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3549 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3552 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3553 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3554 target[0] = target[1] = 52;
3555 a1[0] = a1[1] = -424;
3556 b0[0] = b0[1] = 5612;
3557 b1[0] = b1[1] = -1393;
3560 /* target[0] = target[1] = nphy->tx_power_max; */
3562 if (dev->phy.rev >= 3) {
3563 if (sprom->fem.ghz2.tssipos)
3564 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3565 if (dev->phy.rev >= 7) {
3566 for (c = 0; c < 2; c++) {
3567 r = c ? 0x190 : 0x170;
3568 if (b43_nphy_ipa(dev))
3569 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3572 if (b43_nphy_ipa(dev)) {
3573 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3574 b43_radio_write(dev,
3575 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3576 b43_radio_write(dev,
3577 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3579 b43_radio_write(dev,
3580 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3581 b43_radio_write(dev,
3582 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3587 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3588 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3589 b43_read32(dev, B43_MMIO_MACCTL);
3593 if (dev->phy.rev >= 7) {
3594 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3595 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3596 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3597 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3599 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3600 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3601 if (dev->phy.rev > 1)
3602 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3603 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3606 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3607 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3609 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3610 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3611 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3612 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3613 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3614 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3615 B43_NPHY_TXPCTL_ITSSI_BINF);
3616 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3617 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3618 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3620 for (c = 0; c < 2; c++) {
3621 for (i = 0; i < 64; i++) {
3622 num = 8 * (16 * b0[c] + b1[c] * i);
3623 den = 32768 + a1[c] * i;
3624 pwr = max((4 * num + den / 2) / den, -8);
3625 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3626 pwr = max(pwr, target[c] + 1);
3629 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3632 b43_nphy_tx_prepare_adjusted_power_table(dev);
3633 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3634 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3636 if (nphy->hang_avoid)
3637 b43_nphy_stay_in_carrier_search(dev, false);
3640 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3642 struct b43_phy *phy = &dev->phy;
3644 const u32 *table = NULL;
3649 table = b43_nphy_get_tx_gain_table(dev);
3650 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3651 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3653 if (phy->rev >= 3) {
3655 nphy->gmval = (table[0] >> 16) & 0x7000;
3658 for (i = 0; i < 128; i++) {
3659 pga_gain = (table[i] >> 24) & 0xF;
3660 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3662 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
3666 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3668 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3674 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3675 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
3677 struct b43_phy_n *nphy = dev->phy.n;
3678 enum ieee80211_band band;
3682 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3683 B43_NPHY_RFCTL_INTC1);
3684 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3685 B43_NPHY_RFCTL_INTC2);
3686 band = b43_current_band(dev->wl);
3687 if (dev->phy.rev >= 3) {
3688 if (band == IEEE80211_BAND_5GHZ)
3693 if (band == IEEE80211_BAND_5GHZ)
3698 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3699 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3701 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3702 nphy->rfctrl_intc1_save);
3703 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3704 nphy->rfctrl_intc2_save);
3708 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3709 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3713 if (dev->phy.rev >= 3) {
3714 if (b43_nphy_ipa(dev)) {
3716 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3717 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3721 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3722 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3726 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3727 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3728 u16 samps, u8 time, bool wait)
3733 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3734 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3736 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
3738 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
3740 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3742 for (i = 1000; i; i--) {
3743 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3744 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3745 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3746 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3747 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3748 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3749 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3750 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3752 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3753 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3754 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3755 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3756 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3757 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3762 memset(est, 0, sizeof(*est));
3765 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3766 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3767 struct b43_phy_n_iq_comp *pcomp)
3770 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3771 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3772 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3773 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
3775 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3776 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3777 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3778 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3783 /* Ready but not used anywhere */
3784 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3785 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3787 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3789 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3791 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3792 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3794 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3795 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3797 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3798 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3799 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3800 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3801 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3802 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3803 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3804 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3807 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3808 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3811 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3813 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3815 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3816 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3818 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3819 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3821 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3822 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3823 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3824 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3825 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3826 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3827 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3828 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3830 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3831 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3833 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3834 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3835 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3836 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3837 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3838 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3839 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3840 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3841 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
3844 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3845 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3847 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3848 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3851 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
3852 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
3853 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3862 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3864 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3869 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3870 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
3876 int iq_nbits, qq_nbits;
3880 struct nphy_iq_est est;
3881 struct b43_phy_n_iq_comp old;
3882 struct b43_phy_n_iq_comp new = { };
3888 b43_nphy_rx_iq_coeffs(dev, false, &old);
3889 b43_nphy_rx_iq_coeffs(dev, true, &new);
3890 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3893 for (i = 0; i < 2; i++) {
3894 if (i == 0 && (mask & 1)) {
3898 } else if (i == 1 && (mask & 2)) {
3911 iq_nbits = fls(abs(iq));
3914 arsh = iq_nbits - 20;
3916 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3919 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3928 brsh = qq_nbits - 11;
3930 b = (qq << (31 - qq_nbits));
3933 b = (qq << (31 - qq_nbits));
3940 b = int_sqrt(b / tmp - a * a) - (1 << 10);
3942 if (i == 0 && (mask & 0x1)) {
3943 if (dev->phy.rev >= 3) {
3950 } else if (i == 1 && (mask & 0x2)) {
3951 if (dev->phy.rev >= 3) {
3964 b43_nphy_rx_iq_coeffs(dev, true, &new);
3967 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3968 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3971 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
3973 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3974 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3975 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3976 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
3979 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3980 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3982 struct b43_phy_n *nphy = dev->phy.n;
3984 u8 channel = dev->phy.channel;
3985 int tone[2] = { 57, 58 };
3986 u32 noise[2] = { 0x3FF, 0x3FF };
3988 B43_WARN_ON(dev->phy.rev < 3);
3990 if (nphy->hang_avoid)
3991 b43_nphy_stay_in_carrier_search(dev, 1);
3993 if (nphy->gband_spurwar_en) {
3994 /* TODO: N PHY Adjust Analog Pfbw (7) */
3995 if (channel == 11 && dev->phy.is_40mhz)
3996 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3998 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3999 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
4002 if (nphy->aband_spurwar_en) {
4003 if (channel == 54) {
4006 } else if (channel == 38 || channel == 102 || channel == 118) {
4007 if (0 /* FIXME */) {
4014 } else if (channel == 134) {
4017 } else if (channel == 151) {
4020 } else if (channel == 153 || channel == 161) {
4028 if (!tone[0] && !noise[0])
4029 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
4031 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4034 if (nphy->hang_avoid)
4035 b43_nphy_stay_in_carrier_search(dev, 0);
4038 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4039 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4041 struct b43_phy_n *nphy = dev->phy.n;
4044 u32 cur_real, cur_imag, real_part, imag_part;
4048 if (nphy->hang_avoid)
4049 b43_nphy_stay_in_carrier_search(dev, true);
4051 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4053 for (i = 0; i < 2; i++) {
4054 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4055 (buffer[i * 2 + 1] & 0x3FF);
4056 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4057 (((i + 26) << 10) | 320));
4058 for (j = 0; j < 128; j++) {
4059 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4060 ((tmp >> 16) & 0xFFFF));
4061 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4066 for (i = 0; i < 2; i++) {
4067 tmp = buffer[5 + i];
4068 real_part = (tmp >> 8) & 0xFF;
4069 imag_part = (tmp & 0xFF);
4070 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4071 (((i + 26) << 10) | 448));
4073 if (dev->phy.rev >= 3) {
4074 cur_real = real_part;
4075 cur_imag = imag_part;
4076 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4079 for (j = 0; j < 128; j++) {
4080 if (dev->phy.rev < 3) {
4081 cur_real = (real_part * loscale[j] + 128) >> 8;
4082 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4083 tmp = ((cur_real & 0xFF) << 8) |
4086 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4087 ((tmp >> 16) & 0xFFFF));
4088 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4093 if (dev->phy.rev >= 3) {
4094 b43_shm_write16(dev, B43_SHM_SHARED,
4095 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4096 b43_shm_write16(dev, B43_SHM_SHARED,
4097 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4100 if (nphy->hang_avoid)
4101 b43_nphy_stay_in_carrier_search(dev, false);
4105 * Restore RSSI Calibration
4106 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4108 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4110 struct b43_phy_n *nphy = dev->phy.n;
4112 u16 *rssical_radio_regs = NULL;
4113 u16 *rssical_phy_regs = NULL;
4115 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4116 if (!nphy->rssical_chanspec_2G.center_freq)
4118 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4119 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4121 if (!nphy->rssical_chanspec_5G.center_freq)
4123 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4124 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4127 if (dev->phy.rev >= 7) {
4129 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4130 rssical_radio_regs[0]);
4131 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4132 rssical_radio_regs[1]);
4135 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4136 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4137 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4138 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4140 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4141 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4142 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4143 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4145 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4146 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4147 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4148 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4151 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4152 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4154 struct b43_phy_n *nphy = dev->phy.n;
4155 u16 *save = nphy->tx_rx_cal_radio_saveregs;
4159 if (dev->phy.rev >= 3) {
4160 for (i = 0; i < 2; i++) {
4161 tmp = (i == 0) ? 0x2000 : 0x3000;
4164 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4165 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4166 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4167 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4168 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4169 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4170 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4171 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4172 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4173 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4174 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
4176 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4177 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4178 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4179 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4180 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4181 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4182 if (nphy->ipa5g_on) {
4183 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4184 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
4186 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4187 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
4189 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4191 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4192 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4193 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4194 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4195 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4196 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
4197 if (nphy->ipa2g_on) {
4198 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4199 b43_radio_write(dev, tmp | B2055_XOCTL2,
4200 (dev->phy.rev < 5) ? 0x11 : 0x01);
4202 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4203 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4206 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4207 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4208 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
4211 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4212 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
4214 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4215 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
4217 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4218 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
4220 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4221 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
4223 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4224 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
4226 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4227 B43_NPHY_BANDCTL_5GHZ)) {
4228 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4229 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
4231 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4232 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
4235 if (dev->phy.rev < 2) {
4236 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4237 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4239 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4240 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4245 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4246 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4248 struct b43_phy_n *nphy = dev->phy.n;
4252 u16 tmp = nphy->txcal_bbmult;
4257 for (i = 0; i < 18; i++) {
4258 scale = (ladder_lo[i].percent * tmp) / 100;
4259 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
4260 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
4262 scale = (ladder_iq[i].percent * tmp) / 100;
4263 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
4264 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
4268 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4269 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4272 for (i = 0; i < 15; i++)
4273 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4274 tbl_tx_filter_coef_rev4[2][i]);
4277 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4278 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4281 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
4282 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4284 for (i = 0; i < 3; i++)
4285 for (j = 0; j < 15; j++)
4286 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4287 tbl_tx_filter_coef_rev4[i][j]);
4289 if (dev->phy.is_40mhz) {
4290 for (j = 0; j < 15; j++)
4291 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4292 tbl_tx_filter_coef_rev4[3][j]);
4293 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4294 for (j = 0; j < 15; j++)
4295 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4296 tbl_tx_filter_coef_rev4[5][j]);
4299 if (dev->phy.channel == 14)
4300 for (j = 0; j < 15; j++)
4301 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4302 tbl_tx_filter_coef_rev4[6][j]);
4305 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4306 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4308 struct b43_phy_n *nphy = dev->phy.n;
4311 struct nphy_txgains target;
4312 const u32 *table = NULL;
4314 if (!nphy->txpwrctrl) {
4317 if (nphy->hang_avoid)
4318 b43_nphy_stay_in_carrier_search(dev, true);
4319 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
4320 if (nphy->hang_avoid)
4321 b43_nphy_stay_in_carrier_search(dev, false);
4323 for (i = 0; i < 2; ++i) {
4324 if (dev->phy.rev >= 3) {
4325 target.ipa[i] = curr_gain[i] & 0x000F;
4326 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4327 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4328 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4330 target.ipa[i] = curr_gain[i] & 0x0003;
4331 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4332 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4333 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4339 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4340 B43_NPHY_TXPCTL_STAT_BIDX) >>
4341 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4342 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4343 B43_NPHY_TXPCTL_STAT_BIDX) >>
4344 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4346 for (i = 0; i < 2; ++i) {
4347 table = b43_nphy_get_tx_gain_table(dev);
4348 if (dev->phy.rev >= 3) {
4349 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4350 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4351 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4352 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4354 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4355 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4356 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4357 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4365 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4366 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4368 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4370 if (dev->phy.rev >= 3) {
4371 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4372 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4373 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4374 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4375 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
4376 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4377 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
4378 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4379 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4380 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4381 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4382 b43_nphy_reset_cca(dev);
4384 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4385 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4386 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4387 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4388 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
4389 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4390 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4394 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4395 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4397 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4400 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4401 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4402 if (dev->phy.rev >= 3) {
4403 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4404 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4406 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4408 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4410 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4412 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4414 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
4415 b43_phy_mask(dev, B43_NPHY_BBCFG,
4416 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4418 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
4420 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
4422 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
4424 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
4425 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4426 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4428 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4429 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4430 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
4432 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4433 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4434 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4435 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4437 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4438 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4439 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4441 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
4442 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
4445 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
4446 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
4449 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
4450 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4451 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4452 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4456 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4457 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4461 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4462 static void b43_nphy_save_cal(struct b43_wldev *dev)
4464 struct b43_phy_n *nphy = dev->phy.n;
4466 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4467 u16 *txcal_radio_regs = NULL;
4468 struct b43_chanspec *iqcal_chanspec;
4471 if (nphy->hang_avoid)
4472 b43_nphy_stay_in_carrier_search(dev, 1);
4474 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4475 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4476 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4477 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4478 table = nphy->cal_cache.txcal_coeffs_2G;
4480 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4481 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4482 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4483 table = nphy->cal_cache.txcal_coeffs_5G;
4486 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4487 /* TODO use some definitions */
4488 if (dev->phy.rev >= 3) {
4489 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4490 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4491 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4492 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4493 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4494 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4495 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4496 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4498 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4499 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4500 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4501 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4503 iqcal_chanspec->center_freq = dev->phy.channel_freq;
4504 iqcal_chanspec->channel_type = dev->phy.channel_type;
4505 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
4507 if (nphy->hang_avoid)
4508 b43_nphy_stay_in_carrier_search(dev, 0);
4511 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4512 static void b43_nphy_restore_cal(struct b43_wldev *dev)
4514 struct b43_phy_n *nphy = dev->phy.n;
4521 u16 *txcal_radio_regs = NULL;
4522 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4524 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4525 if (!nphy->iqcal_chanspec_2G.center_freq)
4527 table = nphy->cal_cache.txcal_coeffs_2G;
4528 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4530 if (!nphy->iqcal_chanspec_5G.center_freq)
4532 table = nphy->cal_cache.txcal_coeffs_5G;
4533 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4536 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
4538 for (i = 0; i < 4; i++) {
4539 if (dev->phy.rev >= 3)
4545 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4546 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4547 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
4549 if (dev->phy.rev < 2)
4550 b43_nphy_tx_iq_workaround(dev);
4552 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4553 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4554 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4556 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4557 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4560 /* TODO use some definitions */
4561 if (dev->phy.rev >= 3) {
4562 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4563 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4564 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4565 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4566 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4567 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4568 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4569 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4571 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4572 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4573 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4574 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4576 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4579 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4580 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4581 struct nphy_txgains target,
4582 bool full, bool mphase)
4584 struct b43_phy_n *nphy = dev->phy.n;
4590 u16 tmp, core, type, count, max, numb, last = 0, cmd;
4598 struct nphy_iqcal_params params[2];
4599 bool updated[2] = { };
4601 b43_nphy_stay_in_carrier_search(dev, true);
4603 if (dev->phy.rev >= 4) {
4604 avoid = nphy->hang_avoid;
4605 nphy->hang_avoid = false;
4608 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4610 for (i = 0; i < 2; i++) {
4611 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
4612 gain[i] = params[i].cal_gain;
4615 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
4617 b43_nphy_tx_cal_radio_setup(dev);
4618 b43_nphy_tx_cal_phy_setup(dev);
4620 phy6or5x = dev->phy.rev >= 6 ||
4621 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4622 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4624 if (dev->phy.is_40mhz) {
4625 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4626 tbl_tx_iqlo_cal_loft_ladder_40);
4627 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4628 tbl_tx_iqlo_cal_iqimb_ladder_40);
4630 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4631 tbl_tx_iqlo_cal_loft_ladder_20);
4632 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4633 tbl_tx_iqlo_cal_iqimb_ladder_20);
4637 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4639 if (!dev->phy.is_40mhz)
4644 if (nphy->mphase_cal_phase_id > 2)
4645 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4646 0xFFFF, 0, true, false);
4648 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
4651 if (nphy->mphase_cal_phase_id > 2) {
4652 table = nphy->mphase_txcal_bestcoeffs;
4654 if (dev->phy.rev < 3)
4657 if (!full && nphy->txiqlocal_coeffsvalid) {
4658 table = nphy->txiqlocal_bestc;
4660 if (dev->phy.rev < 3)
4664 if (dev->phy.rev >= 3) {
4665 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4666 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4668 table = tbl_tx_iqlo_cal_startcoefs;
4669 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4674 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
4677 if (dev->phy.rev >= 3)
4678 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4680 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4682 if (dev->phy.rev >= 3)
4683 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4685 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4689 count = nphy->mphase_txcal_cmdidx;
4691 (u16)(count + nphy->mphase_txcal_numcmds));
4697 for (; count < numb; count++) {
4699 if (dev->phy.rev >= 3)
4700 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4702 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4704 if (dev->phy.rev >= 3)
4705 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4707 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4710 core = (cmd & 0x3000) >> 12;
4711 type = (cmd & 0x0F00) >> 8;
4713 if (phy6or5x && updated[core] == 0) {
4714 b43_nphy_update_tx_cal_ladder(dev, core);
4715 updated[core] = true;
4718 tmp = (params[core].ncorr[type] << 8) | 0x66;
4719 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4721 if (type == 1 || type == 3 || type == 4) {
4722 buffer[0] = b43_ntab_read(dev,
4723 B43_NTAB16(15, 69 + core));
4724 diq_start = buffer[0];
4726 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4730 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4731 for (i = 0; i < 2000; i++) {
4732 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4738 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4740 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4743 if (type == 1 || type == 3 || type == 4)
4744 buffer[0] = diq_start;
4748 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4750 last = (dev->phy.rev < 3) ? 6 : 7;
4752 if (!mphase || nphy->mphase_cal_phase_id == last) {
4753 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
4754 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
4755 if (dev->phy.rev < 3) {
4761 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4763 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
4765 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4767 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4770 if (dev->phy.rev < 3)
4772 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4773 nphy->txiqlocal_bestc);
4774 nphy->txiqlocal_coeffsvalid = true;
4775 nphy->txiqlocal_chanspec.center_freq =
4776 dev->phy.channel_freq;
4777 nphy->txiqlocal_chanspec.channel_type =
4778 dev->phy.channel_type;
4781 if (dev->phy.rev < 3)
4783 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4784 nphy->mphase_txcal_bestcoeffs);
4787 b43_nphy_stop_playback(dev);
4788 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4791 b43_nphy_tx_cal_phy_cleanup(dev);
4792 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4794 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4795 b43_nphy_tx_iq_workaround(dev);
4797 if (dev->phy.rev >= 4)
4798 nphy->hang_avoid = avoid;
4800 b43_nphy_stay_in_carrier_search(dev, false);
4805 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4806 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4808 struct b43_phy_n *nphy = dev->phy.n;
4813 if (!nphy->txiqlocal_coeffsvalid ||
4814 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4815 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
4818 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4819 for (i = 0; i < 4; i++) {
4820 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4827 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4828 nphy->txiqlocal_bestc);
4829 for (i = 0; i < 4; i++)
4831 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4833 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4834 &nphy->txiqlocal_bestc[5]);
4835 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4836 &nphy->txiqlocal_bestc[5]);
4840 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4841 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4842 struct nphy_txgains target, u8 type, bool debug)
4844 struct b43_phy_n *nphy = dev->phy.n;
4849 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
4851 enum ieee80211_band band;
4855 u16 lna[3] = { 3, 3, 1 };
4856 u16 hpf1[3] = { 7, 2, 0 };
4857 u16 hpf2[3] = { 2, 0, 0 };
4861 struct nphy_iqcal_params cal_params[2];
4862 struct nphy_iq_est est;
4864 bool playtone = true;
4867 b43_nphy_stay_in_carrier_search(dev, 1);
4869 if (dev->phy.rev < 2)
4870 b43_nphy_reapply_tx_cal_coeffs(dev);
4871 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4872 for (i = 0; i < 2; i++) {
4873 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4874 cal_gain[i] = cal_params[i].cal_gain;
4876 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
4878 for (i = 0; i < 2; i++) {
4880 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4881 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4882 afectl_core = B43_NPHY_AFECTL_C1;
4884 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4885 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4886 afectl_core = B43_NPHY_AFECTL_C2;
4889 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4890 tmp[2] = b43_phy_read(dev, afectl_core);
4891 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4892 tmp[4] = b43_phy_read(dev, rfctl[0]);
4893 tmp[5] = b43_phy_read(dev, rfctl[1]);
4895 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4896 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4897 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4898 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4900 b43_phy_set(dev, afectl_core, 0x0006);
4901 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4903 band = b43_current_band(dev->wl);
4905 if (nphy->rxcalparams & 0xFF000000) {
4906 if (band == IEEE80211_BAND_5GHZ)
4907 b43_phy_write(dev, rfctl[0], 0x140);
4909 b43_phy_write(dev, rfctl[0], 0x110);
4911 if (band == IEEE80211_BAND_5GHZ)
4912 b43_phy_write(dev, rfctl[0], 0x180);
4914 b43_phy_write(dev, rfctl[0], 0x120);
4917 if (band == IEEE80211_BAND_5GHZ)
4918 b43_phy_write(dev, rfctl[1], 0x148);
4920 b43_phy_write(dev, rfctl[1], 0x114);
4922 if (nphy->rxcalparams & 0x10000) {
4923 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4925 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4929 for (j = 0; j < 4; j++) {
4935 if (power[1] > 10000) {
4940 if (power[0] > 10000) {
4950 cur_lna = lna[index];
4951 cur_hpf1 = hpf1[index];
4952 cur_hpf2 = hpf2[index];
4953 cur_hpf += desired - hweight32(power[index]);
4954 cur_hpf = clamp_val(cur_hpf, 0, 10);
4961 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4963 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
4965 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4966 b43_nphy_stop_playback(dev);
4969 ret = b43_nphy_tx_tone(dev, 4000,
4970 (nphy->rxcalparams & 0xFFFF),
4974 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4980 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4989 power[i] = ((real + imag) / 1024) + 1;
4991 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4993 b43_nphy_stop_playback(dev);
5000 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5001 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5002 b43_phy_write(dev, rfctl[1], tmp[5]);
5003 b43_phy_write(dev, rfctl[0], tmp[4]);
5004 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5005 b43_phy_write(dev, afectl_core, tmp[2]);
5006 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5012 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
5013 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5014 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
5016 b43_nphy_stay_in_carrier_search(dev, 0);
5021 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5022 struct nphy_txgains target, u8 type, bool debug)
5027 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5028 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5029 struct nphy_txgains target, u8 type, bool debug)
5031 if (dev->phy.rev >= 3)
5032 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5034 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5037 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5038 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5040 struct b43_phy *phy = &dev->phy;
5041 struct b43_phy_n *nphy = phy->n;
5042 /* u16 buf[16]; it's rev3+ */
5044 nphy->phyrxchain = mask;
5046 if (0 /* FIXME clk */)
5049 b43_mac_suspend(dev);
5051 if (nphy->hang_avoid)
5052 b43_nphy_stay_in_carrier_search(dev, true);
5054 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5055 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5057 if ((mask & 0x3) != 0x3) {
5058 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5059 if (dev->phy.rev >= 3) {
5063 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5064 if (dev->phy.rev >= 3) {
5069 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5071 if (nphy->hang_avoid)
5072 b43_nphy_stay_in_carrier_search(dev, false);
5074 b43_mac_enable(dev);
5077 /**************************************************
5079 **************************************************/
5081 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5082 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5084 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5086 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5088 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5090 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5092 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5095 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5096 static void b43_nphy_bphy_init(struct b43_wldev *dev)
5102 for (i = 0; i < 16; i++) {
5103 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5107 for (i = 0; i < 16; i++) {
5108 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5111 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5114 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5115 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5117 if (dev->phy.rev >= 3) {
5120 if (0 /* FIXME */) {
5121 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5122 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5123 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5124 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5127 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5128 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5130 switch (dev->dev->bus_type) {
5131 #ifdef CONFIG_B43_BCMA
5133 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5137 #ifdef CONFIG_B43_SSB
5139 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5145 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5146 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5147 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5151 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5152 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5153 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5154 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5159 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
5160 static int b43_phy_initn(struct b43_wldev *dev)
5162 struct ssb_sprom *sprom = dev->dev->bus_sprom;
5163 struct b43_phy *phy = &dev->phy;
5164 struct b43_phy_n *nphy = phy->n;
5166 struct nphy_txgains target;
5168 enum ieee80211_band tmp2;
5172 bool do_cal = false;
5174 if ((dev->phy.rev >= 3) &&
5175 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
5176 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
5177 switch (dev->dev->bus_type) {
5178 #ifdef CONFIG_B43_BCMA
5180 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5181 BCMA_CC_CHIPCTL, 0x40);
5184 #ifdef CONFIG_B43_SSB
5186 chipco_set32(&dev->dev->sdev->bus->chipco,
5187 SSB_CHIPCO_CHIPCTL, 0x40);
5192 nphy->deaf_count = 0;
5193 b43_nphy_tables_init(dev);
5194 nphy->crsminpwr_adjusted = false;
5195 nphy->noisevars_adjusted = false;
5197 /* Clear all overrides */
5198 if (dev->phy.rev >= 3) {
5199 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5200 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5201 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5202 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5204 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5206 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5207 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
5208 if (dev->phy.rev < 6) {
5209 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5210 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5212 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5213 ~(B43_NPHY_RFSEQMODE_CAOVER |
5214 B43_NPHY_RFSEQMODE_TROVER));
5215 if (dev->phy.rev >= 3)
5216 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
5217 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5219 if (dev->phy.rev <= 2) {
5220 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5221 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5222 ~B43_NPHY_BPHY_CTL3_SCALE,
5223 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5225 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5226 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5228 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
5229 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5230 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
5231 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5233 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5234 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5235 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5236 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
5238 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
5239 b43_nphy_update_txrx_chain(dev);
5242 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5243 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5246 tmp2 = b43_current_band(dev->wl);
5247 if (b43_nphy_ipa(dev)) {
5248 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5249 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5250 nphy->papd_epsilon_offset[0] << 7);
5251 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5252 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5253 nphy->papd_epsilon_offset[1] << 7);
5254 b43_nphy_int_pa_set_tx_dig_filters(dev);
5255 } else if (phy->rev >= 5) {
5256 b43_nphy_ext_pa_set_tx_dig_filters(dev);
5259 b43_nphy_workarounds(dev);
5261 /* Reset CCA, in init code it differs a little from standard way */
5262 b43_phy_force_clock(dev, 1);
5263 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5264 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5265 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
5266 b43_phy_force_clock(dev, 0);
5268 b43_mac_phy_clock_set(dev, true);
5270 b43_nphy_pa_override(dev, false);
5271 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5272 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5273 b43_nphy_pa_override(dev, true);
5275 b43_nphy_classifier(dev, 0, 0);
5276 b43_nphy_read_clip_detection(dev, clip);
5277 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5278 b43_nphy_bphy_init(dev);
5280 tx_pwr_state = nphy->txpwrctrl;
5281 b43_nphy_tx_power_ctrl(dev, false);
5282 b43_nphy_tx_power_fix(dev);
5283 b43_nphy_tx_power_ctl_idle_tssi(dev);
5284 b43_nphy_tx_power_ctl_setup(dev);
5285 b43_nphy_tx_gain_table_upload(dev);
5287 if (nphy->phyrxchain != 3)
5288 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
5289 if (nphy->mphase_cal_phase_id > 0)
5290 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5292 do_rssi_cal = false;
5293 if (phy->rev >= 3) {
5294 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5295 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
5297 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
5300 b43_nphy_rssi_cal(dev);
5302 b43_nphy_restore_rssi_cal(dev);
5304 b43_nphy_rssi_cal(dev);
5307 if (!((nphy->measure_hold & 0x6) != 0)) {
5308 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5309 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
5311 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
5317 target = b43_nphy_get_tx_gains(dev);
5319 if (nphy->antsel_type == 2)
5320 b43_nphy_superswitch_init(dev, true);
5321 if (nphy->perical != 2) {
5322 b43_nphy_rssi_cal(dev);
5323 if (phy->rev >= 3) {
5324 nphy->cal_orig_pwr_idx[0] =
5325 nphy->txpwrindex[0].index_internal;
5326 nphy->cal_orig_pwr_idx[1] =
5327 nphy->txpwrindex[1].index_internal;
5328 /* TODO N PHY Pre Calibrate TX Gain */
5329 target = b43_nphy_get_tx_gains(dev);
5331 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5332 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5333 b43_nphy_save_cal(dev);
5334 } else if (nphy->mphase_cal_phase_id == 0)
5335 ;/* N PHY Periodic Calibration with arg 3 */
5337 b43_nphy_restore_cal(dev);
5341 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
5342 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
5343 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5344 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5345 if (phy->rev >= 3 && phy->rev <= 6)
5346 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
5347 b43_nphy_tx_lp_fbw(dev);
5349 b43_nphy_spur_workaround(dev);
5354 /**************************************************
5355 * Channel switching ops.
5356 **************************************************/
5358 static void b43_chantab_phy_upload(struct b43_wldev *dev,
5359 const struct b43_phy_n_sfo_cfg *e)
5361 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5362 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5363 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5364 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5365 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5366 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5369 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5370 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5372 switch (dev->dev->bus_type) {
5373 #ifdef CONFIG_B43_BCMA
5375 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5379 #ifdef CONFIG_B43_SSB
5381 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5388 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
5389 static void b43_nphy_channel_setup(struct b43_wldev *dev,
5390 const struct b43_phy_n_sfo_cfg *e,
5391 struct ieee80211_channel *new_channel)
5393 struct b43_phy *phy = &dev->phy;
5394 struct b43_phy_n *nphy = dev->phy.n;
5395 int ch = new_channel->hw_value;
5401 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5402 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
5403 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5404 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
5405 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5406 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
5407 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
5408 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
5409 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5410 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5411 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
5412 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
5413 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
5416 b43_chantab_phy_upload(dev, e);
5418 if (new_channel->hw_value == 14) {
5419 b43_nphy_classifier(dev, 2, 0);
5420 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5422 b43_nphy_classifier(dev, 2, 2);
5423 if (new_channel->band == IEEE80211_BAND_2GHZ)
5424 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5427 if (!nphy->txpwrctrl)
5428 b43_nphy_tx_power_fix(dev);
5430 if (dev->phy.rev < 3)
5431 b43_nphy_adjust_lna_gain_table(dev);
5433 b43_nphy_tx_lp_fbw(dev);
5435 if (dev->phy.rev >= 3 &&
5436 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5438 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5440 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5441 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5443 } else { /* 40MHz */
5444 if (nphy->aband_spurwar_en &&
5445 (ch == 38 || ch == 102 || ch == 118))
5446 avoid = dev->dev->chip_id == 0x4716;
5449 b43_nphy_pmu_spur_avoid(dev, avoid);
5451 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5452 dev->dev->chip_id == 43225) {
5453 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5454 avoid ? 0x5341 : 0x8889);
5455 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5458 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5459 ; /* TODO: reset PLL */
5462 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5464 b43_phy_mask(dev, B43_NPHY_BBCFG,
5465 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5467 b43_nphy_reset_cca(dev);
5469 /* wl sets useless phy_isspuravoid here */
5472 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5475 b43_nphy_spur_workaround(dev);
5478 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
5479 static int b43_nphy_set_channel(struct b43_wldev *dev,
5480 struct ieee80211_channel *channel,
5481 enum nl80211_channel_type channel_type)
5483 struct b43_phy *phy = &dev->phy;
5485 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5486 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
5490 if (dev->phy.rev >= 3) {
5491 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5492 channel->center_freq);
5496 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5502 /* Channel is set later in common code, but we need to set it on our
5503 own to let this function's subcalls work properly. */
5504 phy->channel = channel->hw_value;
5505 phy->channel_freq = channel->center_freq;
5507 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5508 b43_channel_type_is_40mhz(channel_type))
5509 ; /* TODO: BMAC BW Set (channel_type) */
5511 if (channel_type == NL80211_CHAN_HT40PLUS)
5512 b43_phy_set(dev, B43_NPHY_RXCTL,
5513 B43_NPHY_RXCTL_BSELU20);
5514 else if (channel_type == NL80211_CHAN_HT40MINUS)
5515 b43_phy_mask(dev, B43_NPHY_RXCTL,
5516 ~B43_NPHY_RXCTL_BSELU20);
5518 if (dev->phy.rev >= 3) {
5519 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
5520 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
5521 b43_radio_2056_setup(dev, tabent_r3);
5522 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
5524 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
5525 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
5526 b43_radio_2055_setup(dev, tabent_r2);
5527 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
5533 /**************************************************
5535 **************************************************/
5537 static int b43_nphy_op_allocate(struct b43_wldev *dev)
5539 struct b43_phy_n *nphy;
5541 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5549 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
5551 struct b43_phy *phy = &dev->phy;
5552 struct b43_phy_n *nphy = phy->n;
5553 struct ssb_sprom *sprom = dev->dev->bus_sprom;
5555 memset(nphy, 0, sizeof(*nphy));
5557 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
5558 nphy->spur_avoid = (phy->rev >= 3) ?
5559 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
5560 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5561 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5562 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
5563 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
5564 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5565 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5566 nphy->tx_pwr_idx[0] = 128;
5567 nphy->tx_pwr_idx[1] = 128;
5569 /* Hardware TX power control and 5GHz power gain */
5570 nphy->txpwrctrl = false;
5571 nphy->pwg_gain_5ghz = false;
5572 if (dev->phy.rev >= 3 ||
5573 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5574 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5575 nphy->txpwrctrl = true;
5576 nphy->pwg_gain_5ghz = true;
5577 } else if (sprom->revision >= 4) {
5578 if (dev->phy.rev >= 2 &&
5579 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5580 nphy->txpwrctrl = true;
5581 #ifdef CONFIG_B43_SSB
5582 if (dev->dev->bus_type == B43_BUS_SSB &&
5583 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5584 struct pci_dev *pdev =
5585 dev->dev->sdev->bus->host_pci;
5586 if (pdev->device == 0x4328 ||
5587 pdev->device == 0x432a)
5588 nphy->pwg_gain_5ghz = true;
5591 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5592 nphy->pwg_gain_5ghz = true;
5596 if (dev->phy.rev >= 3) {
5597 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5598 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5602 static void b43_nphy_op_free(struct b43_wldev *dev)
5604 struct b43_phy *phy = &dev->phy;
5605 struct b43_phy_n *nphy = phy->n;
5611 static int b43_nphy_op_init(struct b43_wldev *dev)
5613 return b43_phy_initn(dev);
5616 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5619 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5620 /* OFDM registers are onnly available on A/G-PHYs */
5621 b43err(dev->wl, "Invalid OFDM PHY access at "
5622 "0x%04X on N-PHY\n", offset);
5625 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5626 /* Ext-G registers are only available on G-PHYs */
5627 b43err(dev->wl, "Invalid EXT-G PHY access at "
5628 "0x%04X on N-PHY\n", offset);
5631 #endif /* B43_DEBUG */
5634 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5636 check_phyreg(dev, reg);
5637 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5638 return b43_read16(dev, B43_MMIO_PHY_DATA);
5641 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5643 check_phyreg(dev, reg);
5644 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5645 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5648 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5651 check_phyreg(dev, reg);
5652 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5653 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
5656 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5658 /* Register 1 is a 32-bit register. */
5659 B43_WARN_ON(reg == 1);
5661 if (dev->phy.rev >= 7)
5662 reg |= 0x200; /* Radio 0x2057 */
5666 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5667 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5670 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5672 /* Register 1 is a 32-bit register. */
5673 B43_WARN_ON(reg == 1);
5675 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5676 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5679 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
5680 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
5683 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5684 b43err(dev->wl, "MAC not suspended\n");
5687 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5688 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
5689 if (dev->phy.rev >= 7) {
5691 } else if (dev->phy.rev >= 3) {
5692 b43_radio_mask(dev, 0x09, ~0x2);
5694 b43_radio_write(dev, 0x204D, 0);
5695 b43_radio_write(dev, 0x2053, 0);
5696 b43_radio_write(dev, 0x2058, 0);
5697 b43_radio_write(dev, 0x205E, 0);
5698 b43_radio_mask(dev, 0x2062, ~0xF0);
5699 b43_radio_write(dev, 0x2064, 0);
5701 b43_radio_write(dev, 0x304D, 0);
5702 b43_radio_write(dev, 0x3053, 0);
5703 b43_radio_write(dev, 0x3058, 0);
5704 b43_radio_write(dev, 0x305E, 0);
5705 b43_radio_mask(dev, 0x3062, ~0xF0);
5706 b43_radio_write(dev, 0x3064, 0);
5709 if (dev->phy.rev >= 7) {
5710 b43_radio_2057_init(dev);
5711 b43_switch_channel(dev, dev->phy.channel);
5712 } else if (dev->phy.rev >= 3) {
5713 b43_radio_init2056(dev);
5714 b43_switch_channel(dev, dev->phy.channel);
5716 b43_radio_init2055(dev);
5721 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
5722 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5724 u16 override = on ? 0x0 : 0x7FFF;
5725 u16 core = on ? 0xD : 0x00FD;
5727 if (dev->phy.rev >= 3) {
5729 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5730 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5731 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5732 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5734 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5735 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5736 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5737 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5740 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5744 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5745 unsigned int new_channel)
5747 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5748 enum nl80211_channel_type channel_type =
5749 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5751 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5752 if ((new_channel < 1) || (new_channel > 14))
5755 if (new_channel > 200)
5759 return b43_nphy_set_channel(dev, channel, channel_type);
5762 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5764 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5769 const struct b43_phy_operations b43_phyops_n = {
5770 .allocate = b43_nphy_op_allocate,
5771 .free = b43_nphy_op_free,
5772 .prepare_structs = b43_nphy_op_prepare_structs,
5773 .init = b43_nphy_op_init,
5774 .phy_read = b43_nphy_op_read,
5775 .phy_write = b43_nphy_op_write,
5776 .phy_maskset = b43_nphy_op_maskset,
5777 .radio_read = b43_nphy_op_radio_read,
5778 .radio_write = b43_nphy_op_radio_write,
5779 .software_rfkill = b43_nphy_op_software_rfkill,
5780 .switch_analog = b43_nphy_op_switch_analog,
5781 .switch_channel = b43_nphy_op_switch_channel,
5782 .get_default_chan = b43_nphy_op_get_default_chan,
5783 .recalc_txpower = b43_nphy_op_recalc_txpower,
5784 .adjust_txpower = b43_nphy_op_adjust_txpower,