drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "main.h"
  36
  37 struct nphy_txgains {
  38         u16 txgm[2];
  39         u16 pga[2];
  40         u16 pad[2];
  41         u16 ipa[2];
  42 };
  43
  44 struct nphy_iqcal_params {
  45         u16 txgm;
  46         u16 pga;
  47         u16 pad;
  48         u16 ipa;
  49         u16 cal_gain;
  50         u16 ncorr[5];
  51 };
  52
  53 struct nphy_iq_est {
  54         s32 iq0_prod;
  55         u32 i0_pwr;
  56         u32 q0_pwr;
  57         s32 iq1_prod;
  58         u32 i1_pwr;
  59         u32 q1_pwr;
  60 };
  61
  62 enum b43_nphy_rf_sequence {
  63         B43_RFSEQ_RX2TX,
  64         B43_RFSEQ_TX2RX,
  65         B43_RFSEQ_RESET2RX,
  66         B43_RFSEQ_UPDATE_GAINH,
  67         B43_RFSEQ_UPDATE_GAINL,
  68         B43_RFSEQ_UPDATE_GAINU,
  69 };
  70
  71 enum b43_nphy_rssi_type {
  72         B43_NPHY_RSSI_X = 0,
  73         B43_NPHY_RSSI_Y,
  74         B43_NPHY_RSSI_Z,
  75         B43_NPHY_RSSI_PWRDET,
  76         B43_NPHY_RSSI_TSSI_I,
  77         B43_NPHY_RSSI_TSSI_Q,
  78         B43_NPHY_RSSI_TBD,
  79 };
  80
  81 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
  82                                                 bool enable);
  83 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  84                                         u8 *events, u8 *delays, u8 length);
  85 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  86                                        enum b43_nphy_rf_sequence seq);
  87 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  88                                                 u16 value, u8 core, bool off);
  89 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  90                                                 u16 value, u8 core);
  91
  92 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  93 {//TODO
  94 }
  95
  96 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  97 {//TODO
  98 }
  99
 100 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
 101                                                         bool ignore_tssi)
 102 {//TODO
 103         return B43_TXPWR_RES_DONE;
 104 }
 105
 106 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 107                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 108 {
 109         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 110         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 111         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 112         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 113         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 114
 115         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 116         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 117         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 118         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 119         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 120
 121         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 122         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 123         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 124         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 125         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 126
 127         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 128         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 129         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 130         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 131         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 132
 133         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 134         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 135         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 136         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 137         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 138
 139         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 140         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 141 }
 142
 143 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 144                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 145 {
 146         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 147         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 148         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 149         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 150         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 151         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 152                                         e->radio_syn_pll_loopfilter1);
 153         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 154                                         e->radio_syn_pll_loopfilter2);
 155         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 156                                         e->radio_syn_pll_loopfilter3);
 157         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 158                                         e->radio_syn_pll_loopfilter4);
 159         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 160                                         e->radio_syn_pll_loopfilter5);
 161         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 162                                         e->radio_syn_reserved_addr27);
 163         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 164                                         e->radio_syn_reserved_addr28);
 165         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 166                                         e->radio_syn_reserved_addr29);
 167         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 168                                         e->radio_syn_logen_vcobuf1);
 169         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 170         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 171         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 172
 173         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 174                                         e->radio_rx0_lnaa_tune);
 175         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 176                                         e->radio_rx0_lnag_tune);
 177
 178         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 179                                         e->radio_tx0_intpaa_boost_tune);
 180         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 181                                         e->radio_tx0_intpag_boost_tune);
 182         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 183                                         e->radio_tx0_pada_boost_tune);
 184         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 185                                         e->radio_tx0_padg_boost_tune);
 186         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 187                                         e->radio_tx0_pgaa_boost_tune);
 188         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 189                                         e->radio_tx0_pgag_boost_tune);
 190         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 191                                         e->radio_tx0_mixa_boost_tune);
 192         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 193                                         e->radio_tx0_mixg_boost_tune);
 194
 195         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 196                                         e->radio_rx1_lnaa_tune);
 197         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 198                                         e->radio_rx1_lnag_tune);
 199
 200         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 201                                         e->radio_tx1_intpaa_boost_tune);
 202         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 203                                         e->radio_tx1_intpag_boost_tune);
 204         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 205                                         e->radio_tx1_pada_boost_tune);
 206         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 207                                         e->radio_tx1_padg_boost_tune);
 208         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 209                                         e->radio_tx1_pgaa_boost_tune);
 210         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 211                                         e->radio_tx1_pgag_boost_tune);
 212         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 213                                         e->radio_tx1_mixa_boost_tune);
 214         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 215                                         e->radio_tx1_mixg_boost_tune);
 216 }
 217
 218 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 219 static void b43_radio_2056_setup(struct b43_wldev *dev,
 220                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 221 {
 222         B43_WARN_ON(dev->phy.rev < 3);
 223
 224         b43_chantab_radio_2056_upload(dev, e);
 225         /* TODO */
 226         udelay(50);
 227         /* VCO calibration */
 228         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 229         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 230         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 231         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 232         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 233         udelay(300);
 234 }
 235
 236 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 237                                    const struct b43_phy_n_sfo_cfg *e)
 238 {
 239         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 240         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 241         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 242         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 243         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 244         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 245 }
 246
 247 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
 248 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
 249 {
 250         struct b43_phy_n *nphy = dev->phy.n;
 251         u8 i;
 252         u16 bmask, val, tmp;
 253         enum ieee80211_band band = b43_current_band(dev->wl);
 254
 255         if (nphy->hang_avoid)
 256                 b43_nphy_stay_in_carrier_search(dev, 1);
 257
 258         nphy->txpwrctrl = enable;
 259         if (!enable) {
 260                 if (dev->phy.rev >= 3 &&
 261                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
 262                      (B43_NPHY_TXPCTL_CMD_COEFF |
 263                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
 264                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
 265                         /* We disable enabled TX pwr ctl, save it's state */
 266                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
 267                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
 268                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
 269                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
 270                 }
 271
 272                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
 273                 for (i = 0; i < 84; i++)
 274                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 275
 276                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
 277                 for (i = 0; i < 84; i++)
 278                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 279
 280                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 281                 if (dev->phy.rev >= 3)
 282                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 283                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
 284
 285                 if (dev->phy.rev >= 3) {
 286                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 287                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 288                 } else {
 289                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 290                 }
 291
 292                 if (dev->phy.rev == 2)
 293                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 294                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
 295                 else if (dev->phy.rev < 2)
 296                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 297                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
 298
 299                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
 300                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
 301         } else {
 302                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
 303                                     nphy->adj_pwr_tbl);
 304                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
 305                                     nphy->adj_pwr_tbl);
 306
 307                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
 308                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 309                 /* wl does useless check for "enable" param here */
 310                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 311                 if (dev->phy.rev >= 3) {
 312                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 313                         if (val)
 314                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 315                 }
 316                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
 317
 318                 if (band == IEEE80211_BAND_5GHZ) {
 319                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
 320                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
 321                         if (dev->phy.rev > 1)
 322                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
 323                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
 324                                                 0x64);
 325                 }
 326
 327                 if (dev->phy.rev >= 3) {
 328                         if (nphy->tx_pwr_idx[0] != 128 &&
 329                             nphy->tx_pwr_idx[1] != 128) {
 330                                 /* Recover TX pwr ctl state */
 331                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
 332                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
 333                                                 nphy->tx_pwr_idx[0]);
 334                                 if (dev->phy.rev > 1)
 335                                         b43_phy_maskset(dev,
 336                                                 B43_NPHY_TXPCTL_INIT,
 337                                                 ~0xff, nphy->tx_pwr_idx[1]);
 338                         }
 339                 }
 340
 341                 if (dev->phy.rev >= 3) {
 342                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
 343                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
 344                 } else {
 345                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
 346                 }
 347
 348                 if (dev->phy.rev == 2)
 349                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
 350                 else if (dev->phy.rev < 2)
 351                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
 352
 353                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
 354                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
 355
 356                 if ((nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 357                     (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ)) {
 358                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
 359                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
 360                 }
 361         }
 362
 363         if (nphy->hang_avoid)
 364                 b43_nphy_stay_in_carrier_search(dev, 0);
 365 }
 366
 367 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
 368 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 369 {
 370         struct b43_phy_n *nphy = dev->phy.n;
 371         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 372
 373         u8 txpi[2], bbmult, i;
 374         u16 tmp, radio_gain, dac_gain;
 375         u16 freq = dev->phy.channel_freq;
 376         u32 txgain;
 377         /* u32 gaintbl; rev3+ */
 378
 379         if (nphy->hang_avoid)
 380                 b43_nphy_stay_in_carrier_search(dev, 1);
 381
 382         if (dev->phy.rev >= 3) {
 383                 txpi[0] = 40;
 384                 txpi[1] = 40;
 385         } else if (sprom->revision < 4) {
 386                 txpi[0] = 72;
 387                 txpi[1] = 72;
 388         } else {
 389                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 390                         txpi[0] = sprom->txpid2g[0];
 391                         txpi[1] = sprom->txpid2g[1];
 392                 } else if (freq >= 4900 && freq < 5100) {
 393                         txpi[0] = sprom->txpid5gl[0];
 394                         txpi[1] = sprom->txpid5gl[1];
 395                 } else if (freq >= 5100 && freq < 5500) {
 396                         txpi[0] = sprom->txpid5g[0];
 397                         txpi[1] = sprom->txpid5g[1];
 398                 } else if (freq >= 5500) {
 399                         txpi[0] = sprom->txpid5gh[0];
 400                         txpi[1] = sprom->txpid5gh[1];
 401                 } else {
 402                         txpi[0] = 91;
 403                         txpi[1] = 91;
 404                 }
 405         }
 406
 407         /*
 408         for (i = 0; i < 2; i++) {
 409                 nphy->txpwrindex[i].index_internal = txpi[i];
 410                 nphy->txpwrindex[i].index_internal_save = txpi[i];
 411         }
 412         */
 413
 414         for (i = 0; i < 2; i++) {
 415                 if (dev->phy.rev >= 3) {
 416                         /* FIXME: support 5GHz */
 417                         txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
 418                         radio_gain = (txgain >> 16) & 0x1FFFF;
 419                 } else {
 420                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
 421                         radio_gain = (txgain >> 16) & 0x1FFF;
 422                 }
 423
 424                 dac_gain = (txgain >> 8) & 0x3F;
 425                 bbmult = txgain & 0xFF;
 426
 427                 if (dev->phy.rev >= 3) {
 428                         if (i == 0)
 429                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 430                         else
 431                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 432                 } else {
 433                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 434                 }
 435
 436                 if (i == 0)
 437                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
 438                 else
 439                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
 440
 441                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
 442                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
 443
 444                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 445                 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 446
 447                 if (i == 0)
 448                         tmp = (tmp & 0x00FF) | (bbmult << 8);
 449                 else
 450                         tmp = (tmp & 0xFF00) | bbmult;
 451
 452                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 453                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
 454
 455                 if (0)
 456                         ; /* TODO */
 457         }
 458
 459         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
 460
 461         if (nphy->hang_avoid)
 462                 b43_nphy_stay_in_carrier_search(dev, 0);
 463 }
 464
 465
 466 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 467 static void b43_radio_2055_setup(struct b43_wldev *dev,
 468                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 469 {
 470         B43_WARN_ON(dev->phy.rev >= 3);
 471
 472         b43_chantab_radio_upload(dev, e);
 473         udelay(50);
 474         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 475         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 476         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 477         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 478         udelay(300);
 479 }
 480
 481 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 482 {
 483         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 484                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 485         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 486                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 487                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 488         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 489                     B43_NPHY_RFCTL_CMD_PORFORCE);
 490 }
 491
 492 static void b43_radio_init2055_post(struct b43_wldev *dev)
 493 {
 494         struct b43_phy_n *nphy = dev->phy.n;
 495         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 496         int i;
 497         u16 val;
 498         bool workaround = false;
 499
 500         if (sprom->revision < 4)
 501                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
 502                               && dev->dev->board_type == 0x46D
 503                               && dev->dev->board_rev >= 0x41);
 504         else
 505                 workaround =
 506                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 507
 508         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 509         if (workaround) {
 510                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 511                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 512         }
 513         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 514         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 515         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 516         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 517         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 518         msleep(1);
 519         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 520         for (i = 0; i < 200; i++) {
 521                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 522                 if (val & 0x80) {
 523                         i = 0;
 524                         break;
 525                 }
 526                 udelay(10);
 527         }
 528         if (i)
 529                 b43err(dev->wl, "radio post init timeout\n");
 530         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 531         b43_switch_channel(dev, dev->phy.channel);
 532         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 533         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 534         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 535         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 536         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 537         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 538         if (!nphy->gain_boost) {
 539                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 540                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 541         } else {
 542                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 543                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 544         }
 545         udelay(2);
 546 }
 547
 548 /*
 549  * Initialize a Broadcom 2055 N-radio
 550  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 551  */
 552 static void b43_radio_init2055(struct b43_wldev *dev)
 553 {
 554         b43_radio_init2055_pre(dev);
 555         if (b43_status(dev) < B43_STAT_INITIALIZED) {
 556                 /* Follow wl, not specs. Do not force uploading all regs */
 557                 b2055_upload_inittab(dev, 0, 0);
 558         } else {
 559                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 560                 b2055_upload_inittab(dev, ghz5, 0);
 561         }
 562         b43_radio_init2055_post(dev);
 563 }
 564
 565 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 566 {
 567         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 568                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 569         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 570         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 571                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 572         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 573                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 574         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 575                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 576 }
 577
 578 static void b43_radio_init2056_post(struct b43_wldev *dev)
 579 {
 580         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 581         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 582         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 583         msleep(1);
 584         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 585         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 586         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 587         /*
 588         if (nphy->init_por)
 589                 Call Radio 2056 Recalibrate
 590         */
 591 }
 592
 593 /*
 594  * Initialize a Broadcom 2056 N-radio
 595  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 596  */
 597 static void b43_radio_init2056(struct b43_wldev *dev)
 598 {
 599         b43_radio_init2056_pre(dev);
 600         b2056_upload_inittabs(dev, 0, 0);
 601         b43_radio_init2056_post(dev);
 602 }
 603
 604 /*
 605  * Upload the N-PHY tables.
 606  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 607  */
 608 static void b43_nphy_tables_init(struct b43_wldev *dev)
 609 {
 610         if (dev->phy.rev < 3)
 611                 b43_nphy_rev0_1_2_tables_init(dev);
 612         else
 613                 b43_nphy_rev3plus_tables_init(dev);
 614 }
 615
 616 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 617 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 618 {
 619         struct b43_phy_n *nphy = dev->phy.n;
 620         enum ieee80211_band band;
 621         u16 tmp;
 622
 623         if (!enable) {
 624                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 625                                                        B43_NPHY_RFCTL_INTC1);
 626                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 627                                                        B43_NPHY_RFCTL_INTC2);
 628                 band = b43_current_band(dev->wl);
 629                 if (dev->phy.rev >= 3) {
 630                         if (band == IEEE80211_BAND_5GHZ)
 631                                 tmp = 0x600;
 632                         else
 633                                 tmp = 0x480;
 634                 } else {
 635                         if (band == IEEE80211_BAND_5GHZ)
 636                                 tmp = 0x180;
 637                         else
 638                                 tmp = 0x120;
 639                 }
 640                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 641                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 642         } else {
 643                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 644                                 nphy->rfctrl_intc1_save);
 645                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 646                                 nphy->rfctrl_intc2_save);
 647         }
 648 }
 649
 650 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 651 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 652 {
 653         struct b43_phy_n *nphy = dev->phy.n;
 654         u16 tmp;
 655         enum ieee80211_band band = b43_current_band(dev->wl);
 656         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 657                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 658
 659         if (dev->phy.rev >= 3) {
 660                 if (ipa) {
 661                         tmp = 4;
 662                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 663                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 664                 }
 665
 666                 tmp = 1;
 667                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 668                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 669         }
 670 }
 671
 672 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 673 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 674 {
 675         u16 bbcfg;
 676
 677         b43_phy_force_clock(dev, 1);
 678         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 679         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 680         udelay(1);
 681         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 682         b43_phy_force_clock(dev, 0);
 683         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 684 }
 685
 686 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 687 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 688 {
 689         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 690
 691         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 692         if (preamble == 1)
 693                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 694         else
 695                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 696
 697         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 698 }
 699
 700 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 701 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 702 {
 703         struct b43_phy_n *nphy = dev->phy.n;
 704
 705         bool override = false;
 706         u16 chain = 0x33;
 707
 708         if (nphy->txrx_chain == 0) {
 709                 chain = 0x11;
 710                 override = true;
 711         } else if (nphy->txrx_chain == 1) {
 712                 chain = 0x22;
 713                 override = true;
 714         }
 715
 716         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 717                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 718                         chain);
 719
 720         if (override)
 721                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 722                                 B43_NPHY_RFSEQMODE_CAOVER);
 723         else
 724                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 725                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 726 }
 727
 728 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 729 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 730                                 u16 samps, u8 time, bool wait)
 731 {
 732         int i;
 733         u16 tmp;
 734
 735         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 736         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 737         if (wait)
 738                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 739         else
 740                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 741
 742         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 743
 744         for (i = 1000; i; i--) {
 745                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 746                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 747                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 748                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 749                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 750                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 751                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 752                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 753
 754                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 755                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 756                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 757                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 758                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 759                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 760                         return;
 761                 }
 762                 udelay(10);
 763         }
 764         memset(est, 0, sizeof(*est));
 765 }
 766
 767 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 768 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 769                                         struct b43_phy_n_iq_comp *pcomp)
 770 {
 771         if (write) {
 772                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 773                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 774                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 775                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 776         } else {
 777                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 778                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 779                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 780                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 781         }
 782 }
 783
 784 #if 0
 785 /* Ready but not used anywhere */
 786 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 787 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 788 {
 789         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 790
 791         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 792         if (core == 0) {
 793                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 794                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 795         } else {
 796                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 797                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 798         }
 799         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 800         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 801         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 802         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 803         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 804         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 805         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 806         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 807 }
 808
 809 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 810 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 811 {
 812         u8 rxval, txval;
 813         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 814
 815         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 816         if (core == 0) {
 817                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 818                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 819         } else {
 820                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 821                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 822         }
 823         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 824         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 825         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 826         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 827         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 828         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 829         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 830         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 831
 832         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 833         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 834
 835         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 836                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
 837                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 838         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 839                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 840         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 841                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 842         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 843                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 844
 845         if (core == 0) {
 846                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 847                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 848         } else {
 849                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 850                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 851         }
 852
 853         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 854         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 855         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 856
 857         if (core == 0) {
 858                 rxval = 1;
 859                 txval = 8;
 860         } else {
 861                 rxval = 4;
 862                 txval = 2;
 863         }
 864         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 865         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 866 }
 867 #endif
 868
 869 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 870 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 871 {
 872         int i;
 873         s32 iq;
 874         u32 ii;
 875         u32 qq;
 876         int iq_nbits, qq_nbits;
 877         int arsh, brsh;
 878         u16 tmp, a, b;
 879
 880         struct nphy_iq_est est;
 881         struct b43_phy_n_iq_comp old;
 882         struct b43_phy_n_iq_comp new = { };
 883         bool error = false;
 884
 885         if (mask == 0)
 886                 return;
 887
 888         b43_nphy_rx_iq_coeffs(dev, false, &old);
 889         b43_nphy_rx_iq_coeffs(dev, true, &new);
 890         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 891         new = old;
 892
 893         for (i = 0; i < 2; i++) {
 894                 if (i == 0 && (mask & 1)) {
 895                         iq = est.iq0_prod;
 896                         ii = est.i0_pwr;
 897                         qq = est.q0_pwr;
 898                 } else if (i == 1 && (mask & 2)) {
 899                         iq = est.iq1_prod;
 900                         ii = est.i1_pwr;
 901                         qq = est.q1_pwr;
 902                 } else {
 903                         continue;
 904                 }
 905
 906                 if (ii + qq < 2) {
 907                         error = true;
 908                         break;
 909                 }
 910
 911                 iq_nbits = fls(abs(iq));
 912                 qq_nbits = fls(qq);
 913
 914                 arsh = iq_nbits - 20;
 915                 if (arsh >= 0) {
 916                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 917                         tmp = ii >> arsh;
 918                 } else {
 919                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 920                         tmp = ii << -arsh;
 921                 }
 922                 if (tmp == 0) {
 923                         error = true;
 924                         break;
 925                 }
 926                 a /= tmp;
 927
 928                 brsh = qq_nbits - 11;
 929                 if (brsh >= 0) {
 930                         b = (qq << (31 - qq_nbits));
 931                         tmp = ii >> brsh;
 932                 } else {
 933                         b = (qq << (31 - qq_nbits));
 934                         tmp = ii << -brsh;
 935                 }
 936                 if (tmp == 0) {
 937                         error = true;
 938                         break;
 939                 }
 940                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 941
 942                 if (i == 0 && (mask & 0x1)) {
 943                         if (dev->phy.rev >= 3) {
 944                                 new.a0 = a & 0x3FF;
 945                                 new.b0 = b & 0x3FF;
 946                         } else {
 947                                 new.a0 = b & 0x3FF;
 948                                 new.b0 = a & 0x3FF;
 949                         }
 950                 } else if (i == 1 && (mask & 0x2)) {
 951                         if (dev->phy.rev >= 3) {
 952                                 new.a1 = a & 0x3FF;
 953                                 new.b1 = b & 0x3FF;
 954                         } else {
 955                                 new.a1 = b & 0x3FF;
 956                                 new.b1 = a & 0x3FF;
 957                         }
 958                 }
 959         }
 960
 961         if (error)
 962                 new = old;
 963
 964         b43_nphy_rx_iq_coeffs(dev, true, &new);
 965 }
 966
 967 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 968 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 969 {
 970         u16 array[4];
 971         int i;
 972
 973         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 974         for (i = 0; i < 4; i++)
 975                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 976
 977         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 978         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 979         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 980         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 981 }
 982
 983 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 984 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 985                                           const u16 *clip_st)
 986 {
 987         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 988         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 989 }
 990
 991 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 992 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 993 {
 994         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 995         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 996 }
 997
 998 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 999 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
1000 {
1001         if (dev->phy.rev >= 3) {
1002                 if (!init)
1003                         return;
1004                 if (0 /* FIXME */) {
1005                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
1006                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
1007                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
1008                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
1009                 }
1010         } else {
1011                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1012                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1013
1014                 switch (dev->dev->bus_type) {
1015 #ifdef CONFIG_B43_BCMA
1016                 case B43_BUS_BCMA:
1017                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1018                                                  0xFC00, 0xFC00);
1019                         break;
1020 #endif
1021 #ifdef CONFIG_B43_SSB
1022                 case B43_BUS_SSB:
1023                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1024                                                 0xFC00, 0xFC00);
1025                         break;
1026 #endif
1027                 }
1028
1029                 b43_write32(dev, B43_MMIO_MACCTL,
1030                         b43_read32(dev, B43_MMIO_MACCTL) &
1031                         ~B43_MACCTL_GPOUTSMSK);
1032                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1033                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
1034                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
1035                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
1036
1037                 if (init) {
1038                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1039                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1040                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1041                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1042                 }
1043         }
1044 }
1045
1046 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
1047 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
1048 {
1049         u16 tmp;
1050
1051         if (dev->dev->core_rev == 16)
1052                 b43_mac_suspend(dev);
1053
1054         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
1055         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
1056                 B43_NPHY_CLASSCTL_WAITEDEN);
1057         tmp &= ~mask;
1058         tmp |= (val & mask);
1059         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
1060
1061         if (dev->dev->core_rev == 16)
1062                 b43_mac_enable(dev);
1063
1064         return tmp;
1065 }
1066
1067 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1068 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1069 {
1070         struct b43_phy *phy = &dev->phy;
1071         struct b43_phy_n *nphy = phy->n;
1072
1073         if (enable) {
1074                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1075                 if (nphy->deaf_count++ == 0) {
1076                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1077                         b43_nphy_classifier(dev, 0x7, 0);
1078                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
1079                         b43_nphy_write_clip_detection(dev, clip);
1080                 }
1081                 b43_nphy_reset_cca(dev);
1082         } else {
1083                 if (--nphy->deaf_count == 0) {
1084                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1085                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
1086                 }
1087         }
1088 }
1089
1090 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1091 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1092 {
1093         struct b43_phy_n *nphy = dev->phy.n;
1094         u16 tmp;
1095
1096         if (nphy->hang_avoid)
1097                 b43_nphy_stay_in_carrier_search(dev, 1);
1098
1099         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1100         if (tmp & 0x1)
1101                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1102         else if (tmp & 0x2)
1103                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1104
1105         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1106
1107         if (nphy->bb_mult_save & 0x80000000) {
1108                 tmp = nphy->bb_mult_save & 0xFFFF;
1109                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1110                 nphy->bb_mult_save = 0;
1111         }
1112
1113         if (nphy->hang_avoid)
1114                 b43_nphy_stay_in_carrier_search(dev, 0);
1115 }
1116
1117 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1118 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1119 {
1120         struct b43_phy_n *nphy = dev->phy.n;
1121
1122         u8 channel = dev->phy.channel;
1123         int tone[2] = { 57, 58 };
1124         u32 noise[2] = { 0x3FF, 0x3FF };
1125
1126         B43_WARN_ON(dev->phy.rev < 3);
1127
1128         if (nphy->hang_avoid)
1129                 b43_nphy_stay_in_carrier_search(dev, 1);
1130
1131         if (nphy->gband_spurwar_en) {
1132                 /* TODO: N PHY Adjust Analog Pfbw (7) */
1133                 if (channel == 11 && dev->phy.is_40mhz)
1134                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1135                 else
1136                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1137                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1138         }
1139
1140         if (nphy->aband_spurwar_en) {
1141                 if (channel == 54) {
1142                         tone[0] = 0x20;
1143                         noise[0] = 0x25F;
1144                 } else if (channel == 38 || channel == 102 || channel == 118) {
1145                         if (0 /* FIXME */) {
1146                                 tone[0] = 0x20;
1147                                 noise[0] = 0x21F;
1148                         } else {
1149                                 tone[0] = 0;
1150                                 noise[0] = 0;
1151                         }
1152                 } else if (channel == 134) {
1153                         tone[0] = 0x20;
1154                         noise[0] = 0x21F;
1155                 } else if (channel == 151) {
1156                         tone[0] = 0x10;
1157                         noise[0] = 0x23F;
1158                 } else if (channel == 153 || channel == 161) {
1159                         tone[0] = 0x30;
1160                         noise[0] = 0x23F;
1161                 } else {
1162                         tone[0] = 0;
1163                         noise[0] = 0;
1164                 }
1165
1166                 if (!tone[0] && !noise[0])
1167                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1168                 else
1169                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1170         }
1171
1172         if (nphy->hang_avoid)
1173                 b43_nphy_stay_in_carrier_search(dev, 0);
1174 }
1175
1176 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1177 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1178 {
1179         struct b43_phy_n *nphy = dev->phy.n;
1180
1181         u8 i;
1182         s16 tmp;
1183         u16 data[4];
1184         s16 gain[2];
1185         u16 minmax[2];
1186         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1187
1188         if (nphy->hang_avoid)
1189                 b43_nphy_stay_in_carrier_search(dev, 1);
1190
1191         if (nphy->gain_boost) {
1192                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1193                         gain[0] = 6;
1194                         gain[1] = 6;
1195                 } else {
1196                         tmp = 40370 - 315 * dev->phy.channel;
1197                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1198                         tmp = 23242 - 224 * dev->phy.channel;
1199                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1200                 }
1201         } else {
1202                 gain[0] = 0;
1203                 gain[1] = 0;
1204         }
1205
1206         for (i = 0; i < 2; i++) {
1207                 if (nphy->elna_gain_config) {
1208                         data[0] = 19 + gain[i];
1209                         data[1] = 25 + gain[i];
1210                         data[2] = 25 + gain[i];
1211                         data[3] = 25 + gain[i];
1212                 } else {
1213                         data[0] = lna_gain[0] + gain[i];
1214                         data[1] = lna_gain[1] + gain[i];
1215                         data[2] = lna_gain[2] + gain[i];
1216                         data[3] = lna_gain[3] + gain[i];
1217                 }
1218                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1219
1220                 minmax[i] = 23 + gain[i];
1221         }
1222
1223         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1224                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1225         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1226                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1227
1228         if (nphy->hang_avoid)
1229                 b43_nphy_stay_in_carrier_search(dev, 0);
1230 }
1231
1232 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1233 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1234 {
1235         struct b43_phy_n *nphy = dev->phy.n;
1236         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1237
1238         /* PHY rev 0, 1, 2 */
1239         u8 i, j;
1240         u8 code;
1241         u16 tmp;
1242         u8 rfseq_events[3] = { 6, 8, 7 };
1243         u8 rfseq_delays[3] = { 10, 30, 1 };
1244
1245         /* PHY rev >= 3 */
1246         bool ghz5;
1247         bool ext_lna;
1248         u16 rssi_gain;
1249         struct nphy_gain_ctl_workaround_entry *e;
1250         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1251         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1252
1253         if (dev->phy.rev >= 3) {
1254                 /* Prepare values */
1255                 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1256                         & B43_NPHY_BANDCTL_5GHZ;
1257                 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1258                 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1259                 if (ghz5 && dev->phy.rev >= 5)
1260                         rssi_gain = 0x90;
1261                 else
1262                         rssi_gain = 0x50;
1263
1264                 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1265
1266                 /* Set Clip 2 detect */
1267                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1268                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1269                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1270                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1271
1272                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1273                                 0x17);
1274                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1275                                 0x17);
1276                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1277                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1278                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1279                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1280                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1281                                 rssi_gain);
1282                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1283                                 rssi_gain);
1284                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1285                                 0x17);
1286                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1287                                 0x17);
1288                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1289                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1290
1291                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1292                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1293                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1294                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1295                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1296                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1297                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1298                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1299                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1300                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1301                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1302                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1303
1304                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1305                 b43_phy_write(dev, 0x2A7, e->init_gain);
1306                 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1307                                         e->rfseq_init);
1308                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1309
1310                 /* TODO: check defines. Do not match variables names */
1311                 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1312                 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1313                 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1314                 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1315                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1316                 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1317
1318                 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1319                 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1320                 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1321                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1322                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1323                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1324                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1325                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1326                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1327                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1328         } else {
1329                 /* Set Clip 2 detect */
1330                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1331                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1332                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1333                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1334
1335                 /* Set narrowband clip threshold */
1336                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1337                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1338
1339                 if (!dev->phy.is_40mhz) {
1340                         /* Set dwell lengths */
1341                         b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1342                         b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1343                         b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1344                         b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1345                 }
1346
1347                 /* Set wideband clip 2 threshold */
1348                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1349                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1350                                 21);
1351                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1352                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1353                                 21);
1354
1355                 if (!dev->phy.is_40mhz) {
1356                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1357                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1358                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1359                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1360                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1361                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1362                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1363                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1364                 }
1365
1366                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1367
1368                 if (nphy->gain_boost) {
1369                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1370                             dev->phy.is_40mhz)
1371                                 code = 4;
1372                         else
1373                                 code = 5;
1374                 } else {
1375                         code = dev->phy.is_40mhz ? 6 : 7;
1376                 }
1377
1378                 /* Set HPVGA2 index */
1379                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1380                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1381                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1382                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1383                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1384                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1385
1386                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1387                 /* specs say about 2 loops, but wl does 4 */
1388                 for (i = 0; i < 4; i++)
1389                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1390                                                         (code << 8 | 0x7C));
1391
1392                 b43_nphy_adjust_lna_gain_table(dev);
1393
1394                 if (nphy->elna_gain_config) {
1395                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1396                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1397                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1398                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1399                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1400
1401                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1402                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1403                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1404                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1405                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1406
1407                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1408                         /* specs say about 2 loops, but wl does 4 */
1409                         for (i = 0; i < 4; i++)
1410                                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1411                                                         (code << 8 | 0x74));
1412                 }
1413
1414                 if (dev->phy.rev == 2) {
1415                         for (i = 0; i < 4; i++) {
1416                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1417                                                 (0x0400 * i) + 0x0020);
1418                                 for (j = 0; j < 21; j++) {
1419                                         tmp = j * (i < 2 ? 3 : 1);
1420                                         b43_phy_write(dev,
1421                                                 B43_NPHY_TABLE_DATALO, tmp);
1422                                 }
1423                         }
1424                 }
1425
1426                 b43_nphy_set_rf_sequence(dev, 5,
1427                                 rfseq_events, rfseq_delays, 3);
1428                 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1429                         ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1430                         0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1431
1432                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1433                         b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1434                                         0xFF80, 4);
1435         }
1436 }
1437
1438 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1439 static void b43_nphy_workarounds(struct b43_wldev *dev)
1440 {
1441         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1442         struct b43_phy *phy = &dev->phy;
1443         struct b43_phy_n *nphy = phy->n;
1444
1445         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1446         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1447
1448         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1449         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1450
1451         u16 tmp16;
1452         u32 tmp32;
1453
1454         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1455                 b43_nphy_classifier(dev, 1, 0);
1456         else
1457                 b43_nphy_classifier(dev, 1, 1);
1458
1459         if (nphy->hang_avoid)
1460                 b43_nphy_stay_in_carrier_search(dev, 1);
1461
1462         b43_phy_set(dev, B43_NPHY_IQFLIP,
1463                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1464
1465         if (dev->phy.rev >= 3) {
1466                 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1467                 tmp32 &= 0xffffff;
1468                 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1469
1470                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1471                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1472                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1473                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1474                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1475                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1476
1477                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1478                 b43_phy_write(dev, 0x2AE, 0x000C);
1479
1480                 /* TODO */
1481
1482                 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1483                         0x2 : 0x9C40;
1484                 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1485
1486                 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1487
1488                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1489                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1490
1491                 b43_nphy_gain_ctrl_workarounds(dev);
1492
1493                 b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1494                 b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1495
1496                 /* TODO */
1497
1498                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1499                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1500                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1501                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1502                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1503                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1504                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1505                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1506                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1507                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1508
1509                 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1510
1511                 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1512                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1513                     (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1514                     b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1515                         tmp32 = 0x00088888;
1516                 else
1517                         tmp32 = 0x88888888;
1518                 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1519                 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1520                 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1521
1522                 if (dev->phy.rev == 4 &&
1523                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1524                         b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1525                                         0x70);
1526                         b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1527                                         0x70);
1528                 }
1529
1530                 b43_phy_write(dev, 0x224, 0x039C);
1531                 b43_phy_write(dev, 0x225, 0x0357);
1532                 b43_phy_write(dev, 0x226, 0x0317);
1533                 b43_phy_write(dev, 0x227, 0x02D7);
1534                 b43_phy_write(dev, 0x228, 0x039C);
1535                 b43_phy_write(dev, 0x229, 0x0357);
1536                 b43_phy_write(dev, 0x22A, 0x0317);
1537                 b43_phy_write(dev, 0x22B, 0x02D7);
1538                 b43_phy_write(dev, 0x22C, 0x039C);
1539                 b43_phy_write(dev, 0x22D, 0x0357);
1540                 b43_phy_write(dev, 0x22E, 0x0317);
1541                 b43_phy_write(dev, 0x22F, 0x02D7);
1542         } else {
1543                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1544                     nphy->band5g_pwrgain) {
1545                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1546                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1547                 } else {
1548                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1549                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1550                 }
1551
1552                 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1553                 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1554                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1555                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1556
1557                 if (dev->phy.rev < 2) {
1558                         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1559                         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1560                         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1561                         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1562                         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1563                         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1564                 }
1565
1566                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1567                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1568                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1569                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1570
1571                 if (sprom->boardflags2_lo & 0x100 &&
1572                     dev->dev->board_type == 0x8B) {
1573                         delays1[0] = 0x1;
1574                         delays1[5] = 0x14;
1575                 }
1576                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1577                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1578
1579                 b43_nphy_gain_ctrl_workarounds(dev);
1580
1581                 if (dev->phy.rev < 2) {
1582                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1583                                 b43_hf_write(dev, b43_hf_read(dev) |
1584                                                 B43_HF_MLADVW);
1585                 } else if (dev->phy.rev == 2) {
1586                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1587                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1588                 }
1589
1590                 if (dev->phy.rev < 2)
1591                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1592                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1593
1594                 /* Set phase track alpha and beta */
1595                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1596                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1597                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1598                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1599                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1600                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1601
1602                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1603                                 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1604                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1605                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1606                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1607
1608                 if (dev->phy.rev == 2)
1609                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1610                                         B43_NPHY_FINERX2_CGC_DECGC);
1611         }
1612
1613         if (nphy->hang_avoid)
1614                 b43_nphy_stay_in_carrier_search(dev, 0);
1615 }
1616
1617 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1618 static int b43_nphy_load_samples(struct b43_wldev *dev,
1619                                         struct b43_c32 *samples, u16 len) {
1620         struct b43_phy_n *nphy = dev->phy.n;
1621         u16 i;
1622         u32 *data;
1623
1624         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1625         if (!data) {
1626                 b43err(dev->wl, "allocation for samples loading failed\n");
1627                 return -ENOMEM;
1628         }
1629         if (nphy->hang_avoid)
1630                 b43_nphy_stay_in_carrier_search(dev, 1);
1631
1632         for (i = 0; i < len; i++) {
1633                 data[i] = (samples[i].i & 0x3FF << 10);
1634                 data[i] |= samples[i].q & 0x3FF;
1635         }
1636         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1637
1638         kfree(data);
1639         if (nphy->hang_avoid)
1640                 b43_nphy_stay_in_carrier_search(dev, 0);
1641         return 0;
1642 }
1643
1644 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1645 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1646                                         bool test)
1647 {
1648         int i;
1649         u16 bw, len, rot, angle;
1650         struct b43_c32 *samples;
1651
1652
1653         bw = (dev->phy.is_40mhz) ? 40 : 20;
1654         len = bw << 3;
1655
1656         if (test) {
1657                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1658                         bw = 82;
1659                 else
1660                         bw = 80;
1661
1662                 if (dev->phy.is_40mhz)
1663                         bw <<= 1;
1664
1665                 len = bw << 1;
1666         }
1667
1668         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1669         if (!samples) {
1670                 b43err(dev->wl, "allocation for samples generation failed\n");
1671                 return 0;
1672         }
1673         rot = (((freq * 36) / bw) << 16) / 100;
1674         angle = 0;
1675
1676         for (i = 0; i < len; i++) {
1677                 samples[i] = b43_cordic(angle);
1678                 angle += rot;
1679                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1680                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1681         }
1682
1683         i = b43_nphy_load_samples(dev, samples, len);
1684         kfree(samples);
1685         return (i < 0) ? 0 : len;
1686 }
1687
1688 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1689 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1690                                         u16 wait, bool iqmode, bool dac_test)
1691 {
1692         struct b43_phy_n *nphy = dev->phy.n;
1693         int i;
1694         u16 seq_mode;
1695         u32 tmp;
1696
1697         if (nphy->hang_avoid)
1698                 b43_nphy_stay_in_carrier_search(dev, true);
1699
1700         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1701                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1702                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1703         }
1704
1705         if (!dev->phy.is_40mhz)
1706                 tmp = 0x6464;
1707         else
1708                 tmp = 0x4747;
1709         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1710
1711         if (nphy->hang_avoid)
1712                 b43_nphy_stay_in_carrier_search(dev, false);
1713
1714         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1715
1716         if (loops != 0xFFFF)
1717                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1718         else
1719                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1720
1721         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1722
1723         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1724
1725         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1726         if (iqmode) {
1727                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1728                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1729         } else {
1730                 if (dac_test)
1731                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1732                 else
1733                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1734         }
1735         for (i = 0; i < 100; i++) {
1736                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1737                         i = 0;
1738                         break;
1739                 }
1740                 udelay(10);
1741         }
1742         if (i)
1743                 b43err(dev->wl, "run samples timeout\n");
1744
1745         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1746 }
1747
1748 /*
1749  * Transmits a known value for LO calibration
1750  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1751  */
1752 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1753                                 bool iqmode, bool dac_test)
1754 {
1755         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1756         if (samp == 0)
1757                 return -1;
1758         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1759         return 0;
1760 }
1761
1762 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1763 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1764 {
1765         struct b43_phy_n *nphy = dev->phy.n;
1766         int i, j;
1767         u32 tmp;
1768         u32 cur_real, cur_imag, real_part, imag_part;
1769
1770         u16 buffer[7];
1771
1772         if (nphy->hang_avoid)
1773                 b43_nphy_stay_in_carrier_search(dev, true);
1774
1775         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1776
1777         for (i = 0; i < 2; i++) {
1778                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1779                         (buffer[i * 2 + 1] & 0x3FF);
1780                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1781                                 (((i + 26) << 10) | 320));
1782                 for (j = 0; j < 128; j++) {
1783                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1784                                         ((tmp >> 16) & 0xFFFF));
1785                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1786                                         (tmp & 0xFFFF));
1787                 }
1788         }
1789
1790         for (i = 0; i < 2; i++) {
1791                 tmp = buffer[5 + i];
1792                 real_part = (tmp >> 8) & 0xFF;
1793                 imag_part = (tmp & 0xFF);
1794                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1795                                 (((i + 26) << 10) | 448));
1796
1797                 if (dev->phy.rev >= 3) {
1798                         cur_real = real_part;
1799                         cur_imag = imag_part;
1800                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1801                 }
1802
1803                 for (j = 0; j < 128; j++) {
1804                         if (dev->phy.rev < 3) {
1805                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1806                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1807                                 tmp = ((cur_real & 0xFF) << 8) |
1808                                         (cur_imag & 0xFF);
1809                         }
1810                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1811                                         ((tmp >> 16) & 0xFFFF));
1812                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1813                                         (tmp & 0xFFFF));
1814                 }
1815         }
1816
1817         if (dev->phy.rev >= 3) {
1818                 b43_shm_write16(dev, B43_SHM_SHARED,
1819                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1820                 b43_shm_write16(dev, B43_SHM_SHARED,
1821                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1822         }
1823
1824         if (nphy->hang_avoid)
1825                 b43_nphy_stay_in_carrier_search(dev, false);
1826 }
1827
1828 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1829 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1830                                         u8 *events, u8 *delays, u8 length)
1831 {
1832         struct b43_phy_n *nphy = dev->phy.n;
1833         u8 i;
1834         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1835         u16 offset1 = cmd << 4;
1836         u16 offset2 = offset1 + 0x80;
1837
1838         if (nphy->hang_avoid)
1839                 b43_nphy_stay_in_carrier_search(dev, true);
1840
1841         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1842         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1843
1844         for (i = length; i < 16; i++) {
1845                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1846                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1847         }
1848
1849         if (nphy->hang_avoid)
1850                 b43_nphy_stay_in_carrier_search(dev, false);
1851 }
1852
1853 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1854 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1855                                        enum b43_nphy_rf_sequence seq)
1856 {
1857         static const u16 trigger[] = {
1858                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1859                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1860                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1861                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1862                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1863                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1864         };
1865         int i;
1866         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1867
1868         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1869
1870         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1871                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1872         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1873         for (i = 0; i < 200; i++) {
1874                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1875                         goto ok;
1876                 msleep(1);
1877         }
1878         b43err(dev->wl, "RF sequence status timeout\n");
1879 ok:
1880         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1881 }
1882
1883 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1884 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1885                                                 u16 value, u8 core, bool off)
1886 {
1887         int i;
1888         u8 index = fls(field);
1889         u8 addr, en_addr, val_addr;
1890         /* we expect only one bit set */
1891         B43_WARN_ON(field & (~(1 << (index - 1))));
1892
1893         if (dev->phy.rev >= 3) {
1894                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1895                 for (i = 0; i < 2; i++) {
1896                         if (index == 0 || index == 16) {
1897                                 b43err(dev->wl,
1898                                         "Unsupported RF Ctrl Override call\n");
1899                                 return;
1900                         }
1901
1902                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1903                         en_addr = B43_PHY_N((i == 0) ?
1904                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1905                         val_addr = B43_PHY_N((i == 0) ?
1906                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1907
1908                         if (off) {
1909                                 b43_phy_mask(dev, en_addr, ~(field));
1910                                 b43_phy_mask(dev, val_addr,
1911                                                 ~(rf_ctrl->val_mask));
1912                         } else {
1913                                 if (core == 0 || ((1 << core) & i) != 0) {
1914                                         b43_phy_set(dev, en_addr, field);
1915                                         b43_phy_maskset(dev, val_addr,
1916                                                 ~(rf_ctrl->val_mask),
1917                                                 (value << rf_ctrl->val_shift));
1918                                 }
1919                         }
1920                 }
1921         } else {
1922                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1923                 if (off) {
1924                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1925                         value = 0;
1926                 } else {
1927                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1928                 }
1929
1930                 for (i = 0; i < 2; i++) {
1931                         if (index <= 1 || index == 16) {
1932                                 b43err(dev->wl,
1933                                         "Unsupported RF Ctrl Override call\n");
1934                                 return;
1935                         }
1936
1937                         if (index == 2 || index == 10 ||
1938                             (index >= 13 && index <= 15)) {
1939                                 core = 1;
1940                         }
1941
1942                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1943                         addr = B43_PHY_N((i == 0) ?
1944                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1945
1946                         if ((core & (1 << i)) != 0)
1947                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1948                                                 (value << rf_ctrl->shift));
1949
1950                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1951                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1952                                         B43_NPHY_RFCTL_CMD_START);
1953                         udelay(1);
1954                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1955                 }
1956         }
1957 }
1958
1959 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1960 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1961                                                 u16 value, u8 core)
1962 {
1963         u8 i, j;
1964         u16 reg, tmp, val;
1965
1966         B43_WARN_ON(dev->phy.rev < 3);
1967         B43_WARN_ON(field > 4);
1968
1969         for (i = 0; i < 2; i++) {
1970                 if ((core == 1 && i == 1) || (core == 2 && !i))
1971                         continue;
1972
1973                 reg = (i == 0) ?
1974                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1975                 b43_phy_mask(dev, reg, 0xFBFF);
1976
1977                 switch (field) {
1978                 case 0:
1979                         b43_phy_write(dev, reg, 0);
1980                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1981                         break;
1982                 case 1:
1983                         if (!i) {
1984                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1985                                                 0xFC3F, (value << 6));
1986                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1987                                                 0xFFFE, 1);
1988                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1989                                                 B43_NPHY_RFCTL_CMD_START);
1990                                 for (j = 0; j < 100; j++) {
1991                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1992                                                 j = 0;
1993                                                 break;
1994                                         }
1995                                         udelay(10);
1996                                 }
1997                                 if (j)
1998                                         b43err(dev->wl,
1999                                                 "intc override timeout\n");
2000                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
2001                                                 0xFFFE);
2002                         } else {
2003                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
2004                                                 0xFC3F, (value << 6));
2005                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
2006                                                 0xFFFE, 1);
2007                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2008                                                 B43_NPHY_RFCTL_CMD_RXTX);
2009                                 for (j = 0; j < 100; j++) {
2010                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
2011                                                 j = 0;
2012                                                 break;
2013                                         }
2014                                         udelay(10);
2015                                 }
2016                                 if (j)
2017                                         b43err(dev->wl,
2018                                                 "intc override timeout\n");
2019                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2020                                                 0xFFFE);
2021                         }
2022                         break;
2023                 case 2:
2024                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2025                                 tmp = 0x0020;
2026                                 val = value << 5;
2027                         } else {
2028                                 tmp = 0x0010;
2029                                 val = value << 4;
2030                         }
2031                         b43_phy_maskset(dev, reg, ~tmp, val);
2032                         break;
2033                 case 3:
2034                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2035                                 tmp = 0x0001;
2036                                 val = value;
2037                         } else {
2038                                 tmp = 0x0004;
2039                                 val = value << 2;
2040                         }
2041                         b43_phy_maskset(dev, reg, ~tmp, val);
2042                         break;
2043                 case 4:
2044                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2045                                 tmp = 0x0002;
2046                                 val = value << 1;
2047                         } else {
2048                                 tmp = 0x0008;
2049                                 val = value << 3;
2050                         }
2051                         b43_phy_maskset(dev, reg, ~tmp, val);
2052                         break;
2053                 }
2054         }
2055 }
2056
2057 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
2058 static void b43_nphy_bphy_init(struct b43_wldev *dev)
2059 {
2060         unsigned int i;
2061         u16 val;
2062
2063         val = 0x1E1F;
2064         for (i = 0; i < 16; i++) {
2065                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2066                 val -= 0x202;
2067         }
2068         val = 0x3E3F;
2069         for (i = 0; i < 16; i++) {
2070                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2071                 val -= 0x202;
2072         }
2073         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2074 }
2075
2076 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2077 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2078                                         s8 offset, u8 core, u8 rail,
2079                                         enum b43_nphy_rssi_type type)
2080 {
2081         u16 tmp;
2082         bool core1or5 = (core == 1) || (core == 5);
2083         bool core2or5 = (core == 2) || (core == 5);
2084
2085         offset = clamp_val(offset, -32, 31);
2086         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2087
2088         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2089                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2090         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2091                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2092         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2093                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2094         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2095                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2096
2097         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2098                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2099         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2100                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2101         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2102                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2103         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2104                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2105
2106         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2107                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2108         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2109                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2110         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2111                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2112         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2113                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2114
2115         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2116                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2117         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2118                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2119         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2120                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2121         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2122                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2123
2124         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2125                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2126         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2127                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2128         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2129                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2130         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2131                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2132
2133         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2134                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2135         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2136                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2137
2138         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2139                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2140         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2141                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2142 }
2143
2144 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2145 {
2146         u16 val;
2147
2148         if (type < 3)
2149                 val = 0;
2150         else if (type == 6)
2151                 val = 1;
2152         else if (type == 3)
2153                 val = 2;
2154         else
2155                 val = 3;
2156
2157         val = (val << 12) | (val << 14);
2158         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2159         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2160
2161         if (type < 3) {
2162                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2163                                 (type + 1) << 4);
2164                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2165                                 (type + 1) << 4);
2166         }
2167
2168         if (code == 0) {
2169                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2170                 if (type < 3) {
2171                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2172                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2173                                   B43_NPHY_RFCTL_CMD_CORESEL));
2174                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2175                                 ~(0x1 << 12 |
2176                                   0x1 << 5 |
2177                                   0x1 << 1 |
2178                                   0x1));
2179                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2180                                 ~B43_NPHY_RFCTL_CMD_START);
2181                         udelay(20);
2182                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2183                 }
2184         } else {
2185                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2186                 if (type < 3) {
2187                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2188                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2189                                   B43_NPHY_RFCTL_CMD_CORESEL),
2190                                 (B43_NPHY_RFCTL_CMD_RXEN |
2191                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2192                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2193                                 (0x1 << 12 |
2194                                   0x1 << 5 |
2195                                   0x1 << 1 |
2196                                   0x1));
2197                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2198                                 B43_NPHY_RFCTL_CMD_START);
2199                         udelay(20);
2200                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2201                 }
2202         }
2203 }
2204
2205 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2206 {
2207         struct b43_phy_n *nphy = dev->phy.n;
2208         u8 i;
2209         u16 reg, val;
2210
2211         if (code == 0) {
2212                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2213                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2214                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2215                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2216                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2217                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2218                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2219                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2220         } else {
2221                 for (i = 0; i < 2; i++) {
2222                         if ((code == 1 && i == 1) || (code == 2 && !i))
2223                                 continue;
2224
2225                         reg = (i == 0) ?
2226                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2227                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2228
2229                         if (type < 3) {
2230                                 reg = (i == 0) ?
2231                                         B43_NPHY_AFECTL_C1 :
2232                                         B43_NPHY_AFECTL_C2;
2233                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2234
2235                                 reg = (i == 0) ?
2236                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2237                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
2238                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2239
2240                                 if (type == 0)
2241                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2242                                 else if (type == 1)
2243                                         val = 16;
2244                                 else
2245                                         val = 32;
2246                                 b43_phy_set(dev, reg, val);
2247
2248                                 reg = (i == 0) ?
2249                                         B43_NPHY_TXF_40CO_B1S0 :
2250                                         B43_NPHY_TXF_40CO_B32S1;
2251                                 b43_phy_set(dev, reg, 0x0020);
2252                         } else {
2253                                 if (type == 6)
2254                                         val = 0x0100;
2255                                 else if (type == 3)
2256                                         val = 0x0200;
2257                                 else
2258                                         val = 0x0300;
2259
2260                                 reg = (i == 0) ?
2261                                         B43_NPHY_AFECTL_C1 :
2262                                         B43_NPHY_AFECTL_C2;
2263
2264                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
2265                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2266
2267                                 if (type != 3 && type != 6) {
2268                                         enum ieee80211_band band =
2269                                                 b43_current_band(dev->wl);
2270
2271                                         if ((nphy->ipa2g_on &&
2272                                                 band == IEEE80211_BAND_2GHZ) ||
2273                                                 (nphy->ipa5g_on &&
2274                                                 band == IEEE80211_BAND_5GHZ))
2275                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2276                                         else
2277                                                 val = 0x11;
2278                                         reg = (i == 0) ? 0x2000 : 0x3000;
2279                                         reg |= B2055_PADDRV;
2280                                         b43_radio_write16(dev, reg, val);
2281
2282                                         reg = (i == 0) ?
2283                                                 B43_NPHY_AFECTL_OVER1 :
2284                                                 B43_NPHY_AFECTL_OVER;
2285                                         b43_phy_set(dev, reg, 0x0200);
2286                                 }
2287                         }
2288                 }
2289         }
2290 }
2291
2292 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2293 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2294 {
2295         if (dev->phy.rev >= 3)
2296                 b43_nphy_rev3_rssi_select(dev, code, type);
2297         else
2298                 b43_nphy_rev2_rssi_select(dev, code, type);
2299 }
2300
2301 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2302 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2303 {
2304         int i;
2305         for (i = 0; i < 2; i++) {
2306                 if (type == 2) {
2307                         if (i == 0) {
2308                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2309                                                   0xFC, buf[0]);
2310                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2311                                                   0xFC, buf[1]);
2312                         } else {
2313                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2314                                                   0xFC, buf[2 * i]);
2315                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2316                                                   0xFC, buf[2 * i + 1]);
2317                         }
2318                 } else {
2319                         if (i == 0)
2320                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2321                                                   0xF3, buf[0] << 2);
2322                         else
2323                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2324                                                   0xF3, buf[2 * i + 1] << 2);
2325                 }
2326         }
2327 }
2328
2329 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2330 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2331                                 u8 nsamp)
2332 {
2333         int i;
2334         int out;
2335         u16 save_regs_phy[9];
2336         u16 s[2];
2337
2338         if (dev->phy.rev >= 3) {
2339                 save_regs_phy[0] = b43_phy_read(dev,
2340                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2341                 save_regs_phy[1] = b43_phy_read(dev,
2342                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2343                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2344                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2345                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2346                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2347                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2348                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2349                 save_regs_phy[8] = 0;
2350         } else {
2351                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2352                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2353                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2354                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2355                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2356                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2357                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2358                 save_regs_phy[7] = 0;
2359                 save_regs_phy[8] = 0;
2360         }
2361
2362         b43_nphy_rssi_select(dev, 5, type);
2363
2364         if (dev->phy.rev < 2) {
2365                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2366                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2367         }
2368
2369         for (i = 0; i < 4; i++)
2370                 buf[i] = 0;
2371
2372         for (i = 0; i < nsamp; i++) {
2373                 if (dev->phy.rev < 2) {
2374                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2375                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2376                 } else {
2377                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2378                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2379                 }
2380
2381                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2382                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2383                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2384                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2385         }
2386         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2387                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2388
2389         if (dev->phy.rev < 2)
2390                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2391
2392         if (dev->phy.rev >= 3) {
2393                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2394                                 save_regs_phy[0]);
2395                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2396                                 save_regs_phy[1]);
2397                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2398                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2399                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2400                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2401                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2402                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2403         } else {
2404                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2405                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2406                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2407                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2408                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2409                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2410                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2411         }
2412
2413         return out;
2414 }
2415
2416 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2417 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2418 {
2419         int i, j;
2420         u8 state[4];
2421         u8 code, val;
2422         u16 class, override;
2423         u8 regs_save_radio[2];
2424         u16 regs_save_phy[2];
2425
2426         s8 offset[4];
2427         u8 core;
2428         u8 rail;
2429
2430         u16 clip_state[2];
2431         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2432         s32 results_min[4] = { };
2433         u8 vcm_final[4] = { };
2434         s32 results[4][4] = { };
2435         s32 miniq[4][2] = { };
2436
2437         if (type == 2) {
2438                 code = 0;
2439                 val = 6;
2440         } else if (type < 2) {
2441                 code = 25;
2442                 val = 4;
2443         } else {
2444                 B43_WARN_ON(1);
2445                 return;
2446         }
2447
2448         class = b43_nphy_classifier(dev, 0, 0);
2449         b43_nphy_classifier(dev, 7, 4);
2450         b43_nphy_read_clip_detection(dev, clip_state);
2451         b43_nphy_write_clip_detection(dev, clip_off);
2452
2453         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2454                 override = 0x140;
2455         else
2456                 override = 0x110;
2457
2458         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2459         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2460         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2461         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2462
2463         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2464         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2465         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2466         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2467
2468         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2469         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2470         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2471         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2472         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2473         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2474
2475         b43_nphy_rssi_select(dev, 5, type);
2476         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2477         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2478
2479         for (i = 0; i < 4; i++) {
2480                 u8 tmp[4];
2481                 for (j = 0; j < 4; j++)
2482                         tmp[j] = i;
2483                 if (type != 1)
2484                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2485                 b43_nphy_poll_rssi(dev, type, results[i], 8);
2486                 if (type < 2)
2487                         for (j = 0; j < 2; j++)
2488                                 miniq[i][j] = min(results[i][2 * j],
2489                                                 results[i][2 * j + 1]);
2490         }
2491
2492         for (i = 0; i < 4; i++) {
2493                 s32 mind = 40;
2494                 u8 minvcm = 0;
2495                 s32 minpoll = 249;
2496                 s32 curr;
2497                 for (j = 0; j < 4; j++) {
2498                         if (type == 2)
2499                                 curr = abs(results[j][i]);
2500                         else
2501                                 curr = abs(miniq[j][i / 2] - code * 8);
2502
2503                         if (curr < mind) {
2504                                 mind = curr;
2505                                 minvcm = j;
2506                         }
2507
2508                         if (results[j][i] < minpoll)
2509                                 minpoll = results[j][i];
2510                 }
2511                 results_min[i] = minpoll;
2512                 vcm_final[i] = minvcm;
2513         }
2514
2515         if (type != 1)
2516                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2517
2518         for (i = 0; i < 4; i++) {
2519                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2520
2521                 if (offset[i] < 0)
2522                         offset[i] = -((abs(offset[i]) + 4) / 8);
2523                 else
2524                         offset[i] = (offset[i] + 4) / 8;
2525
2526                 if (results_min[i] == 248)
2527                         offset[i] = code - 32;
2528
2529                 core = (i / 2) ? 2 : 1;
2530                 rail = (i % 2) ? 1 : 0;
2531
2532                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2533                                                 type);
2534         }
2535
2536         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2537         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2538
2539         switch (state[2]) {
2540         case 1:
2541                 b43_nphy_rssi_select(dev, 1, 2);
2542                 break;
2543         case 4:
2544                 b43_nphy_rssi_select(dev, 1, 0);
2545                 break;
2546         case 2:
2547                 b43_nphy_rssi_select(dev, 1, 1);
2548                 break;
2549         default:
2550                 b43_nphy_rssi_select(dev, 1, 1);
2551                 break;
2552         }
2553
2554         switch (state[3]) {
2555         case 1:
2556                 b43_nphy_rssi_select(dev, 2, 2);
2557                 break;
2558         case 4:
2559                 b43_nphy_rssi_select(dev, 2, 0);
2560                 break;
2561         default:
2562                 b43_nphy_rssi_select(dev, 2, 1);
2563                 break;
2564         }
2565
2566         b43_nphy_rssi_select(dev, 0, type);
2567
2568         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2569         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2570         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2571         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2572
2573         b43_nphy_classifier(dev, 7, class);
2574         b43_nphy_write_clip_detection(dev, clip_state);
2575         /* Specs don't say about reset here, but it makes wl and b43 dumps
2576            identical, it really seems wl performs this */
2577         b43_nphy_reset_cca(dev);
2578 }
2579
2580 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2581 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2582 {
2583         /* TODO */
2584 }
2585
2586 /*
2587  * RSSI Calibration
2588  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2589  */
2590 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2591 {
2592         if (dev->phy.rev >= 3) {
2593                 b43_nphy_rev3_rssi_cal(dev);
2594         } else {
2595                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2596                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2597                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2598         }
2599 }
2600
2601 /*
2602  * Restore RSSI Calibration
2603  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2604  */
2605 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2606 {
2607         struct b43_phy_n *nphy = dev->phy.n;
2608
2609         u16 *rssical_radio_regs = NULL;
2610         u16 *rssical_phy_regs = NULL;
2611
2612         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2613                 if (!nphy->rssical_chanspec_2G.center_freq)
2614                         return;
2615                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2616                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2617         } else {
2618                 if (!nphy->rssical_chanspec_5G.center_freq)
2619                         return;
2620                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2621                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2622         }
2623
2624         /* TODO use some definitions */
2625         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2626         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2627
2628         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2629         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2630         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2631         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2632
2633         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2634         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2635         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2636         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2637
2638         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2639         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2640         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2641         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2642 }
2643
2644 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2645 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2646 {
2647         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2648                 if (dev->phy.rev >= 6) {
2649                         /* TODO If the chip is 47162
2650                                 return txpwrctrl_tx_gain_ipa_rev5 */
2651                         return txpwrctrl_tx_gain_ipa_rev6;
2652                 } else if (dev->phy.rev >= 5) {
2653                         return txpwrctrl_tx_gain_ipa_rev5;
2654                 } else {
2655                         return txpwrctrl_tx_gain_ipa;
2656                 }
2657         } else {
2658                 return txpwrctrl_tx_gain_ipa_5g;
2659         }
2660 }
2661
2662 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2663 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2664 {
2665         struct b43_phy_n *nphy = dev->phy.n;
2666         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2667         u16 tmp;
2668         u8 offset, i;
2669
2670         if (dev->phy.rev >= 3) {
2671             for (i = 0; i < 2; i++) {
2672                 tmp = (i == 0) ? 0x2000 : 0x3000;
2673                 offset = i * 11;
2674
2675                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2676                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2677                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2678                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2679                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2680                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2681                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2682                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2683                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2684                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2685                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2686
2687                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2688                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2689                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2690                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2691                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2692                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2693                         if (nphy->ipa5g_on) {
2694                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2695                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2696                         } else {
2697                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2698                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2699                         }
2700                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2701                 } else {
2702                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2703                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2704                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2705                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2706                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2707                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2708                         if (nphy->ipa2g_on) {
2709                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2710                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2711                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2712                         } else {
2713                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2714                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2715                         }
2716                 }
2717                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2718                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2719                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2720             }
2721         } else {
2722                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2723                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2724
2725                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2726                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2727
2728                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2729                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2730
2731                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2732                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2733
2734                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2735                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2736
2737                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2738                     B43_NPHY_BANDCTL_5GHZ)) {
2739                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2740                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2741                 } else {
2742                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2743                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2744                 }
2745
2746                 if (dev->phy.rev < 2) {
2747                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2748                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2749                 } else {
2750                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2751                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2752                 }
2753         }
2754 }
2755
2756 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2757 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2758                                         struct nphy_txgains target,
2759                                         struct nphy_iqcal_params *params)
2760 {
2761         int i, j, indx;
2762         u16 gain;
2763
2764         if (dev->phy.rev >= 3) {
2765                 params->txgm = target.txgm[core];
2766                 params->pga = target.pga[core];
2767                 params->pad = target.pad[core];
2768                 params->ipa = target.ipa[core];
2769                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2770                                         (params->pad << 4) | (params->ipa);
2771                 for (j = 0; j < 5; j++)
2772                         params->ncorr[j] = 0x79;
2773         } else {
2774                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2775                         (target.txgm[core] << 8);
2776
2777                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2778                         1 : 0;
2779                 for (i = 0; i < 9; i++)
2780                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2781                                 break;
2782                 i = min(i, 8);
2783
2784                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2785                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2786                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2787                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2788                                         (params->pad << 2);
2789                 for (j = 0; j < 4; j++)
2790                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2791         }
2792 }
2793
2794 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2795 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2796 {
2797         struct b43_phy_n *nphy = dev->phy.n;
2798         int i;
2799         u16 scale, entry;
2800
2801         u16 tmp = nphy->txcal_bbmult;
2802         if (core == 0)
2803                 tmp >>= 8;
2804         tmp &= 0xff;
2805
2806         for (i = 0; i < 18; i++) {
2807                 scale = (ladder_lo[i].percent * tmp) / 100;
2808                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2809                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2810
2811                 scale = (ladder_iq[i].percent * tmp) / 100;
2812                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2813                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2814         }
2815 }
2816
2817 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2818 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2819 {
2820         int i;
2821         for (i = 0; i < 15; i++)
2822                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2823                                 tbl_tx_filter_coef_rev4[2][i]);
2824 }
2825
2826 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2827 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2828 {
2829         int i, j;
2830         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2831         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2832
2833         for (i = 0; i < 3; i++)
2834                 for (j = 0; j < 15; j++)
2835                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2836                                         tbl_tx_filter_coef_rev4[i][j]);
2837
2838         if (dev->phy.is_40mhz) {
2839                 for (j = 0; j < 15; j++)
2840                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2841                                         tbl_tx_filter_coef_rev4[3][j]);
2842         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2843                 for (j = 0; j < 15; j++)
2844                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2845                                         tbl_tx_filter_coef_rev4[5][j]);
2846         }
2847
2848         if (dev->phy.channel == 14)
2849                 for (j = 0; j < 15; j++)
2850                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2851                                         tbl_tx_filter_coef_rev4[6][j]);
2852 }
2853
2854 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2855 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2856 {
2857         struct b43_phy_n *nphy = dev->phy.n;
2858
2859         u16 curr_gain[2];
2860         struct nphy_txgains target;
2861         const u32 *table = NULL;
2862
2863         if (!nphy->txpwrctrl) {
2864                 int i;
2865
2866                 if (nphy->hang_avoid)
2867                         b43_nphy_stay_in_carrier_search(dev, true);
2868                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2869                 if (nphy->hang_avoid)
2870                         b43_nphy_stay_in_carrier_search(dev, false);
2871
2872                 for (i = 0; i < 2; ++i) {
2873                         if (dev->phy.rev >= 3) {
2874                                 target.ipa[i] = curr_gain[i] & 0x000F;
2875                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2876                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2877                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2878                         } else {
2879                                 target.ipa[i] = curr_gain[i] & 0x0003;
2880                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2881                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2882                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2883                         }
2884                 }
2885         } else {
2886                 int i;
2887                 u16 index[2];
2888                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2889                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2890                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2891                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2892                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2893                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2894
2895                 for (i = 0; i < 2; ++i) {
2896                         if (dev->phy.rev >= 3) {
2897                                 enum ieee80211_band band =
2898                                         b43_current_band(dev->wl);
2899
2900                                 if ((nphy->ipa2g_on &&
2901                                      band == IEEE80211_BAND_2GHZ) ||
2902                                     (nphy->ipa5g_on &&
2903                                      band == IEEE80211_BAND_5GHZ)) {
2904                                         table = b43_nphy_get_ipa_gain_table(dev);
2905                                 } else {
2906                                         if (band == IEEE80211_BAND_5GHZ) {
2907                                                 if (dev->phy.rev == 3)
2908                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2909                                                 else if (dev->phy.rev == 4)
2910                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2911                                                 else
2912                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2913                                         } else {
2914                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2915                                         }
2916                                 }
2917
2918                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2919                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2920                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2921                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2922                         } else {
2923                                 table = b43_ntab_tx_gain_rev0_1_2;
2924
2925                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2926                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2927                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2928                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2929                         }
2930                 }
2931         }
2932
2933         return target;
2934 }
2935
2936 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2937 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2938 {
2939         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2940
2941         if (dev->phy.rev >= 3) {
2942                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2943                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2944                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2945                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2946                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2947                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2948                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2949                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2950                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2951                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2952                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2953                 b43_nphy_reset_cca(dev);
2954         } else {
2955                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2956                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2957                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2958                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2959                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2960                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2961                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2962         }
2963 }
2964
2965 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2966 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2967 {
2968         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2969         u16 tmp;
2970
2971         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2972         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2973         if (dev->phy.rev >= 3) {
2974                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2975                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2976
2977                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2978                 regs[2] = tmp;
2979                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2980
2981                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2982                 regs[3] = tmp;
2983                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2984
2985                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2986                 b43_phy_mask(dev, B43_NPHY_BBCFG,
2987                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2988
2989                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2990                 regs[5] = tmp;
2991                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2992
2993                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2994                 regs[6] = tmp;
2995                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2996                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2997                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2998
2999                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3000                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3001                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
3002
3003                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3004                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3005                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3006                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3007         } else {
3008                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3009                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3010                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3011                 regs[2] = tmp;
3012                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
3013                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
3014                 regs[3] = tmp;
3015                 tmp |= 0x2000;
3016                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
3017                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
3018                 regs[4] = tmp;
3019                 tmp |= 0x2000;
3020                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
3021                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3022                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3023                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3024                         tmp = 0x0180;
3025                 else
3026                         tmp = 0x0120;
3027                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3028                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3029         }
3030 }
3031
3032 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3033 static void b43_nphy_save_cal(struct b43_wldev *dev)
3034 {
3035         struct b43_phy_n *nphy = dev->phy.n;
3036
3037         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3038         u16 *txcal_radio_regs = NULL;
3039         struct b43_chanspec *iqcal_chanspec;
3040         u16 *table = NULL;
3041
3042         if (nphy->hang_avoid)
3043                 b43_nphy_stay_in_carrier_search(dev, 1);
3044
3045         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3046                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3047                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3048                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3049                 table = nphy->cal_cache.txcal_coeffs_2G;
3050         } else {
3051                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3052                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3053                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3054                 table = nphy->cal_cache.txcal_coeffs_5G;
3055         }
3056
3057         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3058         /* TODO use some definitions */
3059         if (dev->phy.rev >= 3) {
3060                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3061                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3062                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3063                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3064                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3065                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3066                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3067                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3068         } else {
3069                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3070                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3071                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3072                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3073         }
3074         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3075         iqcal_chanspec->channel_type = dev->phy.channel_type;
3076         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3077
3078         if (nphy->hang_avoid)
3079                 b43_nphy_stay_in_carrier_search(dev, 0);
3080 }
3081
3082 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3083 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3084 {
3085         struct b43_phy_n *nphy = dev->phy.n;
3086
3087         u16 coef[4];
3088         u16 *loft = NULL;
3089         u16 *table = NULL;
3090
3091         int i;
3092         u16 *txcal_radio_regs = NULL;
3093         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3094
3095         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3096                 if (!nphy->iqcal_chanspec_2G.center_freq)
3097                         return;
3098                 table = nphy->cal_cache.txcal_coeffs_2G;
3099                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3100         } else {
3101                 if (!nphy->iqcal_chanspec_5G.center_freq)
3102                         return;
3103                 table = nphy->cal_cache.txcal_coeffs_5G;
3104                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3105         }
3106
3107         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3108
3109         for (i = 0; i < 4; i++) {
3110                 if (dev->phy.rev >= 3)
3111                         table[i] = coef[i];
3112                 else
3113                         coef[i] = 0;
3114         }
3115
3116         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3117         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3118         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3119
3120         if (dev->phy.rev < 2)
3121                 b43_nphy_tx_iq_workaround(dev);
3122
3123         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3124                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3125                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3126         } else {
3127                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3128                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3129         }
3130
3131         /* TODO use some definitions */
3132         if (dev->phy.rev >= 3) {
3133                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3134                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3135                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3136                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3137                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3138                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3139                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3140                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3141         } else {
3142                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3143                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3144                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3145                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3146         }
3147         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3148 }
3149
3150 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3151 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3152                                 struct nphy_txgains target,
3153                                 bool full, bool mphase)
3154 {
3155         struct b43_phy_n *nphy = dev->phy.n;
3156         int i;
3157         int error = 0;
3158         int freq;
3159         bool avoid = false;
3160         u8 length;
3161         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3162         const u16 *table;
3163         bool phy6or5x;
3164
3165         u16 buffer[11];
3166         u16 diq_start = 0;
3167         u16 save[2];
3168         u16 gain[2];
3169         struct nphy_iqcal_params params[2];
3170         bool updated[2] = { };
3171
3172         b43_nphy_stay_in_carrier_search(dev, true);
3173
3174         if (dev->phy.rev >= 4) {
3175                 avoid = nphy->hang_avoid;
3176                 nphy->hang_avoid = 0;
3177         }
3178
3179         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3180
3181         for (i = 0; i < 2; i++) {
3182                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3183                 gain[i] = params[i].cal_gain;
3184         }
3185
3186         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3187
3188         b43_nphy_tx_cal_radio_setup(dev);
3189         b43_nphy_tx_cal_phy_setup(dev);
3190
3191         phy6or5x = dev->phy.rev >= 6 ||
3192                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3193                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3194         if (phy6or5x) {
3195                 if (dev->phy.is_40mhz) {
3196                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3197                                         tbl_tx_iqlo_cal_loft_ladder_40);
3198                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3199                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3200                 } else {
3201                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3202                                         tbl_tx_iqlo_cal_loft_ladder_20);
3203                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3204                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3205                 }
3206         }
3207
3208         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3209
3210         if (!dev->phy.is_40mhz)
3211                 freq = 2500;
3212         else
3213                 freq = 5000;
3214
3215         if (nphy->mphase_cal_phase_id > 2)
3216                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3217                                         0xFFFF, 0, true, false);
3218         else
3219                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3220
3221         if (error == 0) {
3222                 if (nphy->mphase_cal_phase_id > 2) {
3223                         table = nphy->mphase_txcal_bestcoeffs;
3224                         length = 11;
3225                         if (dev->phy.rev < 3)
3226                                 length -= 2;
3227                 } else {
3228                         if (!full && nphy->txiqlocal_coeffsvalid) {
3229                                 table = nphy->txiqlocal_bestc;
3230                                 length = 11;
3231                                 if (dev->phy.rev < 3)
3232                                         length -= 2;
3233                         } else {
3234                                 full = true;
3235                                 if (dev->phy.rev >= 3) {
3236                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3237                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3238                                 } else {
3239                                         table = tbl_tx_iqlo_cal_startcoefs;
3240                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3241                                 }
3242                         }
3243                 }
3244
3245                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3246
3247                 if (full) {
3248                         if (dev->phy.rev >= 3)
3249                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3250                         else
3251                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3252                 } else {
3253                         if (dev->phy.rev >= 3)
3254                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3255                         else
3256                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3257                 }
3258
3259                 if (mphase) {
3260                         count = nphy->mphase_txcal_cmdidx;
3261                         numb = min(max,
3262                                 (u16)(count + nphy->mphase_txcal_numcmds));
3263                 } else {
3264                         count = 0;
3265                         numb = max;
3266                 }
3267
3268                 for (; count < numb; count++) {
3269                         if (full) {
3270                                 if (dev->phy.rev >= 3)
3271                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3272                                 else
3273                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3274                         } else {
3275                                 if (dev->phy.rev >= 3)
3276                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3277                                 else
3278                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3279                         }
3280
3281                         core = (cmd & 0x3000) >> 12;
3282                         type = (cmd & 0x0F00) >> 8;
3283
3284                         if (phy6or5x && updated[core] == 0) {
3285                                 b43_nphy_update_tx_cal_ladder(dev, core);
3286                                 updated[core] = 1;
3287                         }
3288
3289                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3290                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3291
3292                         if (type == 1 || type == 3 || type == 4) {
3293                                 buffer[0] = b43_ntab_read(dev,
3294                                                 B43_NTAB16(15, 69 + core));
3295                                 diq_start = buffer[0];
3296                                 buffer[0] = 0;
3297                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3298                                                 0);
3299                         }
3300
3301                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3302                         for (i = 0; i < 2000; i++) {
3303                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3304                                 if (tmp & 0xC000)
3305                                         break;
3306                                 udelay(10);
3307                         }
3308
3309                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3310                                                 buffer);
3311                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3312                                                 buffer);
3313
3314                         if (type == 1 || type == 3 || type == 4)
3315                                 buffer[0] = diq_start;
3316                 }
3317
3318                 if (mphase)
3319                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3320
3321                 last = (dev->phy.rev < 3) ? 6 : 7;
3322
3323                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3324                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3325                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3326                         if (dev->phy.rev < 3) {
3327                                 buffer[0] = 0;
3328                                 buffer[1] = 0;
3329                                 buffer[2] = 0;
3330                                 buffer[3] = 0;
3331                         }
3332                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3333                                                 buffer);
3334                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3335                                                 buffer);
3336                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3337                                                 buffer);
3338                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3339                                                 buffer);
3340                         length = 11;
3341                         if (dev->phy.rev < 3)
3342                                 length -= 2;
3343                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3344                                                 nphy->txiqlocal_bestc);
3345                         nphy->txiqlocal_coeffsvalid = true;
3346                         nphy->txiqlocal_chanspec.center_freq =
3347                                                         dev->phy.channel_freq;
3348                         nphy->txiqlocal_chanspec.channel_type =
3349                                                         dev->phy.channel_type;
3350                 } else {
3351                         length = 11;
3352                         if (dev->phy.rev < 3)
3353                                 length -= 2;
3354                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3355                                                 nphy->mphase_txcal_bestcoeffs);
3356                 }
3357
3358                 b43_nphy_stop_playback(dev);
3359                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3360         }
3361
3362         b43_nphy_tx_cal_phy_cleanup(dev);
3363         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3364
3365         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3366                 b43_nphy_tx_iq_workaround(dev);
3367
3368         if (dev->phy.rev >= 4)
3369                 nphy->hang_avoid = avoid;
3370
3371         b43_nphy_stay_in_carrier_search(dev, false);
3372
3373         return error;
3374 }
3375
3376 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3377 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3378 {
3379         struct b43_phy_n *nphy = dev->phy.n;
3380         u8 i;
3381         u16 buffer[7];
3382         bool equal = true;
3383
3384         if (!nphy->txiqlocal_coeffsvalid ||
3385             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3386             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3387                 return;
3388
3389         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3390         for (i = 0; i < 4; i++) {
3391                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3392                         equal = false;
3393                         break;
3394                 }
3395         }
3396
3397         if (!equal) {
3398                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3399                                         nphy->txiqlocal_bestc);
3400                 for (i = 0; i < 4; i++)
3401                         buffer[i] = 0;
3402                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3403                                         buffer);
3404                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3405                                         &nphy->txiqlocal_bestc[5]);
3406                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3407                                         &nphy->txiqlocal_bestc[5]);
3408         }
3409 }
3410
3411 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3412 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3413                         struct nphy_txgains target, u8 type, bool debug)
3414 {
3415         struct b43_phy_n *nphy = dev->phy.n;
3416         int i, j, index;
3417         u8 rfctl[2];
3418         u8 afectl_core;
3419         u16 tmp[6];
3420         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3421         u32 real, imag;
3422         enum ieee80211_band band;
3423
3424         u8 use;
3425         u16 cur_hpf;
3426         u16 lna[3] = { 3, 3, 1 };
3427         u16 hpf1[3] = { 7, 2, 0 };
3428         u16 hpf2[3] = { 2, 0, 0 };
3429         u32 power[3] = { };
3430         u16 gain_save[2];
3431         u16 cal_gain[2];
3432         struct nphy_iqcal_params cal_params[2];
3433         struct nphy_iq_est est;
3434         int ret = 0;
3435         bool playtone = true;
3436         int desired = 13;
3437
3438         b43_nphy_stay_in_carrier_search(dev, 1);
3439
3440         if (dev->phy.rev < 2)
3441                 b43_nphy_reapply_tx_cal_coeffs(dev);
3442         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3443         for (i = 0; i < 2; i++) {
3444                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3445                 cal_gain[i] = cal_params[i].cal_gain;
3446         }
3447         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3448
3449         for (i = 0; i < 2; i++) {
3450                 if (i == 0) {
3451                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3452                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3453                         afectl_core = B43_NPHY_AFECTL_C1;
3454                 } else {
3455                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3456                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3457                         afectl_core = B43_NPHY_AFECTL_C2;
3458                 }
3459
3460                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3461                 tmp[2] = b43_phy_read(dev, afectl_core);
3462                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3463                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3464                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3465
3466                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3467                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3468                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3469                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3470                                 (1 - i));
3471                 b43_phy_set(dev, afectl_core, 0x0006);
3472                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3473
3474                 band = b43_current_band(dev->wl);
3475
3476                 if (nphy->rxcalparams & 0xFF000000) {
3477                         if (band == IEEE80211_BAND_5GHZ)
3478                                 b43_phy_write(dev, rfctl[0], 0x140);
3479                         else
3480                                 b43_phy_write(dev, rfctl[0], 0x110);
3481                 } else {
3482                         if (band == IEEE80211_BAND_5GHZ)
3483                                 b43_phy_write(dev, rfctl[0], 0x180);
3484                         else
3485                                 b43_phy_write(dev, rfctl[0], 0x120);
3486                 }
3487
3488                 if (band == IEEE80211_BAND_5GHZ)
3489                         b43_phy_write(dev, rfctl[1], 0x148);
3490                 else
3491                         b43_phy_write(dev, rfctl[1], 0x114);
3492
3493                 if (nphy->rxcalparams & 0x10000) {
3494                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3495                                         (i + 1));
3496                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3497                                         (2 - i));
3498                 }
3499
3500                 for (j = 0; j < 4; j++) {
3501                         if (j < 3) {
3502                                 cur_lna = lna[j];
3503                                 cur_hpf1 = hpf1[j];
3504                                 cur_hpf2 = hpf2[j];
3505                         } else {
3506                                 if (power[1] > 10000) {
3507                                         use = 1;
3508                                         cur_hpf = cur_hpf1;
3509                                         index = 2;
3510                                 } else {
3511                                         if (power[0] > 10000) {
3512                                                 use = 1;
3513                                                 cur_hpf = cur_hpf1;
3514                                                 index = 1;
3515                                         } else {
3516                                                 index = 0;
3517                                                 use = 2;
3518                                                 cur_hpf = cur_hpf2;
3519                                         }
3520                                 }
3521                                 cur_lna = lna[index];
3522                                 cur_hpf1 = hpf1[index];
3523                                 cur_hpf2 = hpf2[index];
3524                                 cur_hpf += desired - hweight32(power[index]);
3525                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3526                                 if (use == 1)
3527                                         cur_hpf1 = cur_hpf;
3528                                 else
3529                                         cur_hpf2 = cur_hpf;
3530                         }
3531
3532                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3533                                         (cur_lna << 2));
3534                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3535                                                                         false);
3536                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3537                         b43_nphy_stop_playback(dev);
3538
3539                         if (playtone) {
3540                                 ret = b43_nphy_tx_tone(dev, 4000,
3541                                                 (nphy->rxcalparams & 0xFFFF),
3542                                                 false, false);
3543                                 playtone = false;
3544                         } else {
3545                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3546                                                         false, false);
3547                         }
3548
3549                         if (ret == 0) {
3550                                 if (j < 3) {
3551                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3552                                                                         false);
3553                                         if (i == 0) {
3554                                                 real = est.i0_pwr;
3555                                                 imag = est.q0_pwr;
3556                                         } else {
3557                                                 real = est.i1_pwr;
3558                                                 imag = est.q1_pwr;
3559                                         }
3560                                         power[i] = ((real + imag) / 1024) + 1;
3561                                 } else {
3562                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3563                                 }
3564                                 b43_nphy_stop_playback(dev);
3565                         }
3566
3567                         if (ret != 0)
3568                                 break;
3569                 }
3570
3571                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3572                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3573                 b43_phy_write(dev, rfctl[1], tmp[5]);
3574                 b43_phy_write(dev, rfctl[0], tmp[4]);
3575                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3576                 b43_phy_write(dev, afectl_core, tmp[2]);
3577                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3578
3579                 if (ret != 0)
3580                         break;
3581         }
3582
3583         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3584         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3585         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3586
3587         b43_nphy_stay_in_carrier_search(dev, 0);
3588
3589         return ret;
3590 }
3591
3592 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3593                         struct nphy_txgains target, u8 type, bool debug)
3594 {
3595         return -1;
3596 }
3597
3598 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3599 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3600                         struct nphy_txgains target, u8 type, bool debug)
3601 {
3602         if (dev->phy.rev >= 3)
3603                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3604         else
3605                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3606 }
3607
3608 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3609 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3610 {
3611         struct b43_phy *phy = &dev->phy;
3612         struct b43_phy_n *nphy = phy->n;
3613         /* u16 buf[16]; it's rev3+ */
3614
3615         nphy->phyrxchain = mask;
3616
3617         if (0 /* FIXME clk */)
3618                 return;
3619
3620         b43_mac_suspend(dev);
3621
3622         if (nphy->hang_avoid)
3623                 b43_nphy_stay_in_carrier_search(dev, true);
3624
3625         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3626                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3627
3628         if ((mask & 0x3) != 0x3) {
3629                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3630                 if (dev->phy.rev >= 3) {
3631                         /* TODO */
3632                 }
3633         } else {
3634                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3635                 if (dev->phy.rev >= 3) {
3636                         /* TODO */
3637                 }
3638         }
3639
3640         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3641
3642         if (nphy->hang_avoid)
3643                 b43_nphy_stay_in_carrier_search(dev, false);
3644
3645         b43_mac_enable(dev);
3646 }
3647
3648 /*
3649  * Init N-PHY
3650  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3651  */
3652 int b43_phy_initn(struct b43_wldev *dev)
3653 {
3654         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3655         struct b43_phy *phy = &dev->phy;
3656         struct b43_phy_n *nphy = phy->n;
3657         u8 tx_pwr_state;
3658         struct nphy_txgains target;
3659         u16 tmp;
3660         enum ieee80211_band tmp2;
3661         bool do_rssi_cal;
3662
3663         u16 clip[2];
3664         bool do_cal = false;
3665
3666         if ((dev->phy.rev >= 3) &&
3667            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3668            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3669                 switch (dev->dev->bus_type) {
3670 #ifdef CONFIG_B43_BCMA
3671                 case B43_BUS_BCMA:
3672                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3673                                       BCMA_CC_CHIPCTL, 0x40);
3674                         break;
3675 #endif
3676 #ifdef CONFIG_B43_SSB
3677                 case B43_BUS_SSB:
3678                         chipco_set32(&dev->dev->sdev->bus->chipco,
3679                                      SSB_CHIPCO_CHIPCTL, 0x40);
3680                         break;
3681 #endif
3682                 }
3683         }
3684         nphy->deaf_count = 0;
3685         b43_nphy_tables_init(dev);
3686         nphy->crsminpwr_adjusted = false;
3687         nphy->noisevars_adjusted = false;
3688
3689         /* Clear all overrides */
3690         if (dev->phy.rev >= 3) {
3691                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3692                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3693                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3694                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3695         } else {
3696                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3697         }
3698         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3699         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3700         if (dev->phy.rev < 6) {
3701                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3702                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3703         }
3704         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3705                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3706                        B43_NPHY_RFSEQMODE_TROVER));
3707         if (dev->phy.rev >= 3)
3708                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3709         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3710
3711         if (dev->phy.rev <= 2) {
3712                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3713                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3714                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3715                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3716         }
3717         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3718         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3719
3720         if (sprom->boardflags2_lo & 0x100 ||
3721             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3722              dev->dev->board_type == 0x8B))
3723                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3724         else
3725                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3726         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3727         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3728         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3729
3730         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3731         b43_nphy_update_txrx_chain(dev);
3732
3733         if (phy->rev < 2) {
3734                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3735                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3736         }
3737
3738         tmp2 = b43_current_band(dev->wl);
3739         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3740             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3741                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3742                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3743                                 nphy->papd_epsilon_offset[0] << 7);
3744                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3745                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3746                                 nphy->papd_epsilon_offset[1] << 7);
3747                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3748         } else if (phy->rev >= 5) {
3749                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3750         }
3751
3752         b43_nphy_workarounds(dev);
3753
3754         /* Reset CCA, in init code it differs a little from standard way */
3755         b43_phy_force_clock(dev, 1);
3756         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3757         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3758         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3759         b43_phy_force_clock(dev, 0);
3760
3761         b43_mac_phy_clock_set(dev, true);
3762
3763         b43_nphy_pa_override(dev, false);
3764         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3765         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3766         b43_nphy_pa_override(dev, true);
3767
3768         b43_nphy_classifier(dev, 0, 0);
3769         b43_nphy_read_clip_detection(dev, clip);
3770         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3771                 b43_nphy_bphy_init(dev);
3772
3773         tx_pwr_state = nphy->txpwrctrl;
3774         b43_nphy_tx_power_ctrl(dev, false);
3775         b43_nphy_tx_power_fix(dev);
3776         /* TODO N PHY TX Power Control Idle TSSI */
3777         /* TODO N PHY TX Power Control Setup */
3778
3779         if (phy->rev >= 3) {
3780                 /* TODO */
3781         } else {
3782                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3783                                         b43_ntab_tx_gain_rev0_1_2);
3784                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3785                                         b43_ntab_tx_gain_rev0_1_2);
3786         }
3787
3788         if (nphy->phyrxchain != 3)
3789                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3790         if (nphy->mphase_cal_phase_id > 0)
3791                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3792
3793         do_rssi_cal = false;
3794         if (phy->rev >= 3) {
3795                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3796                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3797                 else
3798                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3799
3800                 if (do_rssi_cal)
3801                         b43_nphy_rssi_cal(dev);
3802                 else
3803                         b43_nphy_restore_rssi_cal(dev);
3804         } else {
3805                 b43_nphy_rssi_cal(dev);
3806         }
3807
3808         if (!((nphy->measure_hold & 0x6) != 0)) {
3809                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3810                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3811                 else
3812                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3813
3814                 if (nphy->mute)
3815                         do_cal = false;
3816
3817                 if (do_cal) {
3818                         target = b43_nphy_get_tx_gains(dev);
3819
3820                         if (nphy->antsel_type == 2)
3821                                 b43_nphy_superswitch_init(dev, true);
3822                         if (nphy->perical != 2) {
3823                                 b43_nphy_rssi_cal(dev);
3824                                 if (phy->rev >= 3) {
3825                                         nphy->cal_orig_pwr_idx[0] =
3826                                             nphy->txpwrindex[0].index_internal;
3827                                         nphy->cal_orig_pwr_idx[1] =
3828                                             nphy->txpwrindex[1].index_internal;
3829                                         /* TODO N PHY Pre Calibrate TX Gain */
3830                                         target = b43_nphy_get_tx_gains(dev);
3831                                 }
3832                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3833                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3834                                                 b43_nphy_save_cal(dev);
3835                         } else if (nphy->mphase_cal_phase_id == 0)
3836                                 ;/* N PHY Periodic Calibration with arg 3 */
3837                 } else {
3838                         b43_nphy_restore_cal(dev);
3839                 }
3840         }
3841
3842         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3843         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3844         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3845         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3846         if (phy->rev >= 3 && phy->rev <= 6)
3847                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3848         b43_nphy_tx_lp_fbw(dev);
3849         if (phy->rev >= 3)
3850                 b43_nphy_spur_workaround(dev);
3851
3852         return 0;
3853 }
3854
3855 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3856 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3857                                 const struct b43_phy_n_sfo_cfg *e,
3858                                 struct ieee80211_channel *new_channel)
3859 {
3860         struct b43_phy *phy = &dev->phy;
3861         struct b43_phy_n *nphy = dev->phy.n;
3862
3863         u16 old_band_5ghz;
3864         u32 tmp32;
3865
3866         old_band_5ghz =
3867                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3868         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3869                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3870                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3871                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3872                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3873                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3874         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3875                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3876                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3877                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3878                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3879                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3880         }
3881
3882         b43_chantab_phy_upload(dev, e);
3883
3884         if (new_channel->hw_value == 14) {
3885                 b43_nphy_classifier(dev, 2, 0);
3886                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3887         } else {
3888                 b43_nphy_classifier(dev, 2, 2);
3889                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3890                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3891         }
3892
3893         if (!nphy->txpwrctrl)
3894                 b43_nphy_tx_power_fix(dev);
3895
3896         if (dev->phy.rev < 3)
3897                 b43_nphy_adjust_lna_gain_table(dev);
3898
3899         b43_nphy_tx_lp_fbw(dev);
3900
3901         if (dev->phy.rev >= 3 && 0) {
3902                 /* TODO */
3903         }
3904
3905         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3906
3907         if (phy->rev >= 3)
3908                 b43_nphy_spur_workaround(dev);
3909 }
3910
3911 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3912 static int b43_nphy_set_channel(struct b43_wldev *dev,
3913                                 struct ieee80211_channel *channel,
3914                                 enum nl80211_channel_type channel_type)
3915 {
3916         struct b43_phy *phy = &dev->phy;
3917
3918         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
3919         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
3920
3921         u8 tmp;
3922
3923         if (dev->phy.rev >= 3) {
3924                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3925                                                         channel->center_freq);
3926                 if (!tabent_r3)
3927                         return -ESRCH;
3928         } else {
3929                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3930                                                         channel->hw_value);
3931                 if (!tabent_r2)
3932                         return -ESRCH;
3933         }
3934
3935         /* Channel is set later in common code, but we need to set it on our
3936            own to let this function's subcalls work properly. */
3937         phy->channel = channel->hw_value;
3938         phy->channel_freq = channel->center_freq;
3939
3940         if (b43_channel_type_is_40mhz(phy->channel_type) !=
3941                 b43_channel_type_is_40mhz(channel_type))
3942                 ; /* TODO: BMAC BW Set (channel_type) */
3943
3944         if (channel_type == NL80211_CHAN_HT40PLUS)
3945                 b43_phy_set(dev, B43_NPHY_RXCTL,
3946                                 B43_NPHY_RXCTL_BSELU20);
3947         else if (channel_type == NL80211_CHAN_HT40MINUS)
3948                 b43_phy_mask(dev, B43_NPHY_RXCTL,
3949                                 ~B43_NPHY_RXCTL_BSELU20);
3950
3951         if (dev->phy.rev >= 3) {
3952                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3953                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3954                 b43_radio_2056_setup(dev, tabent_r3);
3955                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3956         } else {
3957                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3958                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3959                 b43_radio_2055_setup(dev, tabent_r2);
3960                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3961         }
3962
3963         return 0;
3964 }
3965
3966 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3967 {
3968         struct b43_phy_n *nphy;
3969
3970         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3971         if (!nphy)
3972                 return -ENOMEM;
3973         dev->phy.n = nphy;
3974
3975         return 0;
3976 }
3977
3978 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3979 {
3980         struct b43_phy *phy = &dev->phy;
3981         struct b43_phy_n *nphy = phy->n;
3982
3983         memset(nphy, 0, sizeof(*nphy));
3984
3985         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
3986         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3987         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3988         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
3989         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
3990         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
3991          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
3992         nphy->tx_pwr_idx[0] = 128;
3993         nphy->tx_pwr_idx[1] = 128;
3994 }
3995
3996 static void b43_nphy_op_free(struct b43_wldev *dev)
3997 {
3998         struct b43_phy *phy = &dev->phy;
3999         struct b43_phy_n *nphy = phy->n;
4000
4001         kfree(nphy);
4002         phy->n = NULL;
4003 }
4004
4005 static int b43_nphy_op_init(struct b43_wldev *dev)
4006 {
4007         return b43_phy_initn(dev);
4008 }
4009
4010 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4011 {
4012 #if B43_DEBUG
4013         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4014                 /* OFDM registers are onnly available on A/G-PHYs */
4015                 b43err(dev->wl, "Invalid OFDM PHY access at "
4016                        "0x%04X on N-PHY\n", offset);
4017                 dump_stack();
4018         }
4019         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4020                 /* Ext-G registers are only available on G-PHYs */
4021                 b43err(dev->wl, "Invalid EXT-G PHY access at "
4022                        "0x%04X on N-PHY\n", offset);
4023                 dump_stack();
4024         }
4025 #endif /* B43_DEBUG */
4026 }
4027
4028 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4029 {
4030         check_phyreg(dev, reg);
4031         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4032         return b43_read16(dev, B43_MMIO_PHY_DATA);
4033 }
4034
4035 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4036 {
4037         check_phyreg(dev, reg);
4038         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4039         b43_write16(dev, B43_MMIO_PHY_DATA, value);
4040 }
4041
4042 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4043                                  u16 set)
4044 {
4045         check_phyreg(dev, reg);
4046         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4047         b43_write16(dev, B43_MMIO_PHY_DATA,
4048                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4049 }
4050
4051 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4052 {
4053         /* Register 1 is a 32-bit register. */
4054         B43_WARN_ON(reg == 1);
4055         /* N-PHY needs 0x100 for read access */
4056         reg |= 0x100;
4057
4058         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4059         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4060 }
4061
4062 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4063 {
4064         /* Register 1 is a 32-bit register. */
4065         B43_WARN_ON(reg == 1);
4066
4067         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4068         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4069 }
4070
4071 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4072 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4073                                         bool blocked)
4074 {
4075         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4076                 b43err(dev->wl, "MAC not suspended\n");
4077
4078         if (blocked) {
4079                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4080                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4081                 if (dev->phy.rev >= 3) {
4082                         b43_radio_mask(dev, 0x09, ~0x2);
4083
4084                         b43_radio_write(dev, 0x204D, 0);
4085                         b43_radio_write(dev, 0x2053, 0);
4086                         b43_radio_write(dev, 0x2058, 0);
4087                         b43_radio_write(dev, 0x205E, 0);
4088                         b43_radio_mask(dev, 0x2062, ~0xF0);
4089                         b43_radio_write(dev, 0x2064, 0);
4090
4091                         b43_radio_write(dev, 0x304D, 0);
4092                         b43_radio_write(dev, 0x3053, 0);
4093                         b43_radio_write(dev, 0x3058, 0);
4094                         b43_radio_write(dev, 0x305E, 0);
4095                         b43_radio_mask(dev, 0x3062, ~0xF0);
4096                         b43_radio_write(dev, 0x3064, 0);
4097                 }
4098         } else {
4099                 if (dev->phy.rev >= 3) {
4100                         b43_radio_init2056(dev);
4101                         b43_switch_channel(dev, dev->phy.channel);
4102                 } else {
4103                         b43_radio_init2055(dev);
4104                 }
4105         }
4106 }
4107
4108 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4109 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4110 {
4111         u16 override = on ? 0x0 : 0x7FFF;
4112         u16 core = on ? 0xD : 0x00FD;
4113
4114         if (dev->phy.rev >= 3) {
4115                 if (on) {
4116                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4117                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4118                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4119                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4120                 } else {
4121                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4122                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4123                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4124                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4125                 }
4126         } else {
4127                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4128         }
4129 }
4130
4131 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4132                                       unsigned int new_channel)
4133 {
4134         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4135         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4136
4137         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4138                 if ((new_channel < 1) || (new_channel > 14))
4139                         return -EINVAL;
4140         } else {
4141                 if (new_channel > 200)
4142                         return -EINVAL;
4143         }
4144
4145         return b43_nphy_set_channel(dev, channel, channel_type);
4146 }
4147
4148 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4149 {
4150         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4151                 return 1;
4152         return 36;
4153 }
4154
4155 const struct b43_phy_operations b43_phyops_n = {
4156         .allocate               = b43_nphy_op_allocate,
4157         .free                   = b43_nphy_op_free,
4158         .prepare_structs        = b43_nphy_op_prepare_structs,
4159         .init                   = b43_nphy_op_init,
4160         .phy_read               = b43_nphy_op_read,
4161         .phy_write              = b43_nphy_op_write,
4162         .phy_maskset            = b43_nphy_op_maskset,
4163         .radio_read             = b43_nphy_op_radio_read,
4164         .radio_write            = b43_nphy_op_radio_write,
4165         .software_rfkill        = b43_nphy_op_software_rfkill,
4166         .switch_analog          = b43_nphy_op_switch_analog,
4167         .switch_channel         = b43_nphy_op_switch_channel,
4168         .get_default_chan       = b43_nphy_op_get_default_chan,
4169         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4170         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4171 };