drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "main.h"
  36
  37 struct nphy_txgains {
  38         u16 txgm[2];
  39         u16 pga[2];
  40         u16 pad[2];
  41         u16 ipa[2];
  42 };
  43
  44 struct nphy_iqcal_params {
  45         u16 txgm;
  46         u16 pga;
  47         u16 pad;
  48         u16 ipa;
  49         u16 cal_gain;
  50         u16 ncorr[5];
  51 };
  52
  53 struct nphy_iq_est {
  54         s32 iq0_prod;
  55         u32 i0_pwr;
  56         u32 q0_pwr;
  57         s32 iq1_prod;
  58         u32 i1_pwr;
  59         u32 q1_pwr;
  60 };
  61
  62 enum b43_nphy_rf_sequence {
  63         B43_RFSEQ_RX2TX,
  64         B43_RFSEQ_TX2RX,
  65         B43_RFSEQ_RESET2RX,
  66         B43_RFSEQ_UPDATE_GAINH,
  67         B43_RFSEQ_UPDATE_GAINL,
  68         B43_RFSEQ_UPDATE_GAINU,
  69 };
  70
  71 enum b43_nphy_rssi_type {
  72         B43_NPHY_RSSI_X = 0,
  73         B43_NPHY_RSSI_Y,
  74         B43_NPHY_RSSI_Z,
  75         B43_NPHY_RSSI_PWRDET,
  76         B43_NPHY_RSSI_TSSI_I,
  77         B43_NPHY_RSSI_TSSI_Q,
  78         B43_NPHY_RSSI_TBD,
  79 };
  80
  81 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
  82 {
  83         enum ieee80211_band band = b43_current_band(dev->wl);
  84         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  85                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
  86 }
  87
  88 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
  89 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
  90 {
  91         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  92                 if (dev->phy.rev >= 6) {
  93                         if (dev->dev->chip_id == 47162)
  94                                 return txpwrctrl_tx_gain_ipa_rev5;
  95                         return txpwrctrl_tx_gain_ipa_rev6;
  96                 } else if (dev->phy.rev >= 5) {
  97                         return txpwrctrl_tx_gain_ipa_rev5;
  98                 } else {
  99                         return txpwrctrl_tx_gain_ipa;
 100                 }
 101         } else {
 102                 return txpwrctrl_tx_gain_ipa_5g;
 103         }
 104 }
 105
 106 /**************************************************
 107  * RF (just without b43_nphy_rf_control_intc_override)
 108  **************************************************/
 109
 110 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
 111 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 112                                        enum b43_nphy_rf_sequence seq)
 113 {
 114         static const u16 trigger[] = {
 115                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 116                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 117                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 118                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 119                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 120                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 121         };
 122         int i;
 123         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
 124
 125         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 126
 127         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 128                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 129         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 130         for (i = 0; i < 200; i++) {
 131                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 132                         goto ok;
 133                 msleep(1);
 134         }
 135         b43err(dev->wl, "RF sequence status timeout\n");
 136 ok:
 137         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
 138 }
 139
 140 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
 141 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
 142                                                 u16 value, u8 core, bool off)
 143 {
 144         int i;
 145         u8 index = fls(field);
 146         u8 addr, en_addr, val_addr;
 147         /* we expect only one bit set */
 148         B43_WARN_ON(field & (~(1 << (index - 1))));
 149
 150         if (dev->phy.rev >= 3) {
 151                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
 152                 for (i = 0; i < 2; i++) {
 153                         if (index == 0 || index == 16) {
 154                                 b43err(dev->wl,
 155                                         "Unsupported RF Ctrl Override call\n");
 156                                 return;
 157                         }
 158
 159                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
 160                         en_addr = B43_PHY_N((i == 0) ?
 161                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
 162                         val_addr = B43_PHY_N((i == 0) ?
 163                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
 164
 165                         if (off) {
 166                                 b43_phy_mask(dev, en_addr, ~(field));
 167                                 b43_phy_mask(dev, val_addr,
 168                                                 ~(rf_ctrl->val_mask));
 169                         } else {
 170                                 if (core == 0 || ((1 << core) & i) != 0) {
 171                                         b43_phy_set(dev, en_addr, field);
 172                                         b43_phy_maskset(dev, val_addr,
 173                                                 ~(rf_ctrl->val_mask),
 174                                                 (value << rf_ctrl->val_shift));
 175                                 }
 176                         }
 177                 }
 178         } else {
 179                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
 180                 if (off) {
 181                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
 182                         value = 0;
 183                 } else {
 184                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
 185                 }
 186
 187                 for (i = 0; i < 2; i++) {
 188                         if (index <= 1 || index == 16) {
 189                                 b43err(dev->wl,
 190                                         "Unsupported RF Ctrl Override call\n");
 191                                 return;
 192                         }
 193
 194                         if (index == 2 || index == 10 ||
 195                             (index >= 13 && index <= 15)) {
 196                                 core = 1;
 197                         }
 198
 199                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
 200                         addr = B43_PHY_N((i == 0) ?
 201                                 rf_ctrl->addr0 : rf_ctrl->addr1);
 202
 203                         if ((core & (1 << i)) != 0)
 204                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
 205                                                 (value << rf_ctrl->shift));
 206
 207                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
 208                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 209                                         B43_NPHY_RFCTL_CMD_START);
 210                         udelay(1);
 211                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
 212                 }
 213         }
 214 }
 215
 216 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
 217 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
 218                                                 u16 value, u8 core)
 219 {
 220         u8 i, j;
 221         u16 reg, tmp, val;
 222
 223         B43_WARN_ON(dev->phy.rev < 3);
 224         B43_WARN_ON(field > 4);
 225
 226         for (i = 0; i < 2; i++) {
 227                 if ((core == 1 && i == 1) || (core == 2 && !i))
 228                         continue;
 229
 230                 reg = (i == 0) ?
 231                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
 232                 b43_phy_mask(dev, reg, 0xFBFF);
 233
 234                 switch (field) {
 235                 case 0:
 236                         b43_phy_write(dev, reg, 0);
 237                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 238                         break;
 239                 case 1:
 240                         if (!i) {
 241                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
 242                                                 0xFC3F, (value << 6));
 243                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
 244                                                 0xFFFE, 1);
 245                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 246                                                 B43_NPHY_RFCTL_CMD_START);
 247                                 for (j = 0; j < 100; j++) {
 248                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
 249                                                 j = 0;
 250                                                 break;
 251                                         }
 252                                         udelay(10);
 253                                 }
 254                                 if (j)
 255                                         b43err(dev->wl,
 256                                                 "intc override timeout\n");
 257                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
 258                                                 0xFFFE);
 259                         } else {
 260                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
 261                                                 0xFC3F, (value << 6));
 262                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 263                                                 0xFFFE, 1);
 264                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 265                                                 B43_NPHY_RFCTL_CMD_RXTX);
 266                                 for (j = 0; j < 100; j++) {
 267                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
 268                                                 j = 0;
 269                                                 break;
 270                                         }
 271                                         udelay(10);
 272                                 }
 273                                 if (j)
 274                                         b43err(dev->wl,
 275                                                 "intc override timeout\n");
 276                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
 277                                                 0xFFFE);
 278                         }
 279                         break;
 280                 case 2:
 281                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 282                                 tmp = 0x0020;
 283                                 val = value << 5;
 284                         } else {
 285                                 tmp = 0x0010;
 286                                 val = value << 4;
 287                         }
 288                         b43_phy_maskset(dev, reg, ~tmp, val);
 289                         break;
 290                 case 3:
 291                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 292                                 tmp = 0x0001;
 293                                 val = value;
 294                         } else {
 295                                 tmp = 0x0004;
 296                                 val = value << 2;
 297                         }
 298                         b43_phy_maskset(dev, reg, ~tmp, val);
 299                         break;
 300                 case 4:
 301                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 302                                 tmp = 0x0002;
 303                                 val = value << 1;
 304                         } else {
 305                                 tmp = 0x0008;
 306                                 val = value << 3;
 307                         }
 308                         b43_phy_maskset(dev, reg, ~tmp, val);
 309                         break;
 310                 }
 311         }
 312 }
 313
 314 /**************************************************
 315  * Various PHY ops
 316  **************************************************/
 317
 318 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 319 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 320                                           const u16 *clip_st)
 321 {
 322         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 323         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 324 }
 325
 326 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 327 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 328 {
 329         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 330         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 331 }
 332
 333 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 334 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 335 {
 336         u16 tmp;
 337
 338         if (dev->dev->core_rev == 16)
 339                 b43_mac_suspend(dev);
 340
 341         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 342         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 343                 B43_NPHY_CLASSCTL_WAITEDEN);
 344         tmp &= ~mask;
 345         tmp |= (val & mask);
 346         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 347
 348         if (dev->dev->core_rev == 16)
 349                 b43_mac_enable(dev);
 350
 351         return tmp;
 352 }
 353
 354 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 355 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 356 {
 357         u16 bbcfg;
 358
 359         b43_phy_force_clock(dev, 1);
 360         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 361         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 362         udelay(1);
 363         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 364         b43_phy_force_clock(dev, 0);
 365         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 366 }
 367
 368 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 369 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 370 {
 371         struct b43_phy *phy = &dev->phy;
 372         struct b43_phy_n *nphy = phy->n;
 373
 374         if (enable) {
 375                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
 376                 if (nphy->deaf_count++ == 0) {
 377                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 378                         b43_nphy_classifier(dev, 0x7, 0);
 379                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 380                         b43_nphy_write_clip_detection(dev, clip);
 381                 }
 382                 b43_nphy_reset_cca(dev);
 383         } else {
 384                 if (--nphy->deaf_count == 0) {
 385                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 386                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 387                 }
 388         }
 389 }
 390
 391 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
 392 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
 393                                         u8 *events, u8 *delays, u8 length)
 394 {
 395         struct b43_phy_n *nphy = dev->phy.n;
 396         u8 i;
 397         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
 398         u16 offset1 = cmd << 4;
 399         u16 offset2 = offset1 + 0x80;
 400
 401         if (nphy->hang_avoid)
 402                 b43_nphy_stay_in_carrier_search(dev, true);
 403
 404         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
 405         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
 406
 407         for (i = length; i < 16; i++) {
 408                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
 409                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
 410         }
 411
 412         if (nphy->hang_avoid)
 413                 b43_nphy_stay_in_carrier_search(dev, false);
 414 }
 415
 416 /**************************************************
 417  * Radio 0x2056
 418  **************************************************/
 419
 420 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 421                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 422 {
 423         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 424         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 425         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 426         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 427         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 428         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 429                                         e->radio_syn_pll_loopfilter1);
 430         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 431                                         e->radio_syn_pll_loopfilter2);
 432         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 433                                         e->radio_syn_pll_loopfilter3);
 434         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 435                                         e->radio_syn_pll_loopfilter4);
 436         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 437                                         e->radio_syn_pll_loopfilter5);
 438         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 439                                         e->radio_syn_reserved_addr27);
 440         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 441                                         e->radio_syn_reserved_addr28);
 442         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 443                                         e->radio_syn_reserved_addr29);
 444         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 445                                         e->radio_syn_logen_vcobuf1);
 446         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 447         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 448         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 449
 450         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 451                                         e->radio_rx0_lnaa_tune);
 452         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 453                                         e->radio_rx0_lnag_tune);
 454
 455         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 456                                         e->radio_tx0_intpaa_boost_tune);
 457         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 458                                         e->radio_tx0_intpag_boost_tune);
 459         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 460                                         e->radio_tx0_pada_boost_tune);
 461         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 462                                         e->radio_tx0_padg_boost_tune);
 463         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 464                                         e->radio_tx0_pgaa_boost_tune);
 465         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 466                                         e->radio_tx0_pgag_boost_tune);
 467         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 468                                         e->radio_tx0_mixa_boost_tune);
 469         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 470                                         e->radio_tx0_mixg_boost_tune);
 471
 472         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 473                                         e->radio_rx1_lnaa_tune);
 474         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 475                                         e->radio_rx1_lnag_tune);
 476
 477         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 478                                         e->radio_tx1_intpaa_boost_tune);
 479         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 480                                         e->radio_tx1_intpag_boost_tune);
 481         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 482                                         e->radio_tx1_pada_boost_tune);
 483         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 484                                         e->radio_tx1_padg_boost_tune);
 485         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 486                                         e->radio_tx1_pgaa_boost_tune);
 487         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 488                                         e->radio_tx1_pgag_boost_tune);
 489         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 490                                         e->radio_tx1_mixa_boost_tune);
 491         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 492                                         e->radio_tx1_mixg_boost_tune);
 493 }
 494
 495 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 496 static void b43_radio_2056_setup(struct b43_wldev *dev,
 497                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 498 {
 499         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 500         enum ieee80211_band band = b43_current_band(dev->wl);
 501         u16 offset;
 502         u8 i;
 503         u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
 504
 505         B43_WARN_ON(dev->phy.rev < 3);
 506
 507         b43_chantab_radio_2056_upload(dev, e);
 508         b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
 509
 510         if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
 511             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 512                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 513                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 514                 if (dev->dev->chip_id == 0x4716) {
 515                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
 516                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
 517                 } else {
 518                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
 519                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
 520                 }
 521         }
 522         if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
 523             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 524                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 525                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 526                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
 527                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
 528         }
 529
 530         if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
 531                 for (i = 0; i < 2; i++) {
 532                         offset = i ? B2056_TX1 : B2056_TX0;
 533                         if (dev->phy.rev >= 5) {
 534                                 b43_radio_write(dev,
 535                                         offset | B2056_TX_PADG_IDAC, 0xcc);
 536
 537                                 if (dev->dev->chip_id == 0x4716) {
 538                                         bias = 0x40;
 539                                         cbias = 0x45;
 540                                         pag_boost = 0x5;
 541                                         pgag_boost = 0x33;
 542                                         mixg_boost = 0x55;
 543                                 } else {
 544                                         bias = 0x25;
 545                                         cbias = 0x20;
 546                                         pag_boost = 0x4;
 547                                         pgag_boost = 0x03;
 548                                         mixg_boost = 0x65;
 549                                 }
 550                                 padg_boost = 0x77;
 551
 552                                 b43_radio_write(dev,
 553                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 554                                         bias);
 555                                 b43_radio_write(dev,
 556                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 557                                         bias);
 558                                 b43_radio_write(dev,
 559                                         offset | B2056_TX_INTPAG_CASCBIAS,
 560                                         cbias);
 561                                 b43_radio_write(dev,
 562                                         offset | B2056_TX_INTPAG_BOOST_TUNE,
 563                                         pag_boost);
 564                                 b43_radio_write(dev,
 565                                         offset | B2056_TX_PGAG_BOOST_TUNE,
 566                                         pgag_boost);
 567                                 b43_radio_write(dev,
 568                                         offset | B2056_TX_PADG_BOOST_TUNE,
 569                                         padg_boost);
 570                                 b43_radio_write(dev,
 571                                         offset | B2056_TX_MIXG_BOOST_TUNE,
 572                                         mixg_boost);
 573                         } else {
 574                                 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
 575                                 b43_radio_write(dev,
 576                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 577                                         bias);
 578                                 b43_radio_write(dev,
 579                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 580                                         bias);
 581                                 b43_radio_write(dev,
 582                                         offset | B2056_TX_INTPAG_CASCBIAS,
 583                                         0x30);
 584                         }
 585                         b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
 586                 }
 587         } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
 588                 /* TODO */
 589         }
 590
 591         udelay(50);
 592         /* VCO calibration */
 593         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 594         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 595         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 596         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 597         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 598         udelay(300);
 599 }
 600
 601 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 602 {
 603         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 604                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 605         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 606         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 607                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 608         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 609                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 610         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 611                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 612 }
 613
 614 static void b43_radio_init2056_post(struct b43_wldev *dev)
 615 {
 616         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 617         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 618         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 619         msleep(1);
 620         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 621         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 622         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 623         /*
 624         if (nphy->init_por)
 625                 Call Radio 2056 Recalibrate
 626         */
 627 }
 628
 629 /*
 630  * Initialize a Broadcom 2056 N-radio
 631  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 632  */
 633 static void b43_radio_init2056(struct b43_wldev *dev)
 634 {
 635         b43_radio_init2056_pre(dev);
 636         b2056_upload_inittabs(dev, 0, 0);
 637         b43_radio_init2056_post(dev);
 638 }
 639
 640 /**************************************************
 641  * Radio 0x2055
 642  **************************************************/
 643
 644 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 645                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 646 {
 647         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 648         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 649         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 650         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 651         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 652
 653         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 654         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 655         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 656         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 657         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 658
 659         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 660         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 661         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 662         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 663         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 664
 665         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 666         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 667         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 668         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 669         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 670
 671         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 672         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 673         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 674         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 675         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 676
 677         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 678         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 679 }
 680
 681 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 682 static void b43_radio_2055_setup(struct b43_wldev *dev,
 683                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 684 {
 685         B43_WARN_ON(dev->phy.rev >= 3);
 686
 687         b43_chantab_radio_upload(dev, e);
 688         udelay(50);
 689         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 690         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 691         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 692         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 693         udelay(300);
 694 }
 695
 696 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 697 {
 698         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 699                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 700         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 701                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 702                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 703         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 704                     B43_NPHY_RFCTL_CMD_PORFORCE);
 705 }
 706
 707 static void b43_radio_init2055_post(struct b43_wldev *dev)
 708 {
 709         struct b43_phy_n *nphy = dev->phy.n;
 710         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 711         int i;
 712         u16 val;
 713         bool workaround = false;
 714
 715         if (sprom->revision < 4)
 716                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
 717                               && dev->dev->board_type == 0x46D
 718                               && dev->dev->board_rev >= 0x41);
 719         else
 720                 workaround =
 721                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 722
 723         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 724         if (workaround) {
 725                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 726                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 727         }
 728         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 729         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 730         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 731         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 732         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 733         msleep(1);
 734         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 735         for (i = 0; i < 200; i++) {
 736                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 737                 if (val & 0x80) {
 738                         i = 0;
 739                         break;
 740                 }
 741                 udelay(10);
 742         }
 743         if (i)
 744                 b43err(dev->wl, "radio post init timeout\n");
 745         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 746         b43_switch_channel(dev, dev->phy.channel);
 747         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 748         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 749         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 750         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 751         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 752         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 753         if (!nphy->gain_boost) {
 754                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 755                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 756         } else {
 757                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 758                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 759         }
 760         udelay(2);
 761 }
 762
 763 /*
 764  * Initialize a Broadcom 2055 N-radio
 765  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 766  */
 767 static void b43_radio_init2055(struct b43_wldev *dev)
 768 {
 769         b43_radio_init2055_pre(dev);
 770         if (b43_status(dev) < B43_STAT_INITIALIZED) {
 771                 /* Follow wl, not specs. Do not force uploading all regs */
 772                 b2055_upload_inittab(dev, 0, 0);
 773         } else {
 774                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 775                 b2055_upload_inittab(dev, ghz5, 0);
 776         }
 777         b43_radio_init2055_post(dev);
 778 }
 779
 780 /**************************************************
 781  * Samples
 782  **************************************************/
 783
 784 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
 785 static int b43_nphy_load_samples(struct b43_wldev *dev,
 786                                         struct b43_c32 *samples, u16 len) {
 787         struct b43_phy_n *nphy = dev->phy.n;
 788         u16 i;
 789         u32 *data;
 790
 791         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
 792         if (!data) {
 793                 b43err(dev->wl, "allocation for samples loading failed\n");
 794                 return -ENOMEM;
 795         }
 796         if (nphy->hang_avoid)
 797                 b43_nphy_stay_in_carrier_search(dev, 1);
 798
 799         for (i = 0; i < len; i++) {
 800                 data[i] = (samples[i].i & 0x3FF << 10);
 801                 data[i] |= samples[i].q & 0x3FF;
 802         }
 803         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
 804
 805         kfree(data);
 806         if (nphy->hang_avoid)
 807                 b43_nphy_stay_in_carrier_search(dev, 0);
 808         return 0;
 809 }
 810
 811 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
 812 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
 813                                         bool test)
 814 {
 815         int i;
 816         u16 bw, len, rot, angle;
 817         struct b43_c32 *samples;
 818
 819
 820         bw = (dev->phy.is_40mhz) ? 40 : 20;
 821         len = bw << 3;
 822
 823         if (test) {
 824                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
 825                         bw = 82;
 826                 else
 827                         bw = 80;
 828
 829                 if (dev->phy.is_40mhz)
 830                         bw <<= 1;
 831
 832                 len = bw << 1;
 833         }
 834
 835         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
 836         if (!samples) {
 837                 b43err(dev->wl, "allocation for samples generation failed\n");
 838                 return 0;
 839         }
 840         rot = (((freq * 36) / bw) << 16) / 100;
 841         angle = 0;
 842
 843         for (i = 0; i < len; i++) {
 844                 samples[i] = b43_cordic(angle);
 845                 angle += rot;
 846                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
 847                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
 848         }
 849
 850         i = b43_nphy_load_samples(dev, samples, len);
 851         kfree(samples);
 852         return (i < 0) ? 0 : len;
 853 }
 854
 855 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
 856 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
 857                                         u16 wait, bool iqmode, bool dac_test)
 858 {
 859         struct b43_phy_n *nphy = dev->phy.n;
 860         int i;
 861         u16 seq_mode;
 862         u32 tmp;
 863
 864         if (nphy->hang_avoid)
 865                 b43_nphy_stay_in_carrier_search(dev, true);
 866
 867         if ((nphy->bb_mult_save & 0x80000000) == 0) {
 868                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
 869                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
 870         }
 871
 872         if (!dev->phy.is_40mhz)
 873                 tmp = 0x6464;
 874         else
 875                 tmp = 0x4747;
 876         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 877
 878         if (nphy->hang_avoid)
 879                 b43_nphy_stay_in_carrier_search(dev, false);
 880
 881         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
 882
 883         if (loops != 0xFFFF)
 884                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
 885         else
 886                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
 887
 888         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
 889
 890         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
 891
 892         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
 893         if (iqmode) {
 894                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
 895                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
 896         } else {
 897                 if (dac_test)
 898                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
 899                 else
 900                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
 901         }
 902         for (i = 0; i < 100; i++) {
 903                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
 904                         i = 0;
 905                         break;
 906                 }
 907                 udelay(10);
 908         }
 909         if (i)
 910                 b43err(dev->wl, "run samples timeout\n");
 911
 912         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
 913 }
 914
 915 /**************************************************
 916  * RSSI
 917  **************************************************/
 918
 919 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
 920 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
 921                                         s8 offset, u8 core, u8 rail,
 922                                         enum b43_nphy_rssi_type type)
 923 {
 924         u16 tmp;
 925         bool core1or5 = (core == 1) || (core == 5);
 926         bool core2or5 = (core == 2) || (core == 5);
 927
 928         offset = clamp_val(offset, -32, 31);
 929         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
 930
 931         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
 932                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
 933         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
 934                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
 935         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
 936                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
 937         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
 938                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
 939
 940         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
 941                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
 942         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
 943                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
 944         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
 945                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
 946         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
 947                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
 948
 949         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
 950                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
 951         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
 952                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
 953         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
 954                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
 955         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
 956                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
 957
 958         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
 959                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
 960         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
 961                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
 962         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
 963                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
 964         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
 965                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
 966
 967         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
 968                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
 969         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
 970                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
 971         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
 972                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
 973         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
 974                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
 975
 976         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
 977                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
 978         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
 979                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
 980
 981         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
 982                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
 983         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
 984                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
 985 }
 986
 987 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
 988 {
 989         u8 i;
 990         u16 reg, val;
 991
 992         if (code == 0) {
 993                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
 994                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
 995                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
 996                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
 997                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
 998                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
 999                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1000                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1001         } else {
1002                 for (i = 0; i < 2; i++) {
1003                         if ((code == 1 && i == 1) || (code == 2 && !i))
1004                                 continue;
1005
1006                         reg = (i == 0) ?
1007                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1008                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1009
1010                         if (type < 3) {
1011                                 reg = (i == 0) ?
1012                                         B43_NPHY_AFECTL_C1 :
1013                                         B43_NPHY_AFECTL_C2;
1014                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1015
1016                                 reg = (i == 0) ?
1017                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1018                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1019                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1020
1021                                 if (type == 0)
1022                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1023                                 else if (type == 1)
1024                                         val = 16;
1025                                 else
1026                                         val = 32;
1027                                 b43_phy_set(dev, reg, val);
1028
1029                                 reg = (i == 0) ?
1030                                         B43_NPHY_TXF_40CO_B1S0 :
1031                                         B43_NPHY_TXF_40CO_B32S1;
1032                                 b43_phy_set(dev, reg, 0x0020);
1033                         } else {
1034                                 if (type == 6)
1035                                         val = 0x0100;
1036                                 else if (type == 3)
1037                                         val = 0x0200;
1038                                 else
1039                                         val = 0x0300;
1040
1041                                 reg = (i == 0) ?
1042                                         B43_NPHY_AFECTL_C1 :
1043                                         B43_NPHY_AFECTL_C2;
1044
1045                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1046                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1047
1048                                 if (type != 3 && type != 6) {
1049                                         enum ieee80211_band band =
1050                                                 b43_current_band(dev->wl);
1051
1052                                         if (b43_nphy_ipa(dev))
1053                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1054                                         else
1055                                                 val = 0x11;
1056                                         reg = (i == 0) ? 0x2000 : 0x3000;
1057                                         reg |= B2055_PADDRV;
1058                                         b43_radio_write16(dev, reg, val);
1059
1060                                         reg = (i == 0) ?
1061                                                 B43_NPHY_AFECTL_OVER1 :
1062                                                 B43_NPHY_AFECTL_OVER;
1063                                         b43_phy_set(dev, reg, 0x0200);
1064                                 }
1065                         }
1066                 }
1067         }
1068 }
1069
1070 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1071 {
1072         u16 val;
1073
1074         if (type < 3)
1075                 val = 0;
1076         else if (type == 6)
1077                 val = 1;
1078         else if (type == 3)
1079                 val = 2;
1080         else
1081                 val = 3;
1082
1083         val = (val << 12) | (val << 14);
1084         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1085         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1086
1087         if (type < 3) {
1088                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1089                                 (type + 1) << 4);
1090                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1091                                 (type + 1) << 4);
1092         }
1093
1094         if (code == 0) {
1095                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1096                 if (type < 3) {
1097                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1098                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1099                                   B43_NPHY_RFCTL_CMD_CORESEL));
1100                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1101                                 ~(0x1 << 12 |
1102                                   0x1 << 5 |
1103                                   0x1 << 1 |
1104                                   0x1));
1105                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1106                                 ~B43_NPHY_RFCTL_CMD_START);
1107                         udelay(20);
1108                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1109                 }
1110         } else {
1111                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1112                 if (type < 3) {
1113                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1114                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1115                                   B43_NPHY_RFCTL_CMD_CORESEL),
1116                                 (B43_NPHY_RFCTL_CMD_RXEN |
1117                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1118                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1119                                 (0x1 << 12 |
1120                                   0x1 << 5 |
1121                                   0x1 << 1 |
1122                                   0x1));
1123                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1124                                 B43_NPHY_RFCTL_CMD_START);
1125                         udelay(20);
1126                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1127                 }
1128         }
1129 }
1130
1131 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1132 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1133 {
1134         if (dev->phy.rev >= 3)
1135                 b43_nphy_rev3_rssi_select(dev, code, type);
1136         else
1137                 b43_nphy_rev2_rssi_select(dev, code, type);
1138 }
1139
1140 /**************************************************
1141  * Others
1142  **************************************************/
1143
1144 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
1145 {//TODO
1146 }
1147
1148 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
1149 {//TODO
1150 }
1151
1152 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
1153                                                         bool ignore_tssi)
1154 {//TODO
1155         return B43_TXPWR_RES_DONE;
1156 }
1157
1158 static void b43_chantab_phy_upload(struct b43_wldev *dev,
1159                                    const struct b43_phy_n_sfo_cfg *e)
1160 {
1161         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
1162         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
1163         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
1164         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
1165         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
1166         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
1167 }
1168
1169 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
1170 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
1171 {
1172         struct b43_phy_n *nphy = dev->phy.n;
1173         u8 i;
1174         u16 bmask, val, tmp;
1175         enum ieee80211_band band = b43_current_band(dev->wl);
1176
1177         if (nphy->hang_avoid)
1178                 b43_nphy_stay_in_carrier_search(dev, 1);
1179
1180         nphy->txpwrctrl = enable;
1181         if (!enable) {
1182                 if (dev->phy.rev >= 3 &&
1183                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
1184                      (B43_NPHY_TXPCTL_CMD_COEFF |
1185                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
1186                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
1187                         /* We disable enabled TX pwr ctl, save it's state */
1188                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
1189                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
1190                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
1191                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
1192                 }
1193
1194                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
1195                 for (i = 0; i < 84; i++)
1196                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
1197
1198                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
1199                 for (i = 0; i < 84; i++)
1200                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
1201
1202                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
1203                 if (dev->phy.rev >= 3)
1204                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
1205                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
1206
1207                 if (dev->phy.rev >= 3) {
1208                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
1209                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
1210                 } else {
1211                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
1212                 }
1213
1214                 if (dev->phy.rev == 2)
1215                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
1216                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
1217                 else if (dev->phy.rev < 2)
1218                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
1219                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
1220
1221                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
1222                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
1223         } else {
1224                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
1225                                     nphy->adj_pwr_tbl);
1226                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
1227                                     nphy->adj_pwr_tbl);
1228
1229                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
1230                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
1231                 /* wl does useless check for "enable" param here */
1232                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
1233                 if (dev->phy.rev >= 3) {
1234                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
1235                         if (val)
1236                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
1237                 }
1238                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
1239
1240                 if (band == IEEE80211_BAND_5GHZ) {
1241                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
1242                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
1243                         if (dev->phy.rev > 1)
1244                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
1245                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
1246                                                 0x64);
1247                 }
1248
1249                 if (dev->phy.rev >= 3) {
1250                         if (nphy->tx_pwr_idx[0] != 128 &&
1251                             nphy->tx_pwr_idx[1] != 128) {
1252                                 /* Recover TX pwr ctl state */
1253                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
1254                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
1255                                                 nphy->tx_pwr_idx[0]);
1256                                 if (dev->phy.rev > 1)
1257                                         b43_phy_maskset(dev,
1258                                                 B43_NPHY_TXPCTL_INIT,
1259                                                 ~0xff, nphy->tx_pwr_idx[1]);
1260                         }
1261                 }
1262
1263                 if (dev->phy.rev >= 3) {
1264                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
1265                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
1266                 } else {
1267                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
1268                 }
1269
1270                 if (dev->phy.rev == 2)
1271                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
1272                 else if (dev->phy.rev < 2)
1273                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
1274
1275                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
1276                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
1277
1278                 if (b43_nphy_ipa(dev)) {
1279                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
1280                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
1281                 }
1282         }
1283
1284         if (nphy->hang_avoid)
1285                 b43_nphy_stay_in_carrier_search(dev, 0);
1286 }
1287
1288 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
1289 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
1290 {
1291         struct b43_phy_n *nphy = dev->phy.n;
1292         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1293
1294         u8 txpi[2], bbmult, i;
1295         u16 tmp, radio_gain, dac_gain;
1296         u16 freq = dev->phy.channel_freq;
1297         u32 txgain;
1298         /* u32 gaintbl; rev3+ */
1299
1300         if (nphy->hang_avoid)
1301                 b43_nphy_stay_in_carrier_search(dev, 1);
1302
1303         if (dev->phy.rev >= 7) {
1304                 txpi[0] = txpi[1] = 30;
1305         } else if (dev->phy.rev >= 3) {
1306                 txpi[0] = 40;
1307                 txpi[1] = 40;
1308         } else if (sprom->revision < 4) {
1309                 txpi[0] = 72;
1310                 txpi[1] = 72;
1311         } else {
1312                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1313                         txpi[0] = sprom->txpid2g[0];
1314                         txpi[1] = sprom->txpid2g[1];
1315                 } else if (freq >= 4900 && freq < 5100) {
1316                         txpi[0] = sprom->txpid5gl[0];
1317                         txpi[1] = sprom->txpid5gl[1];
1318                 } else if (freq >= 5100 && freq < 5500) {
1319                         txpi[0] = sprom->txpid5g[0];
1320                         txpi[1] = sprom->txpid5g[1];
1321                 } else if (freq >= 5500) {
1322                         txpi[0] = sprom->txpid5gh[0];
1323                         txpi[1] = sprom->txpid5gh[1];
1324                 } else {
1325                         txpi[0] = 91;
1326                         txpi[1] = 91;
1327                 }
1328         }
1329         if (dev->phy.rev < 7 &&
1330             (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
1331                 txpi[0] = txpi[1] = 91;
1332
1333         /*
1334         for (i = 0; i < 2; i++) {
1335                 nphy->txpwrindex[i].index_internal = txpi[i];
1336                 nphy->txpwrindex[i].index_internal_save = txpi[i];
1337         }
1338         */
1339
1340         for (i = 0; i < 2; i++) {
1341                 if (dev->phy.rev >= 3) {
1342                         if (b43_nphy_ipa(dev)) {
1343                                 txgain = *(b43_nphy_get_ipa_gain_table(dev) +
1344                                                 txpi[i]);
1345                         } else if (b43_current_band(dev->wl) ==
1346                                    IEEE80211_BAND_5GHZ) {
1347                                 /* FIXME: use 5GHz tables */
1348                                 txgain =
1349                                         b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
1350                         } else {
1351                                 if (dev->phy.rev >= 5 &&
1352                                     sprom->fem.ghz5.extpa_gain == 3)
1353                                         ; /* FIXME: 5GHz_txgain_HiPwrEPA */
1354                                 txgain =
1355                                         b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
1356                         }
1357                         radio_gain = (txgain >> 16) & 0x1FFFF;
1358                 } else {
1359                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
1360                         radio_gain = (txgain >> 16) & 0x1FFF;
1361                 }
1362
1363                 if (dev->phy.rev >= 7)
1364                         dac_gain = (txgain >> 8) & 0x7;
1365                 else
1366                         dac_gain = (txgain >> 8) & 0x3F;
1367                 bbmult = txgain & 0xFF;
1368
1369                 if (dev->phy.rev >= 3) {
1370                         if (i == 0)
1371                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
1372                         else
1373                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
1374                 } else {
1375                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
1376                 }
1377
1378                 if (i == 0)
1379                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
1380                 else
1381                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
1382
1383                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
1384
1385                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
1386                 if (i == 0)
1387                         tmp = (tmp & 0x00FF) | (bbmult << 8);
1388                 else
1389                         tmp = (tmp & 0xFF00) | bbmult;
1390                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
1391
1392                 if (b43_nphy_ipa(dev)) {
1393                         u32 tmp32;
1394                         u16 reg = (i == 0) ?
1395                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
1396                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
1397                                                               576 + txpi[i]));
1398                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
1399                         b43_phy_set(dev, reg, 0x4);
1400                 }
1401         }
1402
1403         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
1404
1405         if (nphy->hang_avoid)
1406                 b43_nphy_stay_in_carrier_search(dev, 0);
1407 }
1408
1409 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
1410 {
1411         struct b43_phy *phy = &dev->phy;
1412
1413         const u32 *table = NULL;
1414 #if 0
1415         TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
1416         u32 rfpwr_offset;
1417         u8 pga_gain;
1418         int i;
1419 #endif
1420
1421         if (phy->rev >= 3) {
1422                 if (b43_nphy_ipa(dev)) {
1423                         table = b43_nphy_get_ipa_gain_table(dev);
1424                 } else {
1425                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1426                                 if (phy->rev == 3)
1427                                         table = b43_ntab_tx_gain_rev3_5ghz;
1428                                 if (phy->rev == 4)
1429                                         table = b43_ntab_tx_gain_rev4_5ghz;
1430                                 else
1431                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
1432                         } else {
1433                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
1434                         }
1435                 }
1436         } else {
1437                 table = b43_ntab_tx_gain_rev0_1_2;
1438         }
1439         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
1440         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
1441
1442         if (phy->rev >= 3) {
1443 #if 0
1444                 nphy->gmval = (table[0] >> 16) & 0x7000;
1445
1446                 for (i = 0; i < 128; i++) {
1447                         pga_gain = (table[i] >> 24) & 0xF;
1448                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1449                                 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
1450                         else
1451                                 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
1452                         b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
1453                                        rfpwr_offset);
1454                         b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
1455                                        rfpwr_offset);
1456                 }
1457 #endif
1458         }
1459 }
1460
1461 /*
1462  * Upload the N-PHY tables.
1463  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
1464  */
1465 static void b43_nphy_tables_init(struct b43_wldev *dev)
1466 {
1467         if (dev->phy.rev < 3)
1468                 b43_nphy_rev0_1_2_tables_init(dev);
1469         else
1470                 b43_nphy_rev3plus_tables_init(dev);
1471 }
1472
1473 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
1474 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
1475 {
1476         struct b43_phy_n *nphy = dev->phy.n;
1477         enum ieee80211_band band;
1478         u16 tmp;
1479
1480         if (!enable) {
1481                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
1482                                                        B43_NPHY_RFCTL_INTC1);
1483                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
1484                                                        B43_NPHY_RFCTL_INTC2);
1485                 band = b43_current_band(dev->wl);
1486                 if (dev->phy.rev >= 3) {
1487                         if (band == IEEE80211_BAND_5GHZ)
1488                                 tmp = 0x600;
1489                         else
1490                                 tmp = 0x480;
1491                 } else {
1492                         if (band == IEEE80211_BAND_5GHZ)
1493                                 tmp = 0x180;
1494                         else
1495                                 tmp = 0x120;
1496                 }
1497                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
1498                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
1499         } else {
1500                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
1501                                 nphy->rfctrl_intc1_save);
1502                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
1503                                 nphy->rfctrl_intc2_save);
1504         }
1505 }
1506
1507 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
1508 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
1509 {
1510         u16 tmp;
1511
1512         if (dev->phy.rev >= 3) {
1513                 if (b43_nphy_ipa(dev)) {
1514                         tmp = 4;
1515                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
1516                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
1517                 }
1518
1519                 tmp = 1;
1520                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
1521                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
1522         }
1523 }
1524
1525 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
1526 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
1527 {
1528         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
1529
1530         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
1531         if (preamble == 1)
1532                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
1533         else
1534                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
1535
1536         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
1537 }
1538
1539 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
1540 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
1541 {
1542         struct b43_phy_n *nphy = dev->phy.n;
1543
1544         bool override = false;
1545         u16 chain = 0x33;
1546
1547         if (nphy->txrx_chain == 0) {
1548                 chain = 0x11;
1549                 override = true;
1550         } else if (nphy->txrx_chain == 1) {
1551                 chain = 0x22;
1552                 override = true;
1553         }
1554
1555         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
1556                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
1557                         chain);
1558
1559         if (override)
1560                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1561                                 B43_NPHY_RFSEQMODE_CAOVER);
1562         else
1563                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
1564                                 ~B43_NPHY_RFSEQMODE_CAOVER);
1565 }
1566
1567 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
1568 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
1569                                 u16 samps, u8 time, bool wait)
1570 {
1571         int i;
1572         u16 tmp;
1573
1574         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
1575         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
1576         if (wait)
1577                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
1578         else
1579                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
1580
1581         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
1582
1583         for (i = 1000; i; i--) {
1584                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
1585                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
1586                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
1587                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
1588                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
1589                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
1590                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
1591                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
1592
1593                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
1594                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
1595                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
1596                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
1597                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
1598                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
1599                         return;
1600                 }
1601                 udelay(10);
1602         }
1603         memset(est, 0, sizeof(*est));
1604 }
1605
1606 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
1607 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
1608                                         struct b43_phy_n_iq_comp *pcomp)
1609 {
1610         if (write) {
1611                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
1612                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
1613                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
1614                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
1615         } else {
1616                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
1617                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
1618                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
1619                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
1620         }
1621 }
1622
1623 #if 0
1624 /* Ready but not used anywhere */
1625 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
1626 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
1627 {
1628         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1629
1630         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
1631         if (core == 0) {
1632                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
1633                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
1634         } else {
1635                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
1636                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
1637         }
1638         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
1639         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
1640         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
1641         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
1642         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
1643         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
1644         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
1645         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
1646 }
1647
1648 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
1649 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
1650 {
1651         u8 rxval, txval;
1652         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1653
1654         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
1655         if (core == 0) {
1656                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1657                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1658         } else {
1659                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1660                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1661         }
1662         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1663         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1664         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1665         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1666         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
1667         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1668         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
1669         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
1670
1671         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
1672         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1673
1674         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
1675                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
1676                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
1677         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
1678                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
1679         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
1680                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
1681         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
1682                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
1683
1684         if (core == 0) {
1685                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
1686                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
1687         } else {
1688                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
1689                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
1690         }
1691
1692         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
1693         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
1694         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
1695
1696         if (core == 0) {
1697                 rxval = 1;
1698                 txval = 8;
1699         } else {
1700                 rxval = 4;
1701                 txval = 2;
1702         }
1703         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
1704         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
1705 }
1706 #endif
1707
1708 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
1709 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
1710 {
1711         int i;
1712         s32 iq;
1713         u32 ii;
1714         u32 qq;
1715         int iq_nbits, qq_nbits;
1716         int arsh, brsh;
1717         u16 tmp, a, b;
1718
1719         struct nphy_iq_est est;
1720         struct b43_phy_n_iq_comp old;
1721         struct b43_phy_n_iq_comp new = { };
1722         bool error = false;
1723
1724         if (mask == 0)
1725                 return;
1726
1727         b43_nphy_rx_iq_coeffs(dev, false, &old);
1728         b43_nphy_rx_iq_coeffs(dev, true, &new);
1729         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
1730         new = old;
1731
1732         for (i = 0; i < 2; i++) {
1733                 if (i == 0 && (mask & 1)) {
1734                         iq = est.iq0_prod;
1735                         ii = est.i0_pwr;
1736                         qq = est.q0_pwr;
1737                 } else if (i == 1 && (mask & 2)) {
1738                         iq = est.iq1_prod;
1739                         ii = est.i1_pwr;
1740                         qq = est.q1_pwr;
1741                 } else {
1742                         continue;
1743                 }
1744
1745                 if (ii + qq < 2) {
1746                         error = true;
1747                         break;
1748                 }
1749
1750                 iq_nbits = fls(abs(iq));
1751                 qq_nbits = fls(qq);
1752
1753                 arsh = iq_nbits - 20;
1754                 if (arsh >= 0) {
1755                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
1756                         tmp = ii >> arsh;
1757                 } else {
1758                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
1759                         tmp = ii << -arsh;
1760                 }
1761                 if (tmp == 0) {
1762                         error = true;
1763                         break;
1764                 }
1765                 a /= tmp;
1766
1767                 brsh = qq_nbits - 11;
1768                 if (brsh >= 0) {
1769                         b = (qq << (31 - qq_nbits));
1770                         tmp = ii >> brsh;
1771                 } else {
1772                         b = (qq << (31 - qq_nbits));
1773                         tmp = ii << -brsh;
1774                 }
1775                 if (tmp == 0) {
1776                         error = true;
1777                         break;
1778                 }
1779                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
1780
1781                 if (i == 0 && (mask & 0x1)) {
1782                         if (dev->phy.rev >= 3) {
1783                                 new.a0 = a & 0x3FF;
1784                                 new.b0 = b & 0x3FF;
1785                         } else {
1786                                 new.a0 = b & 0x3FF;
1787                                 new.b0 = a & 0x3FF;
1788                         }
1789                 } else if (i == 1 && (mask & 0x2)) {
1790                         if (dev->phy.rev >= 3) {
1791                                 new.a1 = a & 0x3FF;
1792                                 new.b1 = b & 0x3FF;
1793                         } else {
1794                                 new.a1 = b & 0x3FF;
1795                                 new.b1 = a & 0x3FF;
1796                         }
1797                 }
1798         }
1799
1800         if (error)
1801                 new = old;
1802
1803         b43_nphy_rx_iq_coeffs(dev, true, &new);
1804 }
1805
1806 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
1807 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
1808 {
1809         u16 array[4];
1810         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
1811
1812         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
1813         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
1814         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
1815         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
1816 }
1817
1818 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
1819 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
1820 {
1821         if (dev->phy.rev >= 3) {
1822                 if (!init)
1823                         return;
1824                 if (0 /* FIXME */) {
1825                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
1826                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
1827                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
1828                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
1829                 }
1830         } else {
1831                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1832                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1833
1834                 switch (dev->dev->bus_type) {
1835 #ifdef CONFIG_B43_BCMA
1836                 case B43_BUS_BCMA:
1837                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1838                                                  0xFC00, 0xFC00);
1839                         break;
1840 #endif
1841 #ifdef CONFIG_B43_SSB
1842                 case B43_BUS_SSB:
1843                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1844                                                 0xFC00, 0xFC00);
1845                         break;
1846 #endif
1847                 }
1848
1849                 b43_write32(dev, B43_MMIO_MACCTL,
1850                         b43_read32(dev, B43_MMIO_MACCTL) &
1851                         ~B43_MACCTL_GPOUTSMSK);
1852                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1853                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
1854                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
1855                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
1856
1857                 if (init) {
1858                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1859                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1860                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1861                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1862                 }
1863         }
1864 }
1865
1866 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1867 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1868 {
1869         struct b43_phy_n *nphy = dev->phy.n;
1870         u16 tmp;
1871
1872         if (nphy->hang_avoid)
1873                 b43_nphy_stay_in_carrier_search(dev, 1);
1874
1875         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1876         if (tmp & 0x1)
1877                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1878         else if (tmp & 0x2)
1879                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1880
1881         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1882
1883         if (nphy->bb_mult_save & 0x80000000) {
1884                 tmp = nphy->bb_mult_save & 0xFFFF;
1885                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1886                 nphy->bb_mult_save = 0;
1887         }
1888
1889         if (nphy->hang_avoid)
1890                 b43_nphy_stay_in_carrier_search(dev, 0);
1891 }
1892
1893 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1894 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1895 {
1896         struct b43_phy_n *nphy = dev->phy.n;
1897
1898         u8 channel = dev->phy.channel;
1899         int tone[2] = { 57, 58 };
1900         u32 noise[2] = { 0x3FF, 0x3FF };
1901
1902         B43_WARN_ON(dev->phy.rev < 3);
1903
1904         if (nphy->hang_avoid)
1905                 b43_nphy_stay_in_carrier_search(dev, 1);
1906
1907         if (nphy->gband_spurwar_en) {
1908                 /* TODO: N PHY Adjust Analog Pfbw (7) */
1909                 if (channel == 11 && dev->phy.is_40mhz)
1910                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1911                 else
1912                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1913                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1914         }
1915
1916         if (nphy->aband_spurwar_en) {
1917                 if (channel == 54) {
1918                         tone[0] = 0x20;
1919                         noise[0] = 0x25F;
1920                 } else if (channel == 38 || channel == 102 || channel == 118) {
1921                         if (0 /* FIXME */) {
1922                                 tone[0] = 0x20;
1923                                 noise[0] = 0x21F;
1924                         } else {
1925                                 tone[0] = 0;
1926                                 noise[0] = 0;
1927                         }
1928                 } else if (channel == 134) {
1929                         tone[0] = 0x20;
1930                         noise[0] = 0x21F;
1931                 } else if (channel == 151) {
1932                         tone[0] = 0x10;
1933                         noise[0] = 0x23F;
1934                 } else if (channel == 153 || channel == 161) {
1935                         tone[0] = 0x30;
1936                         noise[0] = 0x23F;
1937                 } else {
1938                         tone[0] = 0;
1939                         noise[0] = 0;
1940                 }
1941
1942                 if (!tone[0] && !noise[0])
1943                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1944                 else
1945                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1946         }
1947
1948         if (nphy->hang_avoid)
1949                 b43_nphy_stay_in_carrier_search(dev, 0);
1950 }
1951
1952 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1953 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1954 {
1955         struct b43_phy_n *nphy = dev->phy.n;
1956
1957         u8 i;
1958         s16 tmp;
1959         u16 data[4];
1960         s16 gain[2];
1961         u16 minmax[2];
1962         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1963
1964         if (nphy->hang_avoid)
1965                 b43_nphy_stay_in_carrier_search(dev, 1);
1966
1967         if (nphy->gain_boost) {
1968                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1969                         gain[0] = 6;
1970                         gain[1] = 6;
1971                 } else {
1972                         tmp = 40370 - 315 * dev->phy.channel;
1973                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1974                         tmp = 23242 - 224 * dev->phy.channel;
1975                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1976                 }
1977         } else {
1978                 gain[0] = 0;
1979                 gain[1] = 0;
1980         }
1981
1982         for (i = 0; i < 2; i++) {
1983                 if (nphy->elna_gain_config) {
1984                         data[0] = 19 + gain[i];
1985                         data[1] = 25 + gain[i];
1986                         data[2] = 25 + gain[i];
1987                         data[3] = 25 + gain[i];
1988                 } else {
1989                         data[0] = lna_gain[0] + gain[i];
1990                         data[1] = lna_gain[1] + gain[i];
1991                         data[2] = lna_gain[2] + gain[i];
1992                         data[3] = lna_gain[3] + gain[i];
1993                 }
1994                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1995
1996                 minmax[i] = 23 + gain[i];
1997         }
1998
1999         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
2000                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
2001         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
2002                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
2003
2004         if (nphy->hang_avoid)
2005                 b43_nphy_stay_in_carrier_search(dev, 0);
2006 }
2007
2008 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2009 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
2010 {
2011         struct b43_phy_n *nphy = dev->phy.n;
2012         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2013
2014         /* PHY rev 0, 1, 2 */
2015         u8 i, j;
2016         u8 code;
2017         u16 tmp;
2018         u8 rfseq_events[3] = { 6, 8, 7 };
2019         u8 rfseq_delays[3] = { 10, 30, 1 };
2020
2021         /* PHY rev >= 3 */
2022         bool ghz5;
2023         bool ext_lna;
2024         u16 rssi_gain;
2025         struct nphy_gain_ctl_workaround_entry *e;
2026         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2027         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2028
2029         if (dev->phy.rev >= 3) {
2030                 /* Prepare values */
2031                 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2032                         & B43_NPHY_BANDCTL_5GHZ;
2033                 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
2034                 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2035                 if (ghz5 && dev->phy.rev >= 5)
2036                         rssi_gain = 0x90;
2037                 else
2038                         rssi_gain = 0x50;
2039
2040                 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2041
2042                 /* Set Clip 2 detect */
2043                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
2044                                 B43_NPHY_C1_CGAINI_CL2DETECT);
2045                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
2046                                 B43_NPHY_C2_CGAINI_CL2DETECT);
2047
2048                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2049                                 0x17);
2050                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2051                                 0x17);
2052                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2053                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2054                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2055                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2056                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2057                                 rssi_gain);
2058                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2059                                 rssi_gain);
2060                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2061                                 0x17);
2062                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2063                                 0x17);
2064                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2065                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2066
2067                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2068                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2069                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2070                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2071                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2072                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2073                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2074                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2075                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2076                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2077                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2078                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2079
2080                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
2081                 b43_phy_write(dev, 0x2A7, e->init_gain);
2082                 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2083                                         e->rfseq_init);
2084                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
2085
2086                 /* TODO: check defines. Do not match variables names */
2087                 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
2088                 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
2089                 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
2090                 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
2091                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
2092                 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
2093
2094                 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
2095                 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
2096                 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
2097                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2098                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2099                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2100                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2101                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2102                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2103                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2104         } else {
2105                 /* Set Clip 2 detect */
2106                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
2107                                 B43_NPHY_C1_CGAINI_CL2DETECT);
2108                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
2109                                 B43_NPHY_C2_CGAINI_CL2DETECT);
2110
2111                 /* Set narrowband clip threshold */
2112                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2113                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2114
2115                 if (!dev->phy.is_40mhz) {
2116                         /* Set dwell lengths */
2117                         b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2118                         b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2119                         b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2120                         b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2121                 }
2122
2123                 /* Set wideband clip 2 threshold */
2124                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2125                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
2126                                 21);
2127                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2128                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
2129                                 21);
2130
2131                 if (!dev->phy.is_40mhz) {
2132                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2133                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2134                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2135                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2136                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2137                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2138                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2139                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2140                 }
2141
2142                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2143
2144                 if (nphy->gain_boost) {
2145                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2146                             dev->phy.is_40mhz)
2147                                 code = 4;
2148                         else
2149                                 code = 5;
2150                 } else {
2151                         code = dev->phy.is_40mhz ? 6 : 7;
2152                 }
2153
2154                 /* Set HPVGA2 index */
2155                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
2156                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
2157                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2158                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
2159                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
2160                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2161
2162                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2163                 /* specs say about 2 loops, but wl does 4 */
2164                 for (i = 0; i < 4; i++)
2165                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2166                                                         (code << 8 | 0x7C));
2167
2168                 b43_nphy_adjust_lna_gain_table(dev);
2169
2170                 if (nphy->elna_gain_config) {
2171                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2172                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2173                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2174                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2175                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2176
2177                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2178                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2179                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2180                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2181                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2182
2183                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2184                         /* specs say about 2 loops, but wl does 4 */
2185                         for (i = 0; i < 4; i++)
2186                                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2187                                                         (code << 8 | 0x74));
2188                 }
2189
2190                 if (dev->phy.rev == 2) {
2191                         for (i = 0; i < 4; i++) {
2192                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2193                                                 (0x0400 * i) + 0x0020);
2194                                 for (j = 0; j < 21; j++) {
2195                                         tmp = j * (i < 2 ? 3 : 1);
2196                                         b43_phy_write(dev,
2197                                                 B43_NPHY_TABLE_DATALO, tmp);
2198                                 }
2199                         }
2200                 }
2201
2202                 b43_nphy_set_rf_sequence(dev, 5,
2203                                 rfseq_events, rfseq_delays, 3);
2204                 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2205                         ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2206                         0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2207
2208                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2209                         b43_phy_maskset(dev, B43_PHY_N(0xC5D),
2210                                         0xFF80, 4);
2211         }
2212 }
2213
2214 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2215 {
2216         struct b43_phy_n *nphy = dev->phy.n;
2217         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2218
2219         /* TX to RX */
2220         u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
2221         u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
2222         /* RX to TX */
2223         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2224                                         0x1F };
2225         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2226         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2227         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2228
2229         u16 tmp16;
2230         u32 tmp32;
2231
2232         b43_phy_write(dev, 0x23f, 0x1f8);
2233         b43_phy_write(dev, 0x240, 0x1f8);
2234
2235         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2236         tmp32 &= 0xffffff;
2237         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2238
2239         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2240         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2241         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2242         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2243         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2244         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2245
2246         b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
2247         b43_phy_write(dev, 0x2AE, 0x000C);
2248
2249         /* TX to RX */
2250         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2251                                  ARRAY_SIZE(tx2rx_events));
2252
2253         /* RX to TX */
2254         if (b43_nphy_ipa(dev))
2255                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2256                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2257         if (nphy->hw_phyrxchain != 3 &&
2258             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2259                 if (b43_nphy_ipa(dev)) {
2260                         rx2tx_delays[5] = 59;
2261                         rx2tx_delays[6] = 1;
2262                         rx2tx_events[7] = 0x1F;
2263                 }
2264                 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
2265                                          ARRAY_SIZE(rx2tx_events));
2266         }
2267
2268         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2269                 0x2 : 0x9C40;
2270         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2271
2272         b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
2273
2274         b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2275         b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2276
2277         b43_nphy_gain_ctrl_workarounds(dev);
2278
2279         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2280         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
2281
2282         /* TODO */
2283
2284         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2285         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2286         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2287         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2288         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2289         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2290         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2291         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2292         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2293         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2294         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2295         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2296
2297         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2298
2299         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2300              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2301             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2302              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2303                 tmp32 = 0x00088888;
2304         else
2305                 tmp32 = 0x88888888;
2306         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2307         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2308         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2309
2310         if (dev->phy.rev == 4 &&
2311                 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2312                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2313                                 0x70);
2314                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2315                                 0x70);
2316         }
2317
2318         b43_phy_write(dev, 0x224, 0x03eb);
2319         b43_phy_write(dev, 0x225, 0x03eb);
2320         b43_phy_write(dev, 0x226, 0x0341);
2321         b43_phy_write(dev, 0x227, 0x0341);
2322         b43_phy_write(dev, 0x228, 0x042b);
2323         b43_phy_write(dev, 0x229, 0x042b);
2324         b43_phy_write(dev, 0x22a, 0x0381);
2325         b43_phy_write(dev, 0x22b, 0x0381);
2326         b43_phy_write(dev, 0x22c, 0x042b);
2327         b43_phy_write(dev, 0x22d, 0x042b);
2328         b43_phy_write(dev, 0x22e, 0x0381);
2329         b43_phy_write(dev, 0x22f, 0x0381);
2330 }
2331
2332 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2333 {
2334         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2335         struct b43_phy *phy = &dev->phy;
2336         struct b43_phy_n *nphy = phy->n;
2337
2338         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2339         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
2340
2341         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2342         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2343
2344         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2345             nphy->band5g_pwrgain) {
2346                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2347                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2348         } else {
2349                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2350                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2351         }
2352
2353         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2354         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2355         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2356         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2357
2358         if (dev->phy.rev < 2) {
2359                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2360                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2361                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2362                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2363                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2364                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2365         }
2366
2367         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2368         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2369         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2370         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2371
2372         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
2373             dev->dev->board_type == 0x8B) {
2374                 delays1[0] = 0x1;
2375                 delays1[5] = 0x14;
2376         }
2377         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2378         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2379
2380         b43_nphy_gain_ctrl_workarounds(dev);
2381
2382         if (dev->phy.rev < 2) {
2383                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2384                         b43_hf_write(dev, b43_hf_read(dev) |
2385                                         B43_HF_MLADVW);
2386         } else if (dev->phy.rev == 2) {
2387                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2388                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2389         }
2390
2391         if (dev->phy.rev < 2)
2392                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2393                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2394
2395         /* Set phase track alpha and beta */
2396         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2397         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2398         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2399         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2400         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2401         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2402
2403         b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2404                         ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2405         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2406         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2407         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2408
2409         if (dev->phy.rev == 2)
2410                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2411                                 B43_NPHY_FINERX2_CGC_DECGC);
2412 }
2413
2414 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2415 static void b43_nphy_workarounds(struct b43_wldev *dev)
2416 {
2417         struct b43_phy *phy = &dev->phy;
2418         struct b43_phy_n *nphy = phy->n;
2419
2420         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2421                 b43_nphy_classifier(dev, 1, 0);
2422         else
2423                 b43_nphy_classifier(dev, 1, 1);
2424
2425         if (nphy->hang_avoid)
2426                 b43_nphy_stay_in_carrier_search(dev, 1);
2427
2428         b43_phy_set(dev, B43_NPHY_IQFLIP,
2429                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2430
2431         if (dev->phy.rev >= 3)
2432                 b43_nphy_workarounds_rev3plus(dev);
2433         else
2434                 b43_nphy_workarounds_rev1_2(dev);
2435
2436         if (nphy->hang_avoid)
2437                 b43_nphy_stay_in_carrier_search(dev, 0);
2438 }
2439
2440 /*
2441  * Transmits a known value for LO calibration
2442  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2443  */
2444 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2445                                 bool iqmode, bool dac_test)
2446 {
2447         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2448         if (samp == 0)
2449                 return -1;
2450         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2451         return 0;
2452 }
2453
2454 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
2455 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
2456 {
2457         struct b43_phy_n *nphy = dev->phy.n;
2458         int i, j;
2459         u32 tmp;
2460         u32 cur_real, cur_imag, real_part, imag_part;
2461
2462         u16 buffer[7];
2463
2464         if (nphy->hang_avoid)
2465                 b43_nphy_stay_in_carrier_search(dev, true);
2466
2467         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2468
2469         for (i = 0; i < 2; i++) {
2470                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
2471                         (buffer[i * 2 + 1] & 0x3FF);
2472                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2473                                 (((i + 26) << 10) | 320));
2474                 for (j = 0; j < 128; j++) {
2475                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
2476                                         ((tmp >> 16) & 0xFFFF));
2477                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2478                                         (tmp & 0xFFFF));
2479                 }
2480         }
2481
2482         for (i = 0; i < 2; i++) {
2483                 tmp = buffer[5 + i];
2484                 real_part = (tmp >> 8) & 0xFF;
2485                 imag_part = (tmp & 0xFF);
2486                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2487                                 (((i + 26) << 10) | 448));
2488
2489                 if (dev->phy.rev >= 3) {
2490                         cur_real = real_part;
2491                         cur_imag = imag_part;
2492                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
2493                 }
2494
2495                 for (j = 0; j < 128; j++) {
2496                         if (dev->phy.rev < 3) {
2497                                 cur_real = (real_part * loscale[j] + 128) >> 8;
2498                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
2499                                 tmp = ((cur_real & 0xFF) << 8) |
2500                                         (cur_imag & 0xFF);
2501                         }
2502                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
2503                                         ((tmp >> 16) & 0xFFFF));
2504                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2505                                         (tmp & 0xFFFF));
2506                 }
2507         }
2508
2509         if (dev->phy.rev >= 3) {
2510                 b43_shm_write16(dev, B43_SHM_SHARED,
2511                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
2512                 b43_shm_write16(dev, B43_SHM_SHARED,
2513                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
2514         }
2515
2516         if (nphy->hang_avoid)
2517                 b43_nphy_stay_in_carrier_search(dev, false);
2518 }
2519
2520 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
2521 static void b43_nphy_bphy_init(struct b43_wldev *dev)
2522 {
2523         unsigned int i;
2524         u16 val;
2525
2526         val = 0x1E1F;
2527         for (i = 0; i < 16; i++) {
2528                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2529                 val -= 0x202;
2530         }
2531         val = 0x3E3F;
2532         for (i = 0; i < 16; i++) {
2533                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2534                 val -= 0x202;
2535         }
2536         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2537 }
2538
2539 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2540 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2541 {
2542         int i;
2543         for (i = 0; i < 2; i++) {
2544                 if (type == 2) {
2545                         if (i == 0) {
2546                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2547                                                   0xFC, buf[0]);
2548                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2549                                                   0xFC, buf[1]);
2550                         } else {
2551                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2552                                                   0xFC, buf[2 * i]);
2553                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2554                                                   0xFC, buf[2 * i + 1]);
2555                         }
2556                 } else {
2557                         if (i == 0)
2558                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2559                                                   0xF3, buf[0] << 2);
2560                         else
2561                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2562                                                   0xF3, buf[2 * i + 1] << 2);
2563                 }
2564         }
2565 }
2566
2567 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2568 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2569                                 u8 nsamp)
2570 {
2571         int i;
2572         int out;
2573         u16 save_regs_phy[9];
2574         u16 s[2];
2575
2576         if (dev->phy.rev >= 3) {
2577                 save_regs_phy[0] = b43_phy_read(dev,
2578                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2579                 save_regs_phy[1] = b43_phy_read(dev,
2580                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2581                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2582                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2583                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2584                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2585                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2586                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2587                 save_regs_phy[8] = 0;
2588         } else {
2589                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2590                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2591                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2592                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2593                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2594                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2595                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2596                 save_regs_phy[7] = 0;
2597                 save_regs_phy[8] = 0;
2598         }
2599
2600         b43_nphy_rssi_select(dev, 5, type);
2601
2602         if (dev->phy.rev < 2) {
2603                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2604                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2605         }
2606
2607         for (i = 0; i < 4; i++)
2608                 buf[i] = 0;
2609
2610         for (i = 0; i < nsamp; i++) {
2611                 if (dev->phy.rev < 2) {
2612                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2613                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2614                 } else {
2615                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2616                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2617                 }
2618
2619                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2620                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2621                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2622                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2623         }
2624         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2625                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2626
2627         if (dev->phy.rev < 2)
2628                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2629
2630         if (dev->phy.rev >= 3) {
2631                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2632                                 save_regs_phy[0]);
2633                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2634                                 save_regs_phy[1]);
2635                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2636                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2637                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2638                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2639                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2640                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2641         } else {
2642                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2643                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2644                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2645                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2646                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2647                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2648                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2649         }
2650
2651         return out;
2652 }
2653
2654 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2655 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2656 {
2657         int i, j;
2658         u8 state[4];
2659         u8 code, val;
2660         u16 class, override;
2661         u8 regs_save_radio[2];
2662         u16 regs_save_phy[2];
2663
2664         s8 offset[4];
2665         u8 core;
2666         u8 rail;
2667
2668         u16 clip_state[2];
2669         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2670         s32 results_min[4] = { };
2671         u8 vcm_final[4] = { };
2672         s32 results[4][4] = { };
2673         s32 miniq[4][2] = { };
2674
2675         if (type == 2) {
2676                 code = 0;
2677                 val = 6;
2678         } else if (type < 2) {
2679                 code = 25;
2680                 val = 4;
2681         } else {
2682                 B43_WARN_ON(1);
2683                 return;
2684         }
2685
2686         class = b43_nphy_classifier(dev, 0, 0);
2687         b43_nphy_classifier(dev, 7, 4);
2688         b43_nphy_read_clip_detection(dev, clip_state);
2689         b43_nphy_write_clip_detection(dev, clip_off);
2690
2691         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2692                 override = 0x140;
2693         else
2694                 override = 0x110;
2695
2696         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2697         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2698         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2699         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2700
2701         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2702         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2703         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2704         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2705
2706         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2707         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2708         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2709         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2710         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2711         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2712
2713         b43_nphy_rssi_select(dev, 5, type);
2714         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2715         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2716
2717         for (i = 0; i < 4; i++) {
2718                 u8 tmp[4];
2719                 for (j = 0; j < 4; j++)
2720                         tmp[j] = i;
2721                 if (type != 1)
2722                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2723                 b43_nphy_poll_rssi(dev, type, results[i], 8);
2724                 if (type < 2)
2725                         for (j = 0; j < 2; j++)
2726                                 miniq[i][j] = min(results[i][2 * j],
2727                                                 results[i][2 * j + 1]);
2728         }
2729
2730         for (i = 0; i < 4; i++) {
2731                 s32 mind = 40;
2732                 u8 minvcm = 0;
2733                 s32 minpoll = 249;
2734                 s32 curr;
2735                 for (j = 0; j < 4; j++) {
2736                         if (type == 2)
2737                                 curr = abs(results[j][i]);
2738                         else
2739                                 curr = abs(miniq[j][i / 2] - code * 8);
2740
2741                         if (curr < mind) {
2742                                 mind = curr;
2743                                 minvcm = j;
2744                         }
2745
2746                         if (results[j][i] < minpoll)
2747                                 minpoll = results[j][i];
2748                 }
2749                 results_min[i] = minpoll;
2750                 vcm_final[i] = minvcm;
2751         }
2752
2753         if (type != 1)
2754                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2755
2756         for (i = 0; i < 4; i++) {
2757                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2758
2759                 if (offset[i] < 0)
2760                         offset[i] = -((abs(offset[i]) + 4) / 8);
2761                 else
2762                         offset[i] = (offset[i] + 4) / 8;
2763
2764                 if (results_min[i] == 248)
2765                         offset[i] = code - 32;
2766
2767                 core = (i / 2) ? 2 : 1;
2768                 rail = (i % 2) ? 1 : 0;
2769
2770                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2771                                                 type);
2772         }
2773
2774         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2775         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2776
2777         switch (state[2]) {
2778         case 1:
2779                 b43_nphy_rssi_select(dev, 1, 2);
2780                 break;
2781         case 4:
2782                 b43_nphy_rssi_select(dev, 1, 0);
2783                 break;
2784         case 2:
2785                 b43_nphy_rssi_select(dev, 1, 1);
2786                 break;
2787         default:
2788                 b43_nphy_rssi_select(dev, 1, 1);
2789                 break;
2790         }
2791
2792         switch (state[3]) {
2793         case 1:
2794                 b43_nphy_rssi_select(dev, 2, 2);
2795                 break;
2796         case 4:
2797                 b43_nphy_rssi_select(dev, 2, 0);
2798                 break;
2799         default:
2800                 b43_nphy_rssi_select(dev, 2, 1);
2801                 break;
2802         }
2803
2804         b43_nphy_rssi_select(dev, 0, type);
2805
2806         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2807         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2808         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2809         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2810
2811         b43_nphy_classifier(dev, 7, class);
2812         b43_nphy_write_clip_detection(dev, clip_state);
2813         /* Specs don't say about reset here, but it makes wl and b43 dumps
2814            identical, it really seems wl performs this */
2815         b43_nphy_reset_cca(dev);
2816 }
2817
2818 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2819 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2820 {
2821         /* TODO */
2822 }
2823
2824 /*
2825  * RSSI Calibration
2826  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2827  */
2828 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2829 {
2830         if (dev->phy.rev >= 3) {
2831                 b43_nphy_rev3_rssi_cal(dev);
2832         } else {
2833                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2834                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2835                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2836         }
2837 }
2838
2839 /*
2840  * Restore RSSI Calibration
2841  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2842  */
2843 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2844 {
2845         struct b43_phy_n *nphy = dev->phy.n;
2846
2847         u16 *rssical_radio_regs = NULL;
2848         u16 *rssical_phy_regs = NULL;
2849
2850         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2851                 if (!nphy->rssical_chanspec_2G.center_freq)
2852                         return;
2853                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2854                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2855         } else {
2856                 if (!nphy->rssical_chanspec_5G.center_freq)
2857                         return;
2858                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2859                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2860         }
2861
2862         /* TODO use some definitions */
2863         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2864         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2865
2866         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2867         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2868         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2869         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2870
2871         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2872         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2873         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2874         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2875
2876         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2877         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2878         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2879         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2880 }
2881
2882 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2883 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2884 {
2885         struct b43_phy_n *nphy = dev->phy.n;
2886         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2887         u16 tmp;
2888         u8 offset, i;
2889
2890         if (dev->phy.rev >= 3) {
2891             for (i = 0; i < 2; i++) {
2892                 tmp = (i == 0) ? 0x2000 : 0x3000;
2893                 offset = i * 11;
2894
2895                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2896                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2897                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2898                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2899                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2900                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2901                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2902                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2903                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2904                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2905                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2906
2907                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2908                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2909                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2910                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2911                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2912                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2913                         if (nphy->ipa5g_on) {
2914                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2915                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2916                         } else {
2917                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2918                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2919                         }
2920                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2921                 } else {
2922                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2923                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2924                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2925                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2926                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2927                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2928                         if (nphy->ipa2g_on) {
2929                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2930                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2931                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2932                         } else {
2933                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2934                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2935                         }
2936                 }
2937                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2938                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2939                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2940             }
2941         } else {
2942                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2943                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2944
2945                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2946                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2947
2948                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2949                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2950
2951                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2952                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2953
2954                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2955                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2956
2957                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2958                     B43_NPHY_BANDCTL_5GHZ)) {
2959                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2960                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2961                 } else {
2962                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2963                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2964                 }
2965
2966                 if (dev->phy.rev < 2) {
2967                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2968                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2969                 } else {
2970                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2971                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2972                 }
2973         }
2974 }
2975
2976 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2977 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2978                                         struct nphy_txgains target,
2979                                         struct nphy_iqcal_params *params)
2980 {
2981         int i, j, indx;
2982         u16 gain;
2983
2984         if (dev->phy.rev >= 3) {
2985                 params->txgm = target.txgm[core];
2986                 params->pga = target.pga[core];
2987                 params->pad = target.pad[core];
2988                 params->ipa = target.ipa[core];
2989                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2990                                         (params->pad << 4) | (params->ipa);
2991                 for (j = 0; j < 5; j++)
2992                         params->ncorr[j] = 0x79;
2993         } else {
2994                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2995                         (target.txgm[core] << 8);
2996
2997                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2998                         1 : 0;
2999                 for (i = 0; i < 9; i++)
3000                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
3001                                 break;
3002                 i = min(i, 8);
3003
3004                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3005                 params->pga = tbl_iqcal_gainparams[indx][i][2];
3006                 params->pad = tbl_iqcal_gainparams[indx][i][3];
3007                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3008                                         (params->pad << 2);
3009                 for (j = 0; j < 4; j++)
3010                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3011         }
3012 }
3013
3014 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3015 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3016 {
3017         struct b43_phy_n *nphy = dev->phy.n;
3018         int i;
3019         u16 scale, entry;
3020
3021         u16 tmp = nphy->txcal_bbmult;
3022         if (core == 0)
3023                 tmp >>= 8;
3024         tmp &= 0xff;
3025
3026         for (i = 0; i < 18; i++) {
3027                 scale = (ladder_lo[i].percent * tmp) / 100;
3028                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
3029                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
3030
3031                 scale = (ladder_iq[i].percent * tmp) / 100;
3032                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
3033                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
3034         }
3035 }
3036
3037 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
3038 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
3039 {
3040         int i;
3041         for (i = 0; i < 15; i++)
3042                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
3043                                 tbl_tx_filter_coef_rev4[2][i]);
3044 }
3045
3046 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
3047 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
3048 {
3049         int i, j;
3050         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
3051         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
3052
3053         for (i = 0; i < 3; i++)
3054                 for (j = 0; j < 15; j++)
3055                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
3056                                         tbl_tx_filter_coef_rev4[i][j]);
3057
3058         if (dev->phy.is_40mhz) {
3059                 for (j = 0; j < 15; j++)
3060                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3061                                         tbl_tx_filter_coef_rev4[3][j]);
3062         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3063                 for (j = 0; j < 15; j++)
3064                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3065                                         tbl_tx_filter_coef_rev4[5][j]);
3066         }
3067
3068         if (dev->phy.channel == 14)
3069                 for (j = 0; j < 15; j++)
3070                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3071                                         tbl_tx_filter_coef_rev4[6][j]);
3072 }
3073
3074 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
3075 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
3076 {
3077         struct b43_phy_n *nphy = dev->phy.n;
3078
3079         u16 curr_gain[2];
3080         struct nphy_txgains target;
3081         const u32 *table = NULL;
3082
3083         if (!nphy->txpwrctrl) {
3084                 int i;
3085
3086                 if (nphy->hang_avoid)
3087                         b43_nphy_stay_in_carrier_search(dev, true);
3088                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
3089                 if (nphy->hang_avoid)
3090                         b43_nphy_stay_in_carrier_search(dev, false);
3091
3092                 for (i = 0; i < 2; ++i) {
3093                         if (dev->phy.rev >= 3) {
3094                                 target.ipa[i] = curr_gain[i] & 0x000F;
3095                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
3096                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
3097                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
3098                         } else {
3099                                 target.ipa[i] = curr_gain[i] & 0x0003;
3100                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
3101                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
3102                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
3103                         }
3104                 }
3105         } else {
3106                 int i;
3107                 u16 index[2];
3108                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
3109                         B43_NPHY_TXPCTL_STAT_BIDX) >>
3110                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3111                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
3112                         B43_NPHY_TXPCTL_STAT_BIDX) >>
3113                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3114
3115                 for (i = 0; i < 2; ++i) {
3116                         if (dev->phy.rev >= 3) {
3117                                 enum ieee80211_band band =
3118                                         b43_current_band(dev->wl);
3119
3120                                 if (b43_nphy_ipa(dev)) {
3121                                         table = b43_nphy_get_ipa_gain_table(dev);
3122                                 } else {
3123                                         if (band == IEEE80211_BAND_5GHZ) {
3124                                                 if (dev->phy.rev == 3)
3125                                                         table = b43_ntab_tx_gain_rev3_5ghz;
3126                                                 else if (dev->phy.rev == 4)
3127                                                         table = b43_ntab_tx_gain_rev4_5ghz;
3128                                                 else
3129                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
3130                                         } else {
3131                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
3132                                         }
3133                                 }
3134
3135                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3136                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3137                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3138                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3139                         } else {
3140                                 table = b43_ntab_tx_gain_rev0_1_2;
3141
3142                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3143                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3144                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3145                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3146                         }
3147                 }
3148         }
3149
3150         return target;
3151 }
3152
3153 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3154 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3155 {
3156         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3157
3158         if (dev->phy.rev >= 3) {
3159                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3160                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3161                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3162                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3163                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
3164                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3165                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
3166                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3167                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3168                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3169                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3170                 b43_nphy_reset_cca(dev);
3171         } else {
3172                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3173                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3174                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3175                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3176                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
3177                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3178                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3179         }
3180 }
3181
3182 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3183 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3184 {
3185         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3186         u16 tmp;
3187
3188         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3189         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3190         if (dev->phy.rev >= 3) {
3191                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3192                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3193
3194                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3195                 regs[2] = tmp;
3196                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3197
3198                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3199                 regs[3] = tmp;
3200                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3201
3202                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
3203                 b43_phy_mask(dev, B43_NPHY_BBCFG,
3204                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
3205
3206                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
3207                 regs[5] = tmp;
3208                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
3209
3210                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
3211                 regs[6] = tmp;
3212                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
3213                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3214                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3215
3216                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3217                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3218                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
3219
3220                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3221                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3222                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3223                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3224         } else {
3225                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3226                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3227                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3228                 regs[2] = tmp;
3229                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
3230                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
3231                 regs[3] = tmp;
3232                 tmp |= 0x2000;
3233                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
3234                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
3235                 regs[4] = tmp;
3236                 tmp |= 0x2000;
3237                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
3238                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3239                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3240                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3241                         tmp = 0x0180;
3242                 else
3243                         tmp = 0x0120;
3244                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3245                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3246         }
3247 }
3248
3249 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3250 static void b43_nphy_save_cal(struct b43_wldev *dev)
3251 {
3252         struct b43_phy_n *nphy = dev->phy.n;
3253
3254         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3255         u16 *txcal_radio_regs = NULL;
3256         struct b43_chanspec *iqcal_chanspec;
3257         u16 *table = NULL;
3258
3259         if (nphy->hang_avoid)
3260                 b43_nphy_stay_in_carrier_search(dev, 1);
3261
3262         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3263                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3264                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3265                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3266                 table = nphy->cal_cache.txcal_coeffs_2G;
3267         } else {
3268                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3269                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3270                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3271                 table = nphy->cal_cache.txcal_coeffs_5G;
3272         }
3273
3274         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3275         /* TODO use some definitions */
3276         if (dev->phy.rev >= 3) {
3277                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3278                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3279                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3280                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3281                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3282                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3283                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3284                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3285         } else {
3286                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3287                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3288                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3289                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3290         }
3291         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3292         iqcal_chanspec->channel_type = dev->phy.channel_type;
3293         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3294
3295         if (nphy->hang_avoid)
3296                 b43_nphy_stay_in_carrier_search(dev, 0);
3297 }
3298
3299 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3300 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3301 {
3302         struct b43_phy_n *nphy = dev->phy.n;
3303
3304         u16 coef[4];
3305         u16 *loft = NULL;
3306         u16 *table = NULL;
3307
3308         int i;
3309         u16 *txcal_radio_regs = NULL;
3310         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3311
3312         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3313                 if (!nphy->iqcal_chanspec_2G.center_freq)
3314                         return;
3315                 table = nphy->cal_cache.txcal_coeffs_2G;
3316                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3317         } else {
3318                 if (!nphy->iqcal_chanspec_5G.center_freq)
3319                         return;
3320                 table = nphy->cal_cache.txcal_coeffs_5G;
3321                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3322         }
3323
3324         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3325
3326         for (i = 0; i < 4; i++) {
3327                 if (dev->phy.rev >= 3)
3328                         table[i] = coef[i];
3329                 else
3330                         coef[i] = 0;
3331         }
3332
3333         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3334         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3335         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3336
3337         if (dev->phy.rev < 2)
3338                 b43_nphy_tx_iq_workaround(dev);
3339
3340         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3341                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3342                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3343         } else {
3344                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3345                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3346         }
3347
3348         /* TODO use some definitions */
3349         if (dev->phy.rev >= 3) {
3350                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3351                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3352                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3353                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3354                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3355                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3356                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3357                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3358         } else {
3359                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3360                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3361                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3362                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3363         }
3364         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3365 }
3366
3367 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3368 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3369                                 struct nphy_txgains target,
3370                                 bool full, bool mphase)
3371 {
3372         struct b43_phy_n *nphy = dev->phy.n;
3373         int i;
3374         int error = 0;
3375         int freq;
3376         bool avoid = false;
3377         u8 length;
3378         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3379         const u16 *table;
3380         bool phy6or5x;
3381
3382         u16 buffer[11];
3383         u16 diq_start = 0;
3384         u16 save[2];
3385         u16 gain[2];
3386         struct nphy_iqcal_params params[2];
3387         bool updated[2] = { };
3388
3389         b43_nphy_stay_in_carrier_search(dev, true);
3390
3391         if (dev->phy.rev >= 4) {
3392                 avoid = nphy->hang_avoid;
3393                 nphy->hang_avoid = 0;
3394         }
3395
3396         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3397
3398         for (i = 0; i < 2; i++) {
3399                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3400                 gain[i] = params[i].cal_gain;
3401         }
3402
3403         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3404
3405         b43_nphy_tx_cal_radio_setup(dev);
3406         b43_nphy_tx_cal_phy_setup(dev);
3407
3408         phy6or5x = dev->phy.rev >= 6 ||
3409                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3410                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3411         if (phy6or5x) {
3412                 if (dev->phy.is_40mhz) {
3413                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3414                                         tbl_tx_iqlo_cal_loft_ladder_40);
3415                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3416                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3417                 } else {
3418                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3419                                         tbl_tx_iqlo_cal_loft_ladder_20);
3420                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3421                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3422                 }
3423         }
3424
3425         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3426
3427         if (!dev->phy.is_40mhz)
3428                 freq = 2500;
3429         else
3430                 freq = 5000;
3431
3432         if (nphy->mphase_cal_phase_id > 2)
3433                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3434                                         0xFFFF, 0, true, false);
3435         else
3436                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3437
3438         if (error == 0) {
3439                 if (nphy->mphase_cal_phase_id > 2) {
3440                         table = nphy->mphase_txcal_bestcoeffs;
3441                         length = 11;
3442                         if (dev->phy.rev < 3)
3443                                 length -= 2;
3444                 } else {
3445                         if (!full && nphy->txiqlocal_coeffsvalid) {
3446                                 table = nphy->txiqlocal_bestc;
3447                                 length = 11;
3448                                 if (dev->phy.rev < 3)
3449                                         length -= 2;
3450                         } else {
3451                                 full = true;
3452                                 if (dev->phy.rev >= 3) {
3453                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3454                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3455                                 } else {
3456                                         table = tbl_tx_iqlo_cal_startcoefs;
3457                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3458                                 }
3459                         }
3460                 }
3461
3462                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3463
3464                 if (full) {
3465                         if (dev->phy.rev >= 3)
3466                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3467                         else
3468                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3469                 } else {
3470                         if (dev->phy.rev >= 3)
3471                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3472                         else
3473                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3474                 }
3475
3476                 if (mphase) {
3477                         count = nphy->mphase_txcal_cmdidx;
3478                         numb = min(max,
3479                                 (u16)(count + nphy->mphase_txcal_numcmds));
3480                 } else {
3481                         count = 0;
3482                         numb = max;
3483                 }
3484
3485                 for (; count < numb; count++) {
3486                         if (full) {
3487                                 if (dev->phy.rev >= 3)
3488                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3489                                 else
3490                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3491                         } else {
3492                                 if (dev->phy.rev >= 3)
3493                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3494                                 else
3495                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3496                         }
3497
3498                         core = (cmd & 0x3000) >> 12;
3499                         type = (cmd & 0x0F00) >> 8;
3500
3501                         if (phy6or5x && updated[core] == 0) {
3502                                 b43_nphy_update_tx_cal_ladder(dev, core);
3503                                 updated[core] = 1;
3504                         }
3505
3506                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3507                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3508
3509                         if (type == 1 || type == 3 || type == 4) {
3510                                 buffer[0] = b43_ntab_read(dev,
3511                                                 B43_NTAB16(15, 69 + core));
3512                                 diq_start = buffer[0];
3513                                 buffer[0] = 0;
3514                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3515                                                 0);
3516                         }
3517
3518                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3519                         for (i = 0; i < 2000; i++) {
3520                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3521                                 if (tmp & 0xC000)
3522                                         break;
3523                                 udelay(10);
3524                         }
3525
3526                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3527                                                 buffer);
3528                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3529                                                 buffer);
3530
3531                         if (type == 1 || type == 3 || type == 4)
3532                                 buffer[0] = diq_start;
3533                 }
3534
3535                 if (mphase)
3536                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3537
3538                 last = (dev->phy.rev < 3) ? 6 : 7;
3539
3540                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3541                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3542                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3543                         if (dev->phy.rev < 3) {
3544                                 buffer[0] = 0;
3545                                 buffer[1] = 0;
3546                                 buffer[2] = 0;
3547                                 buffer[3] = 0;
3548                         }
3549                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3550                                                 buffer);
3551                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3552                                                 buffer);
3553                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3554                                                 buffer);
3555                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3556                                                 buffer);
3557                         length = 11;
3558                         if (dev->phy.rev < 3)
3559                                 length -= 2;
3560                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3561                                                 nphy->txiqlocal_bestc);
3562                         nphy->txiqlocal_coeffsvalid = true;
3563                         nphy->txiqlocal_chanspec.center_freq =
3564                                                         dev->phy.channel_freq;
3565                         nphy->txiqlocal_chanspec.channel_type =
3566                                                         dev->phy.channel_type;
3567                 } else {
3568                         length = 11;
3569                         if (dev->phy.rev < 3)
3570                                 length -= 2;
3571                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3572                                                 nphy->mphase_txcal_bestcoeffs);
3573                 }
3574
3575                 b43_nphy_stop_playback(dev);
3576                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3577         }
3578
3579         b43_nphy_tx_cal_phy_cleanup(dev);
3580         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3581
3582         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3583                 b43_nphy_tx_iq_workaround(dev);
3584
3585         if (dev->phy.rev >= 4)
3586                 nphy->hang_avoid = avoid;
3587
3588         b43_nphy_stay_in_carrier_search(dev, false);
3589
3590         return error;
3591 }
3592
3593 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3594 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3595 {
3596         struct b43_phy_n *nphy = dev->phy.n;
3597         u8 i;
3598         u16 buffer[7];
3599         bool equal = true;
3600
3601         if (!nphy->txiqlocal_coeffsvalid ||
3602             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3603             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3604                 return;
3605
3606         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3607         for (i = 0; i < 4; i++) {
3608                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3609                         equal = false;
3610                         break;
3611                 }
3612         }
3613
3614         if (!equal) {
3615                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3616                                         nphy->txiqlocal_bestc);
3617                 for (i = 0; i < 4; i++)
3618                         buffer[i] = 0;
3619                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3620                                         buffer);
3621                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3622                                         &nphy->txiqlocal_bestc[5]);
3623                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3624                                         &nphy->txiqlocal_bestc[5]);
3625         }
3626 }
3627
3628 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3629 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3630                         struct nphy_txgains target, u8 type, bool debug)
3631 {
3632         struct b43_phy_n *nphy = dev->phy.n;
3633         int i, j, index;
3634         u8 rfctl[2];
3635         u8 afectl_core;
3636         u16 tmp[6];
3637         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3638         u32 real, imag;
3639         enum ieee80211_band band;
3640
3641         u8 use;
3642         u16 cur_hpf;
3643         u16 lna[3] = { 3, 3, 1 };
3644         u16 hpf1[3] = { 7, 2, 0 };
3645         u16 hpf2[3] = { 2, 0, 0 };
3646         u32 power[3] = { };
3647         u16 gain_save[2];
3648         u16 cal_gain[2];
3649         struct nphy_iqcal_params cal_params[2];
3650         struct nphy_iq_est est;
3651         int ret = 0;
3652         bool playtone = true;
3653         int desired = 13;
3654
3655         b43_nphy_stay_in_carrier_search(dev, 1);
3656
3657         if (dev->phy.rev < 2)
3658                 b43_nphy_reapply_tx_cal_coeffs(dev);
3659         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3660         for (i = 0; i < 2; i++) {
3661                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3662                 cal_gain[i] = cal_params[i].cal_gain;
3663         }
3664         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3665
3666         for (i = 0; i < 2; i++) {
3667                 if (i == 0) {
3668                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3669                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3670                         afectl_core = B43_NPHY_AFECTL_C1;
3671                 } else {
3672                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3673                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3674                         afectl_core = B43_NPHY_AFECTL_C2;
3675                 }
3676
3677                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3678                 tmp[2] = b43_phy_read(dev, afectl_core);
3679                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3680                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3681                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3682
3683                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3684                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3685                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3686                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3687                                 (1 - i));
3688                 b43_phy_set(dev, afectl_core, 0x0006);
3689                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3690
3691                 band = b43_current_band(dev->wl);
3692
3693                 if (nphy->rxcalparams & 0xFF000000) {
3694                         if (band == IEEE80211_BAND_5GHZ)
3695                                 b43_phy_write(dev, rfctl[0], 0x140);
3696                         else
3697                                 b43_phy_write(dev, rfctl[0], 0x110);
3698                 } else {
3699                         if (band == IEEE80211_BAND_5GHZ)
3700                                 b43_phy_write(dev, rfctl[0], 0x180);
3701                         else
3702                                 b43_phy_write(dev, rfctl[0], 0x120);
3703                 }
3704
3705                 if (band == IEEE80211_BAND_5GHZ)
3706                         b43_phy_write(dev, rfctl[1], 0x148);
3707                 else
3708                         b43_phy_write(dev, rfctl[1], 0x114);
3709
3710                 if (nphy->rxcalparams & 0x10000) {
3711                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3712                                         (i + 1));
3713                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3714                                         (2 - i));
3715                 }
3716
3717                 for (j = 0; j < 4; j++) {
3718                         if (j < 3) {
3719                                 cur_lna = lna[j];
3720                                 cur_hpf1 = hpf1[j];
3721                                 cur_hpf2 = hpf2[j];
3722                         } else {
3723                                 if (power[1] > 10000) {
3724                                         use = 1;
3725                                         cur_hpf = cur_hpf1;
3726                                         index = 2;
3727                                 } else {
3728                                         if (power[0] > 10000) {
3729                                                 use = 1;
3730                                                 cur_hpf = cur_hpf1;
3731                                                 index = 1;
3732                                         } else {
3733                                                 index = 0;
3734                                                 use = 2;
3735                                                 cur_hpf = cur_hpf2;
3736                                         }
3737                                 }
3738                                 cur_lna = lna[index];
3739                                 cur_hpf1 = hpf1[index];
3740                                 cur_hpf2 = hpf2[index];
3741                                 cur_hpf += desired - hweight32(power[index]);
3742                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3743                                 if (use == 1)
3744                                         cur_hpf1 = cur_hpf;
3745                                 else
3746                                         cur_hpf2 = cur_hpf;
3747                         }
3748
3749                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3750                                         (cur_lna << 2));
3751                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3752                                                                         false);
3753                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3754                         b43_nphy_stop_playback(dev);
3755
3756                         if (playtone) {
3757                                 ret = b43_nphy_tx_tone(dev, 4000,
3758                                                 (nphy->rxcalparams & 0xFFFF),
3759                                                 false, false);
3760                                 playtone = false;
3761                         } else {
3762                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3763                                                         false, false);
3764                         }
3765
3766                         if (ret == 0) {
3767                                 if (j < 3) {
3768                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3769                                                                         false);
3770                                         if (i == 0) {
3771                                                 real = est.i0_pwr;
3772                                                 imag = est.q0_pwr;
3773                                         } else {
3774                                                 real = est.i1_pwr;
3775                                                 imag = est.q1_pwr;
3776                                         }
3777                                         power[i] = ((real + imag) / 1024) + 1;
3778                                 } else {
3779                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3780                                 }
3781                                 b43_nphy_stop_playback(dev);
3782                         }
3783
3784                         if (ret != 0)
3785                                 break;
3786                 }
3787
3788                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3789                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3790                 b43_phy_write(dev, rfctl[1], tmp[5]);
3791                 b43_phy_write(dev, rfctl[0], tmp[4]);
3792                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3793                 b43_phy_write(dev, afectl_core, tmp[2]);
3794                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3795
3796                 if (ret != 0)
3797                         break;
3798         }
3799
3800         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3801         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3802         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3803
3804         b43_nphy_stay_in_carrier_search(dev, 0);
3805
3806         return ret;
3807 }
3808
3809 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3810                         struct nphy_txgains target, u8 type, bool debug)
3811 {
3812         return -1;
3813 }
3814
3815 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3816 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3817                         struct nphy_txgains target, u8 type, bool debug)
3818 {
3819         if (dev->phy.rev >= 3)
3820                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3821         else
3822                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3823 }
3824
3825 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3826 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3827 {
3828         struct b43_phy *phy = &dev->phy;
3829         struct b43_phy_n *nphy = phy->n;
3830         /* u16 buf[16]; it's rev3+ */
3831
3832         nphy->phyrxchain = mask;
3833
3834         if (0 /* FIXME clk */)
3835                 return;
3836
3837         b43_mac_suspend(dev);
3838
3839         if (nphy->hang_avoid)
3840                 b43_nphy_stay_in_carrier_search(dev, true);
3841
3842         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3843                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3844
3845         if ((mask & 0x3) != 0x3) {
3846                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3847                 if (dev->phy.rev >= 3) {
3848                         /* TODO */
3849                 }
3850         } else {
3851                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3852                 if (dev->phy.rev >= 3) {
3853                         /* TODO */
3854                 }
3855         }
3856
3857         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3858
3859         if (nphy->hang_avoid)
3860                 b43_nphy_stay_in_carrier_search(dev, false);
3861
3862         b43_mac_enable(dev);
3863 }
3864
3865 /*
3866  * Init N-PHY
3867  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3868  */
3869 int b43_phy_initn(struct b43_wldev *dev)
3870 {
3871         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3872         struct b43_phy *phy = &dev->phy;
3873         struct b43_phy_n *nphy = phy->n;
3874         u8 tx_pwr_state;
3875         struct nphy_txgains target;
3876         u16 tmp;
3877         enum ieee80211_band tmp2;
3878         bool do_rssi_cal;
3879
3880         u16 clip[2];
3881         bool do_cal = false;
3882
3883         if ((dev->phy.rev >= 3) &&
3884            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3885            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3886                 switch (dev->dev->bus_type) {
3887 #ifdef CONFIG_B43_BCMA
3888                 case B43_BUS_BCMA:
3889                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3890                                       BCMA_CC_CHIPCTL, 0x40);
3891                         break;
3892 #endif
3893 #ifdef CONFIG_B43_SSB
3894                 case B43_BUS_SSB:
3895                         chipco_set32(&dev->dev->sdev->bus->chipco,
3896                                      SSB_CHIPCO_CHIPCTL, 0x40);
3897                         break;
3898 #endif
3899                 }
3900         }
3901         nphy->deaf_count = 0;
3902         b43_nphy_tables_init(dev);
3903         nphy->crsminpwr_adjusted = false;
3904         nphy->noisevars_adjusted = false;
3905
3906         /* Clear all overrides */
3907         if (dev->phy.rev >= 3) {
3908                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3909                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3910                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3911                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3912         } else {
3913                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3914         }
3915         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3916         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3917         if (dev->phy.rev < 6) {
3918                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3919                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3920         }
3921         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3922                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3923                        B43_NPHY_RFSEQMODE_TROVER));
3924         if (dev->phy.rev >= 3)
3925                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3926         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3927
3928         if (dev->phy.rev <= 2) {
3929                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3930                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3931                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3932                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3933         }
3934         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3935         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3936
3937         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
3938             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3939              dev->dev->board_type == 0x8B))
3940                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3941         else
3942                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3943         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3944         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3945         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3946
3947         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3948         b43_nphy_update_txrx_chain(dev);
3949
3950         if (phy->rev < 2) {
3951                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3952                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3953         }
3954
3955         tmp2 = b43_current_band(dev->wl);
3956         if (b43_nphy_ipa(dev)) {
3957                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3958                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3959                                 nphy->papd_epsilon_offset[0] << 7);
3960                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3961                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3962                                 nphy->papd_epsilon_offset[1] << 7);
3963                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3964         } else if (phy->rev >= 5) {
3965                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3966         }
3967
3968         b43_nphy_workarounds(dev);
3969
3970         /* Reset CCA, in init code it differs a little from standard way */
3971         b43_phy_force_clock(dev, 1);
3972         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3973         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3974         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3975         b43_phy_force_clock(dev, 0);
3976
3977         b43_mac_phy_clock_set(dev, true);
3978
3979         b43_nphy_pa_override(dev, false);
3980         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3981         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3982         b43_nphy_pa_override(dev, true);
3983
3984         b43_nphy_classifier(dev, 0, 0);
3985         b43_nphy_read_clip_detection(dev, clip);
3986         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3987                 b43_nphy_bphy_init(dev);
3988
3989         tx_pwr_state = nphy->txpwrctrl;
3990         b43_nphy_tx_power_ctrl(dev, false);
3991         b43_nphy_tx_power_fix(dev);
3992         /* TODO N PHY TX Power Control Idle TSSI */
3993         /* TODO N PHY TX Power Control Setup */
3994         b43_nphy_tx_gain_table_upload(dev);
3995
3996         if (nphy->phyrxchain != 3)
3997                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3998         if (nphy->mphase_cal_phase_id > 0)
3999                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
4000
4001         do_rssi_cal = false;
4002         if (phy->rev >= 3) {
4003                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4004                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
4005                 else
4006                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
4007
4008                 if (do_rssi_cal)
4009                         b43_nphy_rssi_cal(dev);
4010                 else
4011                         b43_nphy_restore_rssi_cal(dev);
4012         } else {
4013                 b43_nphy_rssi_cal(dev);
4014         }
4015
4016         if (!((nphy->measure_hold & 0x6) != 0)) {
4017                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4018                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
4019                 else
4020                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
4021
4022                 if (nphy->mute)
4023                         do_cal = false;
4024
4025                 if (do_cal) {
4026                         target = b43_nphy_get_tx_gains(dev);
4027
4028                         if (nphy->antsel_type == 2)
4029                                 b43_nphy_superswitch_init(dev, true);
4030                         if (nphy->perical != 2) {
4031                                 b43_nphy_rssi_cal(dev);
4032                                 if (phy->rev >= 3) {
4033                                         nphy->cal_orig_pwr_idx[0] =
4034                                             nphy->txpwrindex[0].index_internal;
4035                                         nphy->cal_orig_pwr_idx[1] =
4036                                             nphy->txpwrindex[1].index_internal;
4037                                         /* TODO N PHY Pre Calibrate TX Gain */
4038                                         target = b43_nphy_get_tx_gains(dev);
4039                                 }
4040                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
4041                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
4042                                                 b43_nphy_save_cal(dev);
4043                         } else if (nphy->mphase_cal_phase_id == 0)
4044                                 ;/* N PHY Periodic Calibration with arg 3 */
4045                 } else {
4046                         b43_nphy_restore_cal(dev);
4047                 }
4048         }
4049
4050         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
4051         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
4052         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
4053         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
4054         if (phy->rev >= 3 && phy->rev <= 6)
4055                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
4056         b43_nphy_tx_lp_fbw(dev);
4057         if (phy->rev >= 3)
4058                 b43_nphy_spur_workaround(dev);
4059
4060         return 0;
4061 }
4062
4063 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
4064 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
4065 {
4066         struct bcma_drv_cc __maybe_unused *cc;
4067         u32 __maybe_unused pmu_ctl;
4068
4069         switch (dev->dev->bus_type) {
4070 #ifdef CONFIG_B43_BCMA
4071         case B43_BUS_BCMA:
4072                 cc = &dev->dev->bdev->bus->drv_cc;
4073                 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
4074                         if (avoid) {
4075                                 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
4076                                 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
4077                                 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
4078                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4079                                 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
4080                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4081                         } else {
4082                                 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
4083                                 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
4084                                 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
4085                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4086                                 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4087                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4088                         }
4089                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4090                 } else if (dev->dev->chip_id == 0x4716) {
4091                         if (avoid) {
4092                                 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
4093                                 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
4094                                 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
4095                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4096                                 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
4097                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4098                         } else {
4099                                 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
4100                                 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
4101                                 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
4102                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4103                                 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4104                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4105                         }
4106                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
4107                                   BCMA_CC_PMU_CTL_NOILPONW;
4108                 } else if (dev->dev->chip_id == 0x4322 ||
4109                            dev->dev->chip_id == 0x4340 ||
4110                            dev->dev->chip_id == 0x4341) {
4111                         bcma_chipco_pll_write(cc, 0x0, 0x11100070);
4112                         bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
4113                         bcma_chipco_pll_write(cc, 0x5, 0x88888854);
4114                         if (avoid)
4115                                 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
4116                         else
4117                                 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
4118                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4119                 } else {
4120                         return;
4121                 }
4122                 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
4123                 break;
4124 #endif
4125 #ifdef CONFIG_B43_SSB
4126         case B43_BUS_SSB:
4127                 /* FIXME */
4128                 break;
4129 #endif
4130         }
4131 }
4132
4133 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
4134 static void b43_nphy_channel_setup(struct b43_wldev *dev,
4135                                 const struct b43_phy_n_sfo_cfg *e,
4136                                 struct ieee80211_channel *new_channel)
4137 {
4138         struct b43_phy *phy = &dev->phy;
4139         struct b43_phy_n *nphy = dev->phy.n;
4140         int ch = new_channel->hw_value;
4141
4142         u16 old_band_5ghz;
4143         u32 tmp32;
4144
4145         old_band_5ghz =
4146                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
4147         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
4148                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4149                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4150                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
4151                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4152                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
4153         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
4154                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
4155                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4156                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4157                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
4158                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4159         }
4160
4161         b43_chantab_phy_upload(dev, e);
4162
4163         if (new_channel->hw_value == 14) {
4164                 b43_nphy_classifier(dev, 2, 0);
4165                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
4166         } else {
4167                 b43_nphy_classifier(dev, 2, 2);
4168                 if (new_channel->band == IEEE80211_BAND_2GHZ)
4169                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
4170         }
4171
4172         if (!nphy->txpwrctrl)
4173                 b43_nphy_tx_power_fix(dev);
4174
4175         if (dev->phy.rev < 3)
4176                 b43_nphy_adjust_lna_gain_table(dev);
4177
4178         b43_nphy_tx_lp_fbw(dev);
4179
4180         if (dev->phy.rev >= 3 &&
4181             dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
4182                 bool avoid = false;
4183                 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
4184                         avoid = true;
4185                 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
4186                         if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
4187                                 avoid = true;
4188                 } else { /* 40MHz */
4189                         if (nphy->aband_spurwar_en &&
4190                             (ch == 38 || ch == 102 || ch == 118))
4191                                 avoid = dev->dev->chip_id == 0x4716;
4192                 }
4193
4194                 b43_nphy_pmu_spur_avoid(dev, avoid);
4195
4196                 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
4197                     dev->dev->chip_id == 43225) {
4198                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
4199                                     avoid ? 0x5341 : 0x8889);
4200                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
4201                 }
4202
4203                 if (dev->phy.rev == 3 || dev->phy.rev == 4)
4204                         ; /* TODO: reset PLL */
4205
4206                 if (avoid)
4207                         b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
4208                 else
4209                         b43_phy_mask(dev, B43_NPHY_BBCFG,
4210                                      ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4211
4212                 b43_nphy_reset_cca(dev);
4213
4214                 /* wl sets useless phy_isspuravoid here */
4215         }
4216
4217         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
4218
4219         if (phy->rev >= 3)
4220                 b43_nphy_spur_workaround(dev);
4221 }
4222
4223 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
4224 static int b43_nphy_set_channel(struct b43_wldev *dev,
4225                                 struct ieee80211_channel *channel,
4226                                 enum nl80211_channel_type channel_type)
4227 {
4228         struct b43_phy *phy = &dev->phy;
4229
4230         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
4231         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
4232
4233         u8 tmp;
4234
4235         if (dev->phy.rev >= 3) {
4236                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4237                                                         channel->center_freq);
4238                 if (!tabent_r3)
4239                         return -ESRCH;
4240         } else {
4241                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4242                                                         channel->hw_value);
4243                 if (!tabent_r2)
4244                         return -ESRCH;
4245         }
4246
4247         /* Channel is set later in common code, but we need to set it on our
4248            own to let this function's subcalls work properly. */
4249         phy->channel = channel->hw_value;
4250         phy->channel_freq = channel->center_freq;
4251
4252         if (b43_channel_type_is_40mhz(phy->channel_type) !=
4253                 b43_channel_type_is_40mhz(channel_type))
4254                 ; /* TODO: BMAC BW Set (channel_type) */
4255
4256         if (channel_type == NL80211_CHAN_HT40PLUS)
4257                 b43_phy_set(dev, B43_NPHY_RXCTL,
4258                                 B43_NPHY_RXCTL_BSELU20);
4259         else if (channel_type == NL80211_CHAN_HT40MINUS)
4260                 b43_phy_mask(dev, B43_NPHY_RXCTL,
4261                                 ~B43_NPHY_RXCTL_BSELU20);
4262
4263         if (dev->phy.rev >= 3) {
4264                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
4265                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
4266                 b43_radio_2056_setup(dev, tabent_r3);
4267                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
4268         } else {
4269                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
4270                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
4271                 b43_radio_2055_setup(dev, tabent_r2);
4272                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
4273         }
4274
4275         return 0;
4276 }
4277
4278 static int b43_nphy_op_allocate(struct b43_wldev *dev)
4279 {
4280         struct b43_phy_n *nphy;
4281
4282         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4283         if (!nphy)
4284                 return -ENOMEM;
4285         dev->phy.n = nphy;
4286
4287         return 0;
4288 }
4289
4290 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
4291 {
4292         struct b43_phy *phy = &dev->phy;
4293         struct b43_phy_n *nphy = phy->n;
4294         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4295
4296         memset(nphy, 0, sizeof(*nphy));
4297
4298         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
4299         nphy->spur_avoid = (phy->rev >= 3) ?
4300                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
4301         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4302         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4303         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
4304         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
4305         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4306          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4307         nphy->tx_pwr_idx[0] = 128;
4308         nphy->tx_pwr_idx[1] = 128;
4309
4310         /* Hardware TX power control and 5GHz power gain */
4311         nphy->txpwrctrl = false;
4312         nphy->pwg_gain_5ghz = false;
4313         if (dev->phy.rev >= 3 ||
4314             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4315              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
4316                 nphy->txpwrctrl = true;
4317                 nphy->pwg_gain_5ghz = true;
4318         } else if (sprom->revision >= 4) {
4319                 if (dev->phy.rev >= 2 &&
4320                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
4321                         nphy->txpwrctrl = true;
4322 #ifdef CONFIG_B43_SSB
4323                         if (dev->dev->bus_type == B43_BUS_SSB &&
4324                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
4325                                 struct pci_dev *pdev =
4326                                         dev->dev->sdev->bus->host_pci;
4327                                 if (pdev->device == 0x4328 ||
4328                                     pdev->device == 0x432a)
4329                                         nphy->pwg_gain_5ghz = true;
4330                         }
4331 #endif
4332                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
4333                         nphy->pwg_gain_5ghz = true;
4334                 }
4335         }
4336
4337         if (dev->phy.rev >= 3) {
4338                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4339                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4340         }
4341 }
4342
4343 static void b43_nphy_op_free(struct b43_wldev *dev)
4344 {
4345         struct b43_phy *phy = &dev->phy;
4346         struct b43_phy_n *nphy = phy->n;
4347
4348         kfree(nphy);
4349         phy->n = NULL;
4350 }
4351
4352 static int b43_nphy_op_init(struct b43_wldev *dev)
4353 {
4354         return b43_phy_initn(dev);
4355 }
4356
4357 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4358 {
4359 #if B43_DEBUG
4360         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4361                 /* OFDM registers are onnly available on A/G-PHYs */
4362                 b43err(dev->wl, "Invalid OFDM PHY access at "
4363                        "0x%04X on N-PHY\n", offset);
4364                 dump_stack();
4365         }
4366         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4367                 /* Ext-G registers are only available on G-PHYs */
4368                 b43err(dev->wl, "Invalid EXT-G PHY access at "
4369                        "0x%04X on N-PHY\n", offset);
4370                 dump_stack();
4371         }
4372 #endif /* B43_DEBUG */
4373 }
4374
4375 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4376 {
4377         check_phyreg(dev, reg);
4378         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4379         return b43_read16(dev, B43_MMIO_PHY_DATA);
4380 }
4381
4382 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4383 {
4384         check_phyreg(dev, reg);
4385         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4386         b43_write16(dev, B43_MMIO_PHY_DATA, value);
4387 }
4388
4389 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4390                                  u16 set)
4391 {
4392         check_phyreg(dev, reg);
4393         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4394         b43_write16(dev, B43_MMIO_PHY_DATA,
4395                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4396 }
4397
4398 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4399 {
4400         /* Register 1 is a 32-bit register. */
4401         B43_WARN_ON(reg == 1);
4402         /* N-PHY needs 0x100 for read access */
4403         reg |= 0x100;
4404
4405         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4406         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4407 }
4408
4409 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4410 {
4411         /* Register 1 is a 32-bit register. */
4412         B43_WARN_ON(reg == 1);
4413
4414         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4415         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4416 }
4417
4418 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4419 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4420                                         bool blocked)
4421 {
4422         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4423                 b43err(dev->wl, "MAC not suspended\n");
4424
4425         if (blocked) {
4426                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4427                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4428                 if (dev->phy.rev >= 3) {
4429                         b43_radio_mask(dev, 0x09, ~0x2);
4430
4431                         b43_radio_write(dev, 0x204D, 0);
4432                         b43_radio_write(dev, 0x2053, 0);
4433                         b43_radio_write(dev, 0x2058, 0);
4434                         b43_radio_write(dev, 0x205E, 0);
4435                         b43_radio_mask(dev, 0x2062, ~0xF0);
4436                         b43_radio_write(dev, 0x2064, 0);
4437
4438                         b43_radio_write(dev, 0x304D, 0);
4439                         b43_radio_write(dev, 0x3053, 0);
4440                         b43_radio_write(dev, 0x3058, 0);
4441                         b43_radio_write(dev, 0x305E, 0);
4442                         b43_radio_mask(dev, 0x3062, ~0xF0);
4443                         b43_radio_write(dev, 0x3064, 0);
4444                 }
4445         } else {
4446                 if (dev->phy.rev >= 3) {
4447                         b43_radio_init2056(dev);
4448                         b43_switch_channel(dev, dev->phy.channel);
4449                 } else {
4450                         b43_radio_init2055(dev);
4451                 }
4452         }
4453 }
4454
4455 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4456 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4457 {
4458         u16 override = on ? 0x0 : 0x7FFF;
4459         u16 core = on ? 0xD : 0x00FD;
4460
4461         if (dev->phy.rev >= 3) {
4462                 if (on) {
4463                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4464                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4465                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4466                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4467                 } else {
4468                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4469                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4470                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4471                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4472                 }
4473         } else {
4474                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4475         }
4476 }
4477
4478 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4479                                       unsigned int new_channel)
4480 {
4481         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4482         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4483
4484         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4485                 if ((new_channel < 1) || (new_channel > 14))
4486                         return -EINVAL;
4487         } else {
4488                 if (new_channel > 200)
4489                         return -EINVAL;
4490         }
4491
4492         return b43_nphy_set_channel(dev, channel, channel_type);
4493 }
4494
4495 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4496 {
4497         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4498                 return 1;
4499         return 36;
4500 }
4501
4502 const struct b43_phy_operations b43_phyops_n = {
4503         .allocate               = b43_nphy_op_allocate,
4504         .free                   = b43_nphy_op_free,
4505         .prepare_structs        = b43_nphy_op_prepare_structs,
4506         .init                   = b43_nphy_op_init,
4507         .phy_read               = b43_nphy_op_read,
4508         .phy_write              = b43_nphy_op_write,
4509         .phy_maskset            = b43_nphy_op_maskset,
4510         .radio_read             = b43_nphy_op_radio_read,
4511         .radio_write            = b43_nphy_op_radio_write,
4512         .software_rfkill        = b43_nphy_op_software_rfkill,
4513         .switch_analog          = b43_nphy_op_switch_analog,
4514         .switch_channel         = b43_nphy_op_switch_channel,
4515         .get_default_chan       = b43_nphy_op_get_default_chan,
4516         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4517         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4518 };