3 Broadcom B43 wireless driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
29 #include "phy_common.h"
40 int b43_phy_allocate(struct b43_wldev *dev)
42 struct b43_phy *phy = &(dev->phy);
49 #ifdef CONFIG_B43_PHY_G
50 phy->ops = &b43_phyops_g;
54 #ifdef CONFIG_B43_PHY_N
55 phy->ops = &b43_phyops_n;
59 #ifdef CONFIG_B43_PHY_LP
60 phy->ops = &b43_phyops_lp;
64 #ifdef CONFIG_B43_PHY_HT
65 phy->ops = &b43_phyops_ht;
69 #ifdef CONFIG_B43_PHY_LCN
70 phy->ops = &b43_phyops_lcn;
74 if (B43_WARN_ON(!phy->ops))
77 err = phy->ops->allocate(dev);
84 void b43_phy_free(struct b43_wldev *dev)
86 dev->phy.ops->free(dev);
90 int b43_phy_init(struct b43_wldev *dev)
92 struct b43_phy *phy = &dev->phy;
93 const struct b43_phy_operations *ops = phy->ops;
96 /* During PHY init we need to use some channel. On the first init this
97 * function is called *before* b43_op_config, so our pointer is NULL.
100 phy->chandef = &dev->wl->hw->conf.chandef;
101 phy->channel = phy->chandef->chan->hw_value;
104 phy->ops->switch_analog(dev, true);
105 b43_software_rfkill(dev, false);
107 err = ops->init(dev);
109 b43err(dev->wl, "PHY init failed\n");
112 phy->do_full_init = false;
114 err = b43_switch_channel(dev, phy->channel);
116 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
123 phy->do_full_init = true;
127 b43_software_rfkill(dev, true);
132 void b43_phy_exit(struct b43_wldev *dev)
134 const struct b43_phy_operations *ops = dev->phy.ops;
136 b43_software_rfkill(dev, true);
137 dev->phy.do_full_init = true;
142 bool b43_has_hardware_pctl(struct b43_wldev *dev)
144 if (!dev->phy.hardware_power_control)
146 if (!dev->phy.ops->supports_hwpctl)
148 return dev->phy.ops->supports_hwpctl(dev);
151 void b43_radio_lock(struct b43_wldev *dev)
156 B43_WARN_ON(dev->phy.radio_locked);
157 dev->phy.radio_locked = true;
160 macctl = b43_read32(dev, B43_MMIO_MACCTL);
161 macctl |= B43_MACCTL_RADIOLOCK;
162 b43_write32(dev, B43_MMIO_MACCTL, macctl);
163 /* Commit the write and wait for the firmware
164 * to finish any radio register access. */
165 b43_read32(dev, B43_MMIO_MACCTL);
169 void b43_radio_unlock(struct b43_wldev *dev)
174 B43_WARN_ON(!dev->phy.radio_locked);
175 dev->phy.radio_locked = false;
178 /* Commit any write */
179 b43_read16(dev, B43_MMIO_PHY_VER);
181 macctl = b43_read32(dev, B43_MMIO_MACCTL);
182 macctl &= ~B43_MACCTL_RADIOLOCK;
183 b43_write32(dev, B43_MMIO_MACCTL, macctl);
186 void b43_phy_lock(struct b43_wldev *dev)
189 B43_WARN_ON(dev->phy.phy_locked);
190 dev->phy.phy_locked = true;
192 B43_WARN_ON(dev->dev->core_rev < 3);
194 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
195 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
198 void b43_phy_unlock(struct b43_wldev *dev)
201 B43_WARN_ON(!dev->phy.phy_locked);
202 dev->phy.phy_locked = false;
204 B43_WARN_ON(dev->dev->core_rev < 3);
206 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
207 b43_power_saving_ctl_bits(dev, 0);
210 static inline void assert_mac_suspended(struct b43_wldev *dev)
214 if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
215 (dev->mac_suspended <= 0)) {
216 b43dbg(dev->wl, "PHY/RADIO register access with "
222 u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
224 assert_mac_suspended(dev);
225 dev->phy.writes_counter = 0;
226 return dev->phy.ops->radio_read(dev, reg);
229 void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
231 assert_mac_suspended(dev);
232 if (b43_bus_host_is_pci(dev->dev) &&
233 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
234 b43_read32(dev, B43_MMIO_MACCTL);
235 dev->phy.writes_counter = 1;
237 dev->phy.ops->radio_write(dev, reg, value);
240 void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
242 b43_radio_write16(dev, offset,
243 b43_radio_read16(dev, offset) & mask);
246 void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
248 b43_radio_write16(dev, offset,
249 b43_radio_read16(dev, offset) | set);
252 void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
254 b43_radio_write16(dev, offset,
255 (b43_radio_read16(dev, offset) & mask) | set);
258 bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
259 u16 value, int delay, int timeout)
264 for (i = 0; i < timeout; i += delay) {
265 val = b43_radio_read(dev, offset);
266 if ((val & mask) == value)
273 u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
275 assert_mac_suspended(dev);
276 dev->phy.writes_counter = 0;
278 if (dev->phy.ops->phy_read)
279 return dev->phy.ops->phy_read(dev, reg);
281 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
282 return b43_read16(dev, B43_MMIO_PHY_DATA);
285 void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
287 assert_mac_suspended(dev);
288 if (b43_bus_host_is_pci(dev->dev) &&
289 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
290 b43_read16(dev, B43_MMIO_PHY_VER);
291 dev->phy.writes_counter = 1;
294 if (dev->phy.ops->phy_write)
295 return dev->phy.ops->phy_write(dev, reg, value);
297 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
298 b43_write16(dev, B43_MMIO_PHY_DATA, value);
301 void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
303 b43_phy_write(dev, destreg, b43_phy_read(dev, srcreg));
306 void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
308 if (dev->phy.ops->phy_maskset) {
309 assert_mac_suspended(dev);
310 dev->phy.ops->phy_maskset(dev, offset, mask, 0);
312 b43_phy_write(dev, offset,
313 b43_phy_read(dev, offset) & mask);
317 void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
319 if (dev->phy.ops->phy_maskset) {
320 assert_mac_suspended(dev);
321 dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
323 b43_phy_write(dev, offset,
324 b43_phy_read(dev, offset) | set);
328 void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
330 if (dev->phy.ops->phy_maskset) {
331 assert_mac_suspended(dev);
332 dev->phy.ops->phy_maskset(dev, offset, mask, set);
334 b43_phy_write(dev, offset,
335 (b43_phy_read(dev, offset) & mask) | set);
339 void b43_phy_put_into_reset(struct b43_wldev *dev)
343 switch (dev->dev->bus_type) {
344 #ifdef CONFIG_B43_BCMA
346 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
347 tmp &= ~B43_BCMA_IOCTL_GMODE;
348 tmp |= B43_BCMA_IOCTL_PHY_RESET;
349 tmp |= BCMA_IOCTL_FGC;
350 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
353 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
354 tmp &= ~BCMA_IOCTL_FGC;
355 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
359 #ifdef CONFIG_B43_SSB
361 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
362 tmp &= ~B43_TMSLOW_GMODE;
363 tmp |= B43_TMSLOW_PHYRESET;
364 tmp |= SSB_TMSLOW_FGC;
365 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
366 usleep_range(1000, 2000);
368 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
369 tmp &= ~SSB_TMSLOW_FGC;
370 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
371 usleep_range(1000, 2000);
378 void b43_phy_take_out_of_reset(struct b43_wldev *dev)
382 switch (dev->dev->bus_type) {
383 #ifdef CONFIG_B43_BCMA
385 /* Unset reset bit (with forcing clock) */
386 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
387 tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
388 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
389 tmp |= BCMA_IOCTL_FGC;
390 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
393 /* Do not force clock anymore */
394 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
395 tmp &= ~BCMA_IOCTL_FGC;
396 tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
397 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
401 #ifdef CONFIG_B43_SSB
403 /* Unset reset bit (with forcing clock) */
404 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
405 tmp &= ~B43_TMSLOW_PHYRESET;
406 tmp &= ~B43_TMSLOW_PHYCLKEN;
407 tmp |= SSB_TMSLOW_FGC;
408 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
409 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
410 usleep_range(1000, 2000);
412 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
413 tmp &= ~SSB_TMSLOW_FGC;
414 tmp |= B43_TMSLOW_PHYCLKEN;
415 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
416 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
417 usleep_range(1000, 2000);
423 int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
425 struct b43_phy *phy = &(dev->phy);
426 u16 channelcookie, savedcookie;
429 /* First we set the channel radio code to prevent the
430 * firmware from sending ghost packets.
432 channelcookie = new_channel;
433 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
434 channelcookie |= B43_SHM_SH_CHAN_5GHZ;
435 /* FIXME: set 40Mhz flag if required */
437 channelcookie |= B43_SHM_SH_CHAN_40MHZ;
438 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
439 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
441 /* Now try to switch the PHY hardware channel. */
442 err = phy->ops->switch_channel(dev, new_channel);
444 goto err_restore_cookie;
446 /* Wait for the radio to tune to the channel and stabilize. */
452 b43_shm_write16(dev, B43_SHM_SHARED,
453 B43_SHM_SH_CHAN, savedcookie);
458 void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
460 struct b43_phy *phy = &dev->phy;
462 b43_mac_suspend(dev);
463 phy->ops->software_rfkill(dev, blocked);
464 phy->radio_on = !blocked;
469 * b43_phy_txpower_adjust_work - TX power workqueue.
471 * Workqueue for updating the TX power parameters in hardware.
473 void b43_phy_txpower_adjust_work(struct work_struct *work)
475 struct b43_wl *wl = container_of(work, struct b43_wl,
476 txpower_adjust_work);
477 struct b43_wldev *dev;
479 mutex_lock(&wl->mutex);
480 dev = wl->current_dev;
482 if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
483 dev->phy.ops->adjust_txpower(dev);
485 mutex_unlock(&wl->mutex);
488 void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
490 struct b43_phy *phy = &dev->phy;
491 unsigned long now = jiffies;
492 enum b43_txpwr_result result;
494 if (!(flags & B43_TXPWR_IGNORE_TIME)) {
495 /* Check if it's time for a TXpower check. */
496 if (time_before(now, phy->next_txpwr_check_time))
497 return; /* Not yet */
499 /* The next check will be needed in two seconds, or later. */
500 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
502 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
503 (dev->dev->board_type == SSB_BOARD_BU4306))
504 return; /* No software txpower adjustment needed */
506 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
507 if (result == B43_TXPWR_RES_DONE)
508 return; /* We are done. */
509 B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
510 B43_WARN_ON(phy->ops->adjust_txpower == NULL);
512 /* We must adjust the transmission power in hardware.
513 * Schedule b43_phy_txpower_adjust_work(). */
514 ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
517 int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
519 const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
520 unsigned int a, b, c, d;
521 unsigned int average;
524 tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
526 b = (tmp >> 8) & 0xFF;
527 c = (tmp >> 16) & 0xFF;
528 d = (tmp >> 24) & 0xFF;
529 if (a == 0 || a == B43_TSSI_MAX ||
530 b == 0 || b == B43_TSSI_MAX ||
531 c == 0 || c == B43_TSSI_MAX ||
532 d == 0 || d == B43_TSSI_MAX)
534 /* The values are OK. Clear them. */
535 tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
536 (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
537 b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
546 /* Get the average of the values with 0.5 added to each value. */
547 average = (a + b + c + d + 2) / 4;
549 /* Adjust for CCK-boost */
550 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
552 average = (average >= 13) ? (average - 13) : 0;
558 void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
560 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
564 bool b43_is_40mhz(struct b43_wldev *dev)
566 return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
569 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
570 void b43_phy_force_clock(struct b43_wldev *dev, bool force)
574 WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
575 dev->phy.type != B43_PHYTYPE_HT);
577 switch (dev->dev->bus_type) {
578 #ifdef CONFIG_B43_BCMA
580 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
582 tmp |= BCMA_IOCTL_FGC;
584 tmp &= ~BCMA_IOCTL_FGC;
585 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
588 #ifdef CONFIG_B43_SSB
590 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
592 tmp |= SSB_TMSLOW_FGC;
594 tmp &= ~SSB_TMSLOW_FGC;
595 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
601 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
602 struct b43_c32 b43_cordic(int theta)
604 static const u32 arctg[] = {
605 2949120, 1740967, 919879, 466945, 234379, 117304,
606 58666, 29335, 14668, 7334, 3667, 1833,
607 917, 458, 229, 115, 57, 29,
613 struct b43_c32 ret = { .i = 39797, .q = 0, };
615 while (theta > (180 << 16))
616 theta -= (360 << 16);
617 while (theta < -(180 << 16))
618 theta += (360 << 16);
620 if (theta > (90 << 16)) {
621 theta -= (180 << 16);
623 } else if (theta < -(90 << 16)) {
624 theta += (180 << 16);
628 for (i = 0; i <= 17; i++) {
630 tmp = ret.i - (ret.q >> i);
635 tmp = ret.i + (ret.q >> i);