drivers/net/wireless/b43/dma.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   DMA ringbuffer and descriptor allocation/management
   6
   7   Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
   8
   9   Some code in this file is derived from the b44.c driver
  10   Copyright (C) 2002 David S. Miller
  11   Copyright (C) Pekka Pietikainen
  12
  13   This program is free software; you can redistribute it and/or modify
  14   it under the terms of the GNU General Public License as published by
  15   the Free Software Foundation; either version 2 of the License, or
  16   (at your option) any later version.
  17
  18   This program is distributed in the hope that it will be useful,
  19   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21   GNU General Public License for more details.
  22
  23   You should have received a copy of the GNU General Public License
  24   along with this program; see the file COPYING.  If not, write to
  25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  26   Boston, MA 02110-1301, USA.
  27
  28 */
  29
  30 #include "b43.h"
  31 #include "dma.h"
  32 #include "main.h"
  33 #include "debugfs.h"
  34 #include "xmit.h"
  35
  36 #include <linux/dma-mapping.h>
  37 #include <linux/pci.h>
  38 #include <linux/delay.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/etherdevice.h>
  41 #include <linux/slab.h>
  42 #include <asm/div64.h>
  43
  44
  45 /* Required number of TX DMA slots per TX frame.
  46  * This currently is 2, because we put the header and the ieee80211 frame
  47  * into separate slots. */
  48 #define TX_SLOTS_PER_FRAME      2
  49
  50 static u32 b43_dma_address(struct b43_dma *dma, dma_addr_t dmaaddr,
  51                            enum b43_addrtype addrtype)
  52 {
  53         u32 uninitialized_var(addr);
  54
  55         switch (addrtype) {
  56         case B43_DMA_ADDR_LOW:
  57                 addr = lower_32_bits(dmaaddr);
  58                 if (dma->translation_in_low) {
  59                         addr &= ~SSB_DMA_TRANSLATION_MASK;
  60                         addr |= dma->translation;
  61                 }
  62                 break;
  63         case B43_DMA_ADDR_HIGH:
  64                 addr = upper_32_bits(dmaaddr);
  65                 if (!dma->translation_in_low) {
  66                         addr &= ~SSB_DMA_TRANSLATION_MASK;
  67                         addr |= dma->translation;
  68                 }
  69                 break;
  70         case B43_DMA_ADDR_EXT:
  71                 if (dma->translation_in_low)
  72                         addr = lower_32_bits(dmaaddr);
  73                 else
  74                         addr = upper_32_bits(dmaaddr);
  75                 addr &= SSB_DMA_TRANSLATION_MASK;
  76                 addr >>= SSB_DMA_TRANSLATION_SHIFT;
  77                 break;
  78         }
  79
  80         return addr;
  81 }
  82
  83 /* 32bit DMA ops. */
  84 static
  85 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
  86                                           int slot,
  87                                           struct b43_dmadesc_meta **meta)
  88 {
  89         struct b43_dmadesc32 *desc;
  90
  91         *meta = &(ring->meta[slot]);
  92         desc = ring->descbase;
  93         desc = &(desc[slot]);
  94
  95         return (struct b43_dmadesc_generic *)desc;
  96 }
  97
  98 static void op32_fill_descriptor(struct b43_dmaring *ring,
  99                                  struct b43_dmadesc_generic *desc,
 100                                  dma_addr_t dmaaddr, u16 bufsize,
 101                                  int start, int end, int irq)
 102 {
 103         struct b43_dmadesc32 *descbase = ring->descbase;
 104         int slot;
 105         u32 ctl;
 106         u32 addr;
 107         u32 addrext;
 108
 109         slot = (int)(&(desc->dma32) - descbase);
 110         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 111
 112         addr = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW);
 113         addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT);
 114
 115         ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
 116         if (slot == ring->nr_slots - 1)
 117                 ctl |= B43_DMA32_DCTL_DTABLEEND;
 118         if (start)
 119                 ctl |= B43_DMA32_DCTL_FRAMESTART;
 120         if (end)
 121                 ctl |= B43_DMA32_DCTL_FRAMEEND;
 122         if (irq)
 123                 ctl |= B43_DMA32_DCTL_IRQ;
 124         ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
 125             & B43_DMA32_DCTL_ADDREXT_MASK;
 126
 127         desc->dma32.control = cpu_to_le32(ctl);
 128         desc->dma32.address = cpu_to_le32(addr);
 129 }
 130
 131 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
 132 {
 133         b43_dma_write(ring, B43_DMA32_TXINDEX,
 134                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 135 }
 136
 137 static void op32_tx_suspend(struct b43_dmaring *ring)
 138 {
 139         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 140                       | B43_DMA32_TXSUSPEND);
 141 }
 142
 143 static void op32_tx_resume(struct b43_dmaring *ring)
 144 {
 145         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 146                       & ~B43_DMA32_TXSUSPEND);
 147 }
 148
 149 static int op32_get_current_rxslot(struct b43_dmaring *ring)
 150 {
 151         u32 val;
 152
 153         val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
 154         val &= B43_DMA32_RXDPTR;
 155
 156         return (val / sizeof(struct b43_dmadesc32));
 157 }
 158
 159 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
 160 {
 161         b43_dma_write(ring, B43_DMA32_RXINDEX,
 162                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 163 }
 164
 165 static const struct b43_dma_ops dma32_ops = {
 166         .idx2desc = op32_idx2desc,
 167         .fill_descriptor = op32_fill_descriptor,
 168         .poke_tx = op32_poke_tx,
 169         .tx_suspend = op32_tx_suspend,
 170         .tx_resume = op32_tx_resume,
 171         .get_current_rxslot = op32_get_current_rxslot,
 172         .set_current_rxslot = op32_set_current_rxslot,
 173 };
 174
 175 /* 64bit DMA ops. */
 176 static
 177 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
 178                                           int slot,
 179                                           struct b43_dmadesc_meta **meta)
 180 {
 181         struct b43_dmadesc64 *desc;
 182
 183         *meta = &(ring->meta[slot]);
 184         desc = ring->descbase;
 185         desc = &(desc[slot]);
 186
 187         return (struct b43_dmadesc_generic *)desc;
 188 }
 189
 190 static void op64_fill_descriptor(struct b43_dmaring *ring,
 191                                  struct b43_dmadesc_generic *desc,
 192                                  dma_addr_t dmaaddr, u16 bufsize,
 193                                  int start, int end, int irq)
 194 {
 195         struct b43_dmadesc64 *descbase = ring->descbase;
 196         int slot;
 197         u32 ctl0 = 0, ctl1 = 0;
 198         u32 addrlo, addrhi;
 199         u32 addrext;
 200
 201         slot = (int)(&(desc->dma64) - descbase);
 202         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 203
 204         addrlo = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW);
 205         addrhi = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_HIGH);
 206         addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT);
 207
 208         if (slot == ring->nr_slots - 1)
 209                 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
 210         if (start)
 211                 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
 212         if (end)
 213                 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
 214         if (irq)
 215                 ctl0 |= B43_DMA64_DCTL0_IRQ;
 216         ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
 217         ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
 218             & B43_DMA64_DCTL1_ADDREXT_MASK;
 219
 220         desc->dma64.control0 = cpu_to_le32(ctl0);
 221         desc->dma64.control1 = cpu_to_le32(ctl1);
 222         desc->dma64.address_low = cpu_to_le32(addrlo);
 223         desc->dma64.address_high = cpu_to_le32(addrhi);
 224 }
 225
 226 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
 227 {
 228         b43_dma_write(ring, B43_DMA64_TXINDEX,
 229                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 230 }
 231
 232 static void op64_tx_suspend(struct b43_dmaring *ring)
 233 {
 234         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 235                       | B43_DMA64_TXSUSPEND);
 236 }
 237
 238 static void op64_tx_resume(struct b43_dmaring *ring)
 239 {
 240         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 241                       & ~B43_DMA64_TXSUSPEND);
 242 }
 243
 244 static int op64_get_current_rxslot(struct b43_dmaring *ring)
 245 {
 246         u32 val;
 247
 248         val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
 249         val &= B43_DMA64_RXSTATDPTR;
 250
 251         return (val / sizeof(struct b43_dmadesc64));
 252 }
 253
 254 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
 255 {
 256         b43_dma_write(ring, B43_DMA64_RXINDEX,
 257                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 258 }
 259
 260 static const struct b43_dma_ops dma64_ops = {
 261         .idx2desc = op64_idx2desc,
 262         .fill_descriptor = op64_fill_descriptor,
 263         .poke_tx = op64_poke_tx,
 264         .tx_suspend = op64_tx_suspend,
 265         .tx_resume = op64_tx_resume,
 266         .get_current_rxslot = op64_get_current_rxslot,
 267         .set_current_rxslot = op64_set_current_rxslot,
 268 };
 269
 270 static inline int free_slots(struct b43_dmaring *ring)
 271 {
 272         return (ring->nr_slots - ring->used_slots);
 273 }
 274
 275 static inline int next_slot(struct b43_dmaring *ring, int slot)
 276 {
 277         B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
 278         if (slot == ring->nr_slots - 1)
 279                 return 0;
 280         return slot + 1;
 281 }
 282
 283 static inline int prev_slot(struct b43_dmaring *ring, int slot)
 284 {
 285         B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
 286         if (slot == 0)
 287                 return ring->nr_slots - 1;
 288         return slot - 1;
 289 }
 290
 291 #ifdef CONFIG_B43_DEBUG
 292 static void update_max_used_slots(struct b43_dmaring *ring,
 293                                   int current_used_slots)
 294 {
 295         if (current_used_slots <= ring->max_used_slots)
 296                 return;
 297         ring->max_used_slots = current_used_slots;
 298         if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
 299                 b43dbg(ring->dev->wl,
 300                        "max_used_slots increased to %d on %s ring %d\n",
 301                        ring->max_used_slots,
 302                        ring->tx ? "TX" : "RX", ring->index);
 303         }
 304 }
 305 #else
 306 static inline
 307     void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
 308 {
 309 }
 310 #endif /* DEBUG */
 311
 312 /* Request a slot for usage. */
 313 static inline int request_slot(struct b43_dmaring *ring)
 314 {
 315         int slot;
 316
 317         B43_WARN_ON(!ring->tx);
 318         B43_WARN_ON(ring->stopped);
 319         B43_WARN_ON(free_slots(ring) == 0);
 320
 321         slot = next_slot(ring, ring->current_slot);
 322         ring->current_slot = slot;
 323         ring->used_slots++;
 324
 325         update_max_used_slots(ring, ring->used_slots);
 326
 327         return slot;
 328 }
 329
 330 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
 331 {
 332         static const u16 map64[] = {
 333                 B43_MMIO_DMA64_BASE0,
 334                 B43_MMIO_DMA64_BASE1,
 335                 B43_MMIO_DMA64_BASE2,
 336                 B43_MMIO_DMA64_BASE3,
 337                 B43_MMIO_DMA64_BASE4,
 338                 B43_MMIO_DMA64_BASE5,
 339         };
 340         static const u16 map32[] = {
 341                 B43_MMIO_DMA32_BASE0,
 342                 B43_MMIO_DMA32_BASE1,
 343                 B43_MMIO_DMA32_BASE2,
 344                 B43_MMIO_DMA32_BASE3,
 345                 B43_MMIO_DMA32_BASE4,
 346                 B43_MMIO_DMA32_BASE5,
 347         };
 348
 349         if (type == B43_DMA_64BIT) {
 350                 B43_WARN_ON(!(controller_idx >= 0 &&
 351                               controller_idx < ARRAY_SIZE(map64)));
 352                 return map64[controller_idx];
 353         }
 354         B43_WARN_ON(!(controller_idx >= 0 &&
 355                       controller_idx < ARRAY_SIZE(map32)));
 356         return map32[controller_idx];
 357 }
 358
 359 static inline
 360     dma_addr_t map_descbuffer(struct b43_dmaring *ring,
 361                               unsigned char *buf, size_t len, int tx)
 362 {
 363         dma_addr_t dmaaddr;
 364
 365         if (tx) {
 366                 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
 367                                          buf, len, DMA_TO_DEVICE);
 368         } else {
 369                 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
 370                                          buf, len, DMA_FROM_DEVICE);
 371         }
 372
 373         return dmaaddr;
 374 }
 375
 376 static inline
 377     void unmap_descbuffer(struct b43_dmaring *ring,
 378                           dma_addr_t addr, size_t len, int tx)
 379 {
 380         if (tx) {
 381                 dma_unmap_single(ring->dev->dev->dma_dev,
 382                                  addr, len, DMA_TO_DEVICE);
 383         } else {
 384                 dma_unmap_single(ring->dev->dev->dma_dev,
 385                                  addr, len, DMA_FROM_DEVICE);
 386         }
 387 }
 388
 389 static inline
 390     void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
 391                                  dma_addr_t addr, size_t len)
 392 {
 393         B43_WARN_ON(ring->tx);
 394         dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
 395                                     addr, len, DMA_FROM_DEVICE);
 396 }
 397
 398 static inline
 399     void sync_descbuffer_for_device(struct b43_dmaring *ring,
 400                                     dma_addr_t addr, size_t len)
 401 {
 402         B43_WARN_ON(ring->tx);
 403         dma_sync_single_for_device(ring->dev->dev->dma_dev,
 404                                    addr, len, DMA_FROM_DEVICE);
 405 }
 406
 407 static inline
 408     void free_descriptor_buffer(struct b43_dmaring *ring,
 409                                 struct b43_dmadesc_meta *meta)
 410 {
 411         if (meta->skb) {
 412                 dev_kfree_skb_any(meta->skb);
 413                 meta->skb = NULL;
 414         }
 415 }
 416
 417 static int alloc_ringmemory(struct b43_dmaring *ring)
 418 {
 419         gfp_t flags = GFP_KERNEL;
 420
 421         /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
 422          * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
 423          * has shown that 4K is sufficient for the latter as long as the buffer
 424          * does not cross an 8K boundary.
 425          *
 426          * For unknown reasons - possibly a hardware error - the BCM4311 rev
 427          * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
 428          * which accounts for the GFP_DMA flag below.
 429          *
 430          * The flags here must match the flags in free_ringmemory below!
 431          */
 432         if (ring->type == B43_DMA_64BIT)
 433                 flags |= GFP_DMA;
 434         ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
 435                                             B43_DMA_RINGMEMSIZE,
 436                                             &(ring->dmabase), flags);
 437         if (!ring->descbase) {
 438                 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
 439                 return -ENOMEM;
 440         }
 441         memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
 442
 443         return 0;
 444 }
 445
 446 static void free_ringmemory(struct b43_dmaring *ring)
 447 {
 448         dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
 449                           ring->descbase, ring->dmabase);
 450 }
 451
 452 /* Reset the RX DMA channel */
 453 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
 454                                       enum b43_dmatype type)
 455 {
 456         int i;
 457         u32 value;
 458         u16 offset;
 459
 460         might_sleep();
 461
 462         offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
 463         b43_write32(dev, mmio_base + offset, 0);
 464         for (i = 0; i < 10; i++) {
 465                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
 466                                                    B43_DMA32_RXSTATUS;
 467                 value = b43_read32(dev, mmio_base + offset);
 468                 if (type == B43_DMA_64BIT) {
 469                         value &= B43_DMA64_RXSTAT;
 470                         if (value == B43_DMA64_RXSTAT_DISABLED) {
 471                                 i = -1;
 472                                 break;
 473                         }
 474                 } else {
 475                         value &= B43_DMA32_RXSTATE;
 476                         if (value == B43_DMA32_RXSTAT_DISABLED) {
 477                                 i = -1;
 478                                 break;
 479                         }
 480                 }
 481                 msleep(1);
 482         }
 483         if (i != -1) {
 484                 b43err(dev->wl, "DMA RX reset timed out\n");
 485                 return -ENODEV;
 486         }
 487
 488         return 0;
 489 }
 490
 491 /* Reset the TX DMA channel */
 492 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
 493                                       enum b43_dmatype type)
 494 {
 495         int i;
 496         u32 value;
 497         u16 offset;
 498
 499         might_sleep();
 500
 501         for (i = 0; i < 10; i++) {
 502                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 503                                                    B43_DMA32_TXSTATUS;
 504                 value = b43_read32(dev, mmio_base + offset);
 505                 if (type == B43_DMA_64BIT) {
 506                         value &= B43_DMA64_TXSTAT;
 507                         if (value == B43_DMA64_TXSTAT_DISABLED ||
 508                             value == B43_DMA64_TXSTAT_IDLEWAIT ||
 509                             value == B43_DMA64_TXSTAT_STOPPED)
 510                                 break;
 511                 } else {
 512                         value &= B43_DMA32_TXSTATE;
 513                         if (value == B43_DMA32_TXSTAT_DISABLED ||
 514                             value == B43_DMA32_TXSTAT_IDLEWAIT ||
 515                             value == B43_DMA32_TXSTAT_STOPPED)
 516                                 break;
 517                 }
 518                 msleep(1);
 519         }
 520         offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
 521         b43_write32(dev, mmio_base + offset, 0);
 522         for (i = 0; i < 10; i++) {
 523                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 524                                                    B43_DMA32_TXSTATUS;
 525                 value = b43_read32(dev, mmio_base + offset);
 526                 if (type == B43_DMA_64BIT) {
 527                         value &= B43_DMA64_TXSTAT;
 528                         if (value == B43_DMA64_TXSTAT_DISABLED) {
 529                                 i = -1;
 530                                 break;
 531                         }
 532                 } else {
 533                         value &= B43_DMA32_TXSTATE;
 534                         if (value == B43_DMA32_TXSTAT_DISABLED) {
 535                                 i = -1;
 536                                 break;
 537                         }
 538                 }
 539                 msleep(1);
 540         }
 541         if (i != -1) {
 542                 b43err(dev->wl, "DMA TX reset timed out\n");
 543                 return -ENODEV;
 544         }
 545         /* ensure the reset is completed. */
 546         msleep(1);
 547
 548         return 0;
 549 }
 550
 551 /* Check if a DMA mapping address is invalid. */
 552 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
 553                                   dma_addr_t addr,
 554                                   size_t buffersize, bool dma_to_device)
 555 {
 556         if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
 557                 return 1;
 558
 559         switch (ring->type) {
 560         case B43_DMA_30BIT:
 561                 if ((u64)addr + buffersize > (1ULL << 30))
 562                         goto address_error;
 563                 break;
 564         case B43_DMA_32BIT:
 565                 if ((u64)addr + buffersize > (1ULL << 32))
 566                         goto address_error;
 567                 break;
 568         case B43_DMA_64BIT:
 569                 /* Currently we can't have addresses beyond
 570                  * 64bit in the kernel. */
 571                 break;
 572         }
 573
 574         /* The address is OK. */
 575         return 0;
 576
 577 address_error:
 578         /* We can't support this address. Unmap it again. */
 579         unmap_descbuffer(ring, addr, buffersize, dma_to_device);
 580
 581         return 1;
 582 }
 583
 584 static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
 585 {
 586         unsigned char *f = skb->data + ring->frameoffset;
 587
 588         return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
 589 }
 590
 591 static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
 592 {
 593         struct b43_rxhdr_fw4 *rxhdr;
 594         unsigned char *frame;
 595
 596         /* This poisons the RX buffer to detect DMA failures. */
 597
 598         rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
 599         rxhdr->frame_len = 0;
 600
 601         B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
 602         frame = skb->data + ring->frameoffset;
 603         memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
 604 }
 605
 606 static int setup_rx_descbuffer(struct b43_dmaring *ring,
 607                                struct b43_dmadesc_generic *desc,
 608                                struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
 609 {
 610         dma_addr_t dmaaddr;
 611         struct sk_buff *skb;
 612
 613         B43_WARN_ON(ring->tx);
 614
 615         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 616         if (unlikely(!skb))
 617                 return -ENOMEM;
 618         b43_poison_rx_buffer(ring, skb);
 619         dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
 620         if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 621                 /* ugh. try to realloc in zone_dma */
 622                 gfp_flags |= GFP_DMA;
 623
 624                 dev_kfree_skb_any(skb);
 625
 626                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 627                 if (unlikely(!skb))
 628                         return -ENOMEM;
 629                 b43_poison_rx_buffer(ring, skb);
 630                 dmaaddr = map_descbuffer(ring, skb->data,
 631                                          ring->rx_buffersize, 0);
 632                 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 633                         b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
 634                         dev_kfree_skb_any(skb);
 635                         return -EIO;
 636                 }
 637         }
 638
 639         meta->skb = skb;
 640         meta->dmaaddr = dmaaddr;
 641         ring->ops->fill_descriptor(ring, desc, dmaaddr,
 642                                    ring->rx_buffersize, 0, 0, 0);
 643
 644         return 0;
 645 }
 646
 647 /* Allocate the initial descbuffers.
 648  * This is used for an RX ring only.
 649  */
 650 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
 651 {
 652         int i, err = -ENOMEM;
 653         struct b43_dmadesc_generic *desc;
 654         struct b43_dmadesc_meta *meta;
 655
 656         for (i = 0; i < ring->nr_slots; i++) {
 657                 desc = ring->ops->idx2desc(ring, i, &meta);
 658
 659                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
 660                 if (err) {
 661                         b43err(ring->dev->wl,
 662                                "Failed to allocate initial descbuffers\n");
 663                         goto err_unwind;
 664                 }
 665         }
 666         mb();
 667         ring->used_slots = ring->nr_slots;
 668         err = 0;
 669       out:
 670         return err;
 671
 672       err_unwind:
 673         for (i--; i >= 0; i--) {
 674                 desc = ring->ops->idx2desc(ring, i, &meta);
 675
 676                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
 677                 dev_kfree_skb(meta->skb);
 678         }
 679         goto out;
 680 }
 681
 682 /* Do initial setup of the DMA controller.
 683  * Reset the controller, write the ring busaddress
 684  * and switch the "enable" bit on.
 685  */
 686 static int dmacontroller_setup(struct b43_dmaring *ring)
 687 {
 688         int err = 0;
 689         u32 value;
 690         u32 addrext;
 691         bool parity = ring->dev->dma.parity;
 692         u32 addrlo;
 693         u32 addrhi;
 694
 695         if (ring->tx) {
 696                 if (ring->type == B43_DMA_64BIT) {
 697                         u64 ringbase = (u64) (ring->dmabase);
 698                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 699                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 700                         addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH);
 701
 702                         value = B43_DMA64_TXENABLE;
 703                         value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
 704                             & B43_DMA64_TXADDREXT_MASK;
 705                         if (!parity)
 706                                 value |= B43_DMA64_TXPARITYDISABLE;
 707                         b43_dma_write(ring, B43_DMA64_TXCTL, value);
 708                         b43_dma_write(ring, B43_DMA64_TXRINGLO, addrlo);
 709                         b43_dma_write(ring, B43_DMA64_TXRINGHI, addrhi);
 710                 } else {
 711                         u32 ringbase = (u32) (ring->dmabase);
 712                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 713                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 714
 715                         value = B43_DMA32_TXENABLE;
 716                         value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
 717                             & B43_DMA32_TXADDREXT_MASK;
 718                         if (!parity)
 719                                 value |= B43_DMA32_TXPARITYDISABLE;
 720                         b43_dma_write(ring, B43_DMA32_TXCTL, value);
 721                         b43_dma_write(ring, B43_DMA32_TXRING, addrlo);
 722                 }
 723         } else {
 724                 err = alloc_initial_descbuffers(ring);
 725                 if (err)
 726                         goto out;
 727                 if (ring->type == B43_DMA_64BIT) {
 728                         u64 ringbase = (u64) (ring->dmabase);
 729                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 730                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 731                         addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH);
 732
 733                         value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
 734                         value |= B43_DMA64_RXENABLE;
 735                         value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
 736                             & B43_DMA64_RXADDREXT_MASK;
 737                         if (!parity)
 738                                 value |= B43_DMA64_RXPARITYDISABLE;
 739                         b43_dma_write(ring, B43_DMA64_RXCTL, value);
 740                         b43_dma_write(ring, B43_DMA64_RXRINGLO, addrlo);
 741                         b43_dma_write(ring, B43_DMA64_RXRINGHI, addrhi);
 742                         b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
 743                                       sizeof(struct b43_dmadesc64));
 744                 } else {
 745                         u32 ringbase = (u32) (ring->dmabase);
 746                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 747                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 748
 749                         value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
 750                         value |= B43_DMA32_RXENABLE;
 751                         value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
 752                             & B43_DMA32_RXADDREXT_MASK;
 753                         if (!parity)
 754                                 value |= B43_DMA32_RXPARITYDISABLE;
 755                         b43_dma_write(ring, B43_DMA32_RXCTL, value);
 756                         b43_dma_write(ring, B43_DMA32_RXRING, addrlo);
 757                         b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
 758                                       sizeof(struct b43_dmadesc32));
 759                 }
 760         }
 761
 762 out:
 763         return err;
 764 }
 765
 766 /* Shutdown the DMA controller. */
 767 static void dmacontroller_cleanup(struct b43_dmaring *ring)
 768 {
 769         if (ring->tx) {
 770                 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
 771                                            ring->type);
 772                 if (ring->type == B43_DMA_64BIT) {
 773                         b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
 774                         b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
 775                 } else
 776                         b43_dma_write(ring, B43_DMA32_TXRING, 0);
 777         } else {
 778                 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
 779                                            ring->type);
 780                 if (ring->type == B43_DMA_64BIT) {
 781                         b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
 782                         b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
 783                 } else
 784                         b43_dma_write(ring, B43_DMA32_RXRING, 0);
 785         }
 786 }
 787
 788 static void free_all_descbuffers(struct b43_dmaring *ring)
 789 {
 790         struct b43_dmadesc_meta *meta;
 791         int i;
 792
 793         if (!ring->used_slots)
 794                 return;
 795         for (i = 0; i < ring->nr_slots; i++) {
 796                 /* get meta - ignore returned value */
 797                 ring->ops->idx2desc(ring, i, &meta);
 798
 799                 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
 800                         B43_WARN_ON(!ring->tx);
 801                         continue;
 802                 }
 803                 if (ring->tx) {
 804                         unmap_descbuffer(ring, meta->dmaaddr,
 805                                          meta->skb->len, 1);
 806                 } else {
 807                         unmap_descbuffer(ring, meta->dmaaddr,
 808                                          ring->rx_buffersize, 0);
 809                 }
 810                 free_descriptor_buffer(ring, meta);
 811         }
 812 }
 813
 814 static u64 supported_dma_mask(struct b43_wldev *dev)
 815 {
 816         u32 tmp;
 817         u16 mmio_base;
 818
 819         tmp = b43_read32(dev, SSB_TMSHIGH);
 820         if (tmp & SSB_TMSHIGH_DMA64)
 821                 return DMA_BIT_MASK(64);
 822         mmio_base = b43_dmacontroller_base(0, 0);
 823         b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
 824         tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
 825         if (tmp & B43_DMA32_TXADDREXT_MASK)
 826                 return DMA_BIT_MASK(32);
 827
 828         return DMA_BIT_MASK(30);
 829 }
 830
 831 static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
 832 {
 833         if (dmamask == DMA_BIT_MASK(30))
 834                 return B43_DMA_30BIT;
 835         if (dmamask == DMA_BIT_MASK(32))
 836                 return B43_DMA_32BIT;
 837         if (dmamask == DMA_BIT_MASK(64))
 838                 return B43_DMA_64BIT;
 839         B43_WARN_ON(1);
 840         return B43_DMA_30BIT;
 841 }
 842
 843 /* Main initialization function. */
 844 static
 845 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
 846                                       int controller_index,
 847                                       int for_tx,
 848                                       enum b43_dmatype type)
 849 {
 850         struct b43_dmaring *ring;
 851         int i, err;
 852         dma_addr_t dma_test;
 853
 854         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 855         if (!ring)
 856                 goto out;
 857
 858         ring->nr_slots = B43_RXRING_SLOTS;
 859         if (for_tx)
 860                 ring->nr_slots = B43_TXRING_SLOTS;
 861
 862         ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
 863                              GFP_KERNEL);
 864         if (!ring->meta)
 865                 goto err_kfree_ring;
 866         for (i = 0; i < ring->nr_slots; i++)
 867                 ring->meta->skb = B43_DMA_PTR_POISON;
 868
 869         ring->type = type;
 870         ring->dev = dev;
 871         ring->mmio_base = b43_dmacontroller_base(type, controller_index);
 872         ring->index = controller_index;
 873         if (type == B43_DMA_64BIT)
 874                 ring->ops = &dma64_ops;
 875         else
 876                 ring->ops = &dma32_ops;
 877         if (for_tx) {
 878                 ring->tx = 1;
 879                 ring->current_slot = -1;
 880         } else {
 881                 if (ring->index == 0) {
 882                         switch (dev->fw.hdr_format) {
 883                         case B43_FW_HDR_598:
 884                                 ring->rx_buffersize = B43_DMA0_RX_FW598_BUFSIZE;
 885                                 ring->frameoffset = B43_DMA0_RX_FW598_FO;
 886                                 break;
 887                         case B43_FW_HDR_410:
 888                         case B43_FW_HDR_351:
 889                                 ring->rx_buffersize = B43_DMA0_RX_FW351_BUFSIZE;
 890                                 ring->frameoffset = B43_DMA0_RX_FW351_FO;
 891                                 break;
 892                         }
 893                 } else
 894                         B43_WARN_ON(1);
 895         }
 896 #ifdef CONFIG_B43_DEBUG
 897         ring->last_injected_overflow = jiffies;
 898 #endif
 899
 900         if (for_tx) {
 901                 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
 902                 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
 903
 904                 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
 905                                             b43_txhdr_size(dev),
 906                                             GFP_KERNEL);
 907                 if (!ring->txhdr_cache)
 908                         goto err_kfree_meta;
 909
 910                 /* test for ability to dma to txhdr_cache */
 911                 dma_test = dma_map_single(dev->dev->dma_dev,
 912                                           ring->txhdr_cache,
 913                                           b43_txhdr_size(dev),
 914                                           DMA_TO_DEVICE);
 915
 916                 if (b43_dma_mapping_error(ring, dma_test,
 917                                           b43_txhdr_size(dev), 1)) {
 918                         /* ugh realloc */
 919                         kfree(ring->txhdr_cache);
 920                         ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
 921                                                     b43_txhdr_size(dev),
 922                                                     GFP_KERNEL | GFP_DMA);
 923                         if (!ring->txhdr_cache)
 924                                 goto err_kfree_meta;
 925
 926                         dma_test = dma_map_single(dev->dev->dma_dev,
 927                                                   ring->txhdr_cache,
 928                                                   b43_txhdr_size(dev),
 929                                                   DMA_TO_DEVICE);
 930
 931                         if (b43_dma_mapping_error(ring, dma_test,
 932                                                   b43_txhdr_size(dev), 1)) {
 933
 934                                 b43err(dev->wl,
 935                                        "TXHDR DMA allocation failed\n");
 936                                 goto err_kfree_txhdr_cache;
 937                         }
 938                 }
 939
 940                 dma_unmap_single(dev->dev->dma_dev,
 941                                  dma_test, b43_txhdr_size(dev),
 942                                  DMA_TO_DEVICE);
 943         }
 944
 945         err = alloc_ringmemory(ring);
 946         if (err)
 947                 goto err_kfree_txhdr_cache;
 948         err = dmacontroller_setup(ring);
 949         if (err)
 950                 goto err_free_ringmemory;
 951
 952       out:
 953         return ring;
 954
 955       err_free_ringmemory:
 956         free_ringmemory(ring);
 957       err_kfree_txhdr_cache:
 958         kfree(ring->txhdr_cache);
 959       err_kfree_meta:
 960         kfree(ring->meta);
 961       err_kfree_ring:
 962         kfree(ring);
 963         ring = NULL;
 964         goto out;
 965 }
 966
 967 #define divide(a, b)    ({      \
 968         typeof(a) __a = a;      \
 969         do_div(__a, b);         \
 970         __a;                    \
 971   })
 972
 973 #define modulo(a, b)    ({      \
 974         typeof(a) __a = a;      \
 975         do_div(__a, b);         \
 976   })
 977
 978 /* Main cleanup function. */
 979 static void b43_destroy_dmaring(struct b43_dmaring *ring,
 980                                 const char *ringname)
 981 {
 982         if (!ring)
 983                 return;
 984
 985 #ifdef CONFIG_B43_DEBUG
 986         {
 987                 /* Print some statistics. */
 988                 u64 failed_packets = ring->nr_failed_tx_packets;
 989                 u64 succeed_packets = ring->nr_succeed_tx_packets;
 990                 u64 nr_packets = failed_packets + succeed_packets;
 991                 u64 permille_failed = 0, average_tries = 0;
 992
 993                 if (nr_packets)
 994                         permille_failed = divide(failed_packets * 1000, nr_packets);
 995                 if (nr_packets)
 996                         average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
 997
 998                 b43dbg(ring->dev->wl, "DMA-%u %s: "
 999                        "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
1000                        "Average tries %llu.%02llu\n",
1001                        (unsigned int)(ring->type), ringname,
1002                        ring->max_used_slots,
1003                        ring->nr_slots,
1004                        (unsigned long long)failed_packets,
1005                        (unsigned long long)nr_packets,
1006                        (unsigned long long)divide(permille_failed, 10),
1007                        (unsigned long long)modulo(permille_failed, 10),
1008                        (unsigned long long)divide(average_tries, 100),
1009                        (unsigned long long)modulo(average_tries, 100));
1010         }
1011 #endif /* DEBUG */
1012
1013         /* Device IRQs are disabled prior entering this function,
1014          * so no need to take care of concurrency with rx handler stuff.
1015          */
1016         dmacontroller_cleanup(ring);
1017         free_all_descbuffers(ring);
1018         free_ringmemory(ring);
1019
1020         kfree(ring->txhdr_cache);
1021         kfree(ring->meta);
1022         kfree(ring);
1023 }
1024
1025 #define destroy_ring(dma, ring) do {                            \
1026         b43_destroy_dmaring((dma)->ring, __stringify(ring));    \
1027         (dma)->ring = NULL;                                     \
1028     } while (0)
1029
1030 void b43_dma_free(struct b43_wldev *dev)
1031 {
1032         struct b43_dma *dma;
1033
1034         if (b43_using_pio_transfers(dev))
1035                 return;
1036         dma = &dev->dma;
1037
1038         destroy_ring(dma, rx_ring);
1039         destroy_ring(dma, tx_ring_AC_BK);
1040         destroy_ring(dma, tx_ring_AC_BE);
1041         destroy_ring(dma, tx_ring_AC_VI);
1042         destroy_ring(dma, tx_ring_AC_VO);
1043         destroy_ring(dma, tx_ring_mcast);
1044 }
1045
1046 static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1047 {
1048         u64 orig_mask = mask;
1049         bool fallback = 0;
1050         int err;
1051
1052         /* Try to set the DMA mask. If it fails, try falling back to a
1053          * lower mask, as we can always also support a lower one. */
1054         while (1) {
1055                 err = dma_set_mask(dev->dev->dma_dev, mask);
1056                 if (!err) {
1057                         err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
1058                         if (!err)
1059                                 break;
1060                 }
1061                 if (mask == DMA_BIT_MASK(64)) {
1062                         mask = DMA_BIT_MASK(32);
1063                         fallback = 1;
1064                         continue;
1065                 }
1066                 if (mask == DMA_BIT_MASK(32)) {
1067                         mask = DMA_BIT_MASK(30);
1068                         fallback = 1;
1069                         continue;
1070                 }
1071                 b43err(dev->wl, "The machine/kernel does not support "
1072                        "the required %u-bit DMA mask\n",
1073                        (unsigned int)dma_mask_to_engine_type(orig_mask));
1074                 return -EOPNOTSUPP;
1075         }
1076         if (fallback) {
1077                 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1078                         (unsigned int)dma_mask_to_engine_type(orig_mask),
1079                         (unsigned int)dma_mask_to_engine_type(mask));
1080         }
1081
1082         return 0;
1083 }
1084
1085 /* Some hardware with 64-bit DMA seems to be bugged and looks for translation
1086  * bit in low address word instead of high one.
1087  */
1088 static bool b43_dma_translation_in_low_word(struct b43_wldev *dev,
1089                                             enum b43_dmatype type)
1090 {
1091         if (type != B43_DMA_64BIT)
1092                 return 1;
1093
1094 #ifdef CONFIG_B43_SSB
1095         if (dev->dev->bus_type == B43_BUS_SSB &&
1096             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
1097             !(dev->dev->sdev->bus->host_pci->is_pcie &&
1098               ssb_read32(dev->dev->sdev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64))
1099                         return 1;
1100 #endif
1101         return 0;
1102 }
1103
1104 int b43_dma_init(struct b43_wldev *dev)
1105 {
1106         struct b43_dma *dma = &dev->dma;
1107         int err;
1108         u64 dmamask;
1109         enum b43_dmatype type;
1110
1111         dmamask = supported_dma_mask(dev);
1112         type = dma_mask_to_engine_type(dmamask);
1113         err = b43_dma_set_mask(dev, dmamask);
1114         if (err)
1115                 return err;
1116
1117         switch (dev->dev->bus_type) {
1118 #ifdef CONFIG_B43_BCMA
1119         case B43_BUS_BCMA:
1120                 dma->translation = bcma_core_dma_translation(dev->dev->bdev);
1121                 break;
1122 #endif
1123 #ifdef CONFIG_B43_SSB
1124         case B43_BUS_SSB:
1125                 dma->translation = ssb_dma_translation(dev->dev->sdev);
1126                 break;
1127 #endif
1128         }
1129         dma->translation_in_low = b43_dma_translation_in_low_word(dev, type);
1130
1131         dma->parity = true;
1132 #ifdef CONFIG_B43_BCMA
1133         /* TODO: find out which SSB devices need disabling parity */
1134         if (dev->dev->bus_type == B43_BUS_BCMA)
1135                 dma->parity = false;
1136 #endif
1137
1138         err = -ENOMEM;
1139         /* setup TX DMA channels. */
1140         dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1141         if (!dma->tx_ring_AC_BK)
1142                 goto out;
1143
1144         dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1145         if (!dma->tx_ring_AC_BE)
1146                 goto err_destroy_bk;
1147
1148         dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1149         if (!dma->tx_ring_AC_VI)
1150                 goto err_destroy_be;
1151
1152         dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1153         if (!dma->tx_ring_AC_VO)
1154                 goto err_destroy_vi;
1155
1156         dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1157         if (!dma->tx_ring_mcast)
1158                 goto err_destroy_vo;
1159
1160         /* setup RX DMA channel. */
1161         dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1162         if (!dma->rx_ring)
1163                 goto err_destroy_mcast;
1164
1165         /* No support for the TX status DMA ring. */
1166         B43_WARN_ON(dev->dev->core_rev < 5);
1167
1168         b43dbg(dev->wl, "%u-bit DMA initialized\n",
1169                (unsigned int)type);
1170         err = 0;
1171 out:
1172         return err;
1173
1174 err_destroy_mcast:
1175         destroy_ring(dma, tx_ring_mcast);
1176 err_destroy_vo:
1177         destroy_ring(dma, tx_ring_AC_VO);
1178 err_destroy_vi:
1179         destroy_ring(dma, tx_ring_AC_VI);
1180 err_destroy_be:
1181         destroy_ring(dma, tx_ring_AC_BE);
1182 err_destroy_bk:
1183         destroy_ring(dma, tx_ring_AC_BK);
1184         return err;
1185 }
1186
1187 /* Generate a cookie for the TX header. */
1188 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1189 {
1190         u16 cookie;
1191
1192         /* Use the upper 4 bits of the cookie as
1193          * DMA controller ID and store the slot number
1194          * in the lower 12 bits.
1195          * Note that the cookie must never be 0, as this
1196          * is a special value used in RX path.
1197          * It can also not be 0xFFFF because that is special
1198          * for multicast frames.
1199          */
1200         cookie = (((u16)ring->index + 1) << 12);
1201         B43_WARN_ON(slot & ~0x0FFF);
1202         cookie |= (u16)slot;
1203
1204         return cookie;
1205 }
1206
1207 /* Inspect a cookie and find out to which controller/slot it belongs. */
1208 static
1209 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1210 {
1211         struct b43_dma *dma = &dev->dma;
1212         struct b43_dmaring *ring = NULL;
1213
1214         switch (cookie & 0xF000) {
1215         case 0x1000:
1216                 ring = dma->tx_ring_AC_BK;
1217                 break;
1218         case 0x2000:
1219                 ring = dma->tx_ring_AC_BE;
1220                 break;
1221         case 0x3000:
1222                 ring = dma->tx_ring_AC_VI;
1223                 break;
1224         case 0x4000:
1225                 ring = dma->tx_ring_AC_VO;
1226                 break;
1227         case 0x5000:
1228                 ring = dma->tx_ring_mcast;
1229                 break;
1230         }
1231         *slot = (cookie & 0x0FFF);
1232         if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1233                 b43dbg(dev->wl, "TX-status contains "
1234                        "invalid cookie: 0x%04X\n", cookie);
1235                 return NULL;
1236         }
1237
1238         return ring;
1239 }
1240
1241 static int dma_tx_fragment(struct b43_dmaring *ring,
1242                            struct sk_buff *skb)
1243 {
1244         const struct b43_dma_ops *ops = ring->ops;
1245         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1246         struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
1247         u8 *header;
1248         int slot, old_top_slot, old_used_slots;
1249         int err;
1250         struct b43_dmadesc_generic *desc;
1251         struct b43_dmadesc_meta *meta;
1252         struct b43_dmadesc_meta *meta_hdr;
1253         u16 cookie;
1254         size_t hdrsize = b43_txhdr_size(ring->dev);
1255
1256         /* Important note: If the number of used DMA slots per TX frame
1257          * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1258          * the file has to be updated, too!
1259          */
1260
1261         old_top_slot = ring->current_slot;
1262         old_used_slots = ring->used_slots;
1263
1264         /* Get a slot for the header. */
1265         slot = request_slot(ring);
1266         desc = ops->idx2desc(ring, slot, &meta_hdr);
1267         memset(meta_hdr, 0, sizeof(*meta_hdr));
1268
1269         header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
1270         cookie = generate_cookie(ring, slot);
1271         err = b43_generate_txhdr(ring->dev, header,
1272                                  skb, info, cookie);
1273         if (unlikely(err)) {
1274                 ring->current_slot = old_top_slot;
1275                 ring->used_slots = old_used_slots;
1276                 return err;
1277         }
1278
1279         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1280                                            hdrsize, 1);
1281         if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1282                 ring->current_slot = old_top_slot;
1283                 ring->used_slots = old_used_slots;
1284                 return -EIO;
1285         }
1286         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1287                              hdrsize, 1, 0, 0);
1288
1289         /* Get a slot for the payload. */
1290         slot = request_slot(ring);
1291         desc = ops->idx2desc(ring, slot, &meta);
1292         memset(meta, 0, sizeof(*meta));
1293
1294         meta->skb = skb;
1295         meta->is_last_fragment = 1;
1296         priv_info->bouncebuffer = NULL;
1297
1298         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1299         /* create a bounce buffer in zone_dma on mapping failure. */
1300         if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1301                 priv_info->bouncebuffer = kmemdup(skb->data, skb->len,
1302                                                   GFP_ATOMIC | GFP_DMA);
1303                 if (!priv_info->bouncebuffer) {
1304                         ring->current_slot = old_top_slot;
1305                         ring->used_slots = old_used_slots;
1306                         err = -ENOMEM;
1307                         goto out_unmap_hdr;
1308                 }
1309
1310                 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
1311                 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1312                         kfree(priv_info->bouncebuffer);
1313                         priv_info->bouncebuffer = NULL;
1314                         ring->current_slot = old_top_slot;
1315                         ring->used_slots = old_used_slots;
1316                         err = -EIO;
1317                         goto out_unmap_hdr;
1318                 }
1319         }
1320
1321         ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1322
1323         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1324                 /* Tell the firmware about the cookie of the last
1325                  * mcast frame, so it can clear the more-data bit in it. */
1326                 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1327                                 B43_SHM_SH_MCASTCOOKIE, cookie);
1328         }
1329         /* Now transfer the whole frame. */
1330         wmb();
1331         ops->poke_tx(ring, next_slot(ring, slot));
1332         return 0;
1333
1334 out_unmap_hdr:
1335         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1336                          hdrsize, 1);
1337         return err;
1338 }
1339
1340 static inline int should_inject_overflow(struct b43_dmaring *ring)
1341 {
1342 #ifdef CONFIG_B43_DEBUG
1343         if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1344                 /* Check if we should inject another ringbuffer overflow
1345                  * to test handling of this situation in the stack. */
1346                 unsigned long next_overflow;
1347
1348                 next_overflow = ring->last_injected_overflow + HZ;
1349                 if (time_after(jiffies, next_overflow)) {
1350                         ring->last_injected_overflow = jiffies;
1351                         b43dbg(ring->dev->wl,
1352                                "Injecting TX ring overflow on "
1353                                "DMA controller %d\n", ring->index);
1354                         return 1;
1355                 }
1356         }
1357 #endif /* CONFIG_B43_DEBUG */
1358         return 0;
1359 }
1360
1361 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1362 static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1363                                                    u8 queue_prio)
1364 {
1365         struct b43_dmaring *ring;
1366
1367         if (dev->qos_enabled) {
1368                 /* 0 = highest priority */
1369                 switch (queue_prio) {
1370                 default:
1371                         B43_WARN_ON(1);
1372                         /* fallthrough */
1373                 case 0:
1374                         ring = dev->dma.tx_ring_AC_VO;
1375                         break;
1376                 case 1:
1377                         ring = dev->dma.tx_ring_AC_VI;
1378                         break;
1379                 case 2:
1380                         ring = dev->dma.tx_ring_AC_BE;
1381                         break;
1382                 case 3:
1383                         ring = dev->dma.tx_ring_AC_BK;
1384                         break;
1385                 }
1386         } else
1387                 ring = dev->dma.tx_ring_AC_BE;
1388
1389         return ring;
1390 }
1391
1392 int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1393 {
1394         struct b43_dmaring *ring;
1395         struct ieee80211_hdr *hdr;
1396         int err = 0;
1397         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1398
1399         hdr = (struct ieee80211_hdr *)skb->data;
1400         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1401                 /* The multicast ring will be sent after the DTIM */
1402                 ring = dev->dma.tx_ring_mcast;
1403                 /* Set the more-data bit. Ucode will clear it on
1404                  * the last frame for us. */
1405                 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1406         } else {
1407                 /* Decide by priority where to put this frame. */
1408                 ring = select_ring_by_priority(
1409                         dev, skb_get_queue_mapping(skb));
1410         }
1411
1412         B43_WARN_ON(!ring->tx);
1413
1414         if (unlikely(ring->stopped)) {
1415                 /* We get here only because of a bug in mac80211.
1416                  * Because of a race, one packet may be queued after
1417                  * the queue is stopped, thus we got called when we shouldn't.
1418                  * For now, just refuse the transmit. */
1419                 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1420                         b43err(dev->wl, "Packet after queue stopped\n");
1421                 err = -ENOSPC;
1422                 goto out;
1423         }
1424
1425         if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1426                 /* If we get here, we have a real error with the queue
1427                  * full, but queues not stopped. */
1428                 b43err(dev->wl, "DMA queue overflow\n");
1429                 err = -ENOSPC;
1430                 goto out;
1431         }
1432
1433         /* Assign the queue number to the ring (if not already done before)
1434          * so TX status handling can use it. The queue to ring mapping is
1435          * static, so we don't need to store it per frame. */
1436         ring->queue_prio = skb_get_queue_mapping(skb);
1437
1438         err = dma_tx_fragment(ring, skb);
1439         if (unlikely(err == -ENOKEY)) {
1440                 /* Drop this packet, as we don't have the encryption key
1441                  * anymore and must not transmit it unencrypted. */
1442                 dev_kfree_skb_any(skb);
1443                 err = 0;
1444                 goto out;
1445         }
1446         if (unlikely(err)) {
1447                 b43err(dev->wl, "DMA tx mapping failure\n");
1448                 goto out;
1449         }
1450         if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
1451             should_inject_overflow(ring)) {
1452                 /* This TX ring is full. */
1453                 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1454                 ring->stopped = 1;
1455                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1456                         b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1457                 }
1458         }
1459 out:
1460
1461         return err;
1462 }
1463
1464 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1465                              const struct b43_txstatus *status)
1466 {
1467         const struct b43_dma_ops *ops;
1468         struct b43_dmaring *ring;
1469         struct b43_dmadesc_meta *meta;
1470         int slot, firstused;
1471         bool frame_succeed;
1472
1473         ring = parse_cookie(dev, status->cookie, &slot);
1474         if (unlikely(!ring))
1475                 return;
1476         B43_WARN_ON(!ring->tx);
1477
1478         /* Sanity check: TX packets are processed in-order on one ring.
1479          * Check if the slot deduced from the cookie really is the first
1480          * used slot. */
1481         firstused = ring->current_slot - ring->used_slots + 1;
1482         if (firstused < 0)
1483                 firstused = ring->nr_slots + firstused;
1484         if (unlikely(slot != firstused)) {
1485                 /* This possibly is a firmware bug and will result in
1486                  * malfunction, memory leaks and/or stall of DMA functionality. */
1487                 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1488                        "Expected %d, but got %d\n",
1489                        ring->index, firstused, slot);
1490                 return;
1491         }
1492
1493         ops = ring->ops;
1494         while (1) {
1495                 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
1496                 /* get meta - ignore returned value */
1497                 ops->idx2desc(ring, slot, &meta);
1498
1499                 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1500                         b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1501                                "on ring %d\n",
1502                                slot, firstused, ring->index);
1503                         break;
1504                 }
1505                 if (meta->skb) {
1506                         struct b43_private_tx_info *priv_info =
1507                                 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1508
1509                         unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1510                         kfree(priv_info->bouncebuffer);
1511                         priv_info->bouncebuffer = NULL;
1512                 } else {
1513                         unmap_descbuffer(ring, meta->dmaaddr,
1514                                          b43_txhdr_size(dev), 1);
1515                 }
1516
1517                 if (meta->is_last_fragment) {
1518                         struct ieee80211_tx_info *info;
1519
1520                         if (unlikely(!meta->skb)) {
1521                                 /* This is a scatter-gather fragment of a frame, so
1522                                  * the skb pointer must not be NULL. */
1523                                 b43dbg(dev->wl, "TX status unexpected NULL skb "
1524                                        "at slot %d (first=%d) on ring %d\n",
1525                                        slot, firstused, ring->index);
1526                                 break;
1527                         }
1528
1529                         info = IEEE80211_SKB_CB(meta->skb);
1530
1531                         /*
1532                          * Call back to inform the ieee80211 subsystem about
1533                          * the status of the transmission.
1534                          */
1535                         frame_succeed = b43_fill_txstatus_report(dev, info, status);
1536 #ifdef CONFIG_B43_DEBUG
1537                         if (frame_succeed)
1538                                 ring->nr_succeed_tx_packets++;
1539                         else
1540                                 ring->nr_failed_tx_packets++;
1541                         ring->nr_total_packet_tries += status->frame_count;
1542 #endif /* DEBUG */
1543                         ieee80211_tx_status(dev->wl->hw, meta->skb);
1544
1545                         /* skb will be freed by ieee80211_tx_status().
1546                          * Poison our pointer. */
1547                         meta->skb = B43_DMA_PTR_POISON;
1548                 } else {
1549                         /* No need to call free_descriptor_buffer here, as
1550                          * this is only the txhdr, which is not allocated.
1551                          */
1552                         if (unlikely(meta->skb)) {
1553                                 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1554                                        "at slot %d (first=%d) on ring %d\n",
1555                                        slot, firstused, ring->index);
1556                                 break;
1557                         }
1558                 }
1559
1560                 /* Everything unmapped and free'd. So it's not used anymore. */
1561                 ring->used_slots--;
1562
1563                 if (meta->is_last_fragment) {
1564                         /* This is the last scatter-gather
1565                          * fragment of the frame. We are done. */
1566                         break;
1567                 }
1568                 slot = next_slot(ring, slot);
1569         }
1570         if (ring->stopped) {
1571                 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
1572                 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1573                 ring->stopped = 0;
1574                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1575                         b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1576                 }
1577         }
1578 }
1579
1580 static void dma_rx(struct b43_dmaring *ring, int *slot)
1581 {
1582         const struct b43_dma_ops *ops = ring->ops;
1583         struct b43_dmadesc_generic *desc;
1584         struct b43_dmadesc_meta *meta;
1585         struct b43_rxhdr_fw4 *rxhdr;
1586         struct sk_buff *skb;
1587         u16 len;
1588         int err;
1589         dma_addr_t dmaaddr;
1590
1591         desc = ops->idx2desc(ring, *slot, &meta);
1592
1593         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1594         skb = meta->skb;
1595
1596         rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1597         len = le16_to_cpu(rxhdr->frame_len);
1598         if (len == 0) {
1599                 int i = 0;
1600
1601                 do {
1602                         udelay(2);
1603                         barrier();
1604                         len = le16_to_cpu(rxhdr->frame_len);
1605                 } while (len == 0 && i++ < 5);
1606                 if (unlikely(len == 0)) {
1607                         dmaaddr = meta->dmaaddr;
1608                         goto drop_recycle_buffer;
1609                 }
1610         }
1611         if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1612                 /* Something went wrong with the DMA.
1613                  * The device did not touch the buffer and did not overwrite the poison. */
1614                 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
1615                 dmaaddr = meta->dmaaddr;
1616                 goto drop_recycle_buffer;
1617         }
1618         if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) {
1619                 /* The data did not fit into one descriptor buffer
1620                  * and is split over multiple buffers.
1621                  * This should never happen, as we try to allocate buffers
1622                  * big enough. So simply ignore this packet.
1623                  */
1624                 int cnt = 0;
1625                 s32 tmp = len;
1626
1627                 while (1) {
1628                         desc = ops->idx2desc(ring, *slot, &meta);
1629                         /* recycle the descriptor buffer. */
1630                         b43_poison_rx_buffer(ring, meta->skb);
1631                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1632                                                    ring->rx_buffersize);
1633                         *slot = next_slot(ring, *slot);
1634                         cnt++;
1635                         tmp -= ring->rx_buffersize;
1636                         if (tmp <= 0)
1637                                 break;
1638                 }
1639                 b43err(ring->dev->wl, "DMA RX buffer too small "
1640                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1641                        len, ring->rx_buffersize, cnt);
1642                 goto drop;
1643         }
1644
1645         dmaaddr = meta->dmaaddr;
1646         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1647         if (unlikely(err)) {
1648                 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1649                 goto drop_recycle_buffer;
1650         }
1651
1652         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1653         skb_put(skb, len + ring->frameoffset);
1654         skb_pull(skb, ring->frameoffset);
1655
1656         b43_rx(ring->dev, skb, rxhdr);
1657 drop:
1658         return;
1659
1660 drop_recycle_buffer:
1661         /* Poison and recycle the RX buffer. */
1662         b43_poison_rx_buffer(ring, skb);
1663         sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1664 }
1665
1666 void b43_dma_rx(struct b43_dmaring *ring)
1667 {
1668         const struct b43_dma_ops *ops = ring->ops;
1669         int slot, current_slot;
1670         int used_slots = 0;
1671
1672         B43_WARN_ON(ring->tx);
1673         current_slot = ops->get_current_rxslot(ring);
1674         B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1675
1676         slot = ring->current_slot;
1677         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1678                 dma_rx(ring, &slot);
1679                 update_max_used_slots(ring, ++used_slots);
1680         }
1681         wmb();
1682         ops->set_current_rxslot(ring, slot);
1683         ring->current_slot = slot;
1684 }
1685
1686 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1687 {
1688         B43_WARN_ON(!ring->tx);
1689         ring->ops->tx_suspend(ring);
1690 }
1691
1692 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1693 {
1694         B43_WARN_ON(!ring->tx);
1695         ring->ops->tx_resume(ring);
1696 }
1697
1698 void b43_dma_tx_suspend(struct b43_wldev *dev)
1699 {
1700         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1701         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1702         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1703         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1704         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1705         b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1706 }
1707
1708 void b43_dma_tx_resume(struct b43_wldev *dev)
1709 {
1710         b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1711         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1712         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1713         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1714         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1715         b43_power_saving_ctl_bits(dev, 0);
1716 }
1717
1718 static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1719                            u16 mmio_base, bool enable)
1720 {
1721         u32 ctl;
1722
1723         if (type == B43_DMA_64BIT) {
1724                 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1725                 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1726                 if (enable)
1727                         ctl |= B43_DMA64_RXDIRECTFIFO;
1728                 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1729         } else {
1730                 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1731                 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1732                 if (enable)
1733                         ctl |= B43_DMA32_RXDIRECTFIFO;
1734                 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1735         }
1736 }
1737
1738 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1739  * This is called from PIO code, so DMA structures are not available. */
1740 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1741                             unsigned int engine_index, bool enable)
1742 {
1743         enum b43_dmatype type;
1744         u16 mmio_base;
1745
1746         type = dma_mask_to_engine_type(supported_dma_mask(dev));
1747
1748         mmio_base = b43_dmacontroller_base(type, engine_index);
1749         direct_fifo_rx(dev, type, mmio_base, enable);
1750 }